HT24LC02
2K 2-Wire CMOS Serial EEPROM
Block Diagram Pin Assignment
1 November 16, 2000
Features
·Operating voltage: 2.4V~5.5V
·Low power consumption
-Operation: 5mA max.
-Standby: 5mA max.
·Internal organization
-2K (HT24LC02): 256´8
·2-wire serial interface
·Write cycle time: 5ms max.
·Automatic erase-before-write operation
·Partial page write allowed
·8-byte Page write modes
·Write operation with built-in timer
·Hardware controlled write protection
·40-year data retention
·106erase/write cycles per word
·8-pin DIP/SOP package
·8-pin TSSOP (HT24LC02 only)
·Commerical temperature range
(0°Cto+70°C)
General Description
The HT24LC02 is a 2K-bit serial read/write
non-volatile memory device using the CMOS
floating gate process. Its 2048 bits of memory
are organized into 256 words and each word is 8
bits. The device is optimized for use in many in-
dustrial and commercial applications where
low power and low voltage operation are essen-
tial. Up to eight HT24LC02 devices may be con-
nected to the same two-wire bus. The
HT24LC02 is guaranteed for 1M erase/write cy-
cles and 40-year data retention.
1
2
3
4
8
7
6
5
H T 2 4 L C 0 2
8 D IP /S O P /T S S O P
A0
A1
A2
VSS
VCC
WP
SCL
SDA
I/O
Control
Logic
Memory
Control
Logic
SCL
SDA
Address
Counter
A0~A2
VCC
VSS
X
D
E
C
EEPROM
Array
Page Buf
YDEC
Sense AM P
R/W Control
HV Pump
WP
Pin Description
Pin Name I/O Description
A0~A2 I Address inputs
SDA I/O Serial data inputs/output
SCL I Serial clock data input
WP I Write protect
VSS ¾Negative power supply
VCC I Positive power supply
Absolute Maximum Ratings
Operating Temperature (Commercial) .................................................................................0°Cto70°C
Storage Temperature .......................................................................................................-50°Cto125°C
Applied VCC Voltage with Respect to VSS ......................................................................-0.3V to 6.0V
Applied Voltage on any Pin with Respect to VSS ....................................................-0.3V to VCC+0.3V
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi-
mum Ratings²may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged expo-
sure to extreme conditions may affect device reliability.
D.C. Characteristics Ta=0°Cto70°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VCC Conditions
VCC Operating Voltage ¾¾ 2.4 ¾5.5 V
ICC1 Operating Current 5V Read at 100kHz ¾¾ 2mA
ICC2 Operating Current 5V Write at 100kHz ¾¾ 5mA
VIL Input Low Voltage ¾¾ -1¾0.3VCC V
VIH Input High Voltage ¾¾
0.7VCC ¾VCC+0.5 V
VOL Output Low Voltage 2.4V IOL=2.1mA ¾¾0.4 V
ILI Input Leakage Current 5V VIN=0 or VCC ¾¾ 1mA
ILO Output Leakage Current 5V VOUT=0 or VCC ¾¾ 1mA
ISTB1 Standby Current 5V VIN=0 or VCC ¾¾ 5mA
ISTB2 Standby Current 2.4V VIN=0 or VCC ¾¾ 4mA
CIN Input Capacitance (See Note) ¾f=1MHz 25°C¾¾ 6pF
COUT Output Capacitance (See Note) ¾f=1MHz 25°C¾¾ 8pF
Note: These parameters are periodically sampled but not 100% tested
HT24LC02
2 November 16, 2000
A.C. Characteristics Ta=0°Cto70°C
Symbol Parameter Remark Standard Mode* VCC=5V±10% Unit
Min. Max. Min. Max.
fSK Clock Frequency ¾¾
100 ¾400 kHz
tHIGH Clock High Time ¾4000 ¾600 ¾ns
tLOW Clock Low Time ¾4700 ¾1200 ¾ns
trSDA and SCL Rise Time Note ¾1000 ¾300 ns
tfSDA and SCL Fall Time Note ¾300 ¾300 ns
tHD:STA START Condition Hold
Time
After this period
the first clock
pulse is generated
4000 ¾600 ¾ns
tSU:STA START Condition
Setup Time
Only relevant for
repeated START
condition
4000 ¾600 ¾ns
tHD:DAT Data Input Hold Time ¾0¾0¾ns
tSU:DAT Data Input Setup Time ¾200 ¾100 ¾ns
tSU:STO STOP Condition Setup
Time ¾4000 ¾600 ¾ns
tAA Output Valid from
Clock ¾¾
3500 ¾900 ns
tBUF Bus Free Time
Time in which the
bus must be free
before a new
transmission can
start
4700 ¾1200 ¾ns
tSP
Input Filter Time
Constant (SDA and SCL
Pins)
Noise suppression
time ¾100 ¾50 ns
tWR Write Cycle Time ¾¾
5¾5ms
Note: These parameters are periodically sampled but not 100% tested
* The standard mode means VCC=2.4V to 5.5V
For relative timing, refer to timing diagrams
HT24LC02
3 November 16, 2000
HT24LC02
4 November 16, 2000
Functional Description
·Serial clock (SCL)
The SCL input is used for positive edge clock
data into each EEPROM device and negative
edge clock data out of each device.
·Serial data (SDA)
The SDA pin is bidirectional for serial data
transfer. The pin is open-drain driven and
may be wired-OR with any number of other
open-drain or open collector devices.
·A0, A1, A2
The A2, A1 and A0 pins are device address in-
puts that are hard wired for the HT24LC02.
As many as eight 2K devices may be ad-
dressed on a single bus system (the device ad-
dressing is discussed in detail under the
Device Addressing section).
·Write protect (WP)
The HT24LC02 has a write protect pin that
provides hardware data protection. The write
protect pin allows normal read/write opera-
tions when connected to the VSS. When the
write protect pin is connected to Vcc, the write
protection feature is enabled and operates as
shown in the following table.
WP Pin
Status Protect Array
At VCC Full Array (2K)
At VSS Normal Read/Write Operations
Memory organization
·HT24LC02, 2K Serial EEPROM
Internally organized with 256 8-bit words,
the 2K requires an 8-bit data word address for
random word addressing.
Device operations
·Clock and data transition
Data transfer may be initiated only when the
bus is not busy. During data transfer, the data
line must remain stable whenever the clock
line is high. Changes in data line while the
clock line is high will be interpreted as a
START or STOP condition.
·Start condition
A high-to-low transition of SDA with SCL
high is a start condition which must precede
any other command (refer to Start and Stop
Definition Timing diagram).
·Stop condition
A low-to-high transition of SDA with SCL
high is a stop condition. After a read se-
quence, the stop command will place the
EEPROM in a standby power mode (refer to
Start and Stop Definition Timing Diagram).
·Acknowledge
All addresses and data words are serially
transmitted to and from the EEPROM in
8-bit words. The EEPROM sends a zero to ac-
knowledge that it has received each word.
This happens during the ninth clock cycle.
Device addressing
The 2K EEPROM devices all require an 8-bit
device address word following a start condition
to enable the chip for a read or write operation.
The device address word consist of a mandatory
one, zero sequence for the first four most signif-
icant bits (refer to the diagram showing the De-
vice Address). This is common to all the
EEPROM device.
The next three bits are the A2, A1 and A0 de-
vice address bits for the 2K EEPROM. These
three bits must compare to their corresponding
hard-wired input pins.
SCL
SDA
D ata allow ed
to change
Address or
acknow ledge
valid
Stop
condition
Start
condition
HT24LC02
5 November 16, 2000
The 8th bit of device address is the read/write
operation select bit. A read operation is initi-
ated if this bit is high and a write operation is
initiated if this bit is low.
If the comparison of the device address succeed
the EEPROM will output a zero at ACK bit. If not,
the chip will return to a standby state.
Write operations
·Byte write
A write operation requires an 8-bit data word
address following the device address word
and acknowledgment. Upon receipt of this ad-
dress, the EEPROM will again respond with a
zero and then clock in the first 8-bit data
word. After receiving the 8-bit data word, the
EEPROM will output a zero and the address-
ing device, such as a microcontroller, must
terminate the write sequence with a stop con-
dition. At this time the EEPROM enters an
internally-timed write cycle to the
non-volatile memory. All inputs are disabled
during this write cycle and EEPROM will not
respond until the write is completed (refer to
Byte write timing).
·Page write
The 2K EEPROM is capable of an 8-byte page
write.
A page write is initiated the same as byte
write, but the microcontroller does not send a
stop condition after the first data word is
clocked in. Instead, after the EEPROM ac-
knowledges the receipt of the first data word,
the microcontroller can transmit up to seven
more data words. The EEPROM will respond
with a zero after each data word received. The
microcontroller must terminate the page
write sequence with a stop condition.
The data word address lower three (2K) bits
are internally incremented following the re-
ceipt of each data word. The higher data word
address bits are not incremented, retaining
the memory page row location (refer to Page
write timing).
·Acknowledge polling
Since the device will not acknowledge during
a write cycle, this can be used to determine
when the cycle is complete (this feature can be
used to maximize bus throughput). Once the
stop condition for a write command has been
issued from the master, the device initiates
the internally timed write cycle. ACK polling
can be initiated immediately. This involves
the master sending a start condition followed
by the control byte for a write command
(R/W=0). If the device is still busy with the
write cycle, then no ACK will be returned. If
the cycle is completed, then the device will re-
turn the ACK and the master can then pro-
ceed with the next read or write command.
R/W
A2 A1 A0S P
D evice address W ord address D ATA
ACK Stop
Start
SDA
ACK ACK
B y te w rite tim in g
R/W1 0 A2 A1 A0
D evice A ddress
10
P
D evice address W ord address D ATA n
ACK
Stop
Start
SDA
ACK ACK
S
ACK
D A T A n + 1 D A T A n + x
Page w rite tim ing
HT24LC02
6 November 16, 2000
·Write protect
The HT24LC02 can be used as a serial ROM
when the WP pin is connected to VCC. Pro-
gramming will be inhibited and the entire
memory will be write-protected.
·Read operations
Read operations are initiated the same way
as write operations with the exception that
the read/write select bit in the device address
word is set to one. There are three read opera-
tions: current address read, random address
read and sequential read.
·Current address read
The internal data word address counter
maintains the last address accessed during
the last read or write operation, incremented
by one. This address stays valid between op-
erations as long as the chip power is main-
tained. The address roll over during read
from the last byte of the last memory page to
the first byte of the first page. The address
roll over during write from the last byte of the
current page to the first byte of the same
page. Once the device address with the
read/write select bit set to one is clocked in
and acknowledged by the EEPROM, the cur-
rent address data word is serially clocked out.
The microcontroller does not respond with an
input zero but generates a following stop con-
dition (refer to Current read timing).
·Random read
A random read requires a dummy byte write
sequence to load in the data word address
which is then clocked in and acknowledged by
the EEPROM. The microcontroller must then
generate another start condition. The
microcontroller now initiates a current ad-
dress read by sending a device address with
the read/write select bit high. The EEPROM
acknowledges the device address and serially
clocks out the data word. The microcontroller
does not respond with a zero but does gener-
ates a following stop condition (refer to Ran-
dom read timing).
S e n d W rite C o m m a n d
Send Stop C ondition
to Initiate W rite C ycle
Send Start
Send C otroll B yte
w ith R /W = 0
(A C K = 0 )?
N ext O peration
No
Yes
Acknowledge polling flow
A2 A1 A0S P
D evice address D A TA
ACK
Stop
Start
SDA
No ACK
C urrent read tim ing
Timing Diagrams
Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end
of the valid start condition of sequential command.
HT24LC02
7 November 16, 2000
·Sequential read
Sequential reads are initiated by either a cur-
rent address read or a random address read. Af-
ter the microcontroller receives a data word, it
responds with an acknowledgment. As long as
the EEPROM receives an acknowledgment, it
will continue to increment the data word ad-
dress and serially clock out sequential data
words. When the memory address limit is
reached, the data word address will roll over
and the sequential read continues. The sequen-
tial read operation is terminated when the
microcontroller does not respond with a zero
but generates a following stop condition.
P
D evice address D A T A n
Stop
Start
SDA
ACK ACK
S
ACK
DATA n+1 DATA n+x
Sequential read tim ing
t
f
t
LO W
t
r
t
HIGH
t
SU
:
STA
t
HD
:
STA
t
SP
t
HD
:
DAT
t
SU
:
DAT
t
SU
:
STO
t
BUF
Valid Valid
SCL
SDA
SDA
OUT
t
AA
t
WR
SCL
SDA 8th bit ACK
Word n
Stop
C ondition
Start
C ondition
HT24LC02
8 November 16, 2000
Copyright Ó2000 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications
will be suitable without further modification, nor recommends the use of its products for application that may pres-
ent a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior
notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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