VIPER28 Peak power high-voltage converter - VIPer Plus Datasheet - production data * Thermal shutdown increases system reliability and IC lifetime Applications 62QDUURZ * Auxiliary power supply for consumer and home equipment ',3 * Power supply for energy meters and data concentrators Figure 1. Typical application Z * AC-DC adapters Description '5$,1 ,sZ &217 (37 9,3HU )% 9'' *1' ZZ Features * 800 V avalanche-rugged power MOSFET allowing achieving ultra wide-range input Vac * Embedded HV startup and sense FET * PWM current-mode controller * OCP with selectable threshold (IDlim) and 2nd OCP with higher value (IDMAX) to protect the IC from transformer saturation or short-circuit of the secondary diode The device is a high-voltage converter that smartly integrates an 800 V rugged power MOSFET with PWM current-mode control.This IC is capable of meeting more stringent energysaving standards as it has very low consumption and operates in burst mode under light load. The device features an adjustable extra power timer (EPT) that enables the IC to sustain overload conditions for a few seconds. The integrated HV startup, sense FET and oscillator with jitter allow the advantage of using minimal components in the application. The device features high-level protections like dual-level OCP, output overvoltage, short-circuit, and thermal shutdown with hysteresis. After the removal of a fault condition, the IC is automatically restarted. * 30 mW no-load consumption at 230 Vac * Two operating frequencies: - 60 kHz (L type) or 115 kHz (H type) Table 1. Device summary Order codes Package * Extra power timer (EPT) blanks the overload current for few seconds VIPER28LN / VIPER28HN DIP-7 * Output overvoltage protection with tight tolerance and digital noise filter VIPER28HD / VIPER28LD * Jittered frequency reduces the EMI Packaging Tube SO16 narrow * Soft-start reduces the stress during startup and increases IC lifetime VIPER28HDTR / VIPER28LDTR Tape and reel * Automatic restart after a fault condition December 2014 This is information on a product in full production. DocID15028 Rev 6 1/31 www.st.com Contents VIPER28 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 Typical circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8 9 2/31 7.1 Power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2 High-voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.3 Power-up and soft startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.5 Auto-restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.6 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.7 Current mode conversion with adjustable current limit setpoint . . . . . . . . 18 7.8 Overvoltage protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.9 About CONT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.10 Feedback and overload protection (OLP) . . . . . . . . . . . . . . . . . . . . . . . . 20 7.11 Burst-mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 23 7.12 Extra power timer (EPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.13 2nd level overcurrent protection and hiccup mode . . . . . . . . . . . . . . . . . . 25 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.1 DIP-7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.2 SO16 Narrow package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DocID15028 Rev 6 VIPER28 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Avalanche ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Controller section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 CONT pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DIP-7 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SO16 Narrow mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DocID15028 Rev 6 3/31 31 List of figures VIPER28 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. 4/31 Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Connection diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Minimum turn-on time test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 OVP threshold test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 IDlim vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 FOSC vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VDRAIN_START vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 IDD0 vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 IDD1 vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Main FET RDSON vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Main FET VBVDSS vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 IDlim vs. RLIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Basic flyback application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Full-featured flyback application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 IDD current during startup and burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Timing diagram: normal power-up and power-down sequences . . . . . . . . . . . . . . . . . . . . 16 Soft-start: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Timing diagram: behavior after short-circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 OVP timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CONT pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 FB pin configuration (option 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 FB pin configuration (option 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Burst mode timing diagram, light load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 EPT timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DIP-7 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SO16 narrow package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DocID15028 Rev 6 VIPER28 1 Block diagram Block diagram Figure 2. Block diagram 9'' '5$,1 /(% (37 ([WUD3RZHU7LPHU 6833/< 89/2 ,QWHUQDO6XSSO\%86 5()(5(1&(92/7$*(6 2/3 +9B21 ,''FK 89/2 62)767$57 2&3 26&,//$725 &217 ,'/,0 %8567 293 293/2*,& 3:0 785121 /2*,& 6 /(% 5 4 5 7+(50$/ 6(1625 ,QWHUQDOUHIHUHQFH , )% UHI 273 /(% /2*,& 2/3 293 QG 2&3 , )% 9)%9)%BOLQ ,)% 2/3 /2*,& 2/3 %856702'( /2*,& 56(16( %8567 )% 2 *1' Typical power Table 2. Typical power 85-265 VAC 230 VAC Nominal power VIPER28xD/xN Adapter(1) Open frame(2) Adapter(1) Open frame(2) 13 W 16 W 10 W 12 W 22 W (peak)(3) 26 W (peak)(3) 17 W (peak)(3) 20 W (peak)(3) 1. Typical continuous power in non-ventilated enclosed adapter measured at 50 C ambient. 2. Maximum practical continuous power in an open frame design at 50 C ambient, with adequate heat sinking. 3. Maximum practical peak power at 50 C ambient, with adequate heat sinking for 2 sec (max). DocID15028 Rev 6 5/31 31 Pin settings 3 VIPER28 Pin settings Figure 3. Connection diagram (top view) Note: The copper area for heat dissipation has to be designed under the DRAIN pins. Table 3. Pin description SO16N Name 1, 2 GND This pin represents the device ground and the source of the power section. 3 N.C. Not connected. 4 N.A. Not available for user. This pin is mechanically connected to the controller die pad of the frame. In order to improve the noise immunity, is highly recommended connect it to GND (pin 1-2). 5 VDD Supply voltage of the control section. This pin also provides the charging current of the external capacitor during startup. 6 Control pin. The following functions can be selected: 1. current limit setpoint adjustment. The default value (set internally) of the cycleby-cycle current limit can be reduced by connecting an external resistor to ground. CONT 2. output voltage monitoring. A voltage exceeding the VOVP threshold (see Table 9: Controller section on page 9) shuts the IC down, reducing device consumption. This function is strobed and digitally filtered for high noise immunity. Control input for duty cycle control. The internal current generator provides bias current for loop regulation. A voltage below the threshold VFBbm activates burstmode operation. A level close to the threshold VFBlin means that we are approaching the cycle-by-cycle overcurrent setpoint. 7 FB 8 EPT This pin allows the connection of an external capacitor for extra power management. If the function is not used, the pin has to be connected to GND. 9...12 N.C. Not connected. 13...16 6/31 Function High-voltage drain pin. The built-in high-voltage switched startup bias current is DRAIN drawn from this pin too. These pins are connected to the metal frame to facilitate heat dissipation. DocID15028 Rev 6 VIPER28 4 Electrical ratings Electrical ratings Table 4. Absolute maximum ratings Value Symbol Parameter Unit Min VDRAIN Drain-to-source (ground) voltage IDRAIN Pulse drain current (limited by TJ = 150 C) VCONT Control input pin voltage VFB Max 800 V 3 A -0.3 6 V Feedback voltage -0.3 5.5 V VEPT EPT input pin voltage -0.3 5 V VDD Supply voltage (IDD = 25 mA) -0.3 Self limited V IDD Input current 25 mA Power dissipation at TA < 40 C (DIP-7) 1 PTOT TJ W Power dissipation at TA < 60 C (SO16N) 1.5 Operating junction temperature range -40 150 C TSTG Storage temperature -55 150 C HBM(ESD) Human body model 2 ESD(CDM) Charge device mode 1.5 kV Table 5. Thermal ratings Max value Symbol Parameter Unit SO16N DIP7 RthJP Thermal resistance junction pin (dissipated power = 1 W) 35 35 C/W RthJA Thermal resistance junction ambient (dissipated power = 1 W) 105 110 C/W RthJA Thermal resistance junction ambient (1) (dissipated power = 1 W) 80 90 C/W 1. When mounted on a standard single side FR4 board with 100 mm2 (0.155 sq inch) of Cu (35 m thick) Table 6. Avalanche ratings Symbol Parameter Test condition Value Unit IAS Avalanche current Repetitive or non repetitive (pulse width limited by TJmax) 1 A EAS Single pulse avalanche energy(1) ID = IAS, VDS=100 V starting TJ = 25C 3 mJ 1. This parameter is derived from characterization data. DocID15028 Rev 6 7/31 31 Electrical ratings 4.1 VIPER28 Electrical characteristics TJ = -25 to 125 C, VDD= 14 V; unless otherwise specified (adjust VDD above VDDon startup threshold before setting to 14 V). Table 7. Power section Symbol Parameter VBVDSS Breakdown voltage IOFF RDS(on) COSS Test condition Min Typ Max Unit IDRAIN = 1 mA, VFB = GND, TJ = 25 C 800 V OFF-state drain current VDRAIN = max rating,VFB = GND, TJ = 25C 60 A Drain-source on-state resistance IDRAIN = 0.4 A, VFB = 3 V, VEPT = GND, TJ = 25 C 7 IDRAIN = 0.4 A, VFB = 3 V, VEPT = GND, TJ = 125 C 14 Effective (energy related) output capacitance VDRAIN = 0 to 640 V, TJ = 25C 40 pF Table 8. Supply section Symbol Parameter Test condition Min Typ Max Unit 60 80 100 V -2 -3 -4 mA -0.4 -0.6 -0.8 mA 23.5 V Voltage VDRAIN_START Drain-source start voltage VDRAIN = 120 V, VEPT = GND, IDDch1 Startup charging current IDDch2 Restart charging current (after fault) VDRAIN = 120 V, VEPT = GND, VDD Operating voltage range After turn-on 8.5 VDD clamp voltage IDD = 20 mA 23.5 VDDclamp VDDon VDD startup threshold VDDoff VDD undervoltage shutdown threshold VDD(RESTART) VDD restart voltage threshold VFB = GND, VDD = 4 V VFB = GND, VDD = 5 V VDRAIN = 120 V, VEPT = GND, VFB = GND VDRAIN = 120 V, VEPT = GND, VFB = GND V 13 14 15 V 7.5 8 8.5 V 4 4.5 5 V Current IDD0 Operating supply current, not switching VFB = GND, FOSC = 0 kHz VEPT = GND, VDD = 10 V 0.9 mA Operating supply current, switching VDRAIN = 120 V, FOSC = 60 kHz 2.5 mA IDD1 VDRAIN = 120 V,FOSC = 115 kHz 3.5 mA IDD_FAULT Operating supply current, with protection tripping VDD = 10 V 400 uA IDD_OFF Operating supply current with VDD < VDD_OFF VDD = 7 V 270 uA 8/31 DocID15028 Rev 6 VIPER28 Electrical ratings Table 9. Controller section Symbol Parameter Test condition Min Typ Max Unit Feed-back pin VFBolp Overload shutdown threshold 4.5 4.8 5.2 V VFBlin Overload detection threshold 3.2 3.5 3.7 V VFBbm Burst mode threshold Voltage falling 0.54 0.6 0.66 V VFBbmhys Burst mode hysteresis Voltage rising IFB1 Feedback sourced current VFB = 0.3 V IFB2 Feedback current-OLP delay VFBlin < VFB < VFBolp RFB(DYN) Dynamic resistance VFB < 3.3 V 100 -150 -200 mV -280 -3 uA uA 14 20 k 2 6 V/A (1) HFB VFB / ID TJ = 25 C CONT pin VCONT_l Low-level clamp voltage ICONT = -100 A VCONT_h High-level clamp voltage ICONT = 1 mA 0.4 0.5 0.6 V 5 5.5 6 V 0.75 0.80 0.85 A Current limitation VFB = 4 V, ICONT = -10 A TJ = 25 C IDlim Max drain current limitation tSS Soft-start time 7.6 8.5 9.4 ms Minimum turn-on time 220 370 480 ns TON_MIN td tLEB ID_BM Propagation delay 100 ns Leading edge blanking (1) 300 ns Peak drain current during burst mode VFB = 0.6 V 160 mA Oscillator section FOSC FD VFB = 1 V VIPER28L 54 60 66 kHz VIPER28H 103 115 127 kHz VIPER28L 4 kHz VIPER28H 8 kHz Modulation depth FM Modulation frequency 200 DMAX Maximum duty cycle 70 250 300 Hz 80 % nd OCP) Overcurrent protection (2 IDMAX (1) Second overcurrent threshold 1.2 A Overvoltage protection VOVP Overvoltage protection threshold DocID15028 Rev 6 2.7 3 3.3 V 9/31 31 Electrical ratings VIPER28 Table 9. Controller section (continued) Symbol tSTROBE Parameter Test condition Min Overvoltage protection strobe time Typ Max Unit 2.2 s 85% IDlim A Extra power management IDLIM_EPT VEPT(STOP) Drain current limit with EPT function (1) EPT shutdown threshold ICONT < -10 A VEPT(RESTART) EPT restart threshold IEPT Sink/source current 3.6 4 4.4 V 0.4 0.6 0.8 V 4 5 6 A 150 160 C 30 C Thermal shutdown TSD THYST Thermal shutdown temperature (1) Thermal shutdown hysteresis (1) 1. Specification guaranteed by characterization. Figure 4. Minimum turn-on time test circuit 14 V GND DRAIN VDD DRAIN 90 % TONmin 50 CONT 10 % Time IDRAIN EPT FB VDRAIN IDLIM 30 V 3.5 V Time Figure 5. OVP threshold test circuit VCONT 14 V GND DRAIN VDD DRAIN CONT FB VOVP 10 kW VDRAIN EPT Time 30 V 2V Time Note: 10/31 Adjust VDD above VDDon startup threshold before setting to 14 V. DocID15028 Rev 6 VIPER28 5 Typical electrical characteristics Typical electrical characteristics Figure 6. IDlim vs. TJ Figure 7. FOSC vs. TJ IDLIM/(IDLIM@25C) AM13881V1 $09 Figure 8. VDRAIN_START vs. TJ Figure 9. IDD0 vs. TJ 9'5$,1B67$57 9'5$,1B67$57#& $09 $09 Figure 10. IDD1 vs. TJ Figure 11. Main FET RDSON vs. TJ $09 DocID15028 Rev 6 $09 11/31 31 Typical electrical characteristics VIPER28 Figure 12. Main FET VBVDSS vs. TJ Figure 13. IDlim vs. RLIM / >/D />/D Z>/D $09 Z>/D $09 Figure 14. Thermal shutdown 9'' 9'' RQ 9'' RII 9'' 5 (6 7 $5 7 WLPH ,'5 $,1 WLPH 776 ' 76 ' 7+<67 1RUPDORSHUDWLRQ 6KXWGRZQDIWHURYHUWHPSHUDWXUH 1RUPDORSHUDWLRQ WLPH $09 12/31 DocID15028 Rev 6 VIPER28 6 Typical circuit Typical circuit Figure 15. Basic flyback application 7 9,1'& a$& ,QSXWYROWDJH &&/ &,1 '287 5&/ &287 '&RXWSXWYROWDJH '&/ '5$,1 5$8; &217 3:0 &RQWUROOHU (37 '$8; 9'' 9,3HU )% 5 5 *1' &)% &9'' 5 5 & 5 $09 Figure 16. Full-featured flyback application 7 9,1'& a$& ,QSXWYROWDJH &&/ &,1 '287 5&/ &287 '&RXWSXWYROWDJH '&/ '293 5293 '5$,1 &217 3:0 &RQWUROOHU (37 5/,0 )% &(37 '$8; 9'' 9,3HU 5 5$8; 5 *1' &)% &9'' 5 5 (37 &(37 VHWWKHH[WUDSRZHUWLPHU &217 5/,0 UHGXFHVWKH2&3WKUHVKROG ,'/,0 52935/,0 VHWWKHRXWSXWRYHUYROWDJHSURWHFWLRQ DocID15028 Rev 6 & 5 $09 13/31 31 Operation 7 VIPER28 Operation The device is a high-performance low-voltage PWM controller chip with an 800 V, avalanche rugged power section. The controller includes the oscillator with jitter, startup circuit with soft-start, PWM logic, current limiting circuit with adjustable setpoint, second overcurrent circuit, burst mode management, Extra Power Timer circuit, UVLO circuit, auto-restart circuit and thermal protection circuit. The current limit setpoint is set by the CONT pin. Burst mode operation guarantees high performance in standby mode and contributes to meeting energy-saving standards. All the fault protections are built in auto-restart mode with very low repetition rate to prevent the IC from overheating. 7.1 Power section and gate driver The power section is implemented with an avalanche-rugged N-channel MOSFET, which guarantees safe operation within the specified energy rating as well as high dv/dt capability. The power section has a BVDSS of 800 V min. and a maximum RDS(on) of 7 at 25 C. The integrated SenseFET structure allows a virtually loss-less current sensing. The gate driver is designed to supply a controlled gate current during both turn-on and turnoff in order to minimize common-mode EMI. Under UVLO conditions an internal pull-down circuit holds the gate low in order to ensure that the power section cannot be turned on accidentally. 7.2 High-voltage startup generator The HV current generator is supplied through the DRAIN pin and it is enabled only if the input bulk capacitor voltage is higher than the VDRAIN_START threshold, 80 V DC typically. When the HV current generator is ON, the IDDch1 current (3 mA typical value) is delivered to the capacitor on the VDD pin. During auto-restart mode after a fault event, the current is reduced to IDDch2 (0.6 mA, typ) in order to have a slow duty cycle during the restart phase. 7.3 Power-up and soft startup When the input voltage rises to the device start threshold, VDRAIN_START, the VDD voltage begins to grow due to the IDDch1 current (see Table 8: Supply section) coming from the internal high-voltage startup circuit. If the VDD voltage reaches the VDDon threshold, the power MOSFET starts switching and the HV current generator is turned OFF. The IC is powered by the energy stored in the capacitor on the VDD pin, CVDD, until the selfsupply circuit (typically an auxiliary winding of the transformer and a steering diode) develops a voltage high enough to sustain the operation. The CVDD capacitor must be correctly sized to avoid fast discharge and keep the required voltage higher than the VDDoff threshold. In fact, an insufficient capacitance value could terminate the switching operation before the controller receives any energy from the auxiliary winding. 14/31 DocID15028 Rev 6 VIPER28 Operation The following formula can be used for the CVDD capacitor calculation: Equation 1 I DDch1 x t SSaux C VDD = ----------------------------------------V DDon - V DDoff The parameter tSSaux is the time needed for the steady state of the auxiliary voltage. This time represents an estimate of the user's application according to the output stage configurations (transformer, output capacitances, etc.). During the converter startup time, the drain current limitation is progressively increased to the maximum value. In this way the stress on the secondary diode is considerably reduced. It also helps to prevent transformer saturation. The soft-start time lasts 8.5 ms and the feature is implemented for every attempt of the startup converter or after a fault. Figure 17. IDD current during startup and burst mode 9'' 9''RQ 9''RII W 9)% 9)%ROS 9)%OLQ 9)%EPK\V 9)%EP ,'5$,1 W W66 ,'B%0 ,'' W ,'' ,'' W ,''FK 67$57 83 %856702'( 1250$/02'( 1250$/02'( $09 DocID15028 Rev 6 15/31 31 Operation VIPER28 Figure 18. Timing diagram: normal power-up and power-down sequences 9 ,1 9,19'5$,1B67$57 +9VWDUWXSLVQRPRUHDFWLYDWHG 9 '5$,1B67$57 9 '' 9 ''RQ UHJXODWLRQLVORVWKHUH WLPH 9 ''RII 9 '' 5(67$57 WLPH , ''FK ,''FK WLPH 9 '5$,1 3RZHU RQ 3RZHURII 1RUPDORSHUDWLRQ WLPH $09 Figure 19. Soft-start: timing diagram ,'5$,1 ,'/,0 W 66 VRIWVWDUW W 9)% W 2/3GHOD\ 9)%ROS 9)%OLQ 9287 W 5HJXODWHGYDOXH W $09 16/31 DocID15028 Rev 6 VIPER28 7.4 Operation Power-down At converter power-down, the system loses its ability to regulate as soon as the decreasing input voltage is low enough for the peak current limitation to be reached. The VDD voltage drops and when it falls below the VDDoff threshold (see Table 8: Supply section) the power MOSFET is switched OFF, the energy transfers to the IC is interrupted and, consequently, the VDD voltage decreases (Table 19: Soft-start: timing diagram), the startup sequence is inhibited and the power-down is completed. This feature is useful as it prevents the converter from attempting a restart and ensures monotonic output voltage decay during system power-down. 7.5 Auto-restart Every time a protection is tripped, the IC is automatically restarted after a duration that depends on the discharge and recharge of the CVDD capacitor. As shown in Figure 20, after a fault the IC is stopped and, consequently, the VDD voltage decreases because of the IC's consumption. As soon as the VDD voltage falls below the threshold VDD(RESTART) and if the DC input voltage is higher than VDRAIN_START threshold, the internal HV current source is turned ON and it starts to charge the CVDD capacitor with the current IDDch2 (0.6 mA, typ). As soon as the VDD voltage reaches the threshold VDD(ON), the IC restarts. Figure 20. Timing diagram: behavior after short-circuit 9 '' 9 ''RQ 6KRUWFLUFXLWRFFXUVKHUH 9 ''RII 9 '' 5 ( 6 7 $5 7 9 )% 9 ) % ROS 9 ) % OLQ WLPH W5(67$57 , '5 $,1 WLPH ''FK ,''FK WLPH ,''FK WLPH $09 DocID15028 Rev 6 17/31 31 Operation 7.6 VIPER28 Oscillator The switching frequency is internally fixed to 60 kHz or 115 kHz. In both cases the switching frequency is modulated by approximately 4 kHz (60 kHz version) or 8 kHz (115 kHz version) at 250 Hz (typical) rate, so that the resulting spread-spectrum action distributes the energy of each harmonic of the switching frequency over a number of side-band harmonics having the same energy on the whole, but smaller amplitudes. 7.7 Current mode conversion with adjustable current limit setpoint The device is a current mode converter. The drain current is sensed and converted to voltage that is applied to the non-inverting pin of the PWM comparator. This voltage is compared with the one on the feedback pin through a voltage divider on a cycle-by-cycle basis. The device has a default current limit value, IDlim, that can be adjusted according to the electrical specification, by the RLIM resistor connected to the CONT pin. The CONT pin has a minimum current sunk needed to activate the IDlim adjustment. Without RLIM or with high RLIM (i.e. 100 k) the current limit is set to the default value (see IDlim, Table 9: Controller section). 7.8 Overvoltage protection (OVP) The device has integrated logic for the monitoring of the output voltage using as an input signal the voltage VCONT during the OFF time of the power MOSFET. This is the time when the voltage from the auxiliary winding tracks the output voltage, through the turn ratio. The CONT pin has to be connected to the auxiliary winding through the diode DOVP and the resistors ROVP and RLIM as shown in Figure 22: CONT pin configuration. When, during the OFF time, the voltage VCONT exceeds four consecutive times the reference voltage VOVP (see Table 9: Controller section), the overvoltage protection will stop the power MOSFET and the converter enters auto-restart mode. In order to bypass the noise immediately after the turn-off of the power MOSFET, the voltage VCONT is sampled inside a short window after the time TSTROBE, see Table 9: Controller section and the Figure 21: OVP timing diagram. The sampled signal, if higher than VOVP, triggers the internal OVP digital signal and increments the internal counter. The same counter is reset every time the signal OVP is not triggered in one oscillator cycle. Referring to Figure 22: CONT pin configuration, the resistor divider ratio kOVP will be given by: Equation 2 V OVP k OVP = --------------------------------------------------------------------------------------------------N AUX -------------- ( V OUTOVP + VDSEC ) - V DAUX N SEC 18/31 DocID15028 Rev 6 VIPER28 Operation Equation 3 R LIM k OVP = ---------------------------------R LIM + R OVP Where: * VOVP is the OVP threshold (see Table 9: Controller section) * VOUT OVP is the converter output voltage value to activate the OVP set by the designer * NAUX is the number of the auxiliary winding turns * NSEC is the number of the secondary winding turns * VDSEC is the secondary diode forward voltage * VDAUX is the auxiliary diode forward voltage * ROVP together with RLIM constitute the output voltage divider Then, fixing RLIM according to the desired IDlim, the ROVP can be calculated by: Equation 4 1 - k OVP R OVP = R LIM x ----------------------k OVP The resistor values will be such that the current sourced and sunk by the CONT pin are within the rated capability of the internal clamp. Figure 21. OVP timing diagram 9'6 9$8; W 9&217 W 9 293 W 76752%( 6752%( 4BNQMJOHUJNF W 293 W &2817(5 5(6(7 &2817(5 67$786 W o o o )$8/7 o o o o W 1250$/23(5$7,21 7(0325$5<',6785%$1&( )(('%$&./223)$,/85( W $09 DocID15028 Rev 6 19/31 31 Operation 7.9 VIPER28 About CONT pin Referring to Figure 22, the CONT pin is used to configure the: 1. reduction of the OCP setpoint (IDlim) 2. output overvoltage protection (OVP) Table 10 lists the external components needed to activate one or more of the CONT pin functions. Figure 22. CONT pin configuration 7 5 /,0UHGXFHVWKH2&3WKUHVKROG , '/,0 5293 5 /,0VHWWKHRXWSXWRYHUYROWDJHSURWHFWLRQ ' $8; I URP6HQVH)(7 62)7 67$57 5293 W R*$7('5,9(5 &217 ,'/,0 2&3 &203$5$725 5/,0 293 /2*,& W R*$7('5,9(5 $09 Table 10. CONT pin configurations Function / component RLIM ROVP DAUX IDlim reduction See Figure 13 No No OVP 80 k See Equation 4 Yes IDlim reduction and OVP(1) See Figure 13 See Equation 4 Yes 1. Select RLIM then ROVP. 7.10 Feedback and overload protection (OLP) The device is a current-mode converter. The feedback pin controls PWM operation as well as burst mode and activates the overload protection. Figure 23: FB pin configuration (option 1) and Figure 24: FB pin configuration (option 2) show the internal current-mode structure. With the feedback pin voltage between VFBbm and VFBlin, (see Table 9: Controller section) the drain current is sensed and converted to voltage that is applied to the non-inverting pin of the PWM comparator. This voltage is compared to the voltage on the feedback pin through a voltage divider on a cycle-by-cycle basis. When these two voltages are equal, the PWM logic orders the switchoff of the power MOSFET. The drain current is always limited to the value of IDlim. 20/31 DocID15028 Rev 6 VIPER28 Operation When the feedback pin voltage reaches the threshold VFBlin, an internal current generator starts to charge the feedback capacitor (CFB) and when the feedback voltage reaches the VFBolp threshold, the converter is turned off and the automatic restart is activated. During startup, when the output voltage is still low, if the feedback network is not properly dimensioned, the feedback voltage could rise up to the overload threshold (VFBolp) generating the switching off of the IC itself. Taking into account that the feedback network also fixes the loop stability, two options can be considered for this network. The time from the overload detection (VFB = VFBlin) to the device shutdown (VFB = VFBolp) must be set by CFB (or CFB1) using the formula: Equation 5 V FBolp - V FBlin T OLP - delay = C FB x ---------------------------------------I FB2 In the option 1 shown in Figure 23: FB pin configuration (option 1), the capacitor CFB has a dual function: guaranteeing the loop compensation and fixing the overload delay time as calculated in Equation 5. Owing to the above considerations, the OLP delay time must be long enough to bypass the initial output voltage transient and check the overload condition only when the output voltage is in steady state. The output transient time depends on the value of the output capacitor and on the load. When the value of the CFB capacitor calculated for the loop stability is too low and cannot ensure enough OLP delay, an alternative compensation network can be used and it is shown in Figure 24: FB pin configuration (option 2). Using this alternative compensation network, two poles (fPFB, fPFB1) and one zero (fZFB) are introduced by the capacitors CFB and CFB1 and the resistor RFB1. The capacitor CFB introduces a pole (fPFB) at higher frequency than fZB and fPFB1. This pole is usually used to compensate the high-frequency zero due to the ESR (equivalent series resistor) of the output capacitance of the flyback converter. The mathematical expressions of these poles and zero frequency are: 1 f ZFB = ----------------------------------------------2 C FB1 R FB1 Equation 6 R FB ( DYN ) + R FB1 f PFB = ------------------------------------------------------------------------------2 C FB ( R FB ( DYN ) RFB1 ) Equation 7 fPFB 1 = 1 2 C FB 1 R FB 1 + R FB ( DYN ( ) ) The RFB(DYN) is the dynamic resistance seen by the FB pin. DocID15028 Rev 6 21/31 31 Operation VIPER28 The CFB1 capacitor fixes the OLP delay and usually CFB1 results in a much higher value than CFB. Equation 5 can be still used to calculate the OLP delay, but CFB1 has to be considered instead of CFB. Using the compensation network shown in option 2, in all cases the loop stability can be set as well as a sufficient OLP delay. Figure 23. FB pin configuration (option 1) & )%IL[HVWKHRYHUORDGGHOD\ DQGVHWWKHORRSFRPSHQVDWLRQ %XUVW0RGH I URP6HQVH)(7 W R*$7( '5,9(5 26&,//$725 3:0 )% 7851 21/2*,& 3:0&75/ &)% 7851 2)) 2/3 /2*,& 9 )%ROS $09 Figure 24. FB pin configuration (option 2) & )%IL[HVWKHRYHUORDGGHOD\ & )% VHWWKHORRSFRPSHQVDWLRQ IURP6HQVH)(7 %XUVW0RGH 3:0 )% 3:0&75/ 5)% 26&,//$725 7851 21/2*,& W R*$7( '5,9(5 &)% &)% 2/3 7851 2)) /2*,& 9 )%ROS $09 22/31 DocID15028 Rev 6 VIPER28 7.11 Operation Burst-mode operation at no load or very light load When the load decreases, the feedback loop reacts by lowering the feedback pin voltage. If it falls below the burst mode threshold, VFBbm, the power MOSFET is no longer allowed to be switched on. After the MOSFET stops, the feedback pin voltage increases and when it exceeds the level, VFBbm + VFBbmhys, the power MOSFET starts switching again. The burst mode thresholds are provided in Table 9: Controller section and Figure 25: Burst mode timing diagram, light load shows this behavior. The system alternates between a period of time where the power MOSFET is switching to a period of time where the power MOSFET is not switching. This mode of operation is the burst mode. The advantage of burst mode operation is an average switching frequency much lower than the normal operation frequency, up to several hundred hertz, minimizing all frequency-related losses. In order to prevent audible noise, during burst mode the drain current peak is clamped to the level, ID_BM, given in Table 9: Controller section. Figure 25. Burst mode timing diagram, light load 9 )% 9 )%EP9 )%EPK\V 9 )%EP WLPH , '' , '' , '' WLPH , '5$,1 , 'B%0 WLPH %XUVW0RGH $09 DocID15028 Rev 6 23/31 31 Operation 7.12 VIPER28 Extra power timer (EPT) The extra power timer feature allows the setting of a blanking time inside which an overload current can be admitted. The timer is set through a capacitor (CEPT) connected to the EPT pin. Its duration is in the range of a few seconds and is limited by thermal constraints. The extra power timer (EPT) is started as soon as the drain current reaches the threshold IDLIM_EPT (typ. 85% of IDlim) and its duration is defined by the time needed to charge the capacitor CEPT up to the value VEPT(STOP) (4V, typ). The charging current is IEPT (5 uA, typ). If the EPT starts, the IC sustains the overload and continues to operate normally if the drain current falls below the threshold IDLIM_EPT (85% of IDlim) before the EPT voltage reaches the value VEPT(STOP). The capacitor CEPT is discharged through the current IEPT (5 uA, typ) and the next EPT is inhibited until the EPT voltage is higher than VEPT(RESTART) (0.6 V, typ). If the EPT starts and the EPT voltage reaches the value VEPT(STOP), the IC stops and it is automatically restarted. The CVDD capacitor is then discharged down to the value VDD(RESTART) (4.5 V, typ) and is recharged, through the HV current source, up to the value VDDon (14 V, typ). Also in this case the capacitor CEPT is discharged through the IEPT current. See Figure 26 and Table 8: Supply section. The EPT pin has to be connected to GND if the function is not used. Figure 26. EPT timing diagram ,'5 $,1 2YHUORDGUHFRYHUHG ZLWKRXWLQWHUUXSWLRQ RIRSHUDWLRQV ,'OLP ,'/,0B( 3 7 ,& V KXWGRZQ 9( 3 7 9( 3 7 9( 3 7 ( [WUD3 RZHU7 LPHU ,& UHV WDUWV LQV RIWV WDUW W 6 723 5 (6 7$5 7 W ,( 3 7 W 9'' 9'' 9'' 21 5 (6 7$5 7 W $09 24/31 DocID15028 Rev 6 VIPER28 7.13 Operation 2nd level overcurrent protection and hiccup mode The device is protected against short-circuit of the secondary rectifier, short-circuit on the secondary winding or a hard-saturation of the flyback transformer. This type of anomalous condition is invoked when the drain current exceeds the threshold IDMAX, see Table 9: Controller section. To distinguish a real malfunction from a disturbance (e.g. induced during ESD tests) a "warning state" is entered after the first signal is tripped. If, in the subsequent switching cycles, the signal is not tripped, a temporary disturbance is assumed and the protection logic will be reset in its idle state; otherwise if the IDMAX threshold is exceeded for two consecutive switching cycles, a real malfunction is assumed and the power MOSFET is turned OFF. The shutdown condition is latched as long as the device is supplied. While it is disabled, no energy is transferred from the auxiliary winding, hence the voltage on the CVDD capacitor decays until the VDD undervoltage threshold (VDDoff), which clears the latch. The startup HV current generator is still off, until the VDD voltage falls below its restart voltage, VDD(RESTART). After this condition the CVDD capacitor is charged again by the IDDch2 current, and the converter switching restarts if VDDon occurs. If the fault condition is not removed, the device enters auto-restart mode. This behavior results in a low-frequency intermittent operation (hiccup-mode operation), with very low stress on the power circuit. DocID15028 Rev 6 25/31 31 Package mechanical data 8 VIPER28 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 8.1 DIP-7 package information Figure 27. DIP-7 package outline 26/31 DocID15028 Rev 6 VIPER28 Package mechanical data Table 11. DIP-7 mechanical data mm Dim. Typ Min A 5,33 A1 0,38 A2 3,30 2,92 4,95 b 0,46 0,36 0,56 b2 1,52 1,14 1,78 c 0,25 0,20 0,36 D 9,27 9,02 10,16 E 7,87 7,62 8,26 E1 6,35 6,10 7,11 e 2,54 eA 7,62 eB L M (6)(8) N 10,92 3,30 (7)(8) 2,92 3,81 0,40 0,60 2,508 0,50 N1 O Max 0,60 0,548 DocID15028 Rev 6 27/31 31 Package mechanical data 8.2 VIPER28 SO16 narrow package information Figure 28. SO16 narrow package outline 28/31 DocID15028 Rev 6 VIPER28 Package mechanical data Table 12. SO16 narrow mechanical data mm Dim. Min. Typ. A Max. 1.75 A1 0.1 A2 1.25 b 0.31 0.51 c 0.17 0.25 D 9.8 9.9 10 E 5.8 6 6.2 E1 3.8 3.9 4 e 0.25 1.27 h 0.25 0.5 L 0.4 1.27 k 0 8 ccc 0.1 DocID15028 Rev 6 29/31 31 Revision history 9 VIPER28 Revision history Table 13. Document revision history 30/31 Date Revision Changes 30-Sep-2008 1 Initial release 22-Jan-2009 2 Updated Figure 3 on page 4 21-Oct-2009 3 Added SO16N and SDIP10 packages 31-Aug-2010 4 Updated Figure 3, Figure 4, Figure 5 on page 10 and Table 3 on page 6 08-Jan-2013 5 Minor text changes to improve readability in Chapter 7.3, Chapter 7.4, Chapter 7.5, Chapter 7.7, Chapter 7.8, Chapter 7.9, Chapter 7.10, Chapter 7.11, Chapter 7.13, in Table 8 on page 8, Table 9 on page 9 and in Figure 21 on page 19 16-Dec-2014 6 Updated title in cover page. Removed SDIP10 package. Content reworked to improve readability. DocID15028 Rev 6 VIPER28 IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2014 STMicroelectronics - All rights reserved DocID15028 Rev 6 31/31 31