40
TM
Features
• Provides Direct Control of Up to 7 Input and 7 Output
Devices When used with a CDP1800-Series Micropro-
cessor
• CHIP ENABLE (CE) Allows Easy Expansion for Multi-
level I /O Systems
Description
The CDP1853/3 and CDP1853C/3 are high-reliability 1 of 8
decoders designed for use in general purpose m icroproces-
sor systems. These devices, which are functionally identical ,
are specifically designed for use as gated N-bit decoders
and interface directly with the 1800-Series microprocessors
without additional components. The CDP1853/3 has a rec-
ommended operating voltage range of 4V to 10.5V, and the
CDP1853C/3 has a recommended operating voltage range
of 4V to 6.5V .
When CHIP EN ABL E (CE ) is high, the selecte d output will be
true (high) from the trailing edge of CLOCK A (high-to-low
transition) to the trailing edge of CLOCK B (high-to-low
transition). All outputs will be low when the device is not
selected (CE = 0) and during conditions of CLOCK A and
CLO CK B as shown in Figure 2. The CDP1 853/3 inp uts N0,
N1, N2, CLOCK A, and CLOCK B are connected to 1800-
series microprocessor outputs N0, N1, N2, TPA, and TPB
respectively, when used to decode I/O commands as shown
in Figure 5. The CHIP ENABLE (CE) input provides the capa-
bility for multiple levels of decoding as shown in Figure 6.
The CDP1853/3 can also be used as a general purpose 1 of
8 decoder for I/O and memory system applications as shown
in Figure 4.
Pinout
16 LEAD SBDIP
TOP VIEW
Ordering Information
PACKAGE TEMP. RANGE 5V 10V PKG.
NO.
SBDIP -55oC to +125oC CDP1853CD3 - D16.3
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
CLK A
N0
N1
OUT 0
OUT 1
OUT 2
VSS
OUT 3
VDD
N2
CE
OUT 4
OUT 5
OUT 6
OUT 7
CLK B
March 1997
Fil e Num ber 1713.2
CDP1853C/3
High- Rel iab ilit y CMO S N-Bit 1 of 8 Decoder
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001. All Rights Reserved
41
CDP1853/3 Functional Diagram
FIGURE 1.
TRUTH TABLE
NOTES:
1. 1 = High level, 0 = Low level, X = Don’t care.
2. Qn-1 = Enable remains in previous st ate.
QN
4
5
6
7
12
11
10
9
1 OF 8
DECODER
OUT 0
OUT 1
OUT 2
OUT 3
OUT 4
OUT 5
OUT 6
OUT 7
2
3
14
N0
N1
N2
13
CE
1
15
CLOCK
A
CLOCK
B
(TPA)
(TPB)
EN
CE CL A CL B EN
1 0 0 Qn-1(Note 2)
1011
1100
1111
0XX0
N2 N1 N0 EN 01234567
000110000000
001101000000
010100100000
011100010000
100100001000
101100000100
110100000010
111100000001
X X X 0 00000000
CDP1853/3, CDP1853C/3
42
Static Electrical Sp ecification s
PARAMETER SYMBOL
CONDITIONS LIMITS
UNITS
VO
(V) VIN
(V) VDD
(V)
-55oC, +25oC+125
oC
MIN MAX MIN MAX
Quiescent Device
Current ISS
(Note 1) - 0, 5 5 -50 - -100 - µA
- 0, 10 10 -500 - -1000 - µA
Output Low Drive
(Sink) Current IOL 0.4 - 5 2.3 - 1.6 - mA
0.5 - 10 3.7 - 2.6 - mA
Output High Drive
(Source) Current IOH 4.6 - 5 - -1.7 - -1.2 mA
9.5 - 10 - -3.7 - -2.6 mA
Output Voltage
Low-Level VOL
(Note 2) - 0, 5 5 - 0.1 - 0 .2 V
- 0, 10 1 0 - 0.1 - 0.2 V
Output Voltage
High-Level VOH
(Note 2) - 0, 5 5 4.9 - 4.8 - V
- 0, 10 10 9. 9 - 9.8 - V
Input Low Voltage VIL 0. 8, 4. 2 - 5 - 1 .5 - 1.5 V
1, 9 - 10 - 3 - 3 V
Input High Voltage VIH 0.8, 4.2 - 5 3 .5 - 3.5 - V
1, 9 - 10 7 - 7 - V
I np ut Le ak age Lo w IIL -05-1--5-µA
-010-1--5-µA
I np ut Le ak age H ig h I IH -55-1-5µA
-1010- 1 - 5µA
Input Capacitance CIN (Note 2)----10-10pF
Output Capacitance COUT (Note 2)----15-15pF
NOTES:
1. The C DP1853C m eets all 5V static electrical character ist ics of the CDP1853 except quiescent device current for w hich the limits are:
ISS = -500µA at -55oC and +25oC an d ISS = -1000µA at +1 25 oC.
2. Gua ran teed but n ot tested .
Dynamic Elec trical Specifications See Figure 2, CL = 100p F, tR, tF = 15ns
PARAMETER SYMBOL VDD
(V)
LIMITS
UNITS
-55oC, +25oC+125
oC
MIN MAX MIN MAX
Propagation Delay Time: tEOH 5 - 175 - 275 ns
Chip Enable (CE) to Output High 10 - 90 - 150 ns
CDP1853/3, CDP1853C/3
43
Di sa ble to Out p ut Low tEOL 5 - 295 - 400 ns
10 - 200 - 250 ns
N Input to Output tNO 5 - 225 - 315 ns
10 - 120 - 165 ns
Clock A to Output Low tAO 5 - 210 - 300 ns
10 - 110 - 150 ns
Clock B to Output Low tBO 5 - 295 - 400 ns
10 - 200 - 250 ns
Pulse W idt h: tCACA 550-75- ns
Clock A 10 25 - 50 - ns
Clock B tCBCB 550-75- ns
10 25 - 50 - ns
Recom mend ed Operati ng Conditions At TA = Full Package Temperature Ran ge. For maximum reli ability, operating condi-
tions should be selected so that operation is always within the following ranges:
PARAMETER
LIMITS
UNITS
CDP1853/3 CDP1853C/3
MIN MAX MIN MAX
DC Operating Volta ge Range 4 10.5 4 6.5 V
Input voltage Range VSS VDD VSS VDD V
Dynamic Elec trical Specifications See Figure 2, CL = 100p F, tR, tF = 15ns
PARAMETER SYMBOL VDD
(V)
LIMITS
UNITS
-55oC, +25oC+125
oC
MIN MAX MIN MAX
CDP1853/3, CDP1853C/3
44
Absolute Maximum Ratings Thermal Information
DC Supply Voltage Range, (VDD)
(All Voltages Referenced to VSS Terminal)
CDP1853/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1853C/3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . ±10mA
Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W)
SBDIP Package. . . . . . . . . . . . . . . . . . 85 22
Device D issi pation Per Output Transi sto r
TA = Full Package Temperature Ran ge
(All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW
Operating Temperature Range (TA)
Package Type D . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC
Sto r ag e Te mperat u re R an ge (T STG) . . . . . . . . . . .-65oC to +150oC
Lead Temperature (During Soldering)
At distance 1/16 ± 1/32 In. (1.59 ± 0.79mm)
from case for 10s max. . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
Timing Diagrams
FIGURE 2A. N - INPUTS TO OUTPUTS DELAY TIME FIGURE 2B. CE TO OUTPUT DELAY TIME
FIGURE 2C. CLOCK B TO OUTPUT DELAY TIME
NOTE:
1. To measure TAO, Clock B must be tied low.
FIGURE 2D. CLOCK A TO OUTPUT DELAY TIME
FIGURE 2. PROPAGATION DELAY TIME DIAGRAMS
NOTE:
1. Output enabled when EN = high. Internal signal shown for refer-
ence only (see Figure 1).
FIGURE 3. TI MING DIAGRAM FIGURE 4. N-BIT DECODER USED AS A 1 OF 8 DECODER
N0 - N2
OUTPUT 0 - 7
TN0
CE
OUTPUT 0 - 7
TEOH TEOL
MIN. CLOCK B
OUTPUT 0 - 7 TBO
CLOCK B
PULSE WIDTH TCBCB
TAO
CLOCK A
OUTPUT 0 - 7
MIN. CLOCK A
PULSE WIDTH TCACA
(SEE NOTE 1)
TPA
TPB
CE
EN
OUTPUT
(NOTE 1)
A
B
C
CHIP ENABLE
VDD
CLK A
N0
N1
OUT 0
OUT 1
OUT 2
OUT 3N2
CE OUT 4
OUT 5
OUT 6
OUT 7
CLK B
CDP1853/3, CDP1853C/3
45
FIGURE 5. N-BIT DECODER IN A ONE LEVEL I/O SYSTEM
CS1
CDP1802 CPU
TPA TPB N0 N1 N2 TPB MRD
CLOCK A CLOCK B CE N0 N1 N2
CDP1853
012 - 67
CS2
CDP1852
INPUT
PORT 7
MODE
CS1 CS2
CDP1852
OUTPUT
PORT 7
SR
MODE TPB
VDD
READ VIA
6F INSTRUCTION
STROBE
DATA
STROBE
DATA BUS
DATA
LOAD VIA
CS2
5 CDP1852 INPUT AND OUTPUT PORTS
VDD
67 INSTRUCTION
LOAD VIA
61 INSTRUCTION
CDP1852
DATA
CS1
OUTPUT
PORT 1
READ VIA
69 INSTRUCTION
DATA
AVAILABLE
CLOCK
AVAILABLE
CS1 CS2
CDP1852
INPUT
PORT 1
CLOCK
MODE MODE
SR TPB
VDD
7 OUTPUT PORTS 7 INPUT PORTS
CDP1853/3, CDP1853C/3
46
All Intersil U.S. pro ducts are manufactured, assem bled and tested utilizing ISO9000 qualit y systems.
Intersil Corporati on’s quali ty certifi cations can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsi diaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For informat ion regarding Int ersil Corporation and its products, see www.i ntersil.com
Bias/Static Burn-In Circuit
NOTE:
1. All resistor s are 47kΩ ±20%.
NOTE:
1. System shown will select up to 56 input and 48 output ports. With additional decoding, the total number of input and output ports can be
further expanded. FIGURE 6. TWO LEVEL I/O USING CDP1853 AND CDP1852
CDP1800 SERIES
N0 N1 N2
TPA
TPB MRDBUS
1
CDP1853
DECODED
“61” INSTRUCTION
DATA BUS
NO, N1, N2
CL CDP1852
CS2
CLOCK A
CLOCK B
CE
CDP1853
“62 - 6F”
INST.
I/O
7 INP UT,
6 OUTP UT
PORTS
CLOCK A
CLOCK B
CE
CDP1853
“62 - 6F”
INST.
I/O
7 INP UT,
6 OUTP UT
PORTS
NO, N1, N2
NO, N1, N2
I/O
7 INPUT,
6 OUTPUT
PORTS
CE
CLOCK A
CLOCK B
CDP1853
“62 - 6F”
INST.
SECTIONS 3 - 7
TPA
CS1
VDD
VSS
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8VDD
VDD
VSS
TYPE VDD TEMPERATURE TIME
CDP1853C 7V +125oC160 Hrs.
CDP1853/3, CDP1853C/3
