fax id: 1111 PRELIMINARY CY7C1345 128K x 36 Synchronous Flow-Through 3.3V Cache RAM Features Functional Description * Supports 117-MHz microprocessor cache systems with zero wait states * 128K by 36 common I/O * Low Standby Power (1.65 mW, L version) * Fast clock-to-output times -- 7.5 ns (117-MHz version) * Two-bit wrap-around counter supporting either interleaved or linear burst sequence * Separate processor and controller address strobes provide direct interface with the processor and external cache controller * Synchronous self-timed write * Asynchronous output enable * 3.3V I/Os * JEDEC-standard pinout * 100-pin TQFP packaging * ZZ "sleep" mode Logic Block Diagram GW The CY7C1345 allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the processor address strobe (ADSP) or the cache controller address strobe (ADSC) inputs. Address advancement is controlled by the address advancement (ADV) input. A synchronous self-timed write mechanism is provided to simplify the write interface. A synchronous chip enable input and an asynchronous output enable input provide easy control for bank selection and output three-state control. MODE (A0,A1) 2 BURST Q0 CE COUNTER Q1 CLR CLK ADV ADSC ADSP A[16:0] The CY7C1345 is a 3.3V 128K by 36 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. Q 17 15 ADDRESS CE REGISTER D 15 17 128K X 36 MEMORY ARRAY DDQ[31:24],DP3Q BYTEWRITE REGISTERS BWE BWS3 BWS 2 DDQ[23:16],DP2Q BYTEWRITE REGISTERS BWS 1 D DQ[15:8],DP1 Q BYTEWRITE REGISTERS D DQ[7:0],DP0 Q BYTEWRITE REGISTERS BWS 0 CE1 CE2 CE3 36 36 D ENABLE Q CE REGISTER CLK INPUT REGISTERS CLK OE SLEEP CONTROL ZZ DQ[31:0] DP[3:0] Selection Guide 7C1345-117 7C1345-100 7C1345-90 7C1345-50 Maximum Access Time (ns) 7.5 8.0 8.5 11.0 Maximum Operating Current (mA) 350 325 300 250 Maximum Standby Current (mA) 2.0 2.0 2.0 2.0 Pentium is a registered trademark of Intel Corporation. Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 August 24, 1998 PRELIMINARY CY7C1345 Pin Configuration A8 A9 81 82 ADSP ADV 83 84 BWE GW CLK VSS OE ADSC 85 86 87 88 89 CE3 BWS0 BWS1 BWS2 BWS3 CE2 CE1 VDD 90 91 92 93 94 95 96 97 A7 DQ7 62 DQ6 VSSQ 20 21 61 60 VDDQ VSSQ DQ26 22 59 DQ5 DQ27 DQ28 DQ29 23 24 58 57 25 56 DQ4 DQ3 DQ2 VSSQ VDDQ DQ30 26 27 55 54 28 53 DQ31 29 30 52 51 DP3 50 63 19 49 18 DQ25 VDDQ A16 DQ24 48 VDD ZZ 47 65 64 A14 A15 VSS A13 66 16 17 46 15 A12 VDD NC DQ8 VSS NC 45 DQ9 68 67 2 44 69 13 14 43 12 DQ23 VSSQ 42 DQ22 DNU DNU A10 A11 VSSQ VDDQ 41 DQ10 71 70 VDD 72 10 11 40 9 VSSQ VDDQ VSS DQ21 39 DQ12 DQ11 38 73 DNU DNU 8 37 DQ20 A0 75 74 36 6 7 A1 DQ19 35 76 A2 5 34 DQ15 DQ14 A3 78 77 VSSQ DQ18 BYTE3 98 3 4 33 79 DQ17 A4 DP1 32 80 2 31 1 MODE A5 DP2 DQ16 VDDQ BYTE2 99 100 A6 100-Lead TQFP VDDQ VSSQ DQ13 VSSQ VDDQ DQ1 DQ0 DP0 BYTE1 BYTE0 PRELIMINARY CY7C1345 Pin Descriptions TQFP Pin Number Name I/O Description 85 ADSC InputSynchronous Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[15:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. 84 ADSP InputSynchronous Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A[15:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. 36, 37 A[1:0] InputSynchronous A1, A0 Address Inputs. These inputs feed the on-chip burst counter as the LSBs as well as being used to access a particular memory location in the memory array. 49 -44, 81-82, 99-100, 32-35 A[16:2] InputSynchronous Address Inputs used in conjunction with A [1:0] to select one of the 64K address locations. Sampled at the rising edge of the CLK, if CE1, CE2, and CE3 are sampled active, and ADSP or ADSC is active LOW. 96-93 BW[3:0] InputSynchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes. Sampled on the rising edge. BW0 controls DQ [7:0] and DP0, BW1 controls DQ[15:8] and DP1, BW2 controls DQ[23:16] and DP2, and BW3 controls DQ [31:24] and DP3. See Write Cycle Descriptions table for furthere details. 83 ADV InputSynchronous Advance Input used to advance the on-chip address counter. When LOW the internal burst counter is advanced in a burst sequence. The burst sequence is selected using the MODE input. 87 BWE InputSynchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. 88 GW InputSynchronous Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is used to conduct a global write, independent of the state of BWE and BW[3:0]. Global writes override byte writes. 89 CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. 98 CE1 InputSynchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. CE1 gates ADSP. 97 CE2 InputSynchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. 92 CE3 InputSynchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. 86 OE InputAsynchronous Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. 64 ZZ InputAsynchronous Snooze input. Active HIGH asynchronous. When HIGH, the device enters a low-power standby mode in which all other inputs are ignored, but the data in the memory array is maintained.Leaving ZZ floating or NC will default the device into an active state. 31 MODE - Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. When left floating or NC, defaults to interleaved burst order. 30-28, 25-22, 19-18, 13-12, 9-6, 3-1, 80-78, 75-72, 69-68, 63-62, 59-56, 53-51 DQ [31:0], DP[3:0] I/OSynchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[16:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE in conjunction with the internal control logic. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ[31:0] and DP[3:0] are placed in a three-state condition. The outputs are automatically three-stated when a Write cycle is detected. 15, 41, 65, 91 VDD Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power supply. 3 PRELIMINARY CY7C1345 Pin Descriptions (continued) TQFP Pin Number Name I/O Description 17, 40, 67, 90 VSS Ground Ground for the I/O circuitry of the device. Should be connected to ground of the system. 5, 10, 14, 21, 26, 55, 60, 71, 76 VSSQ Ground Ground for the device. Should be connected to ground of the system. 4, 11, 20, 27, 54, 61, 70, 77 VDDQ I/O Power Supply Power supply for the I/O circuitry. Should be connected to a 3.3V power supply. 1,16, 30, 50-51, 66, 80 NC - No connects. 38, 39, 42, 43 DNU - Do not use pins. Should be left unconnected or tied LOW. Functional Description serted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core. If the OE input is asserted LOW, the requested data will be available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the RAM core. The write inputs (GW, BWE, and BW[3:0]) are ignored during this first clock cycle. If the write inputs are asserted active (see Write Cycle Descriptions table for appropriate states that indicate a write) on the next clock rise, the appropriate data will be latched and written into the device. Byte writes are allowed. During byte writes, BW0 controls DQ [7:0], BW1 controls DQ[15:8], BW2 controls DQ[23:16], and BW3 controls DQ [31:24]. All I/Os are three-stated during a byte write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be three-stated prior to the presentation of data to DQ[31:0]. As a safety precaution, the data lines are three-stated once a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1338 provides an on-chip 2-bit wraparound burst counter inside the SRAM. The burst counter is fed by A [1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE will select a linear burst sequence. A HIGH on MODE will select an interleaved burst order. Leaving MODE unconnected will cause the device to default to a interleaved burst sequence. Table 1. Counter Implementation for the Intel Pentium(R)/80486 Processor's Sequence. Single Write Accesses Initiated by ADSC First Address AX + 1, Ax 00 01 10 11 This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BW[3:0]) indicate a write access. ADSC is ignored if ADSP is active LOW. The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the RAM core. The information presented to DQ[31:0] will be written into the specified address location. Byte writes are allowed. During byte writes, BW0 controls DQ[7:0], BW1 controls DQ [15:8], BW2 controls DQ[23:16], and BWS3 controls DQ [31:24]. All I/Os are three-stated when a write is detected, even a byte write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be three-stated prior to the presentation of data to DQ[31:0]. As a safety precaution, the data lines are three-stated once a write cycle is detected, regardless of the state of OE. Second Address AX + 1, Ax 01 00 11 10 Third Address AX + 1, Ax 10 11 00 01 Fourth Address AX + 1, Ax 11 10 01 00 Table 2. Counter Implementation for a Linear Sequence. First Address AX + 1, Ax 00 01 10 11 Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE 1, CE2, and CE3 are all as- 4 Second Address AX + 1, Ax 01 10 11 00 Third Address AX + 1, Ax 10 11 00 01 Fourth Address AX + 1, Ax 11 00 01 10 PRELIMINARY Sleep Mode CY7C1345 sidered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CE1, CE 2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Leaving ZZ unconnected defaults the device into an active state. The ZZ input pin is an asynchronous input. Asserting ZZ HIGH places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not con- Cycle Description Table[1, 2, 3] Cycle Description ADD Used CE1 CE3 CE2 ZZ ADSP Deselected Cycle, Power-down None H X X L Deselected Cycle, Power-down None L X L L Deselected Cycle, Power-down None L H X Deselected Cycle, Power-down None L X L Deselected Cycle, Power-down None X X Snooze Mode, Power-down None X X Read Cycle, Begin Burst External L Read Cycle, Begin Burst External Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst ADSP ADV WE OE CLK DQ X L X X X L-H High-Z L X X X X L-H High-Z L L X X X X L-H High-Z L H L X X X L-H High-Z X L H L X X X L-H High-Z X H X X X X X X High-Z L H L L X X X L L-H Q L L H L L X X X H L-H High-Z External L L H L H L X L X L-H D External L L H L H L X H L L-H Q External L L H L H L X H H L-H High-Z Read Cycle, Continue Burst Next X X X L H H L H L L-H Q Read Cycle, Continue Burst Next X X X L H H L H H L-H High-Z Read Cycle, Continue Burst Next H X X L X H L H L L-H Q Read Cycle, Continue Burst Next H X X L X H L H H L-H High-Z Write Cycle, Continue Burst Next X X X L H H L L X L-H D Write Cycle, Continue Burst Next H X X L X H L L X L-H D Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q Read Cycle, Suspend Burst Current X X X L H H H H H L-H High-Z Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q Read Cycle, Suspend Burst Current H X X L X H H H H L-H High-Z Write Cycle, Suspend Burst Current X X X L H H H L X L-H D Write Cycle, Suspend Burst Current H X X L X H H L X L-H D Notes: 1. X=Don't Care, 1=Logic HIGH, 0=Logic LOW. 2. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWS[3:0]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a don't care for the remainder of the write cycle. 3. OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ=High-Z when OE is inactive, and DQ=data when OE is active. 5 PRELIMINARY CY7C1345 Write Cycle Descriptions[1, 2, 3, 4] Function GW BWE BW3 BW2 BW1 BW0 Read 1 1 X X X X Read 1 0 1 1 1 1 Write Byte 0,DP0 1 0 1 1 1 0 Write Byte 1,DP1 1 0 1 1 0 1 Write Bytes 1, 0,DP0,DP1 1 0 1 1 0 0 Write Byte 2,DP2 1 0 1 0 1 1 Write Bytes 2, 0,DP2,DP0 1 0 1 0 1 0 Write Bytes 2, 1,DP2,DP1 1 0 1 0 0 1 Write Bytes 2, 1, 0,DP2,DP1,DP0 1 0 1 0 0 0 Write Byte 3,DP3 1 0 0 1 1 1 Write Bytes 3, 0,DP3,DP0 1 0 0 1 1 0 Write Bytes 3, 1,DP3,DP0 1 0 0 1 0 1 Write Bytes 3, 1, 0,DP3,DP1,DP0 1 0 0 1 0 0 Write Bytes 3, 2,DP3,DP2 1 0 0 0 1 1 Write Bytes 3, 2, 0,DP3,DP2,DP0 1 0 0 0 1 0 Write Bytes 3, 2, 1,DP3,DP2,DP1 1 0 0 0 0 1 Write All Bytes 1 0 0 0 0 0 Write All Bytes 0 X X X X X DC Input Voltage[5] ................................ -0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Storage Temperature .................................-65 C to +150C Latch-Up Current.................................................... >200 mA Ambient Temperature with Power Applied .............................................-55C to +125C Operating Range Supply Voltage on VDD Relative to GND........ -0.5V to +4.6V Ambient Range Temperature[6] DC Voltage Applied to Outputs in High Z State[5] ....................................-0.5V to VDD + 0.5V Com'l Notes: 4. When a write cycle is detected, all I/Os are three-stated, even during byte writes. 5. Minimum voltage equals -2.0V for pulse durations of less than 20 ns. 6. TA is the "instant on" case temperature. 6 0C to +70C VDD VDDQ 3.135V to 3.6V 2.375V to VDD PRELIMINARY CY7C1345 Electrical Characteristics Over the Operating Range Parameter Description VOH Output HIGH Voltage VOL Output LOW Voltage Test Conditions Min. VDDQ = 3.3V, V DD = Min., IOH=-4.0 mA 2.4 VDDQ = 2.5V, V DD = Min., IOH=-2.0 mA 1.7 Max. Unit V V VDDQ = 3.3V, V DD = Min., IOL=8.0 mA 0.4 V VDDQ = 2.5V, V DD = Min., IOL=2.0 mA 0.7 V VIH Input HIGH Voltage 1.7 VDD + 0.3V V VIL Input LOW Voltage[5] -0.3 0.8 V IX Input Load Current (except ZZ and MODE) GND VI VDDQ -1 1 A Input Current of MODE Input = VSS -30 Input = VDDQ Input Current of ZZ 5 Output Leakage Current IOS Output Short Circuit Current IDD VDD Operating Supply Current ISB1 ISB2 ISB3 ISB4 [7] 30 A 5 A -300 mA 8.5-ns cycle, 117 MHz 350 mA 10-ns cycle, 100 MHz 325 mA 11-ns cycle, 90 MHz 300 mA 20-ns cycle, 50 MHz 250 mA Automatic CE Power-Down Current--TTL Inputs switching 8.5-ns cycle, 117 MHz 125 mA 10-ns cycle, 100 MHz 110 mA 11-ns cycle, 90 MHz 100 mA 20-ns cycle, 50 MHz 75 mA GND VI VDD, Output Disabled VDD=Max., VOUT=GND VDD=Max., IOUT=0 mA, f=fMAX =1/tCYC Max. VDD, Device Deselected, VIN VIH or VIN VIL f = fMAX = 1/tCYC A A -5 Input = VSS Input = VDDQ IOZ A -5 Max. VDD, Device Deselected, Std version - All speeds VIN 0.3V or VIN > VDDQ - 0.3V, L version - All speeds f=0 10 mA 2 mA Max. VDD, Device Deselected, 8.5-ns cycle, 117 MHz Automatic CE Power-Down Current--CMOS Inputs switching, VIN VDDQ- 0.3V or VIN 0.3V, 10-ns cycle, 100 MHz F=Max f=fMAX, inputs switching 11-ns cycle, 90 MHz 95 mA 85 mA 70 mA Automatic CE Power-Down Current -- CMOS Inputs static Automatic CE Power-Down Current Max. VDD, Device Deselected, -- CMOS Inputs static, F=Max VIN VDD -0.3V or VIN 0.3V, f=fMAX, inputs static 20-ns cycle, 50 MHz 60 mA 8.5-ns cycle, 117 MHz 60 mA 10-ns cycle, 100 MHz 50 mA 11-ns cycle, 90 MHz 40 mA 20-ns cycle, 50 MHz 35 mA Notes: 7. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 7 PRELIMINARY CY7C1345 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit ICCZZ Snooze mode standby current ZZ > VDD - 0.2V 3 mA ICCZZ (L Version) Snooze mode standby current ZZ > VDD - 0.2V 800 A tZZS Device operation to ZZ ZZ > VDD - 0.2V 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns Capacitance[8] Parameter Description Input Capacitance I/O Capacitance CIN CI/O Test Conditions TA = 25C, f = 1 MHz, VDD = 5.0V Max. 5.0 8.0 Unit pF pF Note: 8. Tested initially and after any design or process changes that may affect these parameters. AC Test Loads and Waveforms R1=317 3.3V OUTPUT Z0 =50 ALL INPUT PULSES OUTPUT 3.0V RL =50 VL =1.5V (a) INCLUDING JIG AND SCOPE 10% R2=351 5 pF GND 3.0 ns (b) 8 90% 90% 10% 3.0 ns PRELIMINARY CY7C1345 Switching Characteristics Over the Operating Range[9] -117 Parameter Description Min. Max. -100 Min. Max. -90 Min. -50 Max. Min. Max. Unit tCYC Clock Cycle Time 8.5 10 11 20 ns tCH Clock HIGH 3.0 4.0 4.5 4.5 ns tCL Clock LOW 3.0 4.0 4.5 4.5 ns tAS Address Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns tAH Address Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tCDV Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise 2.0 2.0 2.0 2.0 ns 7.5 8.0 8.5 11.0 ns tADS ADSP, ADSC Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns tADH ADSP, ADSC Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tWES BWS[1:0], GW,BWE Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns tWEH BWS[1:0], GW,BWE Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tADVS ADV Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns tADVH ADV Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tDS Data Input Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns tDH Data Input Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tCES Chip Enable Set-Up 2.0 2.0 2.0 2.0 ns tCEH Chip Enable Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tCHZ tCLZ Clock to High-Z Clock to Low-Z [10,11] 3.5 [10,11] 0 [10,12] tEOHZ OE HIGH to Output High-Z tEOLZ OE LOW to Output Low-Z[10,12] tEOV OE LOW to Output Valid 3.5 0 3.5 0 0 3.5 0 3.5 3.5 0 3.5 0 3.5 3.5 ns 3.5 0 3.5 ns ns ns 3.5 ns Note: 9. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and output loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC test loads. 10. tCHZ, t CLZ, tEOHZ, and tEOLZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 11. At any given voltage and temperature, t CHZ (max) is less than tCLZ (min). 12. This parameter is sampled and not 100% tested. 9 PRELIMINARY CY7C1345 Timing Diagrams Read/Write Timing tCYC tCH tCL CLK tAH tAS ADD A B D C tADH tADS ADSP tADH tADS ADSC tADVH tADVS ADV tCEH tCES CE1 tCEH tCES CE tWEH tWES WE ADSP ignored with CE1 HIGH OE tEOHZ tCLZ Data Q(A) In/Out Q(B) Q (B+1) Q (B+2) Q (B+3) Q(B) D(C) D (C+1) D (C+2) D (C+3) Q(D) tCDV tDOH tCHZ Device originally deselected WE is the combination of BWE, BWS [1:0], and GW to define a write cycle (see Write Cycle Definition table). CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X, Qx stands for Data-out X. = UNDEFINED = DON'T CARE 10 PRELIMINARY CY7C1345 Timing Diagrams (continued) Pipeline Timing tCH tCYC tCL CLK tAS ADD C B A E D F G H tADH tADS ADSP ADSC ADV tCEH tCES CE1 CE tWEH tWES WE ADSP ignored with CE1 HIGH OE tCLZ Data Q(A) In/Out Q(B) Q(C) D (E) Q(D) D (F) D (G) D (H) D(C) tCDV tDOH tCHZ Device originally deselected WE is the combination of BWE, BWS [1:0], and GW to define a write cycle (see Write Cycle Definition table). CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X, Qx stands for Data-out X. = UNDEFINED = DON'T CARE 11 PRELIMINARY Timing Diagrams (continued) OE Switching Waveforms OE tEOV tEOHZ I/Os three-state tEOLZ 12 CY7C1345 PRELIMINARY CY7C1345 Timing Diagrams (continued) ZZ Mode Timing [13,14] CLK ADSP HIGH ADSC CE1 CE2 LOW HIGH CE3 ZZ ICC tZZS ICC(active) ICCZZ tZZREC I/Os Three-state Note: 13. Device must be deselected when entering ZZ mode. See Cycle Description for all possible signal conditions to deselect the device. 14. I/Os are in three-state when exiting ZZ sleep mode. 13 PRELIMINARY CY7C1345 Ordering Information Speed (MHz) Ordering Code Package Name Package Type Operating Range 117 CY7C1345-117AC A101 100-Lead Thin Quad Flat Pack Commercial 100 CY7C1345-100AC A101 100-Lead Thin Quad Flat Pack Commercial 90 CY7C1345-90AC A101 100-Lead Thin Quad Flat Pack Commercial 50 CY7C1345-50AC A101 100-Lead Thin Quad Flat Pack Commercial Document #: 38-00725 Package Diagram 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-A (c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.