December 2002
Advance Information
Copyright © Alliance Semiconductor. All rights reserved.
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AS7C331MPFS18A
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1M x 18 pipelined burst synchronous SRAM
Features
• Organization: 1,048,576 x18 bits
• Fast clock speeds to 250MHz in LVTTL/LVCMOS
• Fast clock to data access: 2.6/2.8/3/3.4 ns
•Fast OE
access time: 2.6/2.8/3/3.4 ns
• Fully synchronous register-to-register op eration
• Single register flow-through mode
• Single-cycle des elect
• Asynchronous output enable control
• Available 100-pin TQFP and 165-ball BGA packages
• Byte write enables
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
DDQ
• NTD™ pipelined architecture available (AS7C331MNTD18A,
AS7C33512NTD32A/ AS7C33512NTD36A)
Logic block diagram
Selection guide
-250 -225 -200 -166 Units
Minimum cycle time 4 4.4 5 6 ns
Maximum clock frequency 250 225 200 166 MHz
Maximum pipelined clock access time 2.6 2.8 3.0 3.4 ns
Maximum operating current 425 400 370 340 mA
Maximum standby current 110 110 110 90 mA
Maximum CMOS standby current (DC) 70 70 70 70 mA
Burst logic
ADV
ADSC
ADSP
CLK
LBO
CLK
CLR
CS
20
18
20
A[19:0]
20 Address
DQ
CS
CLK
register
1M
[
18
Memory
array
18
18
DQb
CLK
DQ
Byte Write
registers
DQa
CLK
DQ
Byte Write
registers
Enable
CLK
DQ
register
Enable
CLK
DQ
delay
register
CE
Output
registers
Input
registers
Power
down
DQ[a,b]
2
CE0
CE1
CE2
BWb
BWa
OE
ZZ
OE
FT
CLK CLK
BWE
GWE
18
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Pin and ball designations
Pin configuration for 100-pin TQFP
Ball assignments for 165-ball BGA
$NC A CE0
BWb
NC CE2 BWE ADSC ADV AA
%NC A CE1
NC
BWa CLK GWE OE ADSP ANC
&
NC
NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPa
'NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa
(NC DQb VDDQ
VDD
VSS VSS VSS VDD VDDQ NC DQa
)NC DQb VDDQ
VDD
VSS VSS VSS VDD VDDQ NC DQa
*NC DQb VDDQ
VDD
VSS VSS VSS VDD VDDQ NC DQa
+FT NC NC
VDD
VSS VSS VSS VDD NC NC ZZ
-DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC
.DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC
/DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC
0DQb NC VDDQ VDD VSS VSS NC VDD VDDQ DQa NC
1DQPb NC VDDQ VSS NC A VSS VSS VDDQ NC NC
3NC NC A A TDI A11
1 A0 and A1 are the two least significant bits (LSB) of th e ad dress field and set the internal burst counter if b urst is desired.
TDOAAAA
5LBO NC
A
A
TMS
A01TCKAAAA
NC
NC
NC
VDDQ
VSSQ
NC
NC
DQb
DQb
VSSQ
VDDQ
DQb
DQb
FT
VDD
NC
VSS
DQb
DQb
VDDQ
VSSQ
DQb
DQb
DQPb
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSSQ
NC
DQa
DQa
DQa
VSSQ
VDDQ
DQa
DQa
VSS
ZZ
DQa
DQa
VDDQ
VSSQ
DQa
DQa
NC
NC
VSSQ
VDDQ
NC
NC
NC
LBO
A
A
A
A
A1
A0
NC
NC
VSS
VDD
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE0
CE1
NC
NC
BWb
BWa
CE2
VDD
VSS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A
A
NC
VDD
A
TQFP 14 × 20 mm
1M x 18
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AS7C331MPFS18A
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Functional description
The AS7C331MPFS18A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device organized as
1,048,576 words X 18 bits and incorporates a two-stage register-register pipeline for highest frequency on any given technology.
Fast cycle times of 4/4.4/5/6 ns with clock access times (tCD) of 2.6/2.8/3/3.4 ns enable 250, 225, 200, and 166 MHz bus frequencies.
Three chip enable (CE) inputs per mit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe
(ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register
when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data
accessed by the current address registered in the address registers by the positive edge of CLK is carried to the data-out registers and driven on
the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but it is sampled on all
subsequent cloc k ed ges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address strobes
are high. Burst mode is selectable with the
LBO
input. With
LBO
unconnected or driven high, burst operations use an interleaved count
sequence. With
LBO
driven low, the device uses a linear count sequence.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global wr ite enable GWE writes all
18 bits regardless of the state of ind ividual BW[a,b] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signals.
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all su bsequent cloc k edges. Output buffers are disabled when
BWn is sampled low, regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented internally
to the next burst address if BWn and ADV are sampled low.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.
•ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
•WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).
•Master chip enable CE0 blocks ADSP, but not ADSC.
The AS7C331MPFS18A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V.
These devices are available in a 100-pin TQFP and 165-ball BGA.
TQFP and BGA capacitance
Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN Address and control pins VIN = 0V 5 pF
I/O capacita nce CI/O I/O pins VIN = VOUT 7pF
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AS7C331MPFS18A
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Signal descriptions
Write enable truth table (per byte)
.H\X = don’t care; L = low; H = high; BWE, BWn = internal write signal
Signal I/O Properties Description
CLK I CLOCK Clock. All inp ut s exc e pt OE, FT, ZZ, and LBO are synchronous to this clock.
A0–A17 I SYNC Address. Sampled when all chip enab les ar e active and when ADSC or ADSP are asserted.
DQ[a,b] I/O SYNC Data. Driven as output when the chip is enabled and when OE is active.
CE0 ISYNC
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the “Synchronous truth table” for more inf o rmation.
CE1, CE2 ISYNC
Synchronous chip enables. Active high and active low, respectively. Sampled on clock
edges when ADSC is active or when CE0 and ADSP are active.
ADSP ISYNC
Address strobe processor. Asserted low to load a new bus address or to enter standby
mode.
ADSC I SYNC Address strobe controller. Asserted low to load a new address or to enter standby mode.
ADV I SYNC Advance. Asserted low to continue burst read/write.
GWE ISYNC
Global write enable. Asserted low to write all 32/36 and 18 bits. When high, BWE and
BW[a,b] control write enable.
BWE I SYNC Byte write enable. Asserted low with GWE high to enable effect of BW[a,b] inputs.
BW[a,b] ISYNC
Write enables. Used to contr ol write of individual bytes when GWE is high and BWE is
low. If an y of BW[a,b] is active with GWE high and BWE low, the cycle is a write cycle. If
all BW[AB] are inactive, the cycle is a read cycle.
OE IASYNC
Asynchronous output enab le. I/O pins ar e driven when OE is active and the chip is in read
mode.
LBO ISTATIC
Count mode. When driven high, count sequence follows Intel XOR convention. When
driven low, count sequence follows linear convention. This signal is internally pulled high.18
TDO O SYNC Serial data-out to the JTAG circuit. Delivers data on the negativ e edge of TCK (BGA only).
TDI I SYNC Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK (BGA only).
TMS I SYNC This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK
(BGA only).
TCK O SYNC Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only).
FT ISTATIC
Flow-through mode.When low, enables single register flow-through mode. Connect to
VDD if unused or for pipelined operation.
ZZ I ASYNC Sleep. Places device in low power mode; data is retained. Connect to GND if unused.
Function GWE BWE BWa BWb
Write all bytes (a, b) LXXX
HLLL
Write byte a H L L H
Write byte b H L H L
Read HHXX
HLHH
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AS7C331MPFS18A
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Synchronous truth table
Key: X = don’t care, L = low, H = high
TQFP and BGA thermal resistance
CE0 CE1 CE2 ADSP ADSC ADV
BWn
1
1 See “Write enable truth table” on page 4 for more information.
OE Address accessed CLK Operation DQ
HXXXLXXX NA L to H DeselectHi
−Z
L L X L XXXX NA L to H DeselectHi
−Z
LLXHLXXX NA L to H DeselectHi
−Z
L XHL XXXX NA L to H DeselectHi
−Z
LXHHLXXX NA L to H DeselectHi
−Z
L H L L X X X L External L to H Begin read Hi−Z2
2 Q in flow-through mode.
L H L L X X X H External L to H Begin read Hi−Z
LHLHLXFL External L to HBegin readHi
−Z2
LHLHLXFH External L to HBegin readHi
−Z
X X X H H L F L Next L to H Continue read Q
X X X H H L F H Next L to H Contin ue read Hi−Z
X X X H H H F L Current L to H Suspend read Q
X X X H H H F H Current L to H Suspend read Hi−Z
H X X X H L F L Next L to H Continue read Q
H X X X H L F H Next L to H Continue r e ad Hi−Z
H X X X H H F L Current L to H Suspend read Q
H X X X H H F H Current L to H Suspend read Hi−Z
LHLHLXTX External L to HBegin writeD
3
3 For a write operation following a read operation,
OE
must be high befor e the input data set up time and must be held high throughout the input hold time
X X X H H L T X Next L to H Continue write D
H X X X H L T X Next L to H Continue write D
X X X H H H T X Current L to H Suspend write D
H X X X H H T X Current L to H Suspend write D
Description Symbol Typical Units Conditions
Thermal resistance
(junction to ambient)1
1 This parameter is sampled.
1 layer θJA 40 °C/W Test conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA/JESD51
4 layer θJA 22 °C/W
Thermal resistance
(junction to top of ca se) 1θJC 8°C/W
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Absolute maximum ratings
Note: Stresses greater than those listed in this table may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating con-
ditions may affect reliability.
Recommended operating conditions
Parameter Symbol Min Max Unit
P owe r supply voltage relative to GND VDD, VDDQ –0.5 +4.6 V
Input voltage relative to GND (input pins) VIN –0.5 VDD + 0.5 V
Input voltage relative to GND (I/O pins) VIN –0.5 VDDQ + 0.5 V
Power dissipation PD–1.8W
DC output current IOUT – 20 mA mA
Storage temperature (plastic) Tstg –65 +150 oC
Temperature under bias Tbias –65 +135 oC
Parameter Symbol Min Nominal Max Unit
Supply voltage VDD 3.135 3.3 3.6 V
VSS 0.0 0.0 0.0
3.3V I/O supply voltage VDDQ 3.135 3.3 3.6 V
VSSQ 0.0 0.0 0.0
2.5V I/O supply voltage VDDQ 2.35 2.5 2.9 V
VSSQ 0.0 0.0 0.0
Input voltages1
1 Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.
Address and
control pins VIH 2.0 – VDD + 0.3 V
VIL –0.32
2 VIL min = –2.0V for pulse width less than 0.2 × tRC.
–0.8
I/O pins VIH 2.0 – VDDQ + 0.3 V
VIL –0.5 – 0.8
Ambient operating temperature TA0–70
°C
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AS7C331MPFS18A
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DC electrical characteristics for 3.3V I/O operation
DC electrical characteristics for 2.5V I/O operation
Parameter Sym Test conditions –250 –225 –200 –166 UnitMin Max Min Max Min Max Min Max
Input leakage
current1
1 LBO, FTX, and ZZX pins and the 165 BGA JTAG pins (TMSX, TDIX, and TCKX) have an internal pull -up, and input leakage = ±10 µa.
|ILI|V
DD = Max, VIN = GND to VDD -22-22-22-22µA
Output leakage
current |ILO|OE ≥ VIH, VDD = Max,
VOUT = GND to VDD -22-22-22-22µA
Operating power
supply current2
2 ICC given with no output loading. ICC increases with faster cycle times and gr eater output loading.
ICC
(Pipelined) CE0 = VIL, CE1 = VIH, CE2 = VIL,
f = fMax, IOUT = 0 mA
– 425 – 400 – 370 – 340 mA
Operating power
supply current2ICC
(Flow-through) – 250 – 225 – 200 – 175 mA
Standby power
supply current
ISB Deselected, f = fMax, ZZ ≤ VIL – 110 – 110 – 110 – 90
mA
ISB1 Deselected, f = 0, ZZ ≤ 0.2V
all VIN ≤ 0.2V or ≥ VDD – 0.2V –70–70–70–70
ISB2
Deselected, f = f
Max
, ZZ
≥
V
DD
– 0.2V
All VIN ≤ VIL or ≥ VIH –60–60–60–60
Output voltage VOL IOL = 8 mA, VDDQ = 3.465V – 0.4 0.4 – 0.4 – 0.4 V
VOH IOH = –4 mA, VDDQ = 3.135V 2.4 – 2.4 2.4 – 2.4 –
Parameter Sym Test conditions –250 –225 –200 –166 UnitMin Max Min Max Min Max Min Max
Output leakage
current |ILO|OE ≥ VIH, VDD = Max,
VOUT = GND to VDD –11–11–11–11µA
Output voltage VOL IOL = 2 mA, VDDQ = 2.65V – 0.7 – 0.7 – 0.7 – 0.7 V
VOH IOH = –2 mA, VDDQ = 2.35V 1.7 – 1.7 – 1.7 – 1.7 –
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Timing characteristics over operating range
Parameter Sym –250 –225 –200 –166 Unit Notes1
1 See “Notes” on page 19.
Min Max Min Max Min Max Min Max
Clock frequency fMax – 250 – 225 – 200 – 166 MHz
Cycle time (pipelined mode) tCYC 4–4.4–5–6–ns
Cycle time (flow-through mode) tCYCF 6.5 – 6.9 – 7.5 – 8.5 – ns
Cloc k ac c e ss time (pipelined mode) tCD – 2.6 – 2.8 – 3.0 – 3.4 ns
Clock access time (flow-through mode) tCDF – 6.5 – 6.9 – 7.5 – 8.5 ns
Output ena ble low to data valid tOE – 2.6 – 2.8 – 3.0 – 3.4 ns
Clock high to output low Z tLZC 0–0–0–0–ns2, 3, 4
Data output invalid from clock high tOH 1.5 – 1.5 – 1.5 – 1.5 – ns 2
Output enable low to output low Z tLZOE 0–0–0–0– ns2, 3, 4
Output ena ble high to output high Z tHZOE – 2.6 – 2.8 – 3.0 – 3.4 ns 2, 3, 4
Clock high to output high Z tHZC – 2.6 – 2.8 – 3.0 – 3.4 ns 2, 3, 4
Output ena ble high to invalid output tOHOE 0– –0–0–ns
Clock high pulse width tCH 1.5 - 1.8 – 1.8 – 2.1 – ns 5
Clock low pulse width tCL 1.5 - 1.8 – 1.8 – 2.2 – ns 5
Address setup to clock high tAS 1.2 - 1.4 – 1.4 – 1.5 – ns 6
Data setup to clock high tDS 1.2 - 1.4 – 1.4 – 1.5 – ns 6
Write setup to clock high tWS 1.2 - 1.4 – 1.4 – 1.5 – ns 6, 7
Chip select setup to clock high tCSS 1.2 - 1.4 – 1.4 – 1.5 – ns 6, 8
Address hold from clock high tAH 0.3 - 0.4 – 0.4 – 0.5 – ns 6
Data hold from clock high tDH 0.3 - 0.4 – 0.4 – 0.5 – ns 6
Write hold from clock high tWH 0.3 - 0.4 – 0.4 – 0.5 – ns 6, 7
Chip select hold from clock high tCSH 0.3 - 0.4 – 0.4 – 0.5 – ns 6, 8
ADV setup to clock high tADVS 1.2 - 1.4 – 1.4 – 1.5 – ns 6
ADSP setup to clock high tADSPS 1.2 - 1.4 – 1.4 – 1.5 – ns 6
ADSC setup to clock high tADSCS 1.2 - 1.4 – 1.4 – 1.5 – ns 6
ADV hold from clock high tADVH 0.3 - 0.4 – 0.4 – 0.5 – ns 6
ADSP hold from clock high t ADSPH 0.3 - 0.4 – 0.4 – 0.5 – ns 6
ADSC hold from clock high tADSCH 0.3 - 0.4 – 0.4 – 0.5 – ns 6
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AS7C331MPFS18A
®
IEEE 1149.1 serial boundary scan (JTAG)
The SRAM incorporates a serial boundary scan test access port (TAP). The port operates in accordance with IEEE Standard 1149.1-1990 but
does not have the set of functions required for full 1149.1 compliance. The inclusion of these functions would place an added delay in the
critical speed path of the SRAM. The TAP controller functionality does not conflict with the operation of other devices using 1149.1 fully
compliant TAPs. It uses JEDEC-standard 2.5V I/O logic levels.
The SRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.
Disabling the JTAG feature
If the JTAG function is not being implemented, its pins/balls can be left unconnected. At power-up, the device will come up in a reset state
which will not interfere with the operation of the device.
Test access port (TAP)
Test clock (TCK)
The test clock is used with only the TAP controller. All inputs are captured on the r ising edge of TCK. All outputs are driven from the falling
edge of TCK.
Test mode select (TMS)
The TAP controller receives commands from TMS input. It is sampled on the rising edge of TCK. You can leave this pin/ball unconnected if the
TAP is not used. The pin/ball is pulled up internally, resulting in a logic high level.
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AS7C331MPFS18A
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Test data-in (TDI)
The TDI pin/ball serially inputs information into the registers and can be connected to the input of any of the registers. The register between
TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For inf orma tion on lo ading the instruction register, see
the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an a pplication. TDI is connected to
the most significant bit (MSB) of any register. (See the TAP Controller Block Diagram.)
Test data-out (TDO)
The TDO output pin/ball serially clocks data-out from the registers. The output is active depending upon the current state of the TAP state
machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See the TAP
Controller State Diagram.)
Performing a TAP RESET
You can perform a RESET by forcing TMS high (VDD) f or fiv e rising edges of TCK. This RESET does not affect the operation of the SRAM and can
be performed while the SRAM is operating.
At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state.
TAP registers
Registers are connected between the TDI and TDO pins/balls. They allow data to be scanned into and out of the SRAM test circuitry. Only one
register can be selected at a time through the instruction register. Data is serially loaded into the TDI pin/ball on the rising edge of TCK. Data is
output on the TDO pin/ball on the falling edge of TCK.
Instruction register
You can serially load three-bit instructions into the instruction register. The register is loaded when it is placed between the TDI and TDO pins/
balls as shown in the TAP Controller Block Diagram. The instruction register is loaded with the IDCODE instruction at power up and also if the
controller is placed in a reset state, as described in the previous section.
When the TAP controller is in the Ca ptur e-IR sta te , the two least significant bits are loaded with a binary “01” pattern to allow for f ault isola tion
of the board-level series test data path.
Bypass register
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit
register that can be placed between the TDI and TDO pins/balls. This allows data to be shifted through the SRAM with minimal delay. The
bypass register is set low (Vss) when the BYPASS instruction is executed.
Boundary scan register
The boundary scan register is connected to all the input and bidirectional pins/balls on the SRAM. The x36 configuration has a 72-bit-long
register and the x18 configuration has a 53-bit-long register.
The boundary scan register is loaded with the contents of the RAM I/O r ing when the TAP controller is in the Capture-DR state and is then
placed between the TDI and TDO pins/balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/RELOAD, and SAMPLE Z
instructions can be used to capture the contents of the I/O ring.
The boundary scan order table shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM
package. The most significant bit (MSB) of the register is connected to TDI, and the least significant bit (LSB) is connected to TDO.
Identification (ID) register
The ID register has a v endor code and other inf ormation described in the Identification Register Definitions table. The ID register is loaded with
a vendor-specific, 32-bit code dur ing the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is
hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state.
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AS7C331MPFS18A
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TAP instruction set
Eight different instructions are possible with the 3-bit instruction register. All combinations are listed in the Instr uction Codes table. Three of
these instructions are reserved and should not be used.
Note that the TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1
instr uctions are not fully implemented. The TAP controller cannot be used to load address, data, or control signals into the SRAM and cannot
preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/
PRELOAD. Instead, it performs a capture of the I/O ring when these instructions are executed.
Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed betw een TDI and TDO. During this
state, instr uctions are shifted through the instr uction register through the TDI and TDO pins/balls. To execute the instruction once it is shifted
in, the TAP controller needs to be moved into the Update-IR state.
EXTEST
The EXTEST instruction, which executes whenever the instruction register is loaded with all 0s, is not implemented in this SRAM TAP controller.
The TAP controller, however, does recognize an all-0 instruction. When an EXTEST instr uct ion is loaded into the instruction register, the SRAM
responds as if a SAMPLE/PRELOAD instr uction has been loaded. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in
a high-Z state.
EXTEST is a mandatory 1149.1 instruction. this device, therefore, is not compliant with 1149.1.
IDCODE
The IDCODE instruction is lo aded into the instruction reg ister up on po wer-up or whenever the TAP controller is given a test logic reset sta te . The
IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between
the TDI and TDO pins/balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins/balls when the TAP controll er is in
a Shift-DR state. It also places all SRAM outputs into a high-Z state.
SAMPLE/PRELOAD
When the SAMPLE/PRELOAD instr uction is loaded into the instr uction register and the TAP controller is in the Capture-DR state, a snapshot of
data on the inputs and bidirectional pins/balls is captured in the boundary scan register. Note that the SAMPLE/PRELO AD is a 1149.1 manda tory
instruction, but the PRELOAD portion of this in struction is not implemented in this device. The TAP controller, therefore, is not fully 1149.1
compliant.
Be aware that the TAP controller clock can operate only at a frequency up to 10 Mhz, while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or outpu t
can undergo a transition. The TAP may then try to capture a signal while in transition (metastable sta te). This will not harm the de vice, but there
is no guarantee as to the value that will be captured. Repeatable results may not be possible.
To gu arantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the
TAP controller’s capture setup plus hold time (tCS plus tCH). The SRAM clock input might not be captur ed correctly if there is no way in a design
to stop (or slow) the cloc k during a SAMPLE/PRELOAD instr uction. If this is an issue, it is possible to capture all other signals and ignore the
value of the CK and CK# captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register
between the TDI and TDO pins.
Note that since the PRELOAD part of the command is not impleme nted, putting the TAP to the Update-DR state while performing a SAMPLE/
PRELOAD instruction will have the same effect as the Pause-DR command.
BYPASS
The advantage of the BYPASS instruction is that it shor tens the boundary scan path when multiple devices are connected together on a board.
When the BYPASS instruction is loaded in the instr uction register and the TAP is placed in a Shift-DR state, the bypass register is placed between
TDI and TDO.
®
AS7C331MPFS18A
12/2/02, v. 0.9.2 Advance Info Alliance Semiconductor 12 of 21
Reserved
Do not use a reserved instruction.These instructions are not implemented but are reserved for future use.
TAP timing diagram
TAP AC electrical characteristics
For notes 1 and 2, +10oC < TJ < +110oC and +2.4V < VDD < +2.6V.
Description Symbol Min Max Units
Clock
Clock cycle time tTHTH 100 ns
Clock frequency fTF 10 MHz
Clock high time tTHTL 40 ns
Clock low time tTLTH 40 ns
Output Times
TCK low to TDO unknown tTLOX 0 ns
TCK low to TDO valid tTLOV 20 ns
TDI valid to TCK high tDVTH 10 ns
TCK high to TDI invalid tTHDX 10 ns
Setup Times
TMS setup tMVTH 10 ns
Capture setup tCS1
1 tCS and tCH ref er to th e setu p and ho ld time r equ ireme nts of l a tching data
from the boundary scan register.
2 Test conditions are specified using the load in the figure TAP AC output
load equivalent.
10 ns
Hold Times
TMS hold tTHMX 10 ns
Capture hold tCH110 ns
W7+7/ W7/7+ W7+7+
W097+ W7+0;
W'97+ W7+'; W7/2;
W7/29
7HVW&ORFN
7&.
7HVW0RGH6HOHFW
706
7HVW'DWD,Q
7',
7HVW'DWD2XW
7'2
'RQ¶WFDUH 8QGHILQHG
12/2/02, v. 0.9.2 Advance Info Alliance Semiconductor 13 of 21
AS7C331MPFS18A
®
3.3V VDD, TAP DC electrical characteristics and operating conditions
(+10oC < TJ < +110oC and +3.135V < VDD < +3.465V unless otherwise noted)
2.5V VDD, TAP DC electrical characteristics and operating conditions
(+10oC < TJ < +110oC and +2.4V < VDD < +2.6V unless otherwise noted)
1. All voltage ref erenced to VSS(GND).
2. Overshoot: VIH(AC) ≤ VDD + 1.5V for t ≤ tKHKH/2
Undershoot: VIL(AC) ≥ -0.5 for t ≤ tKHKH/2
Power-up: VIH ≤ +2.6V and VDD ≤ 2.4V and VDDQ ≤ 1.4V for t ≤ 200ms
During normal operation, VDDQ must not exceed VDD. Control input signals (such as LD, R/W, etc.) may not have pulsed widths less than tKHKL(Min) or oper-
ate at frequencies exceeding fKF(Max).
Description Conditions Symbol Min Max Units Notes
Input high (logic 1) voltage VIH 2.0 VDD + 0.3 V 1, 2
Input low (logic 0) voltage VIL -0.3 0.8 V 1, 2
Input leakage current 0V ≤ VIN ≤ VDD ILI-5.0 5.0 µA
Output leakage current Outputs disa bled,
0V ≤ VIN ≤ VDDQ(DQx) ILO-5.0 5.0 µA
Output low voltage IOLC = 100µAV
OL1 0.7 V 1
Output low voltage IOLT = 2mA VOL2 0.8 V 1
Output high voltage IOHS = -100µAV
OH1 2.9 V 1
Output high voltage IOHT = -2mA VOH2 2.0 V 1
Description Conditions Symbol Min Max Units Notes
Input high (logic 1) voltage VIH 1.7 VDD + 0.3 V 1, 2
Input low (logic 0) voltage VIL -0.3 0.7 V 1, 2
Input leakage current 0V ≤ VIN ≤ VDD ILI-5.0 5.0 µA
Output leakage current Outputs disabled,
0V ≤ VIN ≤ VDDQ(DQx) ILO-5.0 5.0 µA
Output low voltage IOLC = 100µAV
OL1 0.2 V 1
Output low voltage IOLT = 2mA VOL2 0.7 V 1
Output high voltage IOHS = -100µAV
OH1 2.1 V 1
Output high voltage IOHT = -2mA VOH2 1.7 V 1
Input pulse levels. . . . . . . . . . . . . . . V ss to 2.5V
Input rise and fall times. . . . . . . . . . . . . . . 1 ns
Input timing reference levels. . . . . . . . . . 1.25V
Output ref erence levels . . . . . . . . . . . . . . 1.25V
Test load termination supply voltage. . . . 1.25V
TAP AC test conditions TAP AC output load equivalent
7'2
Ω
=2 Ω
9
S)
®
AS7C331MPFS18A
12/2/02, v. 0.9.2 Advance Info Alliance Semiconductor 14 of 21
Identification register definitions
Scan register sizes
Instruction codes
Instruction field 1M x 18 Description
Revision number (31:28) xxxx Reserved for version number.
Device depth (27:23) xxxxx Defines the depth of 1Mb words.
Device width (22:18) xxxxx Defines the width of x18 bits.
Device ID (17:12) xxxxxx Reserved for future use.
JEDEC ID code (11:1) 00000110100 Allows unique identification of SRAM vendor.
ID register presence indicator (0) 1 Indicates the presence of an ID register.
Register name Bit size
Instruction 3
Bypass 1
ID 32
Boundary scan x18:53 x36:72
Instruction Code Description
EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to high-Z state. This instruction is not 1149.1-compliant.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a high-Z state.
Reserved 011 Do not use. This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1-compliant.
Reserved 101 Do not use. This instruction is reserved for future use.
Reserved 110 Do not use. This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
12/2/02, v. 0.9.2 Advance Info Alliance Semiconductor 15 of 21
AS7C331MPFS18A
®
165-ball BGA boundary scan order (x18)
Bit #s Signal Name Ball ID
1SA 11P
2SA 6N
3SA 8P
4SA 8R
5SA 9R
6SA 9P
7SA 10P
8SA 10R
9SA 11R
10 DQa 10M
11 DQa 10L
12 DQa 10K
13 DQa 10J
14 ZZ 11H
15 DQa 11G
16 DQa 11F
17 DQa 11E
18 DQa 11D
19 DQPa 11C
20 SA 11A
21 SA 10A
22 SA 10B
23 ADV 9A
24 ADSP 9B
25 ADSC 8A
26 OE 8B
27 BWE 7A
Bit #s Signal Name Ball ID
28 GWE 7B
29 CLK 6B
30 CE2 6A
31 BWa 5B
32 BWb 4A
33 CE1 3B
34 CE0 3A
35 SA 2A
36 SA 2B
37 DQb 2D
38 DQb 2E
39 DQb 2F
40 DQb 2G
41 FT 1H
42 DQb 1J
43 DQb 1K
44 DQb 1L
45 DQb 1M
46 DQPb 1N
47 LBO 1R
48 SA 3P
49 SA 3R
50 SA 4R
51 SA 4P
52 SA1 6P
53 SA0 6R
®
AS7C331MPFS18A
12/2/02, v. 0.9.2 Advance Info Alliance Semiconductor 16 of 21
Key to switching waveforms
Timing waveform of read cycle
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = lo w.
BW[a:b] is don’t care.
Undefined/don’t careFalling inputRising input
t
CYC
t
CH
t
CL
t
ADSPS
t
ADSPH
t
AS
t
AH
t
WS
t
ADVS
t
OH
CLK
ADSP
ADSC
Address
GWE, BW E
CE0, CE2
ADV
OE
D
OUT
t
CSS
t
CSH
t
HZC
t
CD
t
WH
t
ADVH
t
HZOE
t
ADSCS
t
ADSCH
Load new address
ADV inserts wait sta tes
Q(A2Ý10)
Q(A2Ý11) Q(A3)
Q(A2)
Q(A2Ý01)
Q(A3Ý01)
Q(A3Ý10)
Q(A1)
A2A1 A3
CE1
(pipelined mode)
D
OUT
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A2Ý01) Q(A3Ý01) Q(A3Ý10)
Q(A3Ý11)
Q(A1)
(flow-through mode)
t
HZC
t
OE
t
LZOE
Read
Q(A1) Suspend
Read
Q(A1)
Read
Q(A2) Burst
Read
Q(A2Ý01)
Read
Q(A3) DSEL
Burst
Read
Q(A2Ý10)
Suspend
Read
Q(A2Ý10)
Burst
Read
Q(A2Ý11)
Burst
Read
Q(A3Ý01)
Burst
Read
Q(A3Ý10)
Burst
Read
Q(A3Ý11)
12/2/02, v. 0.9.2 Advance Info Alliance Semiconductor 17 of 21
AS7C331MPFS18A
®
Timing waveform of write cycle
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
t
CYC
t
CL
t
ADSPS
t
ADSPH
t
ADSCS
t
ADSCH
t
AS
t
AH
t
WS
t
WH
t
CSS
t
ADVS
t
DS
t
DH
CLK
ADSP
ADSC
Address
BWE
CE0, CE2
ADV
OE
Data In
t
CSH
t
ADVH
D(A2Ý01) D(A2Ý10) D(A3)D(A2) D(A2Ý01) D(A3Ý01) D(A3Ý10)
D(A1) D(A2Ý11)
ADV suspends burst
ADSC loads new address
A1 A2 A3
t
CH
CE1
BW[a:d]
Read Q(A1) Suspend
Write
D(A1)
Read
Q(A2) Suspend
Write
D(A2)
ADV
Burst
Write
D(A2Ý01)
Suspend
Write
D(A2Ý01)
ADV
Burst
Write
Q(A2Ý10)
Write
D(A3)Burst
Write
D(A3Ý01)
ADV
Burst
Write
Q(A2Ý11)
ADV
Burst
Write
D(A3Ý10)
®
AS7C331MPFS18A
12/2/02, v. 0.9.2 Advance Info Alliance Semiconductor 18 of 21
Timing waveform of read/write cycle
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = lo w.
t
CH
t
CYC
t
CL
t
ADSPS
t
ADSPH
t
AS
t
AH
t
WS
t
WH
t
ADVS
t
DS
t
DH
t
OH
CLK
ADSP
Address
GWE
CE0, CE2
ADV
OE
D
IN
D
OUT
t
LZC
t
ADVH
t
LZOE
t
OE
t
CD
Q(A1)
Q(A3Ý01)
D(A2)
Q(A3)
Q(A3Ý10) Q(A3Ý11)
A1 A2 A3
CE1
t
HZOE
(pipelined mode)
D
OUT
Q(A1)
Q(A3Ý01) Q(A3Ý10)
(flow-through mode)
t
CDF
Q(A3Ý11)
DSEL Suspend
Read
Q(A1)
Read
Q(A1) Suspend
Write
D(A2)
ADV
Burst
Read
D(A3Ý01)
Suspend
Read
Q(A3Ý11)
ADV
Burst
Read
Q(A3Ý10)
ADV
Burst
Read
Q(A3Ý11)
Read
Q(A2) Read
Q(A3)
12/2/02, v. 0.9.2 Advance Info Alliance Semiconductor 19 of 21
AS7C331MPFS18A
®
AC test conditions
Notes
1 For test condit ions, see “AC Test Conditions”, Figures A, B, and C.
2 This parameter is measured with output load condition in Figure C.
3 This parameter is sampled but not 100% tested.
4t
HZOE is less than tLZOE, and tHZC is less than tLZC at any given temperature and voltage.
5t
CH is measured as high above VIH, and tCL is measured as low below VIL.
6 This is a synchronous device . All addresses must meet the specif ied setup and hold times f or all rising edges of CLK. All other synchronous inputs must meet
the setup and hold times for all rising edges of CLK when chip is enabled.
7 Write refers to GWE, BWE, and BW[a,b]
.
8 Chip select refers to CE0, CE1, and CE2.
Z
0
= 50
Ω
D
OUT
50
Ω
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
GND
90%
10%
+3.0V
• Output load: For tLZC, tLZOE, tHZOE, tHZC, see Figure C. For all others, see Figure B.
• Input pulse level: GND to 3V. See Figure A.
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
V
L
= 1.5V
for 3.3V I/O;
V
L
= V
DDQ
/2
for 2.5V I/O
Thevenin equivalent:
353
Ω/1538Ω
5 pF*
319
Ω/1667Ω
D
OUT
GND
Figure C: Output load(B)
*including scope
and jig capacitance
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
®
AS7C331MPFS18A
12/2/02, v. 0.9.2 Advance Info Alliance Semiconductor 20 of 21
Package dimensions
100-pin TQFP (quad flat pack)
165-ball BGA (ball grid array)
He E
Hd
D
b
e
α
TQFP
Min Max
A1 0.05 0.15
A2 1.35 1.45
b0.22 0.38
c0.09 0.20
D13.90 14.10
E19.90 20.10
e0.65 nominal
Hd 15.90 16.10
He 21.90 22.10
L0.45 0.75
L1 1.00 nominal
α0° 7°
Dimensions in millimeters
A1 A2
L1
L
c
;
+
'
)
(
*
$
&
%
0
3
1
5
-
/
.
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$OOPHDVXUHPHQWVDUHLQPP
0LQ 7\S 0D[
$
%
&
'
(
)
*
+
,
=
=
;<
0$;
=
7RS9LHZ %RWWRP9LHZ
6LGH9LHZ 'HWDLORI6ROGHU%DOO
$
%
&
$
(
'
'
)+
*,
+
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)
(
*
$
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0
3
1
5
-
/
.
=
0
0
© C o py rig h t A llian ce S emicon d uc tor C or po ra tion . A ll r igh ts re ser ve d. Our th re e- po int log o , ou r n ame an d In telliw a tt are trad e m ar ks o r r eg ister ed trad emark s o f A llia nc e. All oth er br an d a nd
p
ro du ct n ames may be the trad e m ar ks o f th eir re spe ctiv e c ompa nie s. A llia nc e re ser ve s the rig ht to m a k e ch an g es to th is do cu m e n t and its p ro d uc ts at an y tim e w itho u t notic e. A llia nc e assu m e s no
resp o ns ibility fo r a ny er ror s tha t may a pp ea r in this do cu m e nt. T he da ta c on tain ed h ere in r ep rese n ts A llian ce ’s be st d ata a nd /or estimate s at th e time o f issu an ce . A llia nc e re serv e s the rig ht to
ch an ge or co rre ct th is d ata a t an y time, witho ut n o tice. If th e p ro du ct des crib e d h ere in is un d er d ev elo pmen t, sig nif ica nt c ha ng es to th ese s pe cific atio n s are po ssib le. The in fo rmatio n in th is
p
ro du ct d ata sh eet is inte nd ed to b e ge ne ral d esc rip tiv e in for m a tion fo r p o ten tial cu sto m e rs a nd us ers, a n d is n o t inte nd ed to operate as, or provide, any guarantee or w arrantee to any user or
cu stomer. A llian ce d oe s no t ass ume an y r esp o nsib ility or liab ility arisin g o ut o f th e a pp lica tion o r u se o f an y pr od uc t d escr ibe d her ein , an d disc laims an y exp re ss o r implied w a rra ntie s re late d to
the sale an d/o r u se o f Allianc e p ro d uc ts inc lud in g lia bility o r w a rra ntie s re lated to fitn ess f or a p artic ula r p ur po se, m er ch an tab ility, or in f rin ge m en t o f an y inte llec tua l pr op er ty r igh ts, ex c ep t as
ex pr ess a gr eed to in Allianc e’s T e rms an d C o n ditio n s of Sa le ( w h ich are av aila ble fro m Allian ce) . A ll sa les o f A lli an ce p ro d uc ts are m a de ex clusively accord ing to A lliance’s T erm s a nd
C on d ition s o f S ale . T h e p urc h ase o f p ro d uc ts fro m A llian ce d o es n o t co nv ey a lic en se u n de r an y pa ten t rig hts, cop y rig ht s, m a sk w orks rights, trademarks, or any other intellectual property rights
of A llian ce or thir d p ar ties. Allian ce d o es n ot a uth o riz e its p ro du cts f or use as c ritica l co m p o ne nts i n life -su p po rtin g syste m s whe re a m alf un ctio n or failu re m a y r easo n ab ly be exp ec ted to res ult
in sig n ific an t inju ry to the use r, a nd th e in clu sion o f A llia nc e p ro du ct s in su ch lif e-su pp o rtin g syste m s implie s th at th e manu fa ctu re r ass umes all r isk of suc h u se a nd a gre es to in de m n ify A llia nc e
against all claim s arising from such use.
AS7C331MPFS18A
®
12/2/02, v. 0.9.2 Advance Info Alliance Semiconductor 21 of 21
Ordering information
Part numbering guide
1. Alliance Semiconductor SRAM prefix
2. Operating volta ge: 33 = 3.3V
3. Or ganization:
1M
4. Pipelined/flow-through mode (each device works in both modes)
5. Deselect: S = single cycle deselect
6. Organization: 18 = x18
7. Production version: A = first production version
8. Clock speed (MHz)
9. Package type: TQ = TQFP; B = BGA
10. Operating tempera tur e: C = com m ercial (
0
°
C to 70
°
C); I = industrial (
-40
°
C to 85
°
C)
Package
&Width -250 H MHz –225 MHz –200 MHz –166 MHz
TQFP x18
AS
7C331MPFS18A
-250TQC
AS7C331MPFS18A
-225TQC AS7C331MPFS18A
-200TQC AS7C331MPFS18A
-166TQC
AS7C331MPFS18A
-225TQI AS7C331MPFS18A
-200TQI AS7C331MPFS18A
-166TQI
BGA x18
AS
7C331MPFS18A
-250BC
AS7C331MPFS18A
-225BC AS7C331MPFS18A
-200BC AS7C331MPFS18A
-166BC
AS7C331MPFS18A
-225BI AS7C331MPFS18A
-200BI AS7C331MPFS18A
-166BI
AS7C 33 1M PF S18 A–XXX TQ or B C/I
1
23
45678
910
