High Performance 256Kx4 CMOS SRAM AS7C1028 AS7C1028L (R) 256Kx4 CMOS SRAM Features * Organization: 262,144 words x 4 bits * High speed - 12/15/20/25/35 ns address access time - 4/4/5/6/8 ns output enable access time * Low power consumption - Active: 660 mW max (15 ns cycle) - Standby: 27.5 mW max, CMOS I/O 5.5 mW max, CMOS I/O, L version - Very low DC component in active power * 2.0V data retention (L version) * Equal access and cycle times * Easy memory expansion with CE and OE inputs * TTL-compatible, three-state I/O * 28-pin JEDEC standard packages - 300 mil PDIP and SOJ - 400 mil PDIP and SOJ * ESD protection > 2000 volts * Latch-up current > 200 mA Logic block diagram Pin arrangement DIP, SOJ GND A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CE OE GND Input buffer 512x512x4 Array (1,048,576) Sense amp I/O3 Row decoder A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O2 I/O1 I/O0 Column decoder WE Control circuit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AS7C1028 Vcc 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc A17 A16 A15 A14 A13 A12 A11 NC I/O0 I/O1 I/O2 I/O3 WE OE CE A A A A A A A A A 9 10 11 12 13 14 15 16 17 Selection guide Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current L 7C1028-12 12 4 130 5.0 1.0 7C1028-15 15 4 120 5.0 1.0 7C1028-20 20 5 110 5.0 1.0 Shaded areas contain advance information. ALLIANCE SEMICONDUCTOR 7C1028-25 25 6 100 5.0 1.0 7C1028-35 35 8 80 5.0 1.0 Unit ns ns mA mA mA AS7C1028 AS7C1028L Functional description The AS7C1028 is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) organized as 262,144 words x 4 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 12/15/20/25/35 ns with output enable access times (tOE) of 4/4/5/6/8 ns are ideal for high performance applications. A chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations. When CE is HIGH the device enters standby mode. The standard AS7C1028 is guaranteed not to exceed 27.5 mW power consumption in standby mode; the L version is guaranteed not to exceed 5.5 mW, and typically requires only 800 W. The L version also offers 2.0V data retention, with maximum power consumption in this mode of 600 W. A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O3 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) HIGH. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is HIGH, or write enable is LOW, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply. The AS7C1028 is packaged in high volume industry standard packages. Absolute maximum ratings Parameter Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Temperature under bias DC output current Symbol Vt PD Tstg Tbias Iout Min -0.5 - -55 -10 - Max +7.0 1.0 +150 +85 20 Unit V W o C o C mA Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE H L L L WE X H H L OE X H L X Data High Z High Z Dout Din Mode Standby (ISB, ISB1) Output Disable Read Write Key: X = Don't Care, L = LOW, H = HIGH Recommended operating conditions Parameter Supply voltage Input voltage V min = -3.0V for pulse width less than t /2 IL RC 2 (Ta = 0C to +70C) Symbol VCC GND VIH VIL Min 4.5 0.0 2.2 -0.5 Typ 5.0 0.0 - - Max 5.5 0.0 VCC+1 0.8 Unit V V V V AS7C1028 AS7C1028L DC operating characteristics1 Parameter Input leakage current Output leakage current Operating power supply current Min Symbol Test Conditions VCC = Max, | ILI | Vin = GND to VCC CE = VIH, VCC = Max, | ILO | Vout = GND to VCC ICC CE = VIL, f = fmax, Iout = 0 mA ISB CE = VIH, f = fmax Standby power supply current ISB1 Output voltage (VCC = 5V10%, GND = 0V, Ta = 0C to +70C) VOL VOH L L CE > VCC-0.2V, f = 0, Vin 0.2V or L Vin VCC-0.2V IOL = 8 mA, VCC = Min IOH = -4 mA, VCC = Min -12 Max Min -15 Max -20 Min Max -25 Min Max Min -35 Max Unit - 1 - 1 - 1 - 1 - 1 A - 1 - 1 - 1 - 1 - 1 A - 130 - 120 - 110 - 100 - 80 mA - 125 - 115 - 105 - 95 - 75 mA - - - 50 45 5.0 - - - 40 35 5.0 - - - 40 35 5.0 - - - 35 30 5.0 - - - 30 25 5.0 mA mA mA - 1.0 - 1.0 - 1.0 - 1.0 - 1.0 mA - 2.4 0.4 - - 2.4 0.4 - - 2.4 0.4 - - 2.4 0.4 - - 2.4 0.4 - V V Capacitance2 (f = 1 MHz, Ta = Room Temperature, VCC = 5V) Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals A, CE, WE, OE I/O Test Conditions Vin = 0V Vin = Vout = 0V Max 5 7 Unit pF pF Key to switching waveforms AAAA AAA AAAA AAAAAAA AAA Rising input AAAA AAA AAAA AAAAAAA AAA AAAA AAA AAAA AAAAAAA AAA Undefined Falling input Read cycle3,9 Parameter Read cycle time Address access time Chip enable (CE) access time Output enable (OE) access time Output hold From address change Chip enable to output in Low Z Chip disable to output in High Z Output enable to output in Low Z Output disable to output in High Z Chip enable to power up time Chip Disable to power down time output/don't care (VCC = 5V10%, GND = 0V, Ta = 0C to +70C) Symbol tRC tAA tACE tOE tOH tCLZ tCHZ tOLZ tOHZ tPU tPD -12 Min Max 12 - - 12 - 12 - 3 3 - 3 - - 3 0 - - 3 0 - - 12 -15 Min Max 15 - - 15 - 15 - 4 3 - 3 - - 4 0 - - 4 0 - - 15 -20 Min Max 20 - - 20 - 20 - 5 3 - 3 - - 5 0 - - 5 0 - - 20 -25 Min Max 25 - - 25 - 25 - 6 3 - 3 - - 6 0 - - 6 0 - - 25 -35 Min Max 35 - - 35 - 35 - 8 3 - 3 - - 8 0 - - 8 0 - - 35 Unit ns ns ns ns ns ns ns ns ns ns ns Notes 3 3 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 3 AS7C1028 AS7C1028L Read waveform 13,6,7,9 Address controlled tRC Address tOH tAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAAAAAAAAAAAAAAAA Dout Data Valid Read waveform 23,6,8,9 CE controlled tRC1 CE AAAAAAAAAAAAAAAAAAAAAAAAA tOE AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A OEAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A tACE Dout tOLZ tOHZ tCHZ AAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA Data Valid tCLZ Supply current tPU tPD 50% (VCC = 5V10%, GND = 0V, Ta = 0C to +70C) -12 4 ISB 50% Write cycle11 Parameter Symbol Write cycle time tWC Chip enable to write end tCW Address setup to write end tAW Address setup time tAS Write pulse width tWP Address hold from end of write tAH Data valid to write end tDW Data hold time tDH Write enable to output in High Z tWZ Output active from write end tOW ICC Min 12 10 10 0 8 0 8 0 - 3 -15 Max - - - - - - - - 5 - Min 15 10 10 0 9 0 9 0 - 3 -20 Max - - - - - - - - 5 - Min 20 12 12 0 12 0 10 0 - 3 -25 Max - - - - - - - - 5 - Min 20 15 15 0 15 0 10 0 - 3 -35 Max - - - - - - - - 5 - Min 30 20 20 0 17 0 15 0 - 3 Max - - - - - - - - 5 - Unit ns ns ns ns ns ns ns ns ns ns Notes 4, 5 4, 5 4, 5 AS7C1028 AS7C1028L Write waveform 110,11 WE controlled tWC tAW tAH Address WE tWP AAAAAAAAAA AAAA AAAAAAAA AAAAAA AA AAAAAAAAAA tAS tDW Din tDH Data Valid tWZ tOW Dout Write waveform 210,11 CE controlled tWC tAW tAH Address tAS tCW CE AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA WE AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA tWP tWZ Din Dout AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA tDW tDH Data Valid AAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAA AAA Data retention characteristics L version only Parameter VCC for data retention Data retention current Chip deselect to data retention time Operation recovery time Input leakage current Symbol VDR ICCDR tCDR tR | ILI | Test Conditions VCC = 2.0V CE VCC-0.2V Vin VCC-0.2V or Vin 0.2V Min 2.0 - 0 tRC - Max - 300 - - 1 Data retention waveform Unit V A ns ns A L version only Data retention mode VCC VDR 2.0V 4.5V tCDR AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA CE AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA VIH 4.5V tR VDR AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIH AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA 5 AS7C1028 AS7C1028L AC test conditions * Output load: see Figure B, except for tCLZ and tCHZ see Figure C. * Input pulse level: GND to 3.0V. See Figure A. * Input rise and fall times: 5 ns. See Figure A. * Input and output timing reference levels: 1.5V. Thevenin Equivalent: 168 Dout +1.728V +5V +5V 480 +3.0V GND Dout 90% 10% 90% 10% Figure A: Input Waveform 255 480 Dout 30 pF* GND Figure B: Output Load 255 6 *including scope and jig capacitance GND Figure C: Output Load for tCLZ, tCHZ Notes 1 2 3 4 5 6 7 8 9 10 11 5 pF* During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled and not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, C. tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured 500mV from steady-state voltage. This parameter is guaranteed but not tested. WE is HIGH for read cycle. CE and OE are LOW for read cycle. Address valid prior to or coincident with CE transition LOW. All read cycle timings are referenced from the last valid address to the first transitioning address. CE or WE must be HIGH during address transitions. All write cycle timings are referenced from the last valid address to the first transitioning address. AS7C1028 AS7C1028L Normalized supply current ICC, ISB vs. ambient temperature Ta 1.4 1.2 1.2 0.8 0.6 0.2 0.0 4.0 Normalized access time t AA vs. supply voltage VCC Normalized access time Ta = 25C 1.0 0.9 4.5 5.0 5.5 Supply voltage (V) Output source current IOH vs. output voltage VOH VCC = 5.0V Ta = 25C 60 40 20 1.25 2.5 3.75 Output voltage (V) 5.0 -10 35 80 125 Ambient temperature (C) 0.2 -10 35 80 125 Ambient temperature (C) Normalized supply current ICC vs. cycle frequency 1/tRC, 1/tWC 1.2 VCC = 5.0V 1.0 0.9 VCC = 5.0V Ta = 25C 1.0 0.8 0.6 0.4 0.2 0.0 -10 35 80 125 Ambient temperature (C) 0 20 40 60 Cycle frequency (MHz) 80 Typical access time change tAA vs. output capacitive loading Output sink current IOL vs. output voltage VOL 35 30 120 VCC = 5.0V Ta = 25C 80 60 40 20 0 0.0 1 1.4 1.1 100 5 -55 Normalized access time tAA vs. ambient temperature Ta 1.2 140 80 0 0.0 1.3 VCC = 5.0V 25 0.04 1.4 0.8 -55 6.0 120 100 ISB 0.4 1.5 1.1 140 0.6 0.0 -55 6.0 1.2 0.8 4.0 Output source current (mA) 4.5 5.0 5.5 Supply voltage (V) 1.4 1.3 0.8 0.2 Output sink current (mA) Normalized access time 1.5 1.0 625 Normalized ICC 0.4 ISB ICC Change in tAA (ns) 1.0 ICC Normalized supply current ISB1 vs. ambient temperature Ta Normalized ISB1 (log scale) Normalized supply current ICC, ISB vs. supply voltage VCC 1.4 Normalized ICC, ISB Normalized ICC, ISB Typical DC and AC characteristics VCC = 4.5V 25 20 15 10 5 0 1.25 2.5 3.75 Output voltage (V) 5.0 0 250 500 750 Capacitance (pF) 1000 7 AS7C1028 AS7C1028L Ordering codes Package \ Access Time 12 ns 15 ns 20 ns 25 ns 35 ns Plastic DIP, 300 mil AS7C1028-12TPC AS7C1028L-12TPC AS7C1028-15TPC AS7C1028L-15TPC AS7C1028-20TPC AS7C1028L-20TPC AS7C1028-25TPC AS7C1028L-25TPC AS7C1028-35TPC AS7C1028L-35TPC Plastic DIP, 400 mil AS7C1028-12PC AS7C1028L-12PC AS7C1028-15PC AS7C1028L-15PC AS7C1028-20PC AS7C1028L-20PC AS7C1028-25PC AS7C1028L-25PC AS7C1028-35PC AS7C1028L-35PC Plastic SOJ, 300 mil AS7C1028-12TJC AS7C1028L-12TJC AS7C1028-15TJC AS7C1028L-15TJC AS7C1028-20TJC AS7C1028L-20TJC AS7C1028-25TJC AS7C1028L-25TJC AS7C1028-35TJC AS7C1028L-35TJC Plastic SOJ, 400 mil AS7C1028-12JC AS7C1028L-12JC AS7C1028-15JC AS7C1028L-15JC AS7C1028-20JC AS7C1028L-20JC AS7C1028-25JC AS7C1028L-25JC AS7C1028-35JC AS7C1028L-35JC Shaded areas contain advance information. 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(787) 746-9897 SINGAPORE Exer Technologies +65-749-1349 Alliance Semiconductor reserves the right to make changes in this data sheet at any time to improve design and supply the best product possible. Publication of advance information does not constitute a committment to produce or supply the product described. The company cannot assume responsibility for circuits shown or represent that they are free from patent infringement. Alliance products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of Alliance. ProMotion(R) and the Alliance logo are registered trademarks of Alliance Semiconductor Corporation. All other trademarks are property of their respective holders. 3099 North First Street Printed in U.S.A. ALLIANCE SEMICONDUCTOR San Jose, CA 95134 Tel (408) 383-4900 Fax (408) 383-4999 Copyright (c) 1996 All rights reserved. www.alsc.com June 1996