AS7C1028-25TPC - Alliance Semiconductor

ALLIANCE SEMICONDUCTOR

High Performance

256K×4

CMOS SRAM

AS7C1028

AS7C1028L

256K×4 CMOS SRAM

Features

• Organization: 262,144 words × 4 bits

• High speed

- 12/15/20/25/35 ns address access time

- 4/4/5/6/8 ns output enable access time

• Low power consumption

- Active: 660 mW max (15 ns cycle)

- Standby:27.5 mW max, CMOS I/O

5.5 mW max, CMOS I/O, L version

- Very low DC component in active power

• 2.0V data retention (L version)

• Equal access and cycle times

• Easy memory expansion with CE and OE inputs

• TTL-compatible, three-state I/O

• 28-pin JEDEC standard packages

- 300 mil PDIP and SOJ

- 400 mil PDIP and SOJ

• ESD protection > 2000 volts

• Latch-up current > 200 mA

Logic block diagram

512×512×4

Array

(1,048,576)

Input buffer

11 A

12 A

13 A

14 A

15 A

16 A

I/O0

I/O3

Vcc

GND

Column decoder

Row decoder

Control

circuit

I/O2

I/O1

Sense amp

Pin arrangement

A10

GND

DIP, SOJ

Vcc

A17

A16

A15

A14

A13

A12

A11

I/O0

I/O1

I/O2

I/O3

AS7C1028

Selection guide

Shaded areas contain advance information.

7C1028-12 7C1028-15 7C1028-20 7C1028-25 7C1028-35 Unit

Maximum address access time 12 15 20 25 35 ns

Maximum output enable access time 44568ns

Maximum operating current 130 120 110 100 80 mA

Maximum CMOS standby current 5.0 5.0 5.0 5.0 5.0 mA

L1.0 1.0 1.0 1.0 1.0 mA

AS7C1028

AS7C1028L

Functional description

The AS7C1028 is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) organized as 262,144 words × 4 bits. It

is designed for memory applications where fast data access, low power, and simple interfacing are desired.

Equal address access and cycle times (tAA, tRC, tWC) of 12/15/20/25/35 ns with output enable access times (tOE) of 4/4/5/6/8 ns are ideal

for high performance applications. A chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations.

When CE is HIGH the device enters standby mode. The standard AS7C1028 is guaranteed not to exceed 27.5 mW power consumption in

standby mode; the L version is guaranteed not to exceed 5.5 mW, and typically requires only 800 µW. The L version also offers 2.0V data

retention, with maximum power consumption in this mode of 600 µW.

A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O3 is written on

the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after

outputs have been disabled with output enable (OE) or write enable (WE).

A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) HIGH. The chip drives

I/O pins with the data word referenced by the input address. When chip enable or output enable is HIGH, or write enable is LOW, output

drivers stay in high-impedance mode.

All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply. The AS7C1028 is packaged in high volume

industry standard packages.

Absolute maximum ratings

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute max-

imum rating conditions for extended periods may affect reliability.

Truth table

Key: X = Don’t Care, L = LOW, H = HIGH

Recommended operating conditions (Ta = 0°C to +70°C)

†VIL min = –3.0V for pulse width less than tRC/2

Parameter Symbol Min Max Unit

Voltage on any pin relative to GND Vt–0.5 +7.0 V

Power dissipation PD–1.0W

Storage temperature (plastic) Tstg –55 +150 oC

Temperature under bias Tbias –10 +85 oC

DC output current Iout –20mA

CE WE OE Data Mode

H X X High Z Standby (ISB, ISB1)

L H H High Z Output Disable

LHLD

out Read

LLXD

in Write

Parameter Symbol Min Typ Max Unit

Supply voltage VCC 4.5 5.0 5.5 V

GND 0.0 0.0 0.0 V

Input voltage VIH 2.2 – VCC+1 V

VIL –0.5†–0.8V

AS7C1028

AS7C1028L

DC operating characteristics1(VCC = 5V±10%, GND = 0V, Ta = 0°C to +70°C)

Capacitance2(f = 1 MHz, Ta = Room Temperature, VCC = 5V)

Key to switching waveforms

Read cycle3,9 (VCC = 5V±10%, GND = 0V, Ta = 0°C to +70°C)

Parameter Symbol Test Conditions

-12 -15 -20 -25 -35

Unit

Min Max Min Max Min Max Min Max Min Max

Input leakage

current | ILI | VCC = Max,

Vin = GND to VCC –1–1–1–1–1µA

Output

leakage current | ILO | CE = VIH, VCC = Max,

Vout = GND to VCC –1–1–1–1–1µA

Operating

power supply

current

ICC CE = VIL, f = fmax,

Iout = 0 mA

–130 – 120 – 110 – 100 – 80 mA

L– 125 – 115 – 105 – 95 – 75 mA

Standby

power supply

current

ISB CE = VIH, f = fmax

–50 – 40 – 40 – 35 – 30 mA

L– 45 – 35 – 35 – 30 – 25 mA

ISB1

CE > VCC–0.2V, f = 0,

Vin ≤ 0.2V or

Vin ≥ VCC–0.2V

–5.0 – 5.0 – 5.0 – 5.0 – 5.0 mA

L– 1.0 – 1.0 – 1.0 – 1.0 – 1.0 mA

Output voltage VOL IOL = 8 mA, VCC = Min – 0.4 – 0.4 – 0.4 – 0.4 – 0.4 V

VOH IOH = –4 mA, VCC = Min 2.4 –2.4–2.4–2.4–2.4– V

Parameter Symbol Signals Test Conditions Max Unit

Input capacitance CIN A, CE, WE, OE Vin = 0V 5 pF

I/O capacitance CI/O I/O Vin = Vout = 0V 7 pF

Parameter Symbol

-12 -15 -20 -25 -35

Unit Notes

Min Max Min Max Min Max Min Max Min Max

Read cycle time tRC 12 –15–20–25–35–ns

Address access time tAA –12 – 15 – 20 – 25 – 35 ns 3

Chip enable (CE) access time tACE –12 – 15 – 20 – 25 – 35 ns 3

Output enable (OE) access time tOE –3–4–5–6–8ns

Output hold From address change tOH 3–3–3–3–3–ns5

Chip enable to output in Low Z tCLZ 3–3–3–3–3–ns4, 5

Chip disable to output in High Z tCHZ –3–4–5–6–8ns4, 5

Output enable to output in Low Z tOLZ 0–0–0–0–0–ns4, 5

Output disable to output in High Z tOHZ –3–4–5–6–8ns4, 5

Chip enable to power up time tPU 0–0–0–0–0–ns4, 5

Chip Disable to power down time tPD –12 – 15 – 20 – 25 – 35 ns 4, 5

AAAA

AAA

Undefined output/don’t care

AAAA

AAA

Falling input

AAAA

AAA

Rising input

AS7C1028

AS7C1028L

Read waveform 13,6,7,9 Address controlled

Read waveform 23,6,8,9 CE controlled

Write cycle11 (VCC = 5V±10%, GND = 0V, Ta = 0°C to +70°C)

Parameter Symbol

-12 -15 -20 -25 -35

Unit Notes

Min Max Min Max Min Max Min Max Min Max

Write cycle time tWC 12 –15–20–20–30–ns

Chip enable to write end tCW 10 –10–12–15–20–ns

Address setup to write end tAW 10 –10–12–15–20–ns

Address setup time tAS 0–0–0–0–0–ns

Write pulse width tWP 8– 9 –12–15–17–ns

Address hold from end of write tAH 0–0–0–0–0–ns

Data valid to write end tDW 8– 9 –10–10–15–ns

Data hold time tDH 0–0–0–0–0–ns4, 5

Write enable to output in High Z tWZ –5–5–5–5–5ns4, 5

Output active from write end tOW 3–3–3–3–3–ns4, 5

AAAA

Address

Dout Data Valid

tOH

tAA

tRC

AAAA

Supply

current

Dout

tRC1

tOE

tOLZ

tACE tCHZ

tCLZ

tPU

tPD ICC

ISB

50% 50%

tOHZ

AAAA

Dat a Vali d

AAAA

AS7C1028

AS7C1028L

Write waveform 110,11 WE controlled

Write waveform 210,11 CE controlled

Data retention characteristics L version only

Data retention waveform L version only

Parameter Symbol Test Conditions Min Max Unit

VCC for data retention VDR VCC = 2.0V

CE ≥ VCC–0.2V

Vin ≥ VCC–0.2V or

Vin ≤ 0.2V

2.0 – V

Data retention current ICCDR –300µA

Chip deselect to data retention time tCDR 0–ns

Operation recovery time tRtRC –ns

Input leakage current | ILI | –1µA

AW tAH

tWC

AAAA

Address

Din

Dout

tDH

tOW

tDW

tWZ

tWP

tAS

Data Valid

tAW

AAAA

Address

Din

Dout

Data Valid

tCW

tWP

tDW tDH

tAH

tWZ

tWC

AAAA

AAA

tAS

AAAA

AAA

VCC

tCDR

Data retention mode

4.5V 4.5V

VDR ≥ 2.0V

VIH VIH

VDR

AS7C1028

AS7C1028L

AC test conditions

Notes

1 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.

2 This parameter is sampled and not 100% tested.

3 For test conditions, see AC Test Conditions, Figures A, B, C.

CLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage.

5 This parameter is guaranteed but not tested.

6WE

is HIGH for read cycle.

7CE

and OE are LOW for read cycle.

8 Address valid prior to or coincident with CE transition LOW.

9 All read cycle timings are referenced from the last valid address to the first transitioning address.

10 CE or WE must be HIGH during address transitions.

11 All write cycle timings are referenced from the last valid address to the first transitioning address.

255Ω

• Output load: see Figure B,

except for tCLZ and tCHZ see Figure C.

• Input pulse level: GND to 3.0V. See Figure A.

• Input rise and fall times: 5 ns. See Figure A.

• Input and output timing reference levels: 1.5V.

5 pF*

480Ω

Dout

GND

+5V

168Ω

Thevenin E q uivalent:

Dout +1.728V

Figure C: Output Load for tCLZ, tCHZ

255Ω30 pF*

480Ω

Dout

GND

+5V

Figure B: Outpu t Load

*including sco pe

10%

90%

10%

90%

GND

+3.0V

Figure A: Input Waveform

and jig capacitance

AS7C1028

AS7C1028L

Typical DC and AC characteristics

Supply voltage (V)

4.0 5.5 6.0

5.04.5

0.0

0.2

0.6

0.8

0.4

1.0

1.2

1.4

Normalized ICC, ISB

Normalized supply current ICC, ISB

Am bi ent temper at ure (°C)

–55 80 125

35–10

0.0

0.2

0.6

0.8

0.4

1.0

1.2

1.4

Normalized ICC, ISB

Normalized supply curr ent ICC, ISB

vs. ambient temperature Ta

vs. supply voltage VCC

ICC

ISB

ICC

ISB

Ambient temperature (°C)

-55 80 125

35-10

0.2

0.04

625

Normalized ISB1 (log scale)

Normalized supply current ISB1

vs. ambi ent t empe rat ure Ta

VCC = 5.0V

Supply voltage (V)

4.0 5.5 6.0

5.04.5

0.8

0.9

1.1

1.2

1.0

1.3

1.4

1.5

Nor malized acces s time

Normalized access time tAA

Ambient temperature (°C)

–55 80 125

35–10

0.8

0.9

1.1

1.2

1.0

1.3

1.4

1.5

Nor malized acces s time

Normalized access time tAA

Cycle frequency (MHz)

060

4020

0.0

0.2

0.6

0.8

0.4

1.0

1.2

1.4

No rm al ized ICC

Normalize d supply current ICC

vs. ambient te mper atur e Tavs. cycle fre quency 1/tRC, 1/tWC

vs. supply voltage VCC

VCC = 5.0V

Ta = 25°C

VCC = 5.0VTa = 25°C

Output voltage (V)

0.0 3.75 5.0

2.51.25

100

120

140

Output source current (mA)

Output sourc e current IOH

Output voltage (V)

0.0 3.75 5.0

2.51.25

Out put sink current (mA)

Output sink current IOL

vs. output voltage VOL

vs. o utput volt age VOH

100

120

140

VCC = 5.0V

Ta = 25°C VCC = 5.0V

Ta = 25°C

Capacitance (pF)

0750

1000

500250

Chang e in tAA (ns )

Typical access time change ∆tAA

vs. output capacitive loading

VCC = 4.5V

AS7C1028

AS7C1028L

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Alliance Semiconductor reserves the right to make changes in this data sheet at any time to improve design and supply the best product possible. Publication of advance information does not constitute a

committment to produce or supply the product described. The company cannot assume responsibility for circuits shown or represent that they are free from patent infringement. Alliance products are not

authorized for use as critical components in life support devices or systems without the express written approval of the president of Alliance. ProMotion® and the Alliance logo are registered trademarks

of Alliance Semiconductor Corporation. All other trademarks are property of their respective holders.

Ordering codes

Shaded areas contain advance information.

Part numbering system

Package \ Access Time 12 ns 15 ns 20 ns 25 ns 35 ns

Plastic DIP, 300 mil AS7C1028-12TPC

AS7C1028L-12TPC

AS7C1028-15TPC

AS7C1028L-15TPC

AS7C1028-20TPC

AS7C1028L-20TPC

AS7C1028-25TPC

AS7C1028L-25TPC

AS7C1028-35TPC

AS7C1028L-35TPC

Plastic DIP, 400 mil AS7C1028-12PC

AS7C1028L-12PC

AS7C1028-15PC

AS7C1028L-15PC

AS7C1028-20PC

AS7C1028L-20PC

AS7C1028-25PC

AS7C1028L-25PC

AS7C1028-35PC

AS7C1028L-35PC

Plastic SOJ, 300 mil AS7C1028-12TJC

AS7C1028L-12TJC

AS7C1028-15TJC

AS7C1028L-15TJC

AS7C1028-20TJC

AS7C1028L-20TJC

AS7C1028-25TJC

AS7C1028L-25TJC

AS7C1028-35TJC

AS7C1028L-35TJC

Plastic SOJ, 400 mil AS7C1028-12JC

AS7C1028L-12JC

AS7C1028-15JC

AS7C1028L-15JC

AS7C1028-20JC

AS7C1028L-20JC

AS7C1028-25JC

AS7C1028L-25JC

AS7C1028-35JC

AS7C1028L-35JC

AS7C 1028 X –XX X C

SRAM prefix Device number Blank = Standard power

L = Low power Access time

Package: TP = PDIP 300 mil

P = PDIP 400 mil

TJ = SOJ 300 mil

J = SOJ 400 mil

Commercial temperature range,

0°C to 70 °C