2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM Features DDR2 SDRAM Mini-RDIMM MT18HTS25672(P)K - 2GB MT18HTS51272(P)K - 4GB For component data sheets, refer to Micron's Web site: www.micron.com Features Figure 1: * 244-pin, mini registered dual in-line memory module (Mini-RDIMM) * Fast data transfer rates: PC2-3200, PC2-4200, or PC2-5300 * Supports ECC error detection and correction * 2GB (512 Meg x 72) and 4GB (1,024 Meg x 72) * VDD = VDDQ = +1.8V * VDDSPD = +1.7V to +3.6V * JEDEC-standard 1.8V I/O (SSTL_18-compatible) * Differential data strobe (DQS, DQS#) option * 4n-bit prefetch architecture * Multiple internal device banks for concurrent operation * Supports redundant output strobe (RDQS/RDQS#) * Programmable CAS latency (CL) * Posted CAS additive latency (AL) * WRITE latency = READ latency - 1 tCK * Programmable burst length (BL) 4 or 8 * Adjustable data-output drive strength * 64ms, 8,192-cycle refresh * On-die termination (ODT) * Serial presence-detect (SPD) with EEPROM * Gold edge contacts * Dual rank, TwinDieTM (2COB) DRAM devices * Phase-lock loop (PLL) to reduce loading on system clock Table 1: 244-Pin Mini-RDIMM (MO-244) PCB height 30.0mm (1.18in) Options Marking * Parity * Operating temperature1 - Commercial (0C TA +70C) - Industrial (-40C TA +85C) * Package - 244-pin DIMM (Pb-free) * Frequency/CAS latency2 - 3.0ns @ CL = 5 (DDR2-667) - 3.75ns @ CL = 4 (DDR2-533) P None I Y -667 -53E Notes: 1. Contact Micron for industrial temperature module offerings. 2. CL = CAS (READ) latency; registered mode will add one clock cycle to CL. Key Timing Parameters Data Rate (MT/s) Speed Grade CL = 5 CL = 4 CL = 3 RCD (ns) t RP (ns) -667 -53E 667 - 533 533 400 400 15 15 15 15 PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512x72K.fm - Rev. B 9/07 EN t 1 t RC (ns) 55 55 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM Features Table 2: Address Table Parameter Refresh count Row address Device bank address Device page size per bank TwinDie device configuration Column address Module rank address Table 3: 2GB 4GB 8K 16K (A0-A13) 8 (BA0- BA2) 1KB 2Gb TwinDie (256 Meg x 8) 1K (A0-A9) 2 (S0#, S1#) 8K 32K (A0-A14) 8 (BA0-BA2) 1KB 4Gb TwinDie (512 Meg x 8) 1K (A0-A9) 2 (S0#, S1#) Part Numbers and Timing Parameters - 2GB Modules Base Device: MT47H256M8THN,1 2Gb TwinDie DDR2 SDRAM Part Number2 MT18HTS25672(P)KY-667__ MT18HTS25672(P)KY-53E__ Table 4: Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) 2GB 2GB 256 Meg x 72 256 Meg x 72 5.3 GB/s 4.3 GB/s 3.0ns/667 MT/s 3.75ns/533 MT/s 5-5-5 4-4-4 Part Numbers and Timing Parameters - 4GB Modules Base Device: MT47H512M8THM,1 4Gb TwinDie DDR2 SDRAM Part Number2 MT18HTS51272(P)KY-667__ MT18HTS51272(P)KY-53E__ Notes: PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512x72K.fm - Rev. B 9/07 EN Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) 4GB 4GB 512 Meg x 72 512 Meg x 72 5.3 GB/s 4.3 GB/s 3.0ns/667 MT/s 3.75ns/533 MT/s 5-5-5 4-4-4 1. Data sheets for the base devices can be found on Micron's Web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT18HTS25672PKY667E1. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Table 5: Pin Assignments 244-Pin Mini-RDIMM Front 244-Pin Mini-RDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 VREF 32 VSS 63 VDDQ 94 DQS5# 123 VSS 154 2 3 4 VSS DQ0 DQ1 33 34 35 DQ24 DQ25 VSS 64 65 66 A2 VDD VSS 95 96 97 DQS5 VSS DQ42 124 125 126 DQ4 DQ5 VSS 155 156 157 5 VSS 36 DQS3# 67 VSS 98 DQ43 127 6 DQS0# 37 DQS3 68 99 VSS 128 7 8 9 10 11 12 DQS0 VSS DQ2 DQ3 VSS DQ8 38 39 40 41 42 43 VSS DQ26 DQ27 VSS CB0 CB1 69 70 71 72 73 74 NU/ PAR_IN VDD A10 BA0 VDD WE# VDDQ 100 101 102 103 104 105 DQ48 DQ49 VSS SA2 NC VSS 13 DQ9 44 VSS 75 CAS# 106 14 VSS 45 DQS8# 76 VDDQ 15 DQS1# 46 DQS8 77 16 17 18 19 20 21 DQS1 VSS NC NC VSS DQ10 47 48 49 50 51 52 VSS CB2 CB3 VSS NC VDDQ 22 DQ11 53 23 VSS 24 25 185 A3 186 187 188 A1 VDD CK0 189 CK0# 220 VSS 190 VDD 221 DQ52 129 130 131 132 133 134 DM0/ RDQS0 NU/ RDQS0# VSS DQ6 DQ7 VSS DQ12 DQ13 DQ29 VSS DM3/ RDQS3 158 NU/ RDQS3# 159 VSS NU/ RDQS5# 217 VSS 218 DQ46 219 DQ47 160 161 162 163 164 165 191 192 193 194 195 196 A0 BA1 VDD RAS# VDDQ S0# 222 223 224 225 226 227 DQS6# 135 VSS 166 VDDQ 107 DQS6 136 ODT0 S1# 108 VSS 137 A13 230 78 79 80 81 82 83 ODT1 VDDQ NC VSS DQ32 DQ33 109 110 111 112 113 114 DQ50 DQ51 VSS DQ56 DQ57 VSS 138 139 140 141 142 143 DM1/ RDQS1 NU/ RDQS1# VSS NC NC VSS DQ14 DQ15 DM8/ 197 RDQS8 167 NU/ 198 RDQS8# 168 VSS 199 169 170 171 172 173 174 CB6 CB7 VSS NC VDDQ CKE1 200 201 202 203 204 205 VDD NC VSS DQ36 DQ37 VSS 231 232 233 234 235 236 CKE0 84 VSS 115 DQS7# 144 VSS 175 VDD 206 54 VDD 85 DQS4# 116 DQS7 145 DQ20 1761 NU/A15 DQ16 DQ17 55 56 86 87 DQS4 VSS 117 118 VSS DQ58 146 147 DQ21 VSS 1772 NU/A14 178 VDDQ 26 VSS 57 BA2 NU/ ERR_OUT VDDQ DM4/ RDQS4 207 NU/ RDQS4# 208 VSS 239 209 DQ38 240 88 DQ34 119 DQ59 148 179 A12 210 DQ39 241 VSS 27 DQS2# 58 A11 89 DQ35 120 VSS 149 180 A9 211 VSS 242 SDA 28 29 30 31 DQS2 VSS DQ18 DQ19 59 60 61 62 A7 VDD A5 A4 90 91 92 93 VSS DQ40 DQ41 VSS 121 122 SA0 SA1 150 151 152 153 DM2/ RDQS2 NU/ RDQS2# VSS DQ22 DQ23 VSS 181 182 183 184 VDD A8 A6 VDDQ 212 213 214 215 DQ44 DQ45 VSS DM5/ RDQS5 243 244 SCL VDDSPD Notes: PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512x72K.fm - Rev. B 9/07 EN DQ28 DQ30 DQ31 VSS CB4 CB5 VSS 216 DQ53 VSS RFU RFU VSS DM6/ RDQS6 228 NU/ RDQS6# 229 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7/ RDQS7 237 NU/ RDQS7# 238 VSS DQ62 DQ63 1. Pin 176 is NU for non-parity and A15 for parity. 2. Pin 177 is NU for 2GB and A14 for 4GB. 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM Pin Assignments and Descriptions Table 6: Pin Descriptions Symbol Type A0-A15 Input (SSTL_18) BA0-BA2 Input (SSTL_18) CK0, CK0# Input (SSTL_18) CKE0, CKE1 Input (SSTL_18) Input (SSTL_18) ODT0, ODT1 PAR_IN RAS#, CAS#, WE# S0#, S1# SA0-SA2 SCL DQ0-DQ63 DQS0-DQS8 CB0-CB7 DM0-DM8/ RDQS0-RDQS8 SDA ERR_OUT VDD VDDQ VDDSPD VREF Input (SSTL_18) Input (SSTL_18) Input (SSTL_18) Input (SSTL_18) Input (SSTL_18) I/O (SSTL_18) I/O (SSTL_18) I/O (SSTL_18) I/O (SSTL_18) I/O (SSTL_18) Output (open drain) Supply Supply Supply Supply PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512x72K.fm - Rev. B 9/07 EN Description Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0-BA2) or all device banks (A10 HIGH). The address inputs also provide the opcode during a LOAD MODE command. A0-A13 (2GB) and A0-A14 (4GB). A0-A15 are connected for parity. Bank address inputs: BA0-BA2 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0-BA2 define which mode register, including MR, EMR, EMR (2), and EMR (3), is loaded during the LOAD MODE command. Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#. Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. On-Die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each of the following pins: DQ, DQS, DQS#, RDQS, RDQS#, CB, and DM. The ODT input will be ignored if disabled via the LOAD MODE command. Parity bit for the address and control bus. Non-parity version is not used. Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Chip select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# provides for external rank selection on systems with multiple ranks. S# is considered part of the command code. Presence-detect address inputs: These pins are used to configure the presence-detect device. Serial clock for presence-detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Data input/output: Bidirectional data bus. Data strobe: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, center-aligned with write data. DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. Check bits. Data input mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. If RDQS is disabled, DQS9-DQS17 become DM0-DM8 and DQS9#-DQS17# are not used. Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module. Parity error found on the address and control bus. Non-parity version is not used. Power supply: 1.8V 0.1V. DQ power supply: 1.8V 0.1V. Serial EEPROM positive power supply: +1.7V to +3.6V. SSTL_18 reference voltage (VDD/2). 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM Pin Assignments and Descriptions Table 6: Pin Descriptions (continued) Symbol Type VSS NC NU RFU Supply - - - PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512x72K.fm - Rev. B 9/07 EN Description Ground. No connect: These pins are not connected on the module. Not used: These pins are not required to be used. Reserved for future use. 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM Functional Block Diagram Functional Block Diagram Figure 2: Functional Block Diagram RS1# RS0# DQS0 DQS0# DM0/RDQS0 NU/RDQS0# DQS4 DQS4# DM4/RDQS4 NU/RDQS4# DM/ RDQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# U1b DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# DM/ RDQS U1t DQS1 DQS1# DM1/RDQS1 NU/RDQS1# NU/ CS# DQS DQS# RDQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U5b DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# U5t DQS5 DQS5# DM5/RDQS5 NU/RDQS5# DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# U13b DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# DM/ RDQS U13t DQS2 DQS2# DM2/RDQS2 NU/RDQS2# NU/ CS# DQS DQS# RDQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U9b DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# U9t DQS6 DQS6# DM6/RDQS6 NU/RDQS6# DM/ RDQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# U2b DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# DM/ RDQS U2t DQS3 DQS3# DM3/RDQS3 NU/RDQS3# NU/ CS# DQS DQS# RDQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 U6b DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# U6t DQS7 DQS7# DM7/RDQS7 NU/RDQS7# DM/ RDQS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# U3b DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# U3t DQS8 DQS8# DM8/RDQS8 NU/RDQS8# DM/ RDQS CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# U12b DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ DM/ RDQS NU/ CS# DQS DQS# RDQS# NU/ CS# DQS DQS# RDQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U8b DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ Rank 1 = U1t-U3t, U5t , U6t, U8t, U9t, U12t, U13t U12t DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 Register x 2 U11 CK0 CK0# PLL U7 U4, U10 R e g i s t e r s SCL ERR_OUT SPD EEPROM WP A0 RS0#: Rank 0 RS1#: Rank 1 RBA0-RBA1/RBA2: DDR2 SDRAM RA0-RA13/RA14: DDR2 SDRAM RRAS#: DDR2 SDRAM RCAS#: DDR2 SDRAM RODT0: Rank 0 RODT1: Rank 1 A1 SDA A2 VSS SA0 SA1 SA2 VDDSPD RWE#: DDR2 SDRAM RCKE0: Rank 0 RCKE1: Rank 1 U8t Rank 0 = U1b-U3b, U5b , U6b, U8b, U9b, U12b, U13b RESET# PAR_IN S0# S1# BA0-BA2 A0-A15 RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 NU/ CS# DQS DQS# RDQS# SPD EEPROM VDD/VDDQ DDR2 SDRAM VREF DDR2 SDRAM VSS DDR2 SDRAM RESET# PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512x72K.fm - Rev. B 9/07 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM General Description General Description The MT18HTS25672(P)K and MT18HTS51272(P)K DDR2 SDRAM modules are highspeed, CMOS, dynamic random access 2GB and 4GB memory modules organized in a x72 configuration. DDR2 SDRAM modules use internally configured, 8-bank 2Gb TwinDie and 4Gb TwinDie DDR2 SDRAM devices. DDR2 SDRAM modules use double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM device during READs and by the memory controller during WRITEs. DQS is edgealigned with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands are registered at every positive edge of CK. Input data is registered on both edges of DQS. PLL and Register Operation DDR2 SDRAM modules operate in registered mode, where the command/address input signals are latched in the registers on the rising clock edge and sent to the DDR2 SDRAM devices on the following rising clock edge (data access is delayed by one clock cycle). A phase-lock loop (PLL) on the module receives and redrives the differential clock signals (CK, CK#) to the DDR2 SDRAM devices. The register(s) and PLL reduce address, command, control, and clock signal loading by isolating DRAM from the system controller. PLL clock timing is defined by JEDEC specifications and ensured by use of the JEDEC clock reference board. Registered mode will add one clock cycle to CL. Parity Option If provided from the system memory controller, PAR_IN is compared within the register to the command and address inputs of the register. An even number of ones among these inputs is defined as valid parity. In the case that invalid parity is detected, ERR_OUT will be set LOW. Serial Presence-Detect Operation DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes are programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the DIMM's SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to VSS on the module, permanently disabling hardware write protect. PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512x72K.fm - Rev. B 9/07 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed in Table 7 may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in the device data sheet are not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 7: Symbol VDD/VDDQ VIN, VOUT II IOZ IVREF TA TC1 Absolute Maximum DC Ratings Parameter Min Max Units VDD/VDDQ supply voltage relative to VSS Voltage on any pin relative to VSS Address inputs Input leakage current; Any input 0V VIN VDD; VREF input 0V VIN 0.95V (All other pins not under RAS#, CAS#, WE# S#, test = 0V) CKE, BA, ODT CK, CK# Output leakage current; 0V VOUT VDDQ; DQs and DQ, DQS, DQS# ODT are disabled VREF leakage current; VREF = Valid VREF level Module ambient operating temperature Commercial Industrial DDR2 SDRAM component case operating Commercial temperature2 Industrial -0.5 -0.5 -5 +2.3 +2.3 +5 V V A -250 -10 +250 +10 A -36 0 -40 0 -40 +36 +70 +85 +85 +95 A C C C C Notes: 1. The refresh rate is required to double when 85C < TC 95C. 2. For further information, refer to technical note "TN-00-08: Thermal Applications," available on Micron's Web site. Input Capacitance Micron encourages designers to simulate the performance of the module to achieve optimum values. Simulations are significantly more accurate and realistic than a gross estimation of module capacitance when inductance and delay parameters associated with trace lengths are used in simulations. JEDEC modules are currently designed using simulations to close timing budgets. Component AC Timing and Operating Conditions Recommended AC operating conditions are given in the DDR2 component data sheets. Component specifications are available on Micron's Web site. Module speed grades correlate with component speed grades, as shown in Table 8. Table 8: Module and Component Speed Grades Module Speed Grade Component Speed Grade -667 -53E -3 -37E PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512x72K.fm - Rev. B 9/07 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM Electrical Specifications IDD Specifications Table 9: IDD Specifications and Conditions - 2GB Values are shown for the MT47H256M8 DDR2 SDRAM only and are computed from values specified in the 2Gb TwinDie (256 Meg x 8) component data sheet Parameter/Condition Symbol -667 -53E Units ICDD0 = (IDD), = (IDD), Operating one bank active-precharge current: tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching ICDD1 Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), t RCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W ICDD2P Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating ICDD2Q Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# ICDD2N is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching ICDD3P Active power-down current: All device banks open; Fast PDN exit tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs MR[12] = 0 are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 t t ICDD3N Active standby current: All device banks open; CK = CK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current: All device banks open; Continuous burst writes; ICDD4W BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching ICDD4R Operating burst read current: All device banks open; Continuous burst reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching ICDD5 Burst refresh current: tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching ICDD6 Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating ICDD7 Operating bank interleave read current: All device banks interleaving reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), t RC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching 918 828 mA 1,008 963 mA 126 126 mA 603 477 mA 648 513 mA 468 378 mA 153 153 mA 738 603 mA 1,548 1,278 mA 1,548 1,413 mA 2,448 2,358 mA 126 126 mA 2,808 2,718 mA tCK PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512x72K.fm - Rev. B 9/07 EN tCK 9 tRC tRC Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM Electrical Specifications Table 10: IDD Specifications and Conditions - 4GB Values are shown for the MT47H512M8 DDR2 SDRAM only and are computed from values specified in the 4Gb TwinDie (512 Meg x 8) component data sheet Parameter/Condition tCK tCK tRC tRC Operating one bank active-precharge current: = (IDD), = (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), t RCD =tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Fast PDN exit Active power-down current: All device banks open; tCK = tCK (IDD); CKE is LOW; Other control and address bus MR[12] = 0 inputs are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current: All device banks open; Continuous burst reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current: tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current: All device banks interleaving reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512x72K.fm - Rev. B 9/07 EN 10 Symbol -667 -53E Units ICDD0 1,017 927 mA ICDD1 1,422 1,062 mA ICDD2P 144 144 mA ICDD2Q 567 477 mA ICDD2N 657 567 mA ICDD3P 432 387 mA 162 162 mA ICDD3N 612 522 mA ICDD4W 1,467 1,287 mA ICDD4R 1,647 1,467 mA ICDD5 2,637 2,457 mA ICDD6 144 144 mA ICDD7 3,177 2,772 mA Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM Register and PLL Specifications Register and PLL Specifications Table 11: Register Specifications SSTU32866 devices or equivalent JESD82-16 Parameter DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage Output high voltage Output low voltage Input current Static standby Static operating Symbol Pins Condition Min Max Units VIH(DC) Address, control, command Address, control, command Address, control, command Address, control, command Parity output Parity output All pins All pins All pins SSTL_18 VREF(DC) + 125 VDDQ + 250 mV SSTL_18 0 VREF(DC) - 125 mV SSTL_18 VREF(DC) + 250 VDD mV SSTL_18 0 VREF(DC) - 250 mV 1.2 - -5 - - - 0.5 +5 100 40 V V A A mA - Varies by manufacturer A - Varies by manufacturer A 2.5 3.5 pF - Varies by manufacturer pF VIL(DC) VIH(AC) VIL(AC) VOH VOL II IDD IDD Dynamic operating (clock tree) IDDD Dynamic operating (per each input) IDDD Input capacitance (per device, per pin) Input capacitance (per device, per pin) CI CI Notes: PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512x72K.fm - Rev. B 9/07 EN LVCMOS LVCMOS VI = VDDQ or VSSQ RESET# = VSSQ (IO = 0) RESET# = VSSQ; VI = VIH(AC) or VIL(DC) IO = 0 n/a RESET# = VDD, VI = VIH(AC) or VIL(AC), IO = 0; CK and CK# switching 50 percent duty cycle n/a RESET# = VDD, VI = VIH(AC) or VIL(AC), IO = 0; CK and CK# switching 50 percent duty cycle; One data input switching at tCK/2, 50 percent duty cycle All inputs except VI = VREF 250mV; RESET# VDDQ = 1.8V RESET# VI = VDDQ or VSSQ 1. Timing and switching specifications for the register listed above are critical for proper operation of the DDR2 SDRAM registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed information for this register is available in JEDEC standard JESD82. 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM Register and PLL Specifications Table 12: PLL Specifications CU877 device or Equivalent JESD82-8.01 Parameter DC high-level input voltage DC low-level input voltage Input voltage (limits) DC high-level input voltage DC low-level input voltage Input differential-pair cross voltage Input differential voltage Input differential voltage Input current Symbol Pins Condition VIH VIL VIN VIH VIL VIX RESET# RESET# RESET#, CK, CK# CK, CK# CK, CK# CK, CK# LVCMOS LVCMOS - Differential Input Differential Input Differential Input VID(DC) VID(AC) II Differential Input Differential Input VI = VDDQ or VSSQ VI = VDDQ or VSSQ RESET# = VSSQ; VI = VIH(AC) or VIL(DC) CK = CK# = LOW CK, CK# = 270 MHz, all outputs open (not connected to PCB) VI = VDDQ or VSSQ Output disabled current IODL CK, CK# CK, CK# RESET# CK, CK# - Static supply current Dynamic supply IDDLD IDD - n/a CIN Each input Input capacitance Table 13: Min Max Units 0.65 x VDD - - 0.35 x VDD -0.3 VDDQ + 0.3 0.65 x VDD - - 0.35 x VDD (VDDQ/2) - 0.15 (VDDQ/2) + 0.15 V V V V V V 0.3 0.6 -10 -250 100 VDDQ + 0.4 VDDQ + 0.4 +10 +250 - V V A A A - - 500 300 A mA 2 3 pF PLL Clock Driver Timing Requirements and Switching Characteristics Parameter Stabilization time Input clock slew rate SSC modulation frequency SSC clock input frequency deviation PLL loop bandwidth (-3dB from unity gain) Notes: PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512x72K.fm - Rev. B 9/07 EN Symbol Min Max Units tL - 1.0 30 0 2.0 15 4 33 -0.50 - s V/ns kHZ % MHz tslr(i) - - - 1. PLL timing and switching specifications are critical for proper operation of the DDR2 DIMM. This is a subset of parameters for the specific PLL used. Detailed PLL information is available in JEDEC standard JESD82-8.01. 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM Serial Presence-Detect Serial Presence-Detect Table 14: Serial Presence-Detect EEPROM DC Operating Conditions Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage: IOUT = 3mA Input leakage current: VIN = GND to VDD Output leakage current: VOUT = GND to VDD Standby current Power supply current, READ: SCL clock frequency = 100 kHz Power supply current, WRITE: SCL clock frequency = 100 kHz Table 15: Symbol Min Max Units VDDSPD VIH VIL VOL ILI ILO ISB ICCR ICCW 1.7 VDDSPD x 0.7 -0.6 - 0.10 0.05 1.6 0.4 2 3.6 VDDSPD + 0.5 VDDSPD x 0.3 0.4 3 3 4 1 3 V V V V A A A mA mA Serial Presence-Detect EEPROM AC Operating Conditions Parameter/Condition SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time Notes: PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512x72K.fm - Rev. B 9/07 EN Symbol Min Max Units Notes tAA 0.2 1.3 200 - 0 0.6 0.6 - 1.3 - - 100 0.6 0.6 - 0.9 - - 300 - - - 50 - 0.3 400 - - - 10 s s ns ns s s s ns s s kHz ns s s ms 1 tBUF tDH tF tHD:DAT tHD:STA tHIGH tI tLOW tR fSCL tSU:DAT tSU:STA t SU:STO tWRC 2 2 3 4 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM Serial Presence-Detect Table 16: Byte Serial Presence-Detect Matrix Description Entry (Version) 2GB 4GB 11 Number of SPD bytes used by Micron Total number of bytes in SPD device Fundamental memory type Number of row addresses on DRAM Number of column addresses on DRAM DIMM height and module ranks Module data width Reserved Module voltage interface levels SDRAM cycle time, tCK (CL = MAX value, see byte 18) SDRAM access from clock,tAC (CL = MAX value, see byte 18) Module configuration type 12 13 14 15 16 17 18 Refresh rate/type DDR2 device width (primary DDR2) Error-checking DDR2 data width Reserved Burst lengths supported Number of banks on DDR2 device CAS latencies supported 19 20 Module thickness DDR2 DIMM type 80 08 08 0E 0A 61 48 00 05 30 3D 45 50 02 06 82 08 08 00 0C 08 38 18 01 10 80 08 08 0F 0A 61 48 00 05 30 3D 45 50 02 06 82 08 08 00 0C 08 38 18 01 10 21 22 23 DDR2 module attributes DDR2 device attributes: weak driver (01) and 50 ODT (03) DDR2 cycle time, tCK, MAX CL - 1 24 DDR2 access from CK, tAC, MAX CL - 1 25 DDR2 cycle time, tCK, MAX CL - 2 26 DDR2 access from CK, tAC, MAX CL - 2 27 28 29 30 31 32 MIN row precharge time, tRP MIN row active-to-row active, tRRD MIN RAS#-to-CAS# delay, tRCD MIN RAS# pulse width, tRAS1 Module rank density Address and command setup time, tISb 33 Address and command hold time, tIHb 34 Data/data mask input setup time, tDSb 128 256 DDR2 SDRAM 14, 15 10 30mm, dual rank 72 0 SSTL 1.8V -667 -53E -667 -53E ECC ECC and parity 7.81s/SELF 8 8 0 4, 8 8 -667 (5, 4, 3) -53E (4, 3) - Registered MiniRDIMM 1 PLL, 2 Reg -667 -53E -667 -53E -667 -53E -667 -53E -667 -53E - - - - 1GB, 2GB -667 -53E -667 -53E - 05 03 01 3D 50 45 50 50 00 45 00 3C 1E 3C 2D 01 20 25 27 37 10 05 03 01 3D 50 45 50 50 00 45 00 3C 1E 3C 2D 02 20 25 27 37 10 0 1 2 3 4 5 6 7 8 9 10 PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512x72K.fm - Rev. B 9/07 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM Serial Presence-Detect Table 16: Byte Serial Presence-Detect Matrix (continued) Description 35 Data/data mask input hold time, DHb 36 37 38 39 40 41 42 WRITE recovery time, tWR WRITE-to-READ command delay, tWTR READ-to-PRECHARGE command delay, tRTP Memory analysis probe Extension for bytes 41 and 42 MIN active-to-active auto/refresh time, tRC MIN AUTO REFRESH-to-ACTIVE/AUTO REFRESH command period, tRFC DDR2 device MAX cycle time, tCK (MAX) DDR2 device MAX DQS-DQ skew time, tDQSQ 43 44 45 Entry (Version) 2GB 4GB -667 -53E - - - - - - - 07 22 3C 1E 1E 00 06 3C 7F 07 22 3C 1E 1E 00 06 3C C5 8.0ns -667 -53E -667 -53E - - Release 1.2 -667 -53E MICRON (continued) 1-12 - 1-9 - - - - - - 80 18 1E 22 28 0F 00 12 21/25 CC/D0 2C 00 Variable data Variable data 01-09 00 Variable data Variable data Variable data 00 FF 80 18 1E 22 28 0F 00 12 69/6G 14/18 2C 00 Variable data Variable data 01-09 00 Variable data Variable data Variable data 00 FF t DDR2 device MAX read data hold skew factor, tQHS 46 47-61 62 63 PLL relock time Optional features, not supported SPD revision Checksum for bytes 0-62 ECC/ECC and parity 64 Manufacturer's JEDEC ID code 65-71 Manufacturer's JEDEC ID code 72 Manufacturing location 73-90 Module part number (ASCII) 91 PCB identification code 92 PCB identification code (continued) 93 Year of manufacture in BCD 94 Week of manufacture in BCD 95-98 Module serial number 99-127 Reserved for manufacturer-specific data 128-255 Reserved for customer-specific data Notes: PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512x72K.fm - Rev. B 9/07 EN 1. The tRC SPD values shown are JEDEC DDR2 device specification values. The actual Micron DDR2 device specification is tRC = 55ns for all speed grades. 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM Module Dimensions Module Dimensions Figure 3: 244-Pin DDR2 Mini-RDIMM Front view 3.8 (0.15) MAX 82.127 (3.233) 81.873 (3.223) 2.0 (0.079) R X2 U4 U1 U2 U3 U5 U6 1.0 (0.039) R X2 1.8 (0.071) D X2 30.152 (1.187) 29.848 (1.175) 20.0 (0.787) TYP 10.0 (0.394) TYP 6.0 (0.236) TYP 1.0 (0.039) TYP 2.0 (0.079) TYP Pin 1 0.5 (0.02) R 0.6 (0.024) 0.45 (0.018) TYP TYP Pin 122 1.1 (0.043) 0.9 (0.035) 42.0 (1.689) TYP 78.0 (3.071) TYP Back view U7 U10 U8 U9 U12 U13 U11 3.3 (0.13) TYP 3.6 (0.142) TYP Pin 244 Pin 123 33.6 (1.323) TYP 38.4 (1.512) TYP 3.2 (0.126) TYP Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for additional design dimensions. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, the Micron logo, and TwinDie are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef82218d23/Source: 09005aef82218d00 HTS18C256_512x72K.fm - Rev. B 9/07 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved.