THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com Wideband, Low-Distortion Fully Differential Amplifiers Check for Samples: THS4502, THS4503 FEATURES DESCRIPTION * * * * * * * The THS4502 and THS4503 are high-performance fully differential amplifiers from Texas Instruments. The THS4502, featuring power-down capability, and the THS4503, without power-down capability, set new performance standards for fully differential amplifiers with unsurpassed linearity, supporting 14-bit operation through 40 MHz. Package options include the 8-pin SOIC and the 8-pin MSOP with PowerPADTM for a smaller footprint, enhanced ac performance, and improved thermal dissipation capability. 1 2 * * * Fully Differential Architecture Bandwidth: 370 MHz Slew Rate: 2800 V/s IMD3: -95 dBc at 30 MHz OIP3: 51 dBm at 30 MHz Output Common-Mode Control Wide Power Supply Voltage Range: 5 V, 5 V, 12 V, 15 V Centered Input Common-Mode Range Power-Down Capability (THS4502) Evaluation Module Available APPLICATIONS * * * * * High Linearity Analog-to-Digital Converter Preamplifier Wireless Communication Receiver Chains Single-Ended to Differential Conversion Differential Line Driver Active Filtering of Differential Signals VIN- 1 8 VIN+ VOCM 2 7 PD VS+ 3 6 VS- VOUT+ 4 5 VOUT- RELATED DEVICES DEVICE (1) DESCRIPTION THS4500/1 370 MHz, 2800 V/s, VICR Includes VS- THS4502/3 370 MHz, 2800 V/s, Centered VICR THS4120/1 3.3 V, 100 MHz, 43 V/s, 3.7 nVHz THS4130/1 15 V, 150 MHz, 51 V/s, 1.3 nVHz THS4140/1 15 V, 160 MHz, 450 V/s, 6.5 nVHz THS4150/1 15 V, 150 MHz, 650 V/s, 7.6 nVHz (1) Even numbered devices feature power-down capability. WARNING The THS4502 and THS4503 may have low-level oscillation when the die temperature (also known as the junction temperature) exceeds +60C. These devices are not recommended for new designs where the die temperature is expected to exceed +60C. For more information, see Maximum Die Temperature to Prevent Oscillation section. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2002-2011, Texas Instruments Incorporated THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10 pF 392 5V 0.1 F 10 F 374 50 + 56.2 VS 1 F 402 - 5V 24.9 THS4502 VOCM + - 24.9 -5 V IN ADC 14 Bit/80 MSps IN Vref 0.1 F 10 F 392 10 pF THIRD-ORDER INTERMODULATION DISTORTION -62 10 392 50 -68 374 5V VOUT +- 2.5 V 56.2 VS 402 -74 800 VOCM - + 12 -5 V 392 Bits IMD 3 - Third-Order Intermodulation Distortion - dBc APPLICATION CIRCUIT DIAGRAM -80 -86 14 -92 -98 16 0 20 40 60 80 100 f - Frequency - MHz PACKAGE/ORDERING INFORMATION ORDERABLE PACKAGE AND NUMBER TEMPERATURE 0C to 70C -40C to 85C (1) PLASTIC MSOP (1) PowerPAD PLASTIC SMALL OUTLINE PLASTIC MSOP (D) (DGN) SYMBOL (DGK) SYMBOL THS4502CD THS4502CDGN BCG THS4502CDGK ATX THS4503CD THS4503CDGN BCK THS4503CDGK ATY THS4502ID THS4502IDGN BCI THS4502IDGK ASX THS4503ID THS4503IDGN BCL THS4503IDGK ASY All packages are available taped and reeled. The R suffix standard quatity is 2500. The T suffix standard quantity is 250 (e.g., THS4502DT). PIN ASSIGNMENTS D, DGN, DGK THS4502 (TOP VIEW) 2 D, DGN, DGK THS4503 (TOP VIEW) V IN- 1 8 V IN+ V IN- 1 8 V IN+ V OCM 2 7 PD V OCM 2 7 NC V S+ 3 6 V S- V S+ 3 6 V S- V OUT+ 4 5 V OUT- V OUT+ 4 5 V OUT- Submit Documentation Feedback Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) UNIT Supply voltage, VS 16.5 V VS Input voltage, VI Output current, IO 150 mA (2) Differential input voltage, VID 4V Continuous power dissipation Maximum junction temperature, TJ See Dissipation Rating Table (3) 150C Maximum junction temperature, continuous operation, long term reliability, TJ Maximum junction temperature to prevent oscillation, TJ Operating free-air temperature range, TA (4) 60C C suffix 0C to 70C I suffix -40C to 85C Storage temperature range, Tstg (1) (2) (3) (4) (5) 125C (5) -65C to 150C Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. The THS450x may incorporate a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI technical brief SLMA002 for more information about utilizing the PowerPAD thermally enhanced package. The absolute maximum temperature under any condition is limited by the constraints of the silicon process. The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device. See Maximum Die Temperature to Prevent Oscillation section in the Application Information of this data sheet. PACKAGE DISSIPATION RATINGS (1) PACKAGE JC (C/W) JA (1) (C/W) D (8 pin) 38.3 97.5 DGN (8 pin) 4.7 58.4 DGK (8 pin) 54.2 260 This data was taken using the JEDEC standard High-K test PCB. RECOMMENDED OPERATING CONDITIONS MIN Dual supply Supply voltage Single supply C suffix Operating free- air temperature, TA I suffix Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 4.5 NOM MAX 5 7.5 5 15 0 70 -40 85 Submit Documentation Feedback UNIT V C 3 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VS = 5 V Rf = Rg = 499 , RL = 800 , G = +1, Single-ended input unless otherwise noted. THS4502 AND THS4503 PARAMETER TEST CONDITIONS OVER TEMPERATURE (1) TYP 25C 25C 0C to 70C -40C to 85C UNITS MIN/ TYP/ MAX AC PERFORMANCE G = +1, PIN = -20 dBm, Rf = 392 370 MHz Typ G = +2, PIN = -30 dBm, Rf = 1 k 175 MHz Typ G = +5, PIN = -30 dBm, Rf = 1.3 k 70 MHz Typ G = +10, PIN = -30 dBm, Rf = 1.3 k 30 MHz Typ G > +10 300 MHz Typ PIN = -20 dBm 150 MHz Typ VP = 2 V 220 MHz Typ Slew rate 4 VPP Step 2800 V/s Typ Rise time 2 VPP Step 0.8 ns Typ Fall time 2 VPP Step 0.6 ns Typ Settling time to 0.01% VO = 4 VPP 8.3 ns Typ Settling time to 0.1% VO = 4 VPP 6.3 ns Typ Small-signal bandwidth Gain-bandwidth product Bandwidth for 0.1 dB flatness Large-signal bandwidth Harmonic distortion G = +1, VO = 2 VPP Typ f = 8 MHz -83 dBc Typ f = 30 MHz -74 dBc Typ f = 8 MHz -97 dBc Typ f = 30 MHz -78 dBc Typ VO = 2VPP, fc= 30 MHz, Rf = 392 , 200 kHz tone spacing -94 dBc Typ fc = 30 MHz, Rf = 392 , Referenced to 50 52 dBm Typ Input voltage noise f > 1 MHz 6.8 nV/Hz Typ Input current noise f > 100 kHz 1.7 pA/Hz Typ Overdrive = 5.5 V 75 ns Typ 2nd harmonic 3rd harmonic Third-order intermodulation distortion Third-order output intercept point Overdrive recovery time DC PERFORMANCE Open-loop voltage gain 55 52 50 50 dB Min Input offset voltage -1 -4/+2 -5/+3 -6/+4 mV Max 10 10 V/C Typ 4 4.6 5 5.2 A Max 10 10 nA/C Typ Average offset voltage drift Input bias current Average bias current drift Input offset current 0.5 1 Average offset current drift 2 2 A Max 40 40 nA/C Typ V Min INPUT Common-mode input range Common-mode rejection ratio 4.0 3.7 3.4 3.4 80 74 70 70 107 || 1 Input impedance dB Min || pF Typ Min OUTPUT Differential output voltage swing RL = 1 k 8 7.6 7.4 7.4 V Differential output current drive RL = 20 120 110 100 100 mA Min PIN = -20 dBm, f = 100 kHz -58 dB Typ f = 1 MHz 0.1 Typ Output balance error Closed-loop output impedance (single-ended) (1) 4 See Maximum Die Temperature to Prevent Oscillation section in the Application Information of this data sheet. Submit Documentation Feedback Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VS = 5 V (continued) Rf = Rg = 499 , RL = 800 , G = +1, Single-ended input unless otherwise noted. THS4502 AND THS4503 PARAMETER TEST CONDITIONS OVER TEMPERATURE (1) TYP 25C 0C to 70C 25C -40C to 85C UNITS MIN/ TYP/ MAX OUTPUT COMMON-MODE VOLTAGE CONTROL Small-signal bandwidth RL = 400 180 MHz Typ Slew rate 2 VPP step 87 V/s Typ 0.98 V/V Min Minimum gain 1 0.98 0.98 Maximum gain 1 1.02 1.02 1.02 V/V Max Common-mode offset voltage +2 -1.6/+6.8 -3.6/+8.8 -4.6/+9.8 mV Max 100 150 170 170 A Max 4 3.7 3.4 3.4 V Min Input bias current VOCM = 2.5 V Input voltage range Input impedance k || pF Typ Maximum default voltage VOCM left floating 25 || 1 0 0.05 0.10 0.10 V Max Minimum default voltage VOCM left floating 0 -0.05 -0.10 -0.10 V Min Specified operating voltage 5 8.25 8.25 8.25 V Max Maximum quiescent current 23 28 32 34 mA Max Minimum quiescent current 23 18 14 12 mA Min Power supply rejection (PSRR) 80 76 73 70 dB Min V Min POWER SUPPLY POWER DOWN (THS4502 ONLY) Enable voltage threshold Device enabled ON above -2.9 V Disable voltage threshold Device disabled OFF below -4.3 V -2.9 V Max Power-down quiescent current 800 1000 -4.3 1200 1200 A Max Input bias current 200 240 260 260 A Max Input impedance 50 || 1 k || pF Typ Turnon time delay 1000 ns Typ Turnoff time delay 800 ns Typ UNITS MIN/T YP/M AX ELECTRICAL CHARACTERISTICS VS = 5 V Rf = Rg = 499 , RL = 800 , G = +1, Single-ended input unless otherwise noted. THS4502 AND THS4503 PARAMETER TEST CONDITIONS OVER TEMPERATURE (1) TYP 25C 25C 0C to 70C -40C to 85C AC PERFORMANCE Small-signal bandwidth G = +1, PIN = -20 dBm, Rf = 392 320 MHz Typ G = +2, PIN = -30 dBm, Rf = 1 k 160 MHz Typ G = +5, PIN = -30 dBm, Rf = 1.3 k 60 MHz Typ G = +10, PIN = -30 dBm, Rf = 1.3 k 30 MHz Typ G > +10 300 MHz Typ PIN = -20 dBm 180 MHz Typ VP = 1 V 200 MHz Typ Slew rate 2 VPP Step 1300 V/s Typ Rise time 2 VPP Step 0.6 ns Typ Fall time 2 VPP Step 0.8 ns Typ VO = 2 V Step 13.1 ns Typ Gain-bandwidth product Bandwidth for 0.1 dB flatness Large-signal bandwidth Settling time to 0.01% (1) See Maximum Die Temperature to Prevent Oscillation section in the Application Information of this data sheet. Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 Submit Documentation Feedback 5 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VS = 5 V (continued) Rf = Rg = 499 , RL = 800 , G = +1, Single-ended input unless otherwise noted. THS4502 AND THS4503 PARAMETER UNITS 8.3 ns Typ f = 8 MHz, -81 dBc Typ f = 30 MHz -60 dBc Typ 25C Settling time to 0.1% VO = 2 V Step Harmonic distortion OVER TEMPERATURE (1) TYP MIN/T YP/M AX TEST CONDITIONS 25C 0C to 70C -40C to 85C VO = 2 VPP 2nd harmonic Typ f = 8 MHz -74 dBc Typ f = 30 MHz -62 dBc Typ Input voltage noise f > 1 MHz 6.8 nV/Hz Typ Input current noise f > 100 kHz 1.6 pA/Hz Typ Overdrive = 5.5 V 75 ns Typ dB Min Max 3rd harmonic Overdrive recovery time DC PERFORMANCE Open-loop voltage gain 54 51 49 49 Input offset voltage -0.6 -3.6/+2.4 -4.6/+3.4 -5.6/+4.4 mV 10 10 V/C Typ 5 5.2 A Max 10 10 nA/C Typ 1.2 1.2 A Max 20 20 nA/C Typ Min Average offset voltage drift Input bias current 4 4.6 0.5 0.7 Average bias current drift Input offset current Average offset current drift INPUT Common-mode input range Common-mode rejection ratio 1/4 1.3 / 3.7 1.6 / 3.4 1.6 / 3.4 V 80 74 70 70 dB Min || pF Typ 107 || 1 Input Impedance OUTPUT RL = 1 k, Referenced to 2.5 V 3.3 2.8 2.6 2.6 V Min Output current drive RL = 20 100 90 80 80 mA Min Output balance error PIN = -20 dBm, f = 100 kHz -58 dB Typ f = 1 MHz 0.1 Typ Small-signal bandwidth RL = 400 180 MHz Typ Slew rate 2 VPP Step 80 V/s Typ 0.98 V/V Min Differential output voltage swing Closed-loop output impedance (single-ended) OUTPUT COMMON-MODE VOLTAGE CONTROL Minimum gain 1 Maximum gain 1 1.02 1.02 1.02 V/V Max Common-mode offset voltage 2 -2.2/6.2 -4.2/8.2 -5.2/9.2 mV Max 1 2 3 3 A Max 1/4 1.2/3.8 1.3/3.7 1.3/3.7 Input bias current VOCM = 2.5 V Input voltage range Input impedance 0.98 0.98 25 || 1 V Min k || pF Typ Maximum default voltage VOCM left floating 2.5 2.55 2.6 2.6 V Max Minimum default voltage VOCM left floating 2.5 2.45 2.4 2.4 V Min Specified operating voltage 5 16.5 16.5 16.5 V Max Maximum quiescent current 20 25 29 31 mA Max Minimum quiescent current 20 16 12 10 mA Min Power supply rejection (+PSRR) 75 72 69 66 dB Min POWER SUPPLY 6 Submit Documentation Feedback Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VS = 5 V (continued) Rf = Rg = 499 , RL = 800 , G = +1, Single-ended input unless otherwise noted. THS4502 AND THS4503 PARAMETER TEST CONDITIONS OVER TEMPERATURE (1) TYP 25C 25C 0C to 70C -40C to 85C UNITS MIN/T YP/M AX POWER DOWN (THS4502 ONLY) Enable voltage threshold Device enabled ON above 2.1 V 2.1 V Min Disable voltage threshold Device disabled OFF below 0.7 V 0.7 V Max A Max Power-down quiescent current 600 800 1200 1200 Input bias current 100 125 140 140 A Max Input impedance 50 || 1 k || pF Typ Turnon time delay 1000 ns Typ Turnoff time delay 800 ns Typ Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 Submit Documentation Feedback 7 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS Table of Graphs (5 V) FIGURE Small signal unity gain frequency response 1 Small signal frequency response 2 0.1 dB gain flatness frequency response 3 Harmonic distortion (single-ended input to differential output) vs Frequency 4, 6, 12, 14 Harmonic distortion (differential input to differential output) vs Frequency 5, 7, 13, 15 Harmonic distortion (single-ended input to differential output) vs Output voltage swing 8, 10, 16, 18 Harmonic distortion (differential input to differential output) vs Output voltage swing 9, 11, 17, 19 Harmonic distortion (single-ended input to differential output) vs Load resistance 20 Harmonic distortion (differential input to differential output) vs Load resistance 21 Third order intermodulation distortion (single-ended input to differential output) vs Frequency 22 Third order output intercept point vs Frequency 23 Slew rate vs Differential output voltage step 24 Settling time 25, 26 Large-signal transient response 27 Small-signal transient response 28 Overdrive recovery 29, 30 Voltage and current noise vs Frequency 31 Rejection ratios vs Frequency 32 Rejection ratios vs Case temperature 33 Output balance error vs Frequency 34 Open-loop gain and phase vs Frequency 35 Open-loop gain vs Case temperature 36 Input bias and offset current vs Case temperature 37 Quiescent current vs Supply voltage 38 Input offset voltage vs Case temperature 39 Common-mode rejection ratio vs Input common-mode range 40 Differential output current drive vs Case temperature 41 Harmonic distortion (single-ended and differential input to differential output) vs Output common-mode voltage 42 Small signal frequency response at VOCM 43 Output offset voltage at VOCM vs Output common-mode voltage 44 Quiescent current vs Power-down voltage 45 Turnon and turnoff delay times 46 Single-ended output impedance in power down vs Frequency 47 Power-down quiescent current vs Case temperature 48 Power-down quiescent current vs Supply voltage 49 8 Submit Documentation Feedback Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com Table of Graphs (5 V) FIGURE Small signal unity gain frequency response 50 Small signal frequency response 51 0.1 dB gain flatness frequency response 52 Harmonic distortion (single-ended input to differential output) vs Frequency 53, 54, 61, 63 Harmonic distortion (differential input to differential output) vs Frequency 55, 56, 62, 64 Harmonic distortion (single-ended input to differential output) vs Output voltage swing 57, 58, 65, 67 Harmonic distortion (differential input to differential output) vs Output voltage swing 59, 60, 66, 68 Harmonic distortion (single-ended input to differential output) vs Load resistance 69 Harmonic distortion (differential input to differential output) vs Load resistance 70 Slew rate vs Differential output voltage step 71 Large-signal transient response 72 Small-signal transient response 73 Voltage and current noise vs Frequency 74 Rejection ratios vs Frequency 75 Rejection ratios vs Case temperature 76 Output balance error vs Frequency 77 Open-loop gain and phase vs Frequency 78 Open-loop gain vs Case temperature 79 Input bias and offset current vs Case temperature 80 Quiescent current vs Supply voltage 81 Input offset voltage vs Case temperature 82 Common-mode rejection ratio vs Input common-mode range 83 Output drive vs Case temperature 84 Harmonic distortion (single-ended and differential input) vs Output common-mode range 85 Small signal frequency response at VOCM 86 Output offset voltage vs Output common-mode voltage 87 Quiescent current vs Power-down voltage 88 Turnon and turnoff delay times 89 Single-ended output impedance in power down vs Frequency 90 Power-down quiescent current vs Case temperature 91 Power-down quiescent current vs Supply voltage 92 Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 Submit Documentation Feedback 9 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (5 V Graphs) 22 20 18 0 -0.5 -1 -1.5 -2 Gain = 1 RL = 800 Rf = 392 PIN = -20 dBm VS = 5 V -3 -3.5 1 0.1 16 12 10 8 Gain = 2, Rf = 1 k 6 4 RL = 800 PIN = -30 dBm VS = 5 V 0 -2 0.1 10 100 0 Gain = 5, Rf = 1.3 k 14 2 -4 0.1 Gain = 10, Rf = 1.3 k 0.1 dB Gain Flatness - dB 1 0.5 -2.5 0.1 dB GAIN FLATNESS FREQUENCY RESPONSE SMALL SIGNAL FREQUENCY RESPONSE Small Signal Gain - dB Small Signal Unity Gain - dB SMALL SIGNAL UNITY GAIN FREQUENCY RESPONSE 1000 1 Rf = 392 -0.1 Rf = 499 -0.2 -0.3 Gain = 1 RL = 800 PIN = -20 dBm VS = 5 V -0.4 10 100 1000 -0.5 f - Frequency - MHz 1 f - Frequency - MHz Figure 1. HARMONIC DISTORTION vs FREQUENCY -40 -50 -60 -70 HD2 -80 -90 0.1 0 -20 -30 -40 -50 1 10 f - Frequency - MHz -60 -70 HD2 -80 -60 -70 HD2 -80 HD3 1 10 f - Frequency - MHz 0.1 100 1 10 100 f - Frequency - MHz Figure 6. HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING -10 -50 -60 -70 HD2 -80 -20 -30 -40 -50 0 Single-Ended Input to Differential Output Gain = 1 RL = 800 Rf = 499 f= 8 MHz VS = 5 V -10 -60 -70 HD2 -80 HD3 -90 HD3 -90 1 10 f - Frequency - MHz Figure 7. Submit Documentation Feedback 100 -20 -30 -40 Differential Input to Differential Output Gain = 1 RL = 800 Rf = 499 f= 8 MHz VS = 5 V -50 -60 -70 HD2 -80 HD3 -90 -100 -100 0.1 -50 -100 Harmonic Distortion - dBc -40 -40 Figure 5. Harmonic Distortion - dBc -30 -30 Figure 4. Differential Input to Differential Output Gain = 1 RL = 800 Rf = 499 VO = 2 VPP VS = 5 V -20 -20 -90 HD3 -100 0.1 100 Single-Ended Input to Differential Output Gain = 1 RL = 800 Rf = 499 VO = 2 VPP VS = 5 V -10 0 0 -10 Harmonic Distortion - dBc HARMONIC DISTORTION vs FREQUENCY -90 HD3 -100 10 HARMONIC DISTORTION vs FREQUENCY Differential Input to Differential Output Gain = 1 RL = 800 Rf = 499 VO = 1 VPP VS = 5 V -10 Harmonic Distortion - dBc Harmonic Distortion - dBc -30 1000 Figure 3. Harmonic Distortion - dBc Single-Ended Input to Differential Output Gain = 1 RL = 800 Rf = 499 VO = 1 VPP VS = 5 V -20 100 Figure 2. 0 0 -10 10 f - Frequency - MHz -100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 VO - Output Voltage Swing - V VO - Output Voltage Swing - V Figure 8. Figure 9. Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (5 V Graphs) (continued) HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING 0 Single-Ended Input to Differential Output Gain = 1 RL = 800 Rf = 499 f= 30 MHz VS = 5 V -30 -40 Harmonic Distortion - dBc -50 HD3 -60 -70 HD2 -80 -30 -40 -50 HD3 -60 -70 HD2 -80 -20 -30 -40 -50 -60 -70 HD2 -80 -90 -90 -90 -100 -100 -100 0 1 2 3 4 5 VO - Output Voltage Swing - V 0 6 1 2 3 4 5 0.1 Figure 12. HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs FREQUENCY 0 Single-Ended Input to Differential Output Gain = 2 RL = 800 Rf = 499 VO = 2 VPP VS = 5 V -60 -70 HD3 -80 -90 -20 -30 -40 -50 -60 -70 HD2 -80 HD3 -90 HD2 -100 1 10 f - Frequency - MHz 100 -40 -50 -60 HD2 -70 -80 HD3 1 10 f - Frequency - MHz 0.1 100 1 10 100 f - Frequency - MHz Figure 14. Figure 15. HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING 0 Differential Input to Differential Output Gain = 2 RL = 800 Rf = 1.3 k f= 8 MHz VS = 5 V -10 Harmonic Distortion - dBc -30 -40 Figure 13. Single-Ended Input to Differential Output Gain = 2 RL = 800 Rf = 1.3 k f= 8 MHz VS = 5 V -20 -30 -100 0.1 0 0 -20 -90 -100 0.1 Differential Input to Differential Output Gain = 2 RL = 800 Rf = 499 VO = 2 VPP VS = 5 V -10 Harmonic Distortion - dBc -10 -50 -10 100 Figure 11. Harmonic Distortion - dBc -40 10 f - Frequency - MHz 0 -30 1 Figure 10. Differential Input to Differential Output Gain = 1 RL = 800 Rf = 499 VO = 1 VPP VS = 5 V -20 HD3 6 VO - Output Voltage Swing - V 0 -10 Harmonic Distortion - dBc -20 Single-Ended Input to Differential Output Gain = 2 RL = 800 Rf = 499 VO = 1 VPP VS = 5 V -10 -50 -60 HD3 -70 -80 HD2 -20 -30 -40 -50 -60 Single-Ended Input to Differential Output Gain = 2 RL = 800 Rf = 1.3 k f= 30 MHz VS = 5 V -10 Harmonic Distortion - dBc Harmonic Distortion - dBc -20 0 Differential Input to Differential Output Gain = 1 RL = 800 Rf = 499 VO = 30 VPP VS = 5 V -10 Harmonic Distortion - dBc 0 -10 Harmonic Distortion - dBc HARMONIC DISTORTION vs FREQUENCY HD3 -70 -80 HD2 -20 -30 -40 -50 -60 HD3 HD2 -70 -80 -90 -90 -90 -100 -100 0 1 2 3 4 5 6 7 8 9 10 0 VO - Output Voltage Swing - V Figure 16. 1 2 3 4 5 6 7 8 VO - Output Voltage Swing - V 9 10 Figure 17. Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 -100 0 1 2 3 4 5 6 7 8 VO - Output Voltage Swing - V 9 10 Figure 18. Submit Documentation Feedback 11 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (5 V Graphs) (continued) 0 Differential Input to Differential Output Gain = 2 RL = 800 Rf = 1.3 k f= 8 MHz VS = 5 V -30 -40 -50 -20 Harmonic Distortion - dBc HD3 -60 HD2 -70 -80 -30 -40 -50 -60 HD2 -70 -80 -90 1 2 3 4 5 6 7 8 9 10 -40 -50 -60 HD2 -70 -80 HD3 -100 0 400 800 1200 0 1600 Figure 19. Figure 20. THIRD-ORDER INTERMODULATION DISTORTION vs FREQUENCY THIRD-ORDER OUTPUT INTERCEPT POINT vs FREQUENCY Gain = 1 RL = 800 Rf = 499 f= 8 MHz VS = 5 V -80 -90 -100 10 45 40 35 OIP3 RL= 800 30 Gain = 1 Rf = 392 VS = 5 V Tone Spacing = 200 kHz 25 20 2000 1500 1000 500 0 0 15 0 100 f - Frequency - MHz 2500 Normalized to 50 50 10 20 30 40 50 60 70 80 90 100 Figure 23. SETTLING TIME 1 1.5 2 2.5 3 3.5 4 Figure 24. SETTLING TIME 1.5 LARGE-SIGNAL TRANSIENT RESPONSE 2.5 3 2 Rising Edge Rising Edge 1 2 VO - Output Voltage - V 1.5 Gain = 1 RL = 800 Rf = 499 f= 1 MHz VS = 5 V 0 0.5 VO - Differential Output Voltage Step - V f - Frequency - MHz Figure 22. 0.5 1600 3000 Normalized to 200 55 1200 SLEW RATE vs DIFFERENTIAL OUTPUT VOLTAGE STEP SR - Slew Rate - V/ s -70 Third-Order Output Intersept Point - dBm Single-Ended Input to Differential Output Gain = 1 VO = 2 VPP Rf = 392 VS = 5 V Tone Spacing = 200 kHz 800 Figure 21. 60 -50 -60 400 RL - Load Resistance - RL - Load Resistance - VO - Output Voltage Swing - V Third-Order Intermodulation Distortion - dBc -30 -90 -100 0 -20 HD3 -90 -100 Differential Input to Differential Output Gain = 1 VO = 2 VPP Rf = 499 f= 30 MHz VS = 5 V -10 -0.5 Falling Edge -1 VO - Output Voltage - V Harmonic Distortion - dBc -20 0 Single-Ended Input to Differential Output Gain = 1 VO = 2 VPP Rf = 499 f= 30 MHz VS = 5 V -10 Harmonic Distortion - dBc 0 -10 VO - Output Voltage - V HARMONIC DISTORTION vs LOAD RESISTANCE HARMONIC DISTORTION vs LOAD RESISTANCE HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING 1 Gain = 1 RL = 800 Rf = 499 f= 1 MHz VS = 5 V 0.5 0 -0.5 -1 -1.5 Falling Edge Gain = 1 RL = 800 Rf = 499 tr/tf = 300 ps VS = 5 V 1 0 -1 -2 -2 -1.5 0 12 5 10 15 20 -2.5 0 5 10 t - Time - ns t - Time - ns Figure 25. Figure 26. Submit Documentation Feedback 15 20 -3 -100 0 100 200 300 400 500 t - Time - ns Figure 27. Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (5 V Graphs) (continued) OVERDRIVE RECOVERY Gain = 1 RL = 800 Rf = 499 tr/tf = 300 ps VS = 5 V 0.1 0 -0.1 -0.2 -0.3 -0.4 -100 3 2 0.5 0 0 -1 -0.5 -2 -1 -3 -1.5 -4 -2 100 200 300 400 -2.5 0 500 4 2 -1 -4 -2 Figure 30. REJECTION RATIOS vs FREQUENCY REJECTION RATIOS vs CASE TEMPERATURE 100 PSRR+ 80 Hz Hz 50 CMMR PSRR- 40 30 20 10 100 1000 0.1 1 10 f - Frequency - MHz f - Frequency - kHz Figure 31. 30 100 Figure 33. 60 OPEN-LOOP GAIN vs CASE TEMPERATURE 30 Gain PIN = -20 dBm RL = 800 Rf = 499 VS = 5 V PIN = -30 dBm RL = 800 Rf = 100 k VS = 5 V Open-Loop Gain - dB 50 -30 -40 -50 -60 RL = 800 VS = 5 V Case Temperature - C OPEN-LOOP GAIN AND PHASE vs FREQUENCY 0 -20 40 Figure 32. OUTPUT BALANCE ERROR vs FREQUENCY -10 50 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 -10 10 k PSRR- 60 10 57 56 0 RL = 800 VS = 5 V 55 40 -30 30 -60 Phase 20 -90 10 -120 Open-Loop Gain - dB 10 70 20 RL = 800 VS = 5 V 0 1 PSRR+ 80 60 In CMMR 90 Rejection Ratios - dB Rejection Ratios - dB I n - Current Noise - pA/ nV/ Vn 10 0.1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 t - Time - s 70 1 0.01 -3 0 Figure 29. 90 100 1 -2 t - Time - s VOLTAGE AND CURRENT NOISE vs FREQUENCY 2 0 0 -6 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Figure 28. Vn - Voltage Noise - 1 1 t - Time - ns Output Balance Error - dB 1.5 -5 0 3 Gain = 4 RL = 800 Rf = 499 Overdrive = 5.5 V VS = 5 V 2 Phase - VO - Output Voltage - V 0.2 Gain = 4 RL = 800 Rf = 499 Overdrive = 4.5 V VS = 5 V 6 Single-Ended Output Voltage - V 0.3 4 OVERDRIVE RECOVERY 2.5 VI - Input Voltage - V 5 Single-Ended Output Voltage - V 0.4 VI - Input Voltage - V SMALL-SIGNAL TRANSIENT RESPONSE 54 53 52 51 50 49 0 0.01 -70 0.1 1 10 100 f - Frequency - MHz 0.1 1 10 100 -150 1000 f - Frequency - MHz Figure 34. Figure 35. Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 48 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Case Temperature - C Figure 36. Submit Documentation Feedback 13 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (5 V Graphs) (continued) 0.14 IIB- 1.75 0.12 1.5 0.11 IIB+ 1.25 0.1 1 0.09 IOS 0.08 0.75 0.5 0.07 0.25 0.06 35 2.5 VS = 5 V TA = 85C 30 VOS - Input Offset Voltage - mV I IB - Input Bias Current - A 0.13 Quiescent Current - mA VS = 5 V 2 I OS - Input Offset Current - A 2.25 INPUT OFFSET VOLTAGE vs CASE TEMPERATURE QUIESCENT CURRENT vs SUPPLY VOLTAGE INPUT BIAS AND OFFSET CURRENT vs CASE TEMPERATURE TA = 25C 25 20 TA = -40C 15 10 5 0.05 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 0 Case Temperature - C 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 2 1.5 1 0.5 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 5 Case Temperature - C VS - Supply Voltage - V Figure 37. Figure 38. 200 VS = 5 V 90 80 70 60 50 40 30 20 10 0 -10 -6 -4 -2 0 2 4 6 0 VS = 5 V Source 100 50 0 -50 Sink -100 -1 HD2-SE -80 -3 1000 Figure 43. Submit Documentation Feedback -2.5 -1.5 -0.5 0.5 1.5 2.5 Figure 41. Figure 42. OUTPUT OFFSET VOLTAGE AT VOCM vs OUTPUT COMMON-MODE VOLTAGE QUIESCENT CURRENT vs POWER-DOWN VOLTAGE 600 30 400 25 200 0 -400 f - Frequency - MHz 14 HD2-Diff -70 -600 3.5 VOC - Output Common-Mode Voltage - V -200 -2 HD3-SE and Diff -60 -100 -3.5 Quiescent Current - mA 0 100 -50 VOCM- mV 3 10 -40 VOS - Output Offset Voltage at Small Signal Frequency Response at VOCM - dB SMALL SIGNAL FREQUENCY RESPONSE AT VOCM 1 -30 -90 -150 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Figure 40. 1 -20 Case Temperature - C Gain = 1 RL = 800 Rf = 499 PIN= -20 dBm VS = 5 V Single-Ended and Differential Input to Differential Output Gain = 1, VO = 2 VPP f= 8 MHz, Rf = 499 VS = 5 V -10 150 Input Common-Mode Voltage Range - V 2 HARMONIC DISTORTION vs OUTPUT COMMON-MODE VOLTAGE Harmonic Distortion - dBc 110 100 DIFFERENTIAL OUTPUT CURRENT DRIVE vs CASE TEMPERATURE Differential Output Current Drive - mA CMRR - Common-Mode Rejection Ratio - dB COMMON-MODE REJECTION RATIO vs INPUT COMMON-MODE RANGE Figure 39. 20 15 10 5 0 -5 -5 -4 -3 -2 -1 0 1 2 3 4 -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 5 VOC - Output Common-Mode Voltage - V Power-Down Voltage - V Figure 44. Figure 45. 0 Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (5 V Graphs) (continued) TURNON AND TURNOFF DELAY TIMES SINGLE-ENDED OUTPUT IMPEDANCE IN POWER DOWN vs FREQUENCY 0.02 0 0 -1 -2 -3 -4 -5 -6 0 0.5 1 1.5 2 2.5 3 100.5 101 t - Time - ms 102 103 1000 900 800 700 600 500 400 Gain = 1 RL = 800 Rf = 392 PIN = -1 dBm VS = 5 V 300 200 100 0 0.1 1.4 1.2 RL = 800 VS = 5 V 1 0.8 0.6 0.4 0.2 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 1 10 100 f - Frequency - MHz Figure 46. POWER-DOWN QUIESCENT CURRENT vs CASE TEMPERATURE Power-Down Quiescent Current - mA Current 1100 ZO- Single-Ended Output Impedance in Power Down - 0.01 Quiescent Current - mA Powerdown Voltage Signal - V 0.03 1000 Figure 47. Case Temperature - C Figure 48. POWER-DOWN QUIESCENT CURRENT vs SUPPLY VOLTAGE Power-Down Quiescent Current - A 1000 RL = 800 900 800 700 600 500 400 300 200 100 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VS - Supply Voltage - V Figure 49. Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 Submit Documentation Feedback 15 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (5 V GRAPHS) SMALL SIGNAL FREQUENCY RESPONSE SMALL SIGNAL UNITY GAIN FREQUENCY RESPONSE 0.1 dB GAIN FLATNESS FREQUENCY RESPONSE 22 Gain = 10, Rf = 1.3 k 20 1 0.2 -1 -2 Gain = 1 RL = 800 Rf = 392 PIN = -20 dBm VS = 5 V 14 12 10 8 6 1 RL = 800 PIN = -30 dBm VS = 5 V 2 0 -2 0.1 -4 0.1 Gain = 2, Rf = 1 k 4 10 100 0 -0.1 Rf = 392 -0.2 -0.3 Gain = 1 RL = 800 PIN = -20 dBm VS = 5 V -0.4 1 10 100 1000 -0.5 f - Frequency - MHz 1000 Rf = 499 0.1 Gain = 5, Rf = 1.3 k 0.1 dB Gain Flatness - dB 0 -3 16 Small Signal Gain - dB Small Signal Unity Gain - dB 18 10 1 f - Frequency - MHz Figure 51. Figure 52. HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs FREQUENCY 0 -40 -50 Harmonic Distortion - dBc -60 -70 -80 HD3 HD2 -90 -40 -50 -60 -70 HD3 -80 HD2 1 10 1 10 100 -40 HD3 0.1 1 10 100 Figure 55. HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING 0 Single-Ended Input to Differential Output Gain = 1 RL = 800 Rf = 499 f= 8 MHz VS = 5 V -10 HD3 -80 -20 -30 -40 -50 -60 HD3 -80 HD2 1 10 f - Frequency - MHz Figure 56. Submit Documentation Feedback 100 -20 -30 -40 -50 HD3 -60 HD2 -70 -80 -90 -100 -100 -100 Single-Ended Input to Differential Output Gain = 1 RL = 800 Rf = 499 f= 30 MHz VS = 5 V -10 -70 -90 HD2 0.1 -80 Figure 54. -60 -90 -70 Figure 53. -50 -70 HD2 -60 f - Frequency - MHz Harmonic Distortion - dBc -30 -50 f - Frequency - MHz Differential Input to Differential Output Gain = 1 RL = 800 Rf = 499 VO = 2 VPP VS = 5 V -20 -40 f - Frequency - MHz 0 0 -10 -30 -100 0.1 100 -20 -90 -100 0.1 Harmonic Distortion - dBc -30 -90 -100 16 -20 Differential Input to Differential Output Gain = 1 RL = 800 Rf = 499 VO = 1 VPP VS = 5 V -10 Harmonic Distortion - dBc Harmonic Distortion - dBc -30 0 Single-Ended Input to Differential Output Gain = 1 RL = 800 Rf = 499 VO = 2 VPP VS = 5 V -10 Harmonic Distortion - dBc Single-Ended Input to Differential Output Gain = 1 RL = 800 Rf = 499 VO = 1 VPP VS = 5 V -20 1000 Figure 50. 0 -10 100 f - Frequency - MHz 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 VO - Output Voltage Swing - V VO - Output Voltage Swing - V Figure 57. Figure 58. 4.5 5 Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (5 V GRAPHS) (continued) HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING 0 Differential Input to Differential Output Gain = 1 RL = 800 Rf = 499 f= 8 MHz VS = 5 V -30 -40 -50 Harmonic Distortion - dBc -20 0 Differential Input to Differential Output Gain = 1 RL = 800 Rf = 499 f= 30 MHz VS = 5 V -10 HD3 -60 -70 -80 -20 -30 -40 -50 HD3 -60 HD2 -70 -80 HD2 -90 -90 -100 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 1 1.5 2 2.5 3 3.5 4 4.5 -100 5 HARMONIC DISTORTION vs FREQUENCY 0.1 HD2 -30 -40 -50 Harmonic Distortion - dBc -20 -60 -70 HD3 -80 1 10 f - Frequency - MHz 100 -20 -30 -40 -50 -60 HD3 -70 -80 HD2 HD2 -90 -100 0.1 Differential Input to Differential Output Gain = 2 RL = 800 Rf = 499 VO = 2 VPP VS = 5 V -10 -90 -100 -100 0.1 1 10 f - Frequency - MHz 0.1 100 1 10 f - Frequency - MHz 100 Figure 62. Figure 63. Figure 64. HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING 0 0 0 Differential Input to Differential Output Gain = 2 RL = 800 Rf = 1.3 k f= 8 MHz VS = 5 V Harmonic Distortion - dBc -10 HD3 -60 -70 -80 HD2 -20 -30 -40 -50 HD3 -60 -70 -80 -20 -30 -40 -50 -80 HD2 -90 -100 -100 -100 1.5 2 2.5 3 3.5 4 HD2 -70 -90 1 HD3 -60 -90 0.5 Single-Ended Input to Differential Output Gain = 2 RL = 800 Rf = 1.3 k f= 30 MHz VS = 5 V -10 Harmonic Distortion - dBc Single-Ended Input to Differential Output Gain = 2 RL = 800 Rf = 1.3 k f= 8 MHz VS = 5 V 0 100 0 Single-Ended Input to Differential Output Gain = 2 RL = 800 Rf = 499 VO = 2 VPP VS = 5 V -10 HD3 -50 HD2 HARMONIC DISTORTION vs FREQUENCY -80 -40 HD3 HARMONIC DISTORTION vs FREQUENCY -70 -30 -80 Figure 61. -60 -20 -70 Figure 60. -50 -10 -60 Figure 59. Harmonic Distortion - dBc Harmonic Distortion - dBc -40 -50 1 10 f - Frequency - MHz -90 Harmonic Distortion - dBc 0.5 0 -30 -40 VO - Output Voltage Swing - V Differential Input to Differential Output Gain = 2 RL = 800 Rf = 499 VO = 1 VPP VS = 5 V -20 -30 VO - Output Voltage Swing - V 0 -10 -20 -90 -100 0 Single-Ended Input to Differential Output Gain = 2 RL = 800 Rf = 499 VO = 1 VPP VS = 5 V -10 Harmonic Distortion - dBc 0 -10 Harmonic Distortion - dBc HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 VO - Output Voltage Swing - V VO - Output Voltage Swing - V VO - Output Voltage Swing - V Figure 65. Figure 66. Figure 67. Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 Submit Documentation Feedback 4.5 5 17 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (5 V GRAPHS) (continued) HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING HARMONIC DISTORTION vs LOAD RESISTANCE 0 Differential Input to Differential Output Gain = 2 RL = 800 Rf = 1.3 k f= 8 MHz VS = 5 V -30 -40 -50 Harmonic Distortion - dBc HD3 -60 HD2 -70 -80 -20 -30 -40 -50 HD2 -60 HD3 -70 -80 -20 -30 -40 -50 -80 -90 -90 -100 -100 1 1.5 2 2.5 3 3.5 4 4.5 5 0 400 Figure 68. 0 1000 800 600 0.4 1.5 0.3 1 Gain = 1 RL = 800 Rf = 499 tr/tf = 300 ps VS = 5 V 0.5 0 -0.5 200 -1 0 100 2 2.5 3 3.5 0.2 Gain = 1 RL = 800 Rf = 499 tr/tf = 300 ps VS = 5 V 0.1 0 -0.1 -0.2 200 300 400 -0.4 -100 500 0 100 200 300 400 t - Time - ns t - Time - ns Figure 72. Figure 73. REJECTION RATIOS vs FREQUENCY REJECTION RATIOS vs CASE TEMPERATURE 0 1.5 1600 -0.3 -100 1 1200 SMALL-SIGNAL TRANSIENT RESPONSE 2 -2 0.5 800 Figure 70. -1.5 400 0 400 RL - Load Resistance - LARGE-SIGNAL TRANSIENT RESPONSE VO - Output Voltage - V Gain = 1 RL = 800 Rf = 499 VS = 5 V 1200 1600 Figure 69. SLEW RATE vs DIFFERENTIAL OUTPUT VOLTAGE STEP 1400 1200 RL - Load Resistance - VO - Output Voltage Swing - V 1600 800 HD3 -70 -90 0.5 HD2 -60 -100 0 Differential Input to Differential Output Gain = 1 VO = 2 VPP Rf = 499 f= 30 MHz VS = 5 V -10 VO - Output Voltage - V Harmonic Distortion - dBc -20 0 Single-Ended Input to Differential Output Gain = 1 VO = 2 VPP Rf = 499 f= 30 MHz VS = 5 V -10 Harmonic Distortion - dBc 0 -10 SR - Slew Rate - V/ s HARMONIC DISTORTION vs LOAD RESISTANCE 500 4 VO - Differential Output Voltage Step - V Figure 71. VOLTAGE AND CURRENT NOISE vs FREQUENCY 90 Hz Hz I n - Current Noise - pA/ 120 PSRR+ 80 10 In 1 0.01 0.1 1 10 100 50 CMMR PSRR- 40 30 20 10 1000 10 k f - Frequency - kHz Figure 74. Submit Documentation Feedback Rejection Ratios - dB Vn 60 -10 0.1 1 10 f - Frequency - MHz 100 CMMR 80 PSRR60 40 20 RL = 800 VS = 5 V 0 18 PSRR+ 100 70 Rejection Ratios - dB Vn - Voltage Noise - nV/ 100 RL = 800 VS = 5 V 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Case Temperature - C Figure 75. Figure 76. Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (5 V GRAPHS) (continued) OPEN-LOOP GAIN AND PHASE vs FREQUENCY 60 -20 PIN = -30 dBm RL = 800 Rf = 100 k VS = 5 V 50 Open-Loop Gain - dB -10 30 Gain PIN = -20 dBm RL = 800 Rf = 499 VS = 5 V -30 -40 -50 57 55 40 -30 30 -60 Phase 20 -90 10 -120 54 53 52 51 50 49 48 -60 47 0 0.01 -70 1 10 f - Frequency - MHz 100 0.1 1 Case Temperature - C 0.12 0.11 IIB+ 1.25 0.1 0.09 1 IOS 0.08 0.5 0.07 0.25 0.06 INPUT OFFSET VOLTAGE vs CASE TEMPERATURE 2.5 VS = 5 V TA = 85C 30 Quiescent Current - mA IIB- Figure 79. 35 I OS - Input Offset Current - A I IB - Input Bias Current - A 0.13 1.75 0.75 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 QUIESCENT CURRENT vs SUPPLY VOLTAGE 0.14 VS = 5 V 1.5 46 Figure 78. INPUT BIAS AND OFFSET CURRENT vs CASE TEMPERATURE 2 100 f - Frequency - MHz Figure 77. 2.25 10 -150 1000 VOS - Input Offset Voltage - mV 0.1 TA = 25C 25 20 TA = -40C 15 10 5 0.05 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 0 Case Temperature - C 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 2 1.5 1 0.5 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 5 Case Temperature - C VS - Supply Voltage - V Figure 80. Figure 81. Figure 82. COMMON-MODE REJECTION RATIO vs INPUT COMMON-MODE RANGE OUTPUT DRIVE vs CASE TEMPERATURE HARMONIC DISTORTION vs OUTPUT COMMON-MODE VOLTAGE 90 150 VS = 5 V 0 VS = 5 V Source -10 80 60 50 40 30 50 0 -50 Sink 20 -100 Harmonic Distortion - dBc 100 70 Output Drive - mA CMRR - Common-Mode Rejection Ratio - dB RL = 800 VS = 5 V 56 0 Open-Loop Gain - dB 0 Output Balance Error - dB OPEN-LOOP GAIN vs CASE TEMPERATURE Phase - OUTPUT BALANCE ERROR vs FREQUENCY -20 -30 -40 -50 -60 -70 Single-Ended and Differential Input Gain = 1 VO = 2 VPP Rf = 499 f= 8 MHz VS = 5 V HD3-Diff HD2-SE HD2-Diff -80 -90 10 -150 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 0 -100 HD3-SE Input Common-Mode Voltage Range - V Case Temperature - C 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 VOCM - Output Common-Mode Voltage - V Figure 83. Figure 84. Figure 85. 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 Submit Documentation Feedback 19 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (5 V GRAPHS) (continued) OUTPUT OFFSET VOLTAGE vs OUTPUT COMMON-MODE VOLTAGE 3 Gain = 1 RL = 800 Rf = 499 PIN= -20 dBm VS = 5 V 1 800 25 600 0 -1 20 400 200 0 -200 -400 -2 15 10 5 -600 -3 10 100 1000 -800 0 0.5 1 0.03 -1 -2 -3 -4 -5 -6 0 0.5 1 1.5 2 2.5 3 100.5 101 t - Time - ms 102 103 3 3.5 4 4.5 0 5 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 Power-down Voltage - V Figure 87. Figure 88. 1100 1000 ZO- Single-Ended Output Impedance in Power Down - 0 Quiescent Current - mA 0.02 0 2.5 SINGLE-ENDED OUTPUT IMPEDANCE IN POWER DOWN vs FREQUENCY TURNON AND TURNOFF DELAY TIMES Current 2 VOC - Output Common-Mode Voltage - V Figure 86. 0.01 1.5 900 800 700 600 500 400 Gain = 1 RL = 400 Rf = 392 PIN = -1 dBm VS = 5 V 300 200 100 0 0.1 1 0.9 RL = 800 VS = 5 V 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 1 10 100 f - Frequency - MHz Figure 89. POWER-DOWN QUIESCENT CURRENT vs CASE TEMPERATURE Power-Down Quiescent Current - mA 1 f - Frequency - MHz Powerdown Voltage Signal - V QUIESCENT CURRENT vs POWER-DOWN VOLTAGE Quiescent Current - mA 2 VOS - Output Offset Voltage - mV Small Signal Frequency Response at VOCM - dB SMALL SIGNAL FREQUENCY RESPONSE at VOCM 1000 Figure 90. Case Temperature - C Figure 91. POWER-DOWN QUIESCENT CURRENT vs SUPPLY VOLTAGE Power-Down Quiescent Current - A 1000 900 800 700 600 500 400 300 200 100 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VS - Supply Voltage - V Figure 92. 20 Submit Documentation Feedback Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com APPLICATION INFORMATION MAXIMUM DIE TEMPERATURE TO PREVENT OSCILLATION The THS4502 and THS4503 may have low level oscillation when the die temperature (also called junction temperature) exceeds +60C and is not recommended for new designs where the die temperature is expected to exceed +60C. 10V, RL = 800 differential, and the quiescent current = 32mA (the maximum over 0C to 70C temperature range). The last entry for each package option lists the worst case where the output voltage is 5V DC. Table 1. Estimated Maximum Ambient Temperature Per Package Option PACKAGE/DEVICE The oscillation is due to internal design and external configuration is not expected to mitigate or reduce the problem. This problem is random due to normal process variations and normal testing cannot identify problem units. SOIC THS4502D THS4503D The THS4500 and THS4501 are recommended replacement devices. Worst Case => PWR Pad MSOP The die temperature depends on the power dissipation and the thermal resistance of the device and can be approximated with the following formula: THS4502DGN THS4503DGN Die Temperature = PDISS x JA + TA Where: PDISS (VS (TOTAL) x IQ) + (VS+ - VOUT) x IOUT Vout JA 0V 28.8C 2 Vpp 28.0C 4 Vpp 6 Vpp 97.5C/W 26.3C 5 DC 25.8C 0V 41.3C 2 Vpp 40.8C 4 Vpp 6 Vpp 58.4C/W Differential signaling offers a number of performance advantages in high-speed analog signal processing systems, including immunity to external common-mode noise, suppression of even-order nonlinearities, and increased dynamic range. Fully differential amplifiers not only serve as the primary means of providing gain to a differential signal chain, but also provide a monolithic solution for converting single-ended signals into differential signals for easier, higher performance processing. The THS4500 family of amplifiers contains products in Texas Instruments' expanding line of high-performance fully differential amplifiers. Information on fully differential amplifier fundamentals, as well as implementation specific information, is presented in the applications section of this data sheet to provide a better understanding of the operation of the THS4500 family of devices, and to simplify the design process for designs using these amplifiers. * Applications Section * Fully Differential Amplifier Terminal Functions * Input Common-Mode Voltage Range and the THS4500 Family * * * * * * * * * * 40.4C 40.1C 39.8C 5 DC 39.5C MSOP 0V -23.2C 2 Vpp -25.3C Worst Case => FULLY DIFFERENTIAL AMPLIFIERS 26.8C Worst Case => THS4502DGK THS4503DGK * 27.3C 8 Vpp 8 Vpp Table 1 shows the estimated maximum ambient temperature (TA max) in C for each package option of the THS4502 and THS4503 using the thermal dissipation rating given in the PACKAGE DISSIPATION RATINGS table for a JEDEC standard High-K test PCB. For each case shown, VS (TOTAL) = TA MAX 4 Vpp 6 Vpp 260C/W -27.1C -28.6C 8 Vpp -29.8C 5 DC -31.3C Choosing the Proper Value for the Feedback and Gain Resistors Application Circuits Using Fully Differential Amplifiers Key Design Considerations for Interfacing to an Analog-to-Digital Converter Setting the Output Common-Mode Voltage With the VOCM Input Saving Power With Power-Down Functionality Linearity: Definitions, Terminology, Circuit Techniques, and Design Tradeoffs An Abbreviated Analysis of Noise in Fully Differential Amplifiers Printed-Circuit Board Layout Techniques for Optimal Performance Power Dissipation and Thermal Considerations Power Supply Decoupling Techniques and Recommendations Evaluation Fixtures, Spice Models, and Applications Support Additional Reference Material Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 Submit Documentation Feedback 21 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com FULLY DIFFERENTIAL AMPLIFIER TERMINAL FUNCTIONS Fully differential amplifiers are typically packaged in eight-pin packages as shown in the diagram. The device pins include two inputs (VIN+,VIN-), two outputs (VOUT-,VOUT+), two power supplies (VS+, VS-), an output common-mode control pin (VOCM), and an optional power-down pin (PD). VIN- 1 8 VIN+ VOCM 2 7 PD VS+ 3 6 VS- VOUT+ 4 A standard configuration for the device is shown in the figure. The functionality of a fully differential amplifier can be imagined as two inverting amplifiers that share a common noninverting terminal (though the voltage is not necessarily fixed). For more information on the basic theory of operation for fully differential amplifiers, refer to the Texas Instruments application note titled Fully Differential Amplifiers, literature number SLOA054. VOCM Rg2 22 Submit Documentation Feedback + - + Rf2 Application Circuit for the THS4500 and THS4501, Featuring Single-Supply Operation With a Ground-Referenced Input Signal Figure 93. Rg1 RS Rf1 +VS RT VS VOCM + - + -VS Rg2 Rf2 Application Circuit for the THS4500 and THS4501, Featuring Split-Supply Operation With an Input Signal Referenced at the Midrail INPUT COMMON-MODE VOLTAGE RANGE AND THE THS4500 FAMILY The key difference between the THS4500/1 and the THS4502/3 is the input common-mode range for the two devices. The THS4502 and THS4503 have an input common-mode range that is centered around midrail, and the THS4500 and THS4501 have an input common-mode range that is shifted to include the negative power supply rail. Selection of one or the other is determined by the nature of the application. Specifically, the THS4500 and THS4501 are designed for use in single-supply applications where the input signal is ground-referenced, as depicted in Figure 93. The THS4502 and THS4503 are designed for use in single-supply or split-supply applications where the input signal is centered between the power supply voltages, as depicted in Figure 94. Rf1 +VS RT VS 5 VOUT- Fully Differential Amplifier Pin Diagram Rg1 RS Figure 94. Equations 1-5 allow for calculation of the required input common-mode range for a given set of input conditions. The equations allow calculation of the input commonmode range requirements given information about the input signal, the output voltage swing, the gain, and the output common-mode voltage. Calculating the maximum and minimum voltage required for VN and VP (the amplifier's input nodes) determines whether or not the input common-mode range is violated or not. Four equations are required. Two calculate the output voltages and two calculate the node voltages at VN and VP (note that only one of these needs calculation, as the amplifier forces a virtual short between the two nodes). V OUT) + V IN)(1-)-V IN-(1-) ) 2V OCM 2 (1) V OUT- + -V IN)(1-) ) V IN-(1-) ) 2V OCM 2 (2) Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com Table 2. Negative-Rail Referenced (continued) V N + V IN-(1-) ) V OUT) (3) RG + RF ) RG Where: (4) V P + V IN)(1-) ) V OUT- (5) VIN+ Vp VOCM VOUT- + - + Rg VIN (VPP) VOCM (V) VOD (VPP) VNMIN (V) VNMAX (V) Gain (V/V) VIN+ (V) VIN(V) VIN (VPP) VOCM (V) VOD (VPP) VNMIN (V) VNMAX (V) 1 0.5 to 4.5 2.5 4 2.5 4 2 3 2 1.5 to 3.5 2.5 2 2.5 4 2.16 2.83 4 2.0 to 3.0 2.5 1 2.5 4 2.3 2.7 8 2.25 to 2.75 2.5 0.5 2.5 4 2.389 2.61 NOTE: This table assumes a midrail referenced, single-ended input signal on a single 5-V supply. VNMIN = VPMIN and VNMAX = VPMAX VOUT+ Vn VIN(V) NOTE: This table assumes a negative-rail referenced, single-ended input signal on a single 5-V supply as shown in Figure 93. VNMIN = VPMIN and VNMAX = VPMAX Rf Rg VIN+ (V) Table 3. Midrail Referenced NOTE The equations denote the device inputs as VN and VP, and the circuit inputs as VIN+ and VIN-. VIN- Gain (V/V) CHOOSING THE PROPER VALUE FOR THE FEEDBACK AND GAIN RESISTORS Rf Diagram For Input Common-Mode Range Equations Figure 95. The two tables below depict the input common-mode range requirements for two different input scenarios, an input referenced around the negative rail and an input referenced around midrail. The tables highlight the differing requirements on input common-mode range, and illustrate reasoning for choosing either the THS4500/1 or the THS4502/3. For signals referenced around the negative power supply, the THS4500/1 should be chosen since its input common-mode range includes the negative supply rail. For all other situations, the THS4502/3 offers slightly improved distortion and noise performance for applications with input signals centered between the power supply rails. Table 2. Negative-Rail Referenced Gain (V/V) VIN+ (V) VIN(V) VIN (VPP) VOCM (V) VOD (VPP) VNMIN (V) VNMAX (V) 1 -2.0 to 2.0 0 4 2.5 4 0.75 1.75 2 -1.0 to 1.0 0 2 2.5 4 0.5 1.167 4 -0.5 to 0.5 0 1 2.5 4 0.3 0.7 8 -0.25 to 0.25 0 0.5 2.5 4 0.167 0.389 The selection of feedback and gain resistors impacts circuit performance in a number of ways. The values in this section provide the optimum high frequency performance (lowest distortion, flat frequency response). Since the THS4500 family of amplifiers is developed with a voltage feedback architecture, the choice of resistor values does not have a dominant effect on bandwidth, unlike a current feedback amplifier. However, resistor choices do have second-order effects. For optimal performance, the following feedback resistor values are recommended. In higher gain configurations (gain greater than two), the feedback resistor values have much less effect on the high frequency performance. Example feedback and gain resistor values are given in the section on basic design considerations (Table 4). Amplifier loading, noise, and the flatness of the frequency response are three design parameters that should be considered when selecting feedback resistors. Larger resistor values contribute more noise and can induce peaking in the ac response in low gain configurations, and smaller resistor values can load the amplifier more heavily, resulting in a reduction in distortion performance. In addition, feedback resistor values, coupled with gain requirements, determine the value of the gain resistors, directly impacting the input impedance of the entire circuit. While there are no strict rules about resistor selection, these trends can provide qualitative design guidance. Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 Submit Documentation Feedback 23 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com APPLICATION CIRCUITS USING FULLY DIFFERENTIAL AMPLIFIERS 1 + Fully differential amplifiers provide designers with a great deal of flexibility in a wide variety of applications. This section provides an overview of some common circuit configurations and gives some design guidelines. Designing the interface to an ADC, driving lines differentially, and filtering with fully differential amplifiers are a few of the circuits that are covered. R3 ) RT || R S R1 + R1 ) R2 2 R3 ) RT || R S ) R4 (7) R R) R (8) (9) V OD 1- 2 +2 1 ) 2 VS V OD 1- 2 +2 1 ) 2 V IN T T S BASIC DESIGN CONSIDERATIONS For more detailed information about balance in fully differential amplifiers, see Fully Differential Amplifiers, referenced at the end of this data sheet. The circuits in Figures 96 through 100 are used to highlight basic design considerations for fully differential amplifier circuit designs. INTERFACING TO AN ANALOG-TO-DIGITAL CONVERTER Table 4. Resistor Values for Balanced Operation in Various Gain Configurations Gain VOD VIN R2 & R4 () R1 () R3 () RT () 1 392 412 383 54.9 1 499 523 487 53.6 2 392 215 187 60.4 2 1.3k 665 634 52.3 5 1.3k 274 249 56.2 5 3.32k 681 649 52.3 10 1.3k 147 118 64.9 10 6.81k 698 681 52.3 NOTE: Values in this table assume a 50 source impedance. R2 R1 Vn RS - + + - R3 VP VoutVOCM RT VS Vout+ R4 Figure 96. Equations for calculating fully differential amplifier resistor values in order to obtain balanced operation in the presence of a 50- source impedance are given in equations 6 through 9. RT + 24 1 1- K 1 - 2(1)K) RS R3 K + R2 R1 R2 + R4 (6) R3 + R1 * Rs || R T Submit Documentation Feedback The THS4500 family of amplifiers are designed specifically to interface to today's highest-performance analog-to-digital converters. This section highlights the key concerns when interfacing to an ADC and provides example ADC/fully differential amplifier interface circuits. Key design concerns when interfacing to an analog-to-digital converter: * Terminate the input source properly. In high-frequency receiver chains, the source feeding the fully differential amplifier requires a specific load impedance (e.g., 50 ). * Design a symmetric printed-circuit board layout. Even-order distortion products are heavily influenced by layout, and careful attention to a symmetric layout will minimize these distortion products. * Minimize inductance in power supply decoupling traces and components. Poor power supply decoupling can have a dramatic effect on circuit performance. Since the outputs are differential, differential currents exist in the power supply pins. Thus, decoupling capacitors should be placed in a manner that minimizes the impedance of the current loop. * Use separate analog and digital power supplies and grounds. Noise (bounce) in the power supplies (created by digital switching currents) can couple directly into the signal path, and power supply noise can create higher distortion products as well. * Use care when filtering. While an RC low-pass filter may be desirable on the output of the amplifier to filter broadband noise, the excess loading can negatively impact the amplifier linearity. Filtering in the feedback path does not have this effect. * AC-coupling allows easier circuit design. If dc-coupling is required, be aware of the excess power dissipation that can occur due to level-shifting the output through the output Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com * * * * * * common-mode voltage control. Do not terminate the output unless required. Many open-loop, class-A amplifiers require 50- termination for proper operation, but closed-loop fully differential amplifiers drive a specific output voltage regardless of the load impedance present. Terminating the output of a fully differential amplifier with a heavy load adversely effects the amplifier's linearity. Comprehend the VOCM input drive requirements. Determine if the ADC's voltage reference can provide the required amount of current to move VOCM to the desired value. A buffer may be needed. Decouple the VOCM pin to eliminate the antenna effect. VOCM is a high-impedance node that can act as an antenna. A large decoupling capacitor on this node eliminates this problem. Be cognizant of the input common-mode range. If the input signal is referenced around the negative power supply rail (e.g., around ground on a single 5 V supply), then the THS4500/1 accommodates the input signal. If the input signal is referenced around midrail, choose the THS4502/3 for the best operation. Packaging makes a difference at higher frequencies. If possible, choose the smaller, thermally enhanced MSOP package for the best performance. As a rule, lower junction temperatures provide better performance. If possible, use a thermally enhanced package, even if the power dissipation is relatively small compared to the maximum power dissipation rating to achieve the best results. Comprehend the effect of the load impedance seen by the fully differential amplifier when performing system-level intercept point calculations. Lighter loads (such as those presented by an ADC) allow smaller intercept points to support the same level of intermodulation distortion performance. EXAMPLE ANALOG-TO-DIGITAL CONVERTER DRIVER CIRCUITS The THS4500 family of devices is designed to drive high-performance ADCs with extremely high linearity, allowing for the maximum effective number of bits at the output of the data converter. Two representative circuits shown below highlight single-supply operation and split supply operation. Specific feedback resistor, gain resistor, and feedback capacitor values are not specified, as their values depend on the frequency of interest. Information on calculating these values can be found in the applications material above. CF RS VS Rg Rf 5V RT 10 F 1 F + VOCM + THS4503 -5 V Rg 0.1 F 5V Riso Riso IN ADS5410 12 Bit/80 MSps IN CM 10 F 0.1 F 0.1 F Rf CF Using the THS4503 With the ADS5410 Figure 97. CF RS VS Rg Rf 5V RT 10 F 1 F 0.1 F + VOCM + THS4501 5V Riso Riso IN ADS5421 14 Bit/40 MSps IN CM Rg Rf CF 0.1 F Using the THS4501 With the ADS5421 Figure 98. FULLY DIFFERENTIAL LINE DRIVERS The THS4500 family of amplifiers can be used as high-frequency, high-swing differential line drivers. Their high power supply voltage rating (16.5 V absolute maximum) allows operation on a single 12-V or a single 15-V supply. The high supply voltage, coupled with the ability to provide differential outputs enables the ability to drive 26 VPP into reasonably heavy loads (250 or greater). The circuit in Figure 99 illustrates the THS4500 family of devices used as high speed line drivers. For line driver applications, close attention must be paid to thermal design constraints due to the typically high level of power dissipation. Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 Submit Documentation Feedback 25 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 CG RS Rg SETTING THE OUTPUT COMMON-MODE VOLTAGE WITH THE VOCM INPUT Rf 15 V RT VS Riso VOCM www.ti.com + - - RL VDD THS4500/2 0.1 F + Riso Rf Rg CS CS VOD = 26 VPP CG Fully Differential Line Driver With High Output Swing Figure 99. Filtering With Fully Differential Amplifiers Similar to their single-ended counterparts, fully differential amplifiers have the ability to couple filtering functionality with voltage gain. Numerous filter topologies can be based on fully differential amplifiers. Several of these are outlined in A Differential Circuit Collection, (literature number SLOA064) referenced at the end of this data sheet. The circuit below depicts a simple two-pole low-pass filter applicable to many different types of systems. The first pole is set by the resistors and capacitors in the feedback paths, and the second pole is set by the isolation resistors and the capacitor across the outputs of the isolation resistors. The output common-mode voltage pin provides a critical function to the fully differential amplifier; it accepts an input voltage and reproduces that input voltage as the output common-mode voltage. In other words, the VOCM input provides the ability to level-shift the outputs to any voltage inside the output voltage swing of the amplifier. A description of the input circuitry of the VOCM pin is shown below to facilitate an easier understanding of the VOCM interface requirements. The VOCM pin has two 50-k resistors between the power supply rails to set the default output common-mode voltage to midrail. A voltage applied to the VOCM pin alters the output common-mode voltage as long as the source has the ability to provide enough current to overdrive the two 50-k resistors. This phenomenon is depicted in the VOCM equivalent circuit diagram. The table contains some representative examples to aid in determining the current drive requirement for the VOCM voltage source. This parameter is especially important when using the reference voltage of an analog-to-digital converter to drive VOCM. Output current drive capabilities differ from part to part, so a voltage buffer may be necessary in some applications. VS+ CF1 Rg1 RS VS R = 50 k IIN Riso RT 2 VOCM - VS+ - VSR R = 50 k + - C VO + Rg2 VSRiso Equivalent Input Circuit for VOCM Rf2 Figure 101. CF2 By design, the input signal applied to the VOCM pin propagates to the outputs as a common-mode signal. As shown in the equivalent circuit diagram, the VOCM input has a high impedance associated with it, dictated by the two 50-k resistors. While the high impedance allows for relaxed drive requirements, it also allows the pin and any associated printed-circuit board traces to act as an antenna. For this reason, a decoupling capacitor is recommended on this node for the sole purpose of filtering any high frequency noise that could couple into the signal path through the VOCM circuitry. A 0.1-F or 1-F capacitance is a reasonable value for eliminating a great deal of broadband interference, but additional, tuned decoupling capacitors should be considered if a A Two-Pole, Low-Pass Filter Design Using a Fully Differential Amplifier With Poles Located at: P1 = (2RfCF)-1 in Hz and P2 = (4RisoC)-1 in Hz Figure 100. Often times, filters like these are used to eliminate broadband noise and out-of-band distortion products in signal acquisition systems. It should be noted that the increased load placed on the output of the amplifier by the second low-pass filter has a detrimental effect on the distortion performance. The preferred method of filtering is using the feedback network, as the typically smaller capacitances required at these points in the circuit do not load the amplifier nearly as heavily in the pass-band. 26 IIN = VOCM Rf1 Submit Documentation Feedback Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com specific source of electromagnetic or radio frequency interference is present elsewhere in the system. Information on the ac performance (bandwidth, slew rate) of the VOCM circuitry is included in the specification table and graph section. Since the VOCM pin provides the ability to set an output common-mode voltage, the ability for increased power dissipation exists. While this does not pose a performance problem for the amplifier, it can cause additional power dissipation of which the system designer should be aware. The circuit shown in Figure 102 demonstrates an example of this phenomenon. For a device operating on a single 5-V supply with an input signal referenced around ground and an output common-mode voltage of 2.5 V, a dc potential exists between the outputs and the inputs of the device. The amplifier sources current into the feedback network in order to provide the circuit with the proper operating point. While there are no serious effects on the circuit performance, the extra power dissipation may need to be included in the system's power budget. I1 = VOCM Rf1+ Rg1 + RS || RT VS Rf1 Rg1 2.5-V DC 5V RT VOCM = 2.5 V + - + Rg2 RL 2.5-V DC Rf2 DC Current Path to Ground I2 = Note that this power-down functionality is just that; the amplifier consumes less power in power-down mode. The power-down mode is not intended to provide a high-impedance output. In other words, the power-down functionality is not intended to allow use as a 3-state bus driver. When in power-down mode, the impedance looking back into the output of the amplifier is dominated by the feedback and gain setting resistors. The time delays associated with turning the device on and off are specified as the time it takes for the amplifier to reach 50% of the nominal quiescent current. The time delays are on the order of microseconds because the amplifier moves in and out of the linear mode of operation in these transitions. LINEARITY; DEFINITIIONS, TERMINOLOGY, CIRCUIT TECHNIQUES, AND DESIGN TRADEOFFS DC Current Path to Ground RS operation. To turn off the amplifier in an effort to conserve power, the power-down pin can be driven towards the negative rail. The threshold voltages for power-on and power-down are relative to the supply rails and given in the specification tables. Above the enable threshold voltage, the device is on. Below the disable threshold voltage, the device is off. Behavior in between these threshold voltages is not specified. VOCM Rf2 + Rg2 Depiction of DC Power Dissipation Caused By Output Level-Shifting in a DC-Coupled Circuit Figure 102. SAVING POWER WITH POWER-DOWN FUNCTIONALITY The THS4500 family of fully differential amplifiers contains devices that come with and without the power-down option. Even-numbered devices have power-down capability, which is described in detail here. The power-down pin of the amplifiers defaults to the positive supply voltage in the absence of an applied voltage (i.e. an internal pullup resistor is present), putting the amplifier in the power-on mode of The THS4500 family of devices features unprecedented distortion performance for monolithic fully differential amplifiers. This section focuses on the fundamentals of distortion, circuit techniques for reducing nonlinearity, and methods for equating distortion of fully differential amplifiers to desired linearity specifications in RF receiver chains. Amplifiers are generally thought of aslinear devices. In other words, the output of an amplifier is a linearly scaled version of the input signal applied to it. In reality, however, amplifier transfer functions are nonlinear. Minimizing amplifier nonlinearity is a primary design goal in many applications. Intercept points are specifications that have long been used as key design criteria in the RF communications world as a metric for the intermodulation distortion performance of a device in the signal chain (e.g., amplifiers, mixers, etc.). Use of the intercept point, rather than strictly the intermodulation distortion, allows for simpler system-level calculations. Intercept points, like noise figures, can be easily cascaded back and forth through a signal chain to determine the overall receiver chain's intermodulation distortion performance. The relationship between intermodulation distortion and intercept point is depicted in Figure 103 and Figure 104. Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 Submit Documentation Feedback 27 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 PO www.ti.com PO Power fc = fc - f1 fc = f2 - fc IMD3 = PS - PO PS fc - 3f PS f1 fc f2 However, with a fully differential amplifier, the output does not require termination as an RF amplifier would. Because closed-loop amplifiers deliver signals to their outputs regardless of the impedance present, it is important to comprehend this when evaluating the intercept point of a fully differential amplifier. The THS4500 series of devices yields optimum distortion performance when loaded with 200 to 1 k, very similar to the input impedance of an analog-to-digital converter over its input frequency band. As a result, terminating the input of the ADC to 50 can actually be detrimental to system performance. This discontinuity between open-loop, class-A amplifiers and closed-loop, class-AB amplifiers becomes apparent when comparing the intercept points of the two types of devices. Equation 10 gives the definition of an intercept point, relative to the intermodulation distortion. fc + 3f f - Frequency - MHz Figure 103. OIP 3 + P O ) POUT (dBm) 1X IMD2 where P O + 10 log 3 V 2Pdiff 2RL 0.001 (10) (11) OIP3 NOTE Po is the output power of a single tone, RL is the differential load resistance, and VP(diff) is the differential peak voltage for a single tone. PO IIP3 IMD3 3X PIN (dBm) PS Figure 104. Due to the intercept point's ease of use in system level calculations for receiver chains, it has become the specification of choice for guiding distortion-related design decisions. Traditionally, these systems use primarily class-A, single-ended RF amplifiers as gain blocks. These RF amplifiers are typically designed to operate in a 50- environment, just like the rest of the receiver chain. Since intercept points are given in dBm, this implies an associated impedance (50 ). 28 Submit Documentation Feedback As can be seen in the equation, when a higher impedance is used, the same level of intermodulation distortion performance results in a lower intercept point. Therefore, it is important to comprehend the impedance seen by the output of the fully differential amplifier when selecting a minimum intercept point. The graphic below shows the relationship between the strict definition of an intercept point with a normalized, or equivalent, intercept point for the THS4502. Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com OIP 3 - Third-Order Output Intercept Point - dBm THIRD-ORDER OUTPUT INTERCEPT POINT vs FREQUENCY Ni eg NA Rg Rf ef 60 Normalized to 200 55 Si Normalized to 50 50 en Ni 45 No Rs + 40 Rt 35 OIP3 RL= 800 es 30 20 i ii 15 0 No et Gain = 1 Rf = 392 VS = 5 V Tone Spacing = 200 kHz 25 So fully-diff amp - i ni eg 10 20 30 40 50 60 70 80 90 100 Rg Rf ef f - Frequency - MHz Figure 105. Comparing specifications between different device types becomes easier when a common impedance level is assumed. For this reason, the intercept points on the THS4500 family of devices are reported normalized to a 50- load impedance. AN ANALYSIS OF NOICE IN FULLY DIFFERENTIAL AMPLIFIERS Noise analysis in fully differential amplifiers is analogous to noise analysis in single-ended amplifiers. The same concepts apply. Below, a generic circuit diagram consisting of a voltage source, a termination resistor, two gain setting resistors, two feedback resistors, and a fully differential amplifier is shown, including all the relevant noise sources. From this circuit, the noise factor (F) and noise figure (NF) are calculated. The figures indicate the appropriate scaling factor for each of the noise sources in two different cases. The first case includes the termination resistor, and the second, simplified case assumes that the voltage source is properly terminated by the gain-setting resistors. With these scaling factors, the amplifier's input noise power (NA) can be calculated by summing each individual noise source with its scaling factor. The noise delivered to the amplifier by the source (NI) and input noise power are used to calculate the noise factor and noise figure as shown in equations 23 through 27. Figure 106. Noise Sources in a Fully Differential Amplifier Circuit NA: Fully Differential Amplifier Noise Source Scale Factor (eni)2 R R ) R 2 g g f R R R ) 2R )R s g s t (12) t (ini)2 Rg2 (13) (iii)2 Rg2 (14) 2 R R2R)2R R ) 2R R R )2R s 4kTRt s g s t 2 4kTRf 4kTRg G 2 s Rg Rf R (15) g g 2 (16) 2 Rg R sR t g) 2R s)Rt (17) Figure 107. Scaling Factors for Individual Noise Sources Assuming a Finite Value Termination Resistor Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 Submit Documentation Feedback 29 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com PRINTED-CIRCUIT BOARD LAYOUT TECHNIQUES FOR OPTIMAL PERFORMANCE NA: Fully Differential Amplifier; termination = 2Rg Noise Source Scale Factor R ) R R 2 (eni)2 f (ini)2 Rg2 (iii)2 Rg2 g (18) s 2 (19) (20) Rg Rf 2 4kTRf R ) Rg g 2 (21) 2 R R ) R 2 g 2 4kTRg (22) s g Figure 108. Scaling Factors for Individual Noise Sources Assuming No termination Resistance is Used (e.g., RT is open) 2 2R R R )2R N + 4kTR R R )R2R)2R t i g (23) g t s t s g g t Figure 109. Input Noise With a Termination Resistor Ni + 4kTR s 2R g Rs ) 2Rg 2 (24) Figure 110. Input Noise Assuming No Termination Resistor N A + SNoise Source F+1) Scale Factor NA NI NF + 10 log (F) (25) (26) (27) Figure 111. Noise Factor and Noise Figure Calculations 30 Submit Documentation Feedback Achieving optimum performance with high frequency amplifier-like devices in the THS4500 family requires careful attention to board layout parasitic and external component types. Recommendations that optimize performance include: * Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and input pins can cause instability. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. * Minimize the distance (< 0.25") from the power supply pins to high frequency 0.1-F decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power supply connections should always be decoupled with these capacitors. Larger (6.8 F or more) tantalum decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. The primary goal is to minimize the impedance seen in the differential-current return paths. * Careful selection and placement of external components preserve the high frequency performance of the THS4500 family. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially-leaded resistors can also provide good high frequency performance. Again, keep their leads and PC board trace length as short as possible. Never use wirewound type resistors in a high frequency application. Since the output pin and inverting input pins are the most sensitive to parasitic capacitance, always position the feedback and series output resistors, if any, as close as possible to the inverting input pins and output pins. Other network components, such as input termination resistors, should be placed close to the gain-setting resistors. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal-film or surface-mount resistors have approximately 0.2 pF in shunt with the resistor. For resistor values > 2.0 k, this parasitic capacitance can add a pole and/or a zero below 400 MHz that can Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com * * * * effect circuit operation. Keep resistor values as low as possible, consistent with load driving considerations. Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and determine if isolation resistors on the outputs are necessary. Low parasitic capacitive loads (< 4 pF) may not need an RS since the THS4500 family is nominally compensated to operate with a 2-pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50- environment is normally not necessary onboard, and in fact, a higher impedance environment improves distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the THS4500 family is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. If the 6-dB attenuation of a doubly terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case. This does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there is some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. Socketing a high speed part like the THS4500 family is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the THS4500 family parts directly onto the board. PowerPAD DESIGN CONSIDERATIONS The THS4500 family is available in a thermally-enhanced PowerPAD family of packages. These packages are constructed using a downset leadframe upon which the die is mounted [see Figure 112(a) and Figure 112(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 112(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface mount with the, heretofore, awkward mechanical methods of heatsinking. DIE Thermal Pad Side View (a) DIE End View (b) Bottom View (c) Figure 112. Views of Thermally Enhanced Package Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the recommended approach. 0.205 0.060 0.017 Pin 1 0.013 0.030 0.075 0.025 0.094 0.010 vias 0.035 0.040 Top View Figure 113. PowerPAD PCB Etch and Via Pattern Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 Submit Documentation Feedback 31 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com 1. Prepare the PCB with a top side etch pattern as shown in Figure 113. There should be etch for the leads as well as etch for the thermal pad. 2. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. 3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the THS4500 family IC. These additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered so that wicking is not a problem. 4. Connect all holes to the internal ground plane. 5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the THS4500 family PowerPAD package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole. 6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the reflow process. 7. Apply solder paste to the exposed thermal pad area and all of the IC terminals. 8. With these preparatory steps in place, the IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. The THS4500 family of devices does not incorporate automatic thermal shutoff protection, so the designer must take care to ensure that the design does not violate the absolute maximum junction temperature of the device. Failure may result if the absolute Submit Documentation Feedback The thermal characteristics of the device are dictated by the package and the PC board. Maximum power dissipation for a given package can be calculated using the following formula. P Dmax + Tmax-T A q JA (28) Where: PDmax is the maximum power dissipation in the amplifier (W). Tmax is the absolute maximum junction temperature (C). TA is the ambient temperature (C). JA = JC + CA JC is the thermal coefficient from the silicon junctions to the case (C/W). CA is the thermal coefficient from the case to ambient air (C/W). For systems where heat dissipation is more critical, the THS4500 family of devices is offered in an 8-pin MSOP with PowerPAD. The thermal coefficient for the MSOP PowerPAD package is substantially improved over the traditional SOIC. Maximum power dissipation levels are depicted in the graph for the two packages. The data for the DGN package assumes a board layout that follows the PowerPAD layout guidelines referenced above and detailed in the PowerPAD application notes in the Additional Reference Materialsection at the end of the data sheet. 3.5 8-Pin DGN Package 3 2.5 2 8-Pin D Package 1.5 1 0.5 0 -40 -20 0 20 40 60 TA - Ambient T emperature - C 80 JA = 170C/W for 8-Pin SOIC (D) JA = 58.4C/W for 8-Pin MSOP (DGN) J = 150C, No Airflow Power Dissipation and Thermal Considerations 32 maximum junction temperature of 150C is exceeded. For best performance, design for a maximum junction temperature of 125C. Between 125C and 150C, damage does not occur, but the performance of the amplifier begins to degrade. PD - Maximum Power Dissipation - W PowerPAD PCB LAYOUT CONSIDERATIONS Figure 114. Maximum Power Dissipation vs Ambient Temperature When determining whether or not the device satisfies the maximum power dissipation requirement, it is important to not only consider quiescent power Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com dissipation, but also dynamic power dissipation. Often times, this is difficult to quantify because the signal pattern is inconsistent, but an estimate of the RMS power dissipation can provide visibility into a possible problem. DRIVING CAPACITIVE LOADS High-speed amplifiers are typically not well-suited for driving large capacitive loads. If necessary, however, the load capacitance should be isolated by two isolation resistors in series with the output. The requisite isolation resistor size depends on the value of the capacitance, but 10 to 25 is a good place to begin the optimization process. Larger isolation resistors decrease the amount of peaking in the frequency response induced by the capacitive load, but this comes at the expense of larger voltage drop across the resistors, increasing the output swing requirements of the system. high frequency return currents, but often is not required. EVALUATION FIXTURES, SPICE MODELS, AND APPLICTIONS SUPPORT Texas Instruments is committed to providing its customers with the highest quality of applications support. To support this goal, an evaluation board has been developed for the THS4500 family of fully differential amplifiers. The evaluation board can be obtained by ordering through the Texas Instruments web site, www.ti.com, or through your local Texas Instruments sales representative. Schematic for the evaluation board is shown below with their default component values. Unpopulated footprints are shown to provide insight into design flexibility. C4 R0805 VS Rf J1 Rg RS VS VS Riso + RT - + C1 R1 CL C0805 C2 R1206 C0805 R2 1 PD U1 THS450X R6 4 7 R0805 3 _ R0805 R0805 R3 8 + 2 5 6 VOCM Riso -VS C0805 R4 PwrPad C5 C0805 C7 C0805 R0805 R7 J2 J3 J2 J3 C6 C0805 -VS R5 R0805 C3 Riso = 10 - 25 C0805 Rf J2 Rg R8 R0805 J3 Use of Isolation Resistors With a Capacitive Load. R9 R0805 R0805 R9 4 J4 3 5 R11 R1206 6 T1 1 Simplified Schematic of the Evaluation Board. Power Supply Decoupling, VOCM, and Power Down Circuitry Not Shown Figure 115. POWER SUPPLY DECOUPLING TECHNIQUES AND RECOMMENDATIONS Power supply decoupling is a critical aspect of any high-performance amplifier design process. Careful decoupling provides higher quality ac performance (most notably improved distortion performance). The following guidelines ensure the highest level of performance. 1. Place decoupling capacitors as close to the power supply inputs as possible, with the goal of minimizing the inductance of the path from ground to the power supply. 2. Placement priority should be as follows: smaller capacitors should be closer to the device. 3. Use of solid power and ground planes is recommended to reduce the inductance along power supply return current paths. 4. Recommended values for power supply decoupling include 10-F and 0.1-F capacitors for each supply. A 1000-pF capacitor can be used across the supplies as well for extremely Figure 116. Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the THS4500 family of devices is available through the Texas Instruments web site (www.ti.com). The PIC is also available for design assistance and detailed product information. These models do a good job of predicting small-signal ac and transient performance under a wide variety of operating conditions. They are not intended to model the distortion characteristics of the amplifier, nor do they attempt to distinguish between the package types in their small-signal ac performance. Detailed information about what is and is not modeled is contained in the model file itself. Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 Submit Documentation Feedback 33 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com ADDITIONAL REFERENCE MATERIAL * * * * * * * 34 PowerPAD Made Easy, application brief, Texas Instruments Literature Number SLMA004. PowerPAD Thermally Enhanced Package, technical brief, Texas Instruments Literature Number SLMA002. Karki, James. Fully Differential Amplifiers.application report, Texas Instruments Literature Number SLOA054D. Karki, James. Fully Differential Amplifiers Applications: Line Termination, Driving High-Speed ADCs, and Differential Transmission Lines. Texas Instruments Analog Applications Journal, February 2001. Carter, Bruce. A Differential Op-Amp Circuit Collection. application report, Texas Instruments Literature Number SLOA064. Carter, Bruce. Differential Op-Amp Single-Supply Design Technique, application report, Texas Instruments Literature Number SLOA072. Karki, James. Designing for Low Distortion with High-Speed Op Amps. Texas Instruments Analog Applications Journal, July 2001. Submit Documentation Feedback Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 THS4502 THS4503 SLOS352E - APRIL 2002 - REVISED OCTOBER 2011 www.ti.com REVISION HISTORY Changes from Revision D (January 2004) to Revision E Page * Added WARNING to DESCRIPTION ................................................................................................................................... 1 * Added Maximum junction temperature to prevent oscillation, TJ and footnote to ABSOLUTE MAXIMUM RATINGS ........ 3 * Deleted power rating and footnote from PACKAGE DISSIPATION RATINGS .................................................................... 3 * Added MAXIMUM DIE TEMPERATURE TO PREVENT OSCILLATION section .............................................................. 21 Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): THS4502 THS4503 Submit Documentation Feedback 35 PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) THS4502CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 4502C THS4502CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 4502C THS4502CDGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 BCG THS4502CDGNG4 ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 BCG THS4502CDGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 BCG THS4502CDGNRG4 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 BCG THS4502ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 4502I THS4502IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 4502I THS4502IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ASX THS4502IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ASX THS4502IDGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BCI THS4502IDGNG4 ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BCI THS4502IDGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BCI THS4502IDGNRG4 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BCI THS4502IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 4502I THS4502IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 4502I THS4503CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 4503C Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Orderable Device Status (1) (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) THS4503CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 4503C THS4503CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ATY THS4503CDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ATY THS4503CDGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 BCK THS4503CDGNG4 ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 BCK THS4503CDGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 BCK THS4503CDGNRG4 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 BCK THS4503CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 4503C THS4503CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 4503C THS4503ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 4503I THS4503IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 4503I THS4503IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ASY THS4503IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ASY THS4503IDGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BCL THS4503IDGNG4 ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BCL THS4503IDGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BCL THS4503IDGNRG4 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BCL The marketing status values are defined as follows: Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF THS4503 : * Enhanced Product: THS4503-EP NOTE: Qualified Version Definitions: Addendum-Page 3 PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 * Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 4 PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant THS4502CDGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4502IDGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4502IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 THS4503CDGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4503CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 THS4503IDGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS4502CDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 THS4502IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 THS4502IDR SOIC D 8 2500 367.0 367.0 35.0 THS4503CDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 THS4503CDR SOIC D 8 2500 367.0 367.0 35.0 THS4503IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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