T89C51CC02UA-SISIM - Atmel - Datasheet.Directory

Rev. 4126F–CA N–12/0 3

Features

•80C51 Core Architect ure

•256 Bytes of On-chip RAM

•256 Bytes of On-chip XRAM

•16K Bytes of On-chip Flash Memory

– Data Retention: 10 Years at 85°C

– Erase/Writ e Cy cle: 100K

•2K Bytes of On-chip Flash for Bootl oader

•2K Bytes of On-chip EEPROM

– Erase/Writ e Cycle: 100K

•14-sources 4-level Interrupts

•Three 16-bit Timers/Counter s

•Full Duplex UART Compatible 80C51

•Maximum Crystal Frequency 40 MHz. In X2 Mode, 20 MHz (CPU Core, 40 MHz)

•Three or Four Ports: 16 or 20 Digital I/O Lines

•Two-channel 16-bi t PC A

– PWM (8-bit)

– High-speed Output

– Timer and Edge Capture

•Double D a ta Pointe r

•21-bit Watchdog Timer (7 Programmab le bits)

•A 10-bit Resolution Analog-t o-Di gital Converter (ADC) with 8 Multiplexed Inputs

•Full CAN Controll er

– Full y Compli ant with CAN rev.# 2.0A and 2.0B

– Optimized Structure for Communi cation Management (V ia SFR)

– 4 Independent Message Objects

-Each Message Obj ect Programmable on Transmission or Reception

-Indi vidual Tag and Mask Fi lt ers up to 29-bit Identi fi er/Channel

-8-byt e Cyclic Data Regist er (FIFO) /Message Object

-16-bi t Stat us and Control Register/Message Object

-16-bi t Time-Stamping Register/Message O bject

-CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message

Object

-Access to Message Object Control and Data Registers Via SFR

-Program mable Reception Buffer Length up to 4 Message Objects

-Prior ity Management of Reception of Hits on Several Message Objects

Simultaneously (Basic CAN Feature)

-Prior ity Management for Transm ission

-Message O bject Overrun Interrupt

– Supports

-Time Triggered Communication

-Autobaud and Listening Mode

-Progra mmabl e Automatic Reply Mode

•1-Mbit/s Maximum Transfer Rate at 8 MHz(1) Crystal Frequency In X2 Mode

•Readable Error Counters

•Programmable Link to On-chip Timer for Time Stamping and Network Synchronization

•Independent Baud Rate Prescaler

•Data, Rem ote, Error and Overload Frame Handling

•Power-saving Modes

– Idle Mode

– Power-down Mode

•Power Supply: 3 V olt s to 5.5 Volts

•Temperature Range: Industr ial (- 40° to +85°C)

•Packages: SOIC28, SOIC24, PLCC28, VQFP32

Note: 1. At BRP = 1 sampli ng point will be fixed.

E nha nced 8- bit

Microcontroller

with CAN

Controller and

Flash

T89C51CC02

4126F–CAN–12/03

Description Part of the CANaryTM fam il y of 8-bit microco ntrollers dedicated t o CAN network app lica-

tions, the T89C51CC02 is a low-pin count 8-bit Flash microcontroller.

In X2 Mode a maximum externa l clock rate of 2 0 MHz reach es a 300 ns cycle time.

Besides the ful l CAN controller T89C51CC02 provides 16K Bytes of Flash memory

including In-System Programming (ISP), 2K Bytes Boot Flash Memory, 2K Bytes

EEPROM and 512 Byte s R AM.

Special attention is payed to the reduction of the electro-magnetic emission of

T89C51CC02.

Block Diagram

Note: 1. 8 analog Inputs/8 Digital I/O.

2. 2-bit I/O Port .

Timer 0 INT

RAM

256x8

T1 RxD

TxD

XTAL2

XTAL1

UART

CPU

Timer 1

INT1

Ctrl

INT0

C51

CORE

P2(2)

Port 1 Port 2Port 3

Parallel I/O Ports

P1(1)

XRAM

256 x 8

IB-bus

PCA

RESET

Watch

Dog

PCA

ECI

Vss

Vcc

Timer 2

T2EX

Port 4

P4(2)

10-bit

ADC

Flash

16K x

Boot

loader

2K x 8

PROM

2K x 8 CAN

CONTROLLER

TxDC

RxDC

VAVCC

VAREF

VAGND

T89C51CC02

4126F–CAN–12/03

Pin Configurations

P3.4/T0

P3.3/INT1

P4.1/RxDC

P3.7

P3.2/INT0

P1.5/AN5

P1.7/AN7

P1.6/AN6

P2.0

VAREF

VAVCC

VAGND

P1.0/

AN0/T2

P1.1/AN1/T2EX

P1.2/AN2/ECI

P1.3 /AN3/CEX0

P1.4/AN4/CEX1

RESE

VCC

VSS

P 4 .0/T xD C

P2.1

P3.6

P 3 .5/T1

P3.1/TxD 13

P3.0/RxD 14 16 XTAL1

15 XTAL2

SO28

P1.3/AN3/CEX0

P1.2/AN2/ECI

P1.1/AN1/T2EX

P 1.0/AN 0 /T2

VAREF

VAGND

RESET

VSS

VCC

XTAL1

XTAL2

P3.7

P4.0/TxDC

P 4 .1/R x DC

P2.1

P3.6

P2.0

P1.4/AN4/CEX1

P1.5/AN5

P1.6/AN6

P1.7/AN7

P3.0/RxD

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

VAVCC

PLCC-28

P3.1/TxD

P3.0/RxD

P4.1/RxDC

P3.4/T0

XTAL2

P1.5/AN5

P1.7/AN7

P1.6/AN6

RESE

VAREF

VAVCC

VAGND

P1.0/

AN0/T2

P1.1/AN1/T2EX

P1.2/AN2/ECI

P1.3/A N3 /CEX0

P1.4/AN4/CEX1

VSS

XT A L1

VCC

P 4.0/Tx DC

P 3 .5 /T 1

P3.3/INT 1

P3.2/INT 0

SO24

T89C51CC02

4126F–CAN–12/03

P1.3/AN3/CEX0

P1.2/AN2/ECI

P1.1/AN1/T2EX

P1.0/AN 0/T2

VAREF

VAGND

RESET

VSS

VCC

XTAL1

XTAL2

P3.7

P4.0/TxDC

P4.1/RxDC

P2.1

P3.6

P2.0

P1.4/AN4/CEX1

P1.5/AN5

P1.6/AN6

P1.7/AN7

P3.0/RxD

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

VAVCC

QFP-32

T89C51CC02

4126F–CAN–12/03

Pin D escri ption

Pin Name Type De scr ipt ion

VSS GND Circuit ground

VCC Supply Voltage

VAREF Reference Voltage fo r ADC (input)

VAVCC Supply Voltage f or ADC

VAG ND Reference Ground for ADC (internal y connected wit h the VSS)

P1.0:7 I/O Por t 1:

Is an 8-bit bi-di recti onal I /O port with i ntern al pull -ups . Port 1 pins ca n be used for digi tal input /outpu t or as

analog i nputs for the Analog Digital Converter (ADC). Por t 1 pi ns that have 1’s written to them are pulled

high by the internal pull-up transistors and can be used as inputs in thi s state. As input s, Port 1 pins that

are being pul led low externally wi ll be the source of current (IIL, See section ’Electrical Characteristic’)

because of the in ter nal pull-ups. Por t 1 pi ns are assi gned to be used as analog inputs via the ADCCF

As a secondary digital functi on, port 1 contains the T imer 2 external t rigger and clock input; the PCA

external clock inpu t and the PCA module I/ O .

P1.0/AN0/T2

Analog in put channel 0,

External clock input for Tim er/counter2.

P1.1/AN1/T2EX

Analog in put channel 1,

Trigger input for Timer/counter2.

P1.2/AN2/ECI

Analog in put channel 2,

PCA external clock input.

P1.3/AN3/CEX0

Analog in put channel 3,

PCA modul e 0 Entry of input/PWM output.

P1.4/AN4/CEX1

Analog in put channel 4,

PCA modul e 1 Entry of input/PWM output.

P1.5/AN5

Analog in put channel 5,

P1.6/AN6

Analog in put channel 6,

P1.7/AN7

Analog in put channel 7,

It can drive CMOS inputs without ext ernal pull-up s.

P2.0:1 I/O Por t 2:

Is an 2-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1’s written to them ar e pulled

high by the internal pull- ups and can be used as inputs in thi s state. As input s, Port 2 pins that are being

pulle d low externally will be a sour ce of current (IIL, on the dat asheet) beca use of the in ter nal pull-ups.

In the T89C51CC02 Port 2 can sink or source 5m A. It can drive CMOS inputs wit hout external pull-ups.

T89C51CC02

4126F–CAN–12/03

P3.0:7 I/O Por t 3:

Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them ar e pulled

high by the internal pull-up transistors and can be used as inputs in thi s state. As input s, Port 3 pins that

are being pul led low externally will be a sour ce of current (IIL, See section ’Electrical Characteristic’)

because of the in ternal pull- ups.

The output latch corresponding to a secondary function must be pr ogrammed to one for that function to

operate (except for TxD and WR). The secondary functions are assigned to the pins of port 3 as follows:

P3.0/RxD: Receiver data input (asynchronous ) or dat a input /output (synchronous) of th e seri al int erface

P3.1/TxD: Tr ansmitter data output (asynchronous ) or cl ock output (synchronous) of the serial interface

P3.2/INT0: External int errupt 0 input/ timer 0 gate contr ol i nput

P3.3/INT1: External int errupt 1 input/ timer 1 gate contr ol i nput

P3.4/T0: Tim er 0 counter input

P3.5/T1: Tim er 1 counter input

P3.6: Regular I/ O port pi n

P3.7: Regular I/ O port pi n

P4.0:1 I/O Por t 4:

Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1’s written to them ar e pulled

high by the internal pull-up s and can be used as input s in thi s state. As input s, Port 4 pins that are bei ng

pulle d low externally wil l be a source of current (II L, on the dat asheet) beca use of the in ter nal pull-up

transis tor.

The output latch corresponding to a secondar y function R xDC must be pr ogrammed to one for that

function to operate. The secondary functions are assigned to the two pi ns of por t 4 as follows:

P4.0/TxDC:

Transmitt er out put of CAN controller

P4.1/RxDC:

Receiver input of CAN controller.

It can drive CMOS inputs without ext ernal pull-up s.

RESET I/O Reset:

A high level on thi s pin during two machine cycles whil e the oscillat or is runni ng resets the device. An

inter nal pull-down re sistor to VSS permits power- on reset using only an ext ernal capa citor to VCC.

XTAL1 I XTAL1:

Input of the i nverting osc il lator amplif ier and input of th e int ernal clock generator circuits. To drive the

device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To

operate above a frequency of 16 MHz, a duty cycle of 50% should be maintai ned.

XTAL2 O XTAL2:

Output from the invert ing oscillator amplifier.

Pin Name Type De scr ipt ion

T89C51CC02

4126F–CAN–12/03

I/O Configurations Each Port SFR operates via type-D l atches, as illu strated i n Figure 1 for Ports 3 and 4. A

CPU ’w rite to latch’ sign al ini tiate s tra nsfer o f i nter nal bus data i nto the typ e-D latch. A

CPU ’read latch’ signa l transf ers the latched Q output onto the internal bus. Similarly, a

’re ad pin’ s ign al tra nsfe rs th e lo gic al leve l of the Port pin . Som e Po rt da ta ins truc tio ns

ac tivate t he ’re ad latch ’ signal while others activa te the ’r ead pi n’ sign al. Latc h instruc -

tions are referred to as Read-Modify-Write instructions. Each I/O line may be

independently programmed as input or output.

Port Structure Fig ure 1 show s the structure of Ports, which have int ernal pull-ups. An extern al source

ca n pull th e pin low. Eac h Port p in can be con fi gured e ithe r for ge neral- purpose I/O or

for its alternate input output function.

To use a pin for general-purpose output, set or clear the corresponding bit in the Px reg-

ister (x = 1 to 4). To use a pin for general-purpose input, set the bit i n the Px register.

This turns off the output FET drive.

To conf igure a pi n for its alternate function , set the bit in the Px register. W hen t he latch

is set, the ’a lternate output function’ signal controls the output level (Se e Figure 1). The

operation of Ports is discussed further in ’Quasi-Bi-directional Port Operation’

paragraph.

Fi gure 1 . Ports Structure

Note: 1. The internal pull-up can be disabled on P1 when analog function is selected.

LATCH

INTERNAL

WRITE

LATCH

READ

LATCH

ALTERNATE

OUTPUT

FUNCTION

VCC

INTERNAL

PULL-UP (1)

ALTERNATE

INPUT

FUNCTION

BUS

P2.x

P3.x

P4.x

P1.x(1)

T89C51CC02

4126F–CAN–12/03

Read-Modify-Write

Instructions Some inst ru ctions read the latch data rather than the pin data. The latch based instruc-

tions read the data, modify the data and then rewrite the latch. These are called ’R ead-

Modify-Write’ instructions. Below is a complete list of these special instructions (See

Ta ble 1). W he n the d esti nat ion opera nd is a Po rt o r a Port bit, t hese ins truc tion s read

the latch rather than the pin:

It is not obv ious that the last three in structions in this li st are Rea d-Modify-Write i nstruc-

tions . These ins tructio ns read t he port (al l 8 bits), mod ify the sp ecifical ly addre ssed bit

and write the new byte back to the latch. These Read-Modify-Write instructions are

directed to the latch rather than the pin in order to avoid possible misinterpretation of

voltage (and therefore, lo gic) levels at the pin. F or example, a Port bit used to drive the

base of an external bipolar transistor cannot rise above the transistor’s bas e-em itter

junction v oltage (a val ue lower than V IL). With a logic on e written to the b it, attempts by

the CPU to read the Port at the pin are misinterpreted as logic zero. A read of t he latch

rather than the pins returns the correct logic one value.

Quasi Bi-directional Port

Operation Po rt 1, Port 3 an d Port 4 ha ve fixed int ernal pu ll-u ps and are referr ed to as ’q uasi-bid i-

rec tional’ Ports . W hen co nfigure d as an input, the pin impeda nce ap pears as l ogic one

and sourc es curren t in re sponse to an extern al log ic zero cond it io n. Resets wr ite logic

one to all P ort latches. If logical zero is subsequently written to a Port latch, it can be

returned to input conditions by a logic one written t o the latch.

Note: Port latch values change near the end of Read-Modify-Write insruction cycles. Output

buffers (and therefore the pin state) are updated early in the instruction after Read-Mod-

ify- Write in struction cycle.

Logical zero-to -one transitions in Port 1, Port 3 and Po rt 4 use an additional pull-up (p1)

to aid this lo gic transition See Fi gure 2. This increas es switch spe ed. T his extra pull -u p

sources 100 times normal internal circuit current during 2 oscillator clock periods. The

intern al pull-up s are fi eld-eff ect transi stors rat her than linear re sistors. P ull-ups consist

of three p-chan nel FE T (pFET) devices. A pF ET is on wh en the gate sens es logic zero

and off when the ga te senses logic one. pFET #1 is turned on for two oscillator periods

im me dia tely aft er a zer o- to-on e tr an sitio n in th e P ort latch . A lo gic o ne a t the Po rt p in

turns on pFET #3 (a weak pull-up) through the inverter. This i nverter and pFET pair form

a latch to drive logic one. pFET #2 is a very weak pull-up switched on whenever the

Table 1. R ead/ Mod ify/Write Instructions

Instruction Description Example

ANL Logical AND ANL P1, A

ORL Logic al OR ORL P2, A

XRL Logical EX-OR XRL P3, A

JBC Jump if bit = 1 and clear bit JBC P1.1, LABEL

CP L Complement bit CP L P3.0

INC Increment INC P2

DEC Decre ment DEC P2

DJNZ Decrement and jump if not zero DJNZ P3, LABEL

MO V Px.y, C Move ca rry bit to bit y of Port x MO V P1.5, C

CLR Px.y Clear bit y of Port x CLR P2.4

SET Px.y Set bit y of Port x SET P3.3

T89C51CC02

4126F–CAN–12/03

ass ociate d nFET i s swit ched off. This is tradi tional CMOS swit ch conv ention. C urre nt

strengt hs are 1/10 that of pFET #3.

Note: During Reset, pFET#1 is not avtivated. During Reset, only the weak pFET#3 pull up the

pin.

Fi gure 2 . Internal Pull-up Configurations

READ PIN

INPUT DATA

P1.x

OUTPUT DATA

2 Osc. PERIOD S

p1(1) p2 p3

VCCVCCVCC

P2.x

P3.x

P4.x

T89C51CC02

4126F–CAN–12/03

SFR Ma pping Tables 3 through Table 11 show the Special Function Registers (SFRs) of the

T89C51CC02.

Table 2. C51 Core S FRs

MnemonicAddName 76543210

ACC E0h Accumulator

B F0h B Register

P SW D0h Prog r a m Status Wor d CY A C F 0 R S 1 RS0 OV F1 P

SP 81h St ack Pointer

DPL 82h Data Pointer Low

byte

LSB of DPTR

DPH 83h Data Pointer High

byte

MSB of DPTR

Table 3. I/O Port SFRs

MnemonicAddName 76543210

P1 90h Port 1

P2 A0h Port 2 (x2)

P3 B0 h Port 3

P4 C0h Port 4 (x2)

Table 4. Timer s S FR s

MnemonicAddName 76543210

TH0 8Ch T imer/Counter 0 High

byte

TL0 8Ah Timer/Counter 0 Low

byte

TH1 8Dh T imer/Counter 1 High

byte

TL1 8Bh Timer/Counter 1 Low

byte

TH2 CDh T imer/Counter 2 High

byte

TL2 CCh Timer/Counter 2 Low

byte

TCON 88h Timer/Counter 0 and

1 control TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

TMOD 89h Timer/Counter 0 and

1 Modes GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00

T89C51CC02

4126F–CAN–12/03

T2CON C8h Time r/ C o un ter 2

control TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#

T2MOD C9h Timer/ Coun ter 2

Mode T2OE DCEN

RCAP2H CBh Time r/ C o un ter 2

Reload/Captur e High

byte

RCAP2L CAh Time r/ C o un ter 2

Reload/Captur e Low

byte

WDTRST A6h WatchDog Timer

Reset

WDTPRG A7h WatchDog Timer

Program S2 S1 S0

Table 4. Timers S FRs (Continued)

MnemonicAddName 76543210

Table 5. Serial I/O Port SFRs

MnemonicAddName 76543210

SCON 98h Serial Control FE/SM0 SM1 SM2 REN TB8 RB8 TI RI

SBUF 99h Serial Data Buffer

SADEN B9h Slave Address Mask

SADDR A9h Slave Address

Table 6. PCA SFRs

MnemonicAddName 76543210

CCON D8h PCA Timer/Counter

Control CF CR CCF4 CCF3 CCF2 CCF1 CCF0

CMOD D9h PCA Timer/Counter

Mode CIDL CPS1 CPS0 ECF

CL E9h PCA Timer/Counter

Low byte

CH F9h PCA Timer/Counter

High byt e

CCAPM0

CCAPM1 DAh

DBh

PCA Timer/Counter

Mode 0

PCA Timer/Counter

Mode 1

ECOM0

ECOM1 CAPP0

CAPP1 CAPN0

CAPN1 MAT0

MAT1 TOG0

TOG1 PWM0

PWM1 ECCF0

ECCF1

CCAP0H

CCAP1H FAh

FBh

PCA Compare

Capture Module 0 H

PCA Compare

Capture Module 1 H

CCAP0H7

CCAP1H7 CCAP0H6

CCAP1H6 CCAP0H5

CCAP1H5 CCAP0H4

CCAP1H4 CCAP0H3

CCAP1H3 CCAP0H2

CCAP1H2 CCAP0H1

CCAP1H1 CCAP0H0

CCAP1H0

T89C51CC02

4126F–CAN–12/03

CCAP0L

CCAP1L EAh

EBh

PCA Compare

Capture Module 0 L

PCA Compare

Capture Module 1 L

CCAP0L7

CCAP1L7 CCAP0L6

CCAP1L6 CCAP0L5

CCAP1L5 CCAP0L4

CCAP1L4 CCAP0L3

CCAP1L3 CCAP0L2

CCAP1L2 CCAP0L1

CCAP1L1 CCAP0L0

CCAP1L0

Table 6. PCA SFRs (Continued)

MnemonicAddName 76543210

Table 7. Interrupt SFRs

MnemonicAddName 76543210

IEN0 A8h Interrupt Enable

Control 0 EA EC ET2 ES ET1 EX1 ET0 EX0

IEN1 E8h Interrupt Enable

Control 1 ETIM EADC ECAN

IPL0 B8h Interrupt Priority

Control Low 0 PPC PT2 PS PT1 PX1 PT0 PX0

IPH0 B7h Interrupt Priority

Control High 0 PPCH PT2H PSH PT1H PX1H PT0H PX0H

IPL1 F8h Interrupt Priority

Control Low 1 POVRL PADCL PCANL

IPH1 F7h Interrupt Priority

Control High1 POVRH PADCH PCANH

Table 8. ADC SFRs

MnemonicAddName 76543210

ADCON F 3h ADC Control PSIDLE ADEN ADEOC ADSST SCH2 SCH1 SCH0

ADCF F6h ADC Configuration CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0

ADCLK F2h ADC Clock PRS4 P RS 3 PRS2 PRS1 PRS0

ADDH F5h ADC Data High byte ADAT9 ADAT8 ADAT7 ADAT6 ADAT5 ADAT4 ADAT3 ADAT2

ADDL F4h ADC Data Low byte ADAT1 ADAT0

Table 9. CAN SFRs

MnemonicAddName 76543210

CANGCON ABh CAN General

Control ABRQ OVRQ TTC SYNCTTC AUT-BAUD TEST ENA GRES

CANGSTA AAh CAN General

Status OVFG TBSY RBSY ENFG BOFF ERRP

CANGIT 9Bh CAN General

Interrupt CANIT OVRTIM OVRBUF SERG CERG FERG AERG

CANBT1 B4h CAN bit Timing 1 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0

CANBT2 B5h CAN bit Timing 2 SJW1 SJW0 PRS2 PRS1 PRS0

CANBT3 B6h CAN bit Timing 3 PHS22 PHS21 PHS20 PHS12 PHS11 PHS10 SMP

T89C51CC02

4126F–CAN–12/03

CANEN CFh CAN Enable

Channel byte ENCH3 ENCH2 ENCH1 ENCH0

CANGIE C1h CAN General

Interrupt Enable ENRX ENTX ENERCH ENBUF ENERG

CANIE C3h CAN Interrupt

Enable Channel

byte IECH3 IECH2 IECH1 IECH0

CANSIT BBh CAN Status Interrupt

Channel byte SIT3 SIT2 SIT1 SIT0

CANTCON A1h CAN Timer Control TPRESC 7 TPRESC 6 TPRESC 5 TPRESC 4 TPRESC 3 TPRESC 2 TPRESC 1 TPRESC 0

CANTIMH ADh CAN Timer high CANTIM 15 CANTIM 14 CANTIM 13 CANTIM 12 CANTIM 11 CANTIM 10 CANT IM 9 CA NTIM 8

CANT IML ACh CAN T imer low CANTIM 7 CANTIM 6 CAN TIM 5 CANTIM 4 CANTIM 3 CANTIM 2 CANT IM 1 CAN TIM 0

CANSTMPH AFh CAN Timer Stamp

high TIMSTMP

15 TIMSTMP

14 TIMSTM P

13 TIMSTMP

12 TIMSTMP 11 TIMSTMP

10 TIMSTMP 9 TIMSTMP 8

CANSTMPL AEh CAN Timer Stamp

low TIMSTMP7 TIMSTMP 6 TIMSTMP 5 TIMSTMP 4 TIMSTMP 3 TIMSTMP 2 TIMSTMP 1 TIMSTMP 0

CANTTCH A5h CAN Timer TTC

high TIMTTC 15 TIMTTC 14 TIMTTC 13 TIMTTC 12 TIMTTC 11 TIMTTC 10 TIMTTC

9TIMTTC

CANTTCL A4h CAN Timer TTC low TIMTTC

7TIMTTC

6TIMTTC

5TIMTTC

4TIMTTC

3TIMTTC

2TIMTTC

1TIMTTC

CANTEC 9Ch CAN Transmit Error

Counter TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0

CANREC 9Dh CAN Receive Error

Counter REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0

CANPAGE B1h CAN Page - - CHNB1 CHNB0 AINC INDX2 INDX1 INDX0

CANSTCH B2h CAN S tatus Channel DLCW TXOK RXOK BERR SERR CERR FERR AERR

CANCONCH B3h CAN Control

Channel CONCH1 CONCH0 RPLV IDE DLC3 DLC2 DLC1 DLC0

CANMSG A3h CAN Message Data MSG7 MSG6 MSG5 MSG4 MSG3 MSG2 MSG1 MSG0

CANIDT1 BCh

CAN Identifier Tag

byte 1(Par t A)

CAN Identifier Tag

byte 1(PartB)

IDT10

IDT28 IDT9

IDT27 IDT8

IDT26 IDT7

IDT25 IDT6

IDT24 IDT5

IDT23 IDT4

IDT22 IDT3

IDT21

CANIDT2 BDh

CAN Identifier Tag

byte 2 (PartA)

CAN Identifier Tag

byte 2 (PartB)

IDT2

IDT20 IDT1

IDT19 IDT0

IDT18 -

IDT17 -

IDT16 -

IDT15 -

IDT14 -

IDT13

CANIDT3 BEh

CAN Identifier

Tag byte 3(PartA)

CAN Identifier

Tag byte 3(PartB)

IDT12

IDT11

IDT10

IDT9

IDT8

IDT7

IDT6

IDT5

CANIDT4 BFh

CAN Identifier

Tag byte 4(PartA)

CAN Identifier

Tag byte 4(PartB)

IDT4

IDT3

IDT2

IDT1

IDT0 RTRTAG -

RB1TAG RB0TAF

CANIDM1 C4h

CAN Identifier Mask

byte 1(PartA)

CAN Identifier Mask

byte 1(PartB)

IDMSK10

IDMSK28

IDMSK9

IDMSK27

IDMSK8

IDMSK26

IDMSK7

IDMSK25

IDMSK6

IDMSK24

IDMSK5

IDMSK23

IDMSK4

IDMSK22

IDMSK3

IDMSK21

Table 9. CAN SFRs (Continued)

MnemonicAddName 76543210

T89C51CC02

4126F–CAN–12/03

CANIDM2 C5h

CAN Identifier Mask

byte 2(PartA)

CAN Identifier Mask

byte 2(PartB)

IDMSK2

IDMSK20

IDMSK1

IDMSK19

IDMSK0

IDMSK18

IDMSK17

IDMSK16

IDMSK15

IDMSK14

IDMSK13

CANIDM3 C6h

CAN Identifier Mask

byte 3(PartA)

CAN Identifier Mask

byte 3(PartB)

IDMSK12

IDMSK11

IDMSK10

IDMSK9

IDMSK8

IDMSK7

IDMSK6

IDMSK5

CANIDM4 C7h

CAN Identifier Mask

byte 4(PartA)

CAN Identifier Mask

byte 4(PartB)

IDMSK4

IDMSK3

IDMSK2

IDMSK1

IDMSK0 RTRMSK - IDEMSK

Table 9. CAN SFRs (Continued)

MnemonicAddName 76543210

Table 10. O ther SFRs

MnemonicAddName 76543210

PCON 87h Power Control SMOD1 SMOD0 POF GF1 GF0 PD IDL

AUXR1 A2h Auxiliary Register 1 ENBOOT GF3 0 DPS

CKCON 8Fh Clock Control CANX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2

FCON D1h Flash Control FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY

EECON D2 h EEPROM Contol EEPL3 EEPL2 EEPL1 EEPL0 EEE EEBUSY

T89C51CC02

4126F–CAN–12/03

Reserved

Notes: 1. These registers are bit-addressable.

Sixteen addresses in the SFR space are both byt e-addressable and bit-addressable. The bit-addressable SFRs are those

whose address ends in 0 and 8. The bit addresses, in thi s area, are 0x80 through to 0xFF.

2. AUXR1 bit ENBOOT is initialized with the content of the BLJB bit inverted.

Table 11. S FR Mapping

0/8(1) 1/9 2/A 3/B 4/C 5/D 6/E 7/F

F8h IPL1

xxxx x000 CH

0000 0000 CCAP0H

0000 0000 CCAP1H

0000 0000 FFh

F0h B

0000 0000 ADCLK

xxx0 0000 ADCON

x000 0000 ADDL

0000 0000 ADDH

0000 0000 ADCF

0000 0000 IPH1

xxxx x000 F7h

E8h IEN1

xxxx x000 CL

0000 0000 CCAP0L

0000 0000 CCAP1L

0000 0000 EFh

E0h ACC

0000 0000 E7h

D8h CCON

0000 0000 CMOD

0xxx x000 CCAPM0

x000 0000 CCAPM1

x000 0000 DFh

D0h PSW

0000 0000 FCON

0000 0000 EECON

xxxx xx00 D7h

C8h T2CON

0000 0000 T2MOD

xxxx xx00 RCAP2L

0000 0000 RCAP2H

0000 0000 TL2

0000 0000 TH2

0000 0000 CANEN

xxxx 0000 CFh

C0h P4

xxxx xx11 CANGIE

1100 0000 CANIE

1111 0000 CANIDM1

xxxx xxxx CANIDM2

xxxx xxxx CANIDM3

xxxx xxxx CANIDM4

xxxx xxxx C7h

B8h IPL0

x000 0000 SADEN

0000 0000 CANSIT

xxxx 0000 CANIDT1

xxxx xxxx CANIDT2

xxxx xxxx CANIDT3

xxxx xxxx CANIDT4

xxxx xxxx BFh

B0h P3

1111 1111 CANPAGE

1100 0000 CANSTCH

xxxx xxxx CANCONCH

xxxx xxxx CANBT1

xxxx xxxx CANBT2

xxxx xxxx CANBT3

xxxx xxxx IPH0

x000 0000 B7h

A8h IEN0

0000 0000 SADDR

0000 0000 CANGSTA

1010 0000 CANGCON

0000 0000 CANTIML

0000 0000 CANTIMH

0000 0000 CANSTMPL

xxxx xxxx CANSTMPH

xxxx xxx x AFh

A0h P2

xxxx xx11 CANTCON

0000 0000 AUXR1(2)

xxxx 00x0 CANMSG

xxxx xxxx CANTTCL

0000 0000 CANTTCH

0000 0000 WDTRST

1111 1111 WDTPRG

xxxx x000 A7h

98h SCON

0000 0000 SBUF

0000 0000 CANGIT

0x00 0000 CANTEC

0000 0000 CANREC

0000 0000 9Fh

90h P1

1111 1111 97h

88h TCON

0000 0000 TMOD

0000 0000 TL0

0000 0000 TL1

0000 0000 TH0

0000 0000 TH1

0000 0000 CKCON

0000 0000 8Fh

80h SP

0000 0111 DPL

0000 0000 DPH

0000 0000 PCON

00x1 0000 87h

0/8(1) 1/9 2/A 3/B 4/C 5/D 6/E 7/F

T89C51CC02

4126F–CAN–12/03

Clock The T89C51CC02 core needs only 6 clock periods per machine cycle. This feature,

called “X2”, provides the following advantages:

• Divides frequency cryst als by 2 (cheaper crystals) while keeping the same CPU

power.

• Sa ves power consumption while keepi ng the same CPU power (oscillator power

saving).

• Sa ves power consum ption by dividing dynamic operat ing frequenc y by 2 in

operating and idle modes.

• Increases CPU power by 2 while keeping the same crystal frequency.

In order to keep the original C51 com patibility, a divider-by-2 is inserted between the

XT AL1 signal and the m ain clo ck input of the c ore (phase gene rator). This divi der may

be disabled by the software.

An extra feature is available to start after Reset in the X2 Mode. This feature can be

enabled by a bit X2B in the Hardware Se curi ty By te. This bit is des cribed in the section

’In-Sys tem Progra mming’ .

Description The X2 bit in the CKCON register (See Tabl e 12) allows switching from 12 clock cycles

per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated

(STD mode).

Se tting this bit activat es the X 2 featur e (X2 Mod e) for the CPU Clock only (See Fi gure

3).

The Timers 0, 1 and 2, Uart, PCA, watchdog or CAN switch in X2 Mode only if the corre-

sponding bit is cleared in the CKCON register.

The clock for the whole circuit and peripheral is first divided by two before being used by

the CPU core and peripherals. This allows any cyc l ic ratio to be ac cepte d on the XTAL1

input . In X2 Mo de, as this di vider is bypassed, the signals on XTAL1 must have a cyclic

rat io betwee n 4 0 to 60% . Figur e 3. sho ws the clock g ene ration b lock d iagram. The X2

bit is validated on the XT AL1 ÷ 2 risi ng edge to a void g lit ches when switc hing from the

X2 to the STD mode. Figure 4 shows the mode switching waveforms.

T89C51CC02

4126F–CAN–12/03

Figu re 3. Clock CPU Generation Diagram

TAL1

TAL2

PCON.1

CPU Core

÷ 2

PERIPH

CLOCK

Clock

Peripheral Clock Symbol

CPU

CLOCK

CPU Core Clock Symbol

CKCON.0

X2B

Hardware Byte

CANX2

CKCON.7 WDX2

CKCON.6 PCAX2

CKCON.5 SIX2

CKCON.4 T2X2

CKCON.3 T1X2

CKCON.2 T0X2

CKCON.1

IDL

PCON.0

CKCON.0

FCan Clock

FWd Clock

FPca Clock

FUart Clock

FT2 Clock

FT1 Clock

FT0 Clock

and ADC

On RESET

T89C51CC02

4126F–CAN–12/03

Figu re 4. Mode Switching Waveforms(1)

Note: 1. In order to prevent any incorrect operation while operating in the X2 Mode, users must be aware that all peripheral s using

the clock frequency as a time ref erence ( UART, tim ers.. .) will hav e thei r time refer ence divi ded by 2. For exampl e, a free run -

ning ti mer generat ing an interrupt every 20 ms wi ll then generate an interrupt every 10 ms. A UART with a 4800 baud rate

w ill h a ve a 9 600 baud rate.

XTAL2

XTAL1

CPU

clock

X2 bit

Mode

STD

Mode STD

Mode

T89C51CC02

4126F–CAN–12/03

CKCON (S:8Fh)

Clock Control Register

Note: 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit

has no effect.

Rese t Value = 0000 0000b

76543210

CANX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2

Bit

Number Bit

Mnemonic Description

7CANX2

CAN Clock (1 )

Clear to select 6 clock perio ds per peripher al clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

6WDX2

Watchdog Clock (1)

Clear to select 6 clock perio ds per peripher al clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

5 PCAX2 Programmable Counter Array Clock (1)

Clear to select 6 clock perio ds per peripher al clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

4SIX2

Enhanc ed UART clock (MODE 0 and 2) (1)

Clear to select 6 clock perio ds per peripher al clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

3T2X2

Timer 2 Clock (1)

Clear to select 6 clock perio ds per peripher al clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

2T1X2

Timer 1 Clock (1)

Clear to select 6 clock perio ds per peripher al clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

1T0X2

Timer 0 Clock (1)

Clear to select 6 clock perio ds per peripher al clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

0X2

CPU Clock

Clear to select 12 clock periods per machine cycle (STD mode) for CPU and al l

th e pe ri p he r al s.

Set to select 6 clock periods per machine cy cle (X2 Mode) and to enable the

individual peripherals ’X2’ bits.

T89C51CC02

4126F–CAN–12/03

Power Management Tw o pow er re duction m odes a re i mplem ente d in the T 89C51 CC0 2: the Idle mo de and

the P ower-do wn mode . These modes are detailed i n the followin g section s. In additio n

to these po wer reduct ion modes, t he clocks of the core and periph erals can be dynam i-

cally divided by 2 using the X2 Mode detailed in Section “Clock”.

Reset Pin I n order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, a

high level has to be applied on the RST pin. A bad level leads to a wrong initialisation of

the internal re gisters like SFRs , PC, etc. and to un predictable beh av ior of the microcon-

troller. A warm reset can be applied either directly on the RST pin or indirectly by an

internal reset source such as a watchdog, PCA, timer, etc.

At Power-up (cold reset) Two conditions are required before enabling a CPU start-up:

• VDD must reach the specified VDD range,

• The level on xtal1 inp ut mus t be outside the specification (VIH, VIL).

If one of these two conditions are not met, the microcontroller does not start correctly

and can execute an instruc tion fetch from anywhere in the program s pace. An active

level ap plied on the RS T pin must be maintained un til both of th e above co nditions are

met. A reset is active when the level VIH1 is reache d and wh en the pulse width c overs

the period of time where VDD and the oscillator are not stabilized. Two parameters have

to be taken into account to determine the reset pulse width:

• VDD rise ti me (vddrst),

• Oscillator star tup t ime (os c r s t).

To determine the capacitor the highest value of these two parameters has to be chosen.

The reset circuitry is s ho wn in Figure 5.

Fi gure 5 . Reset Circuitry

Tabl e 13 a nd Table 14 give som e typi cal exam ples for thre e values of VDD rise time s,

two v alues of oscillator start -up time and two pull- down res isto r value s.

Table 13. Minimum Reset Capacitor for a 50K Pull-down Resistor

oscrst/vddrst 1ms 10ms 100ms

5ms 820nF 1.2µF 12µF

20ms 2.7µF 3.9µF 12µF

VDD

Rrst

Crst

RST pin

Internal reset

Reset input circuitry

T89C51CC02

4126F–CAN–12/03

Table 14. Minimum Reset Capacitor for a 15k Pull-down Resistor

Note: These values assum e VDD star ts from 0v to the nominal value. If the time between two

on/off sequences is too fast, the power-supply decoupling capacitors may not be fully

discharged, leading to a bad reset sequence.

During a Normal

Operation (Warm Reset) Reset pi n mus t be m a int a ined fo r at le as t 2 mac h ine cyc les (2 4 o s c illator c lock per io ds )

to apply a reset sequence during normal operation. The number of clock periods is

mode ind epende nt (X2 or X1).

Watchdog Reset A 1K resistor must be added in series with the capacitor to allow the use of watchdog

reset pulse output on the RST pin or when an external power-supply supervisor is used.

Figure 6 shows the reset circuitry when a capacitor is us ed.

Fi gure 6 . Reset Circuitry for a Watch dog Conf iguration

Figure 7 shows the reset circuitry when an external reset circuit is used.

Fi gure 7 . Reset Circuitry Example Using an External Reset Circuit

oscrst/vddrst 1ms 10ms 100ms

5ms 2.7µF 4.7µF 47µF

20ms 10µF 15µF 47µF

VDD

Rrst

Crst

1k RST pin

Internal reset

watchdog

To other on-board cir cuitry

Reset input circuitry

VDD

Rrst

1k RST pin

Intern al reset

watchdog

To other on-board cir cuitry

Reset input circuitry

RST

External reset

circuit

T89C51CC02

4126F–CAN–12/03

Reset Recomme nd ation

to Prevent Flash

Corruption

When a Flash program memory is embedded on-chip, it is strongly recommended to

use an external reset chip (brown out device) to apply a reset (Figure 7). It prevents sys-

tem malfunction during periods o f insufficient power-supply voltage (p ower-su pply

failure, power supply switched off, etc.).

Idle Mode Idle mode is a power reduction mode that reduces the power consumption. In this mode,

program exec ution halts. Idle mode freezes the clock to the CPU at known states while

the peripherals continue to be clocked. The CPU status before entering Idle mode is

pr eserved, i .e., the p rogram c ounter a nd pro gram stat us word regi ster retai n their data

for the duration of Idle mode. The contents of the SFRs and RAM are also retained. The

status of the Port pins during Idle mode is detailed in T able 13.

Ente ring Idle Mode To enter Idle mode, set the I DL bit in PCO N regi ster (See Table 1 5). The T 89C51CC02

enters Idle mode upon execut ion of t he i nstruction that se ts IDL bit. The in struction that

sets IDL bit is the last instruction executed.

Note: If IDL bit and PD bit are set simultaneously, the T89C51CC02 enters Power-down m ode.

Then it does not go in Idle mode when exiting Power-down mode.

Exi t ing Idle Mode T here are two ways to exit Idle mode:

1. Generate an enabled interrupt.

Hardware clears IDL bit in PCON register which restores the clock to the CPU. Exe-

cution resu mes with the interrupt service routine. U pon completion of the interrupt

service rou tine, p rogram execution res um es with t he i nstruction imm edia tely follow-

ing the instruction that activated Idle mode. The general purpose flags (GF1 and

GF0 in PCON regist er) may be u sed to ind icate whether an i nterrupt occurred dur-

ing norm al o peration or during Idle m ode . W hen I dle mode is exited by an interrupt,

the interrupt service routine may exam ine GF 1 and GF0.

2. Generate a reset.

A l ogic hi gh on the R ST pi n clears I DL bit i n PCO N regist er direc tly and asynch ro-

nously. This restores the clock to the CPU. Program execution momentarily

resumes with the instruction imme diately following the instruction th at ac tivated the

Idle mode and may continue for a number of clo ck cycles before the internal reset

algo rithm take s contro l. Rese t initializes t he T8 9C51CC 02 a nd vecto rs the CPU to

addres s C:0000h.

Notes: 1. During the time that execution resumes, the internal RAM cannot be accessed; how-

ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at

the Port pins, the instruction immediately following the instruction that activated Idle

mode should not write to a Port pin or to the external RAM.

2. If Id le mode i s invoked by ADC Idle, the ADC conversi on com pletion will e xi t Id le .

Power-d own Mode The Power-down mode places the T89C51CC02 in a very low power state. Power-down

mo de stops the oscillator, fre ezes all cloc k at known states. The CPU status prior t o

entering Power-down mode is preserved, i.e., the program counter, program status

word register retain their data for the duration of Power-down mode. In addition, the

SF Rs and RA M contents are preserv ed. T he s tatus of th e Port pins during Powe r-d own

mode is detailed in Table 13.

Entering Power-d own Mode To enter Power-down mode, set PD bit i n PC ON register. The T89 C51CC02 enters the

Power-down mode upon execution of the instruction that sets PD bit . The instruction

that sets PD bit is the last instruction executed.

T89C51CC02

4126F–CAN–12/03

Exiting Pow er-down Mode Note: If VDD was reduced during the Power-down mode, do not exit Power-down mode until

VDD is restor ed to the normal operating level.

There are two ways to exit the P owe r-down mode :

1. Generate an enabled external interrupt.

– The T89C51CC02 provides capability to exit fr om Power-down using INT0#,

INT1#.

Hardware clears PD bit in PCON register which starts the oscillator and

restores the clocks to the CPU and peripherals. Using INTx# i nput,

execution resumes when th e input is released (See Figure 8). Execution

resumes with the interrupt service routine. Upon completion of the interrupt

service routine, program execution resumes with t he i nstruction i mmediately

following the instruc tion that activate d Power-dow n mode.

Notes: 1. The external interrupt used to exit Power-down mode must be configured as level

sensitive (INT0# and INT1#) and must be assigned the highest priority. In addition,

the duration of the interrupt must be long enough to allow the oscillator to stabilize.

The execution will only resume when the interrupt is deasserted.

2. Exit from pow er-down by ext ernal interrupt does not affect t he SFRs nor the internal

RAM content.

Figu re 8. Power-d own Exit Waveform Using INT1:0#

2. Generate a reset.

– A logic high on the RST pin clears PD bit in PCON register directly and

asynchronously. This starts the oscillator and restores the clock to the CPU

and peripherals. Program execution m ome ntarily resumes with the

instruction immediately following the instruction that activated Power-down

mode and may continue for a number of cl ock cycles be fore the internal

reset algorithm takes control. Reset initializes the T89C51CC02 and vectors

the CPU to addres s 0000h.

Notes: 1. During the time that execution resumes, the internal RAM cannot be accessed; how-

ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at

the Port pins, the instruction immediately following the instruction that activated the

Power-down mode shoul d not write to a Port pi n or to t he external RAM.

2. Exit from power-down by reset redefines all the SFRs, bu t does not af fect the internal

RAM content.

INT1:0#

OSC

Power-down phase Oscillator restart phase Activ e ph as eActive phase

T89C51CC02

4126F–CAN–12/03

Registers Table 15. PCO N Register

PCON (S:87h)

Power Control Register

Rese t Value = 00X1 0000b

Not bit addressable

76543210

SMOD1 SMOD0 - POF GF1 GF0 PD IDL

Bit

Number Bit

Mnemonic Description

7SMOD1

Serial port Mode bit 1

Set to select double baud rate in mode 1, 2 or 3.

6SMOD0

Serial port Mode bit 0

Clear to select SM0 bit in SCON register.

Set to select FE bit in SCON register.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

4POF

Power-off Flag

Clear to recognize next reset type.

Set by ha rdw are whe n V CC rises f rom 0 to it s nomi na l vo lt ag e. Can al so be s et by

software.

3GF1

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

2GF0

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

1PD

Power-down Mode bit

Cleared by hardware when reset occurs.

Set to en ter power-down mode.

0IDL

Idle Mo de bit

Clear by hardware when interrupt or reset occurs.

Set to enter idle mode.

T89C51CC02

4126F–CAN–12/03

Data Memory The T89C5 1CC02 provides dat a memory access in two different spaces:

The internal space mapp ed in three separate segme nts:

• The lower 128 Bytes RAM segm ent.

• The uppe r 128 Bytes RAM segm ent .

• The expanded 256 B ytes RAM segm ent (XRAM).

A fourth internal segme nt is available but dedicated to Special Function Registers,

SF Rs, (addresses 80h to F Fh) accessible by direct addressing mode.

Figure 9 shows the internal data memory space s organization.

Fi gure 9 . Internal memory - RAM

Internal Space

Lower 128 Bytes RAM The lowe r 128 B yte s of RAM (See F igu re 10 ) are acc essi ble fr om add ress 0 0h to 7Fh

using direct or in dire ct ad dressing mode s. T he lowest 32 Bytes are grouped into 4

bank s of 8 reg isters (R0 to R7). Two bits RS 0 and RS 1 in PS W registe r (S ee T able 17)

select which bank is in use according to Table 16. This allows more efficient use of code

space, since register instructions are shorter than instructions that use direct address-

ing, and can be used for context switching in interrupt servi ce routines.

Table 16. Register Bank Selection

The next 16 By tes above the register banks form a block of bit-addressable memory

space. The C51 instruction set includes a wide selection of singlebit instructions, and

the 128 bits in this area can be directly addressed by these instructions. The bit

addres ses in this area are 00h to 7Fh.

256 B yt es

Upper

128 B y tes

Internal RAM

Lower

128 B y tes

Internal RAM

Special

Function

Registers

80h 80h

00h

FFh FFh

00h

FFh

Direct Addressing

Addressing

7Fh

Inte rnal XRAM

Direct or Indirect

Indirect Addressing

RS1 RS0 Description

0 0 Register bank 0 from 00h to 07h

0 1 Register bank 0 from 08h to 0Fh

1 0 Register bank 0 from 10h to 17h

1 1 Register bank 0 from 18h to 1Fh

T89C51CC02

4126F–CAN–12/03

Fi gure 1 0. Lower 128 Bytes Internal RAM Organization

Upper 128 Bytes RAM The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect

addres sing mod e.

Exp anded RAM The on-chip 256 Bytes of expanded RAM (XRAM) are accessible f rom address 0000h to

00F Fh u sing indirect add ressing mode through MOVX instructions. In this add ress

range.

Note: Lower 128 Bytes RAM, Upper 128 Bytes RAM, and expanded RAM are made of volatile

memory cells. This means that the RAM content is indeterminate after power-up and

must then be initialized properly.

bit-Addressable Space

4 Banks of

8 Reg is ters

R0-R7

30h

7Fh

(bit Addresses 0-7Fh)

20h

2Fh

18h 1Fh

10h 17h

08h 0Fh

00h 07h

T89C51CC02

4126F–CAN–12/03

Dual Data Pointer

Description The T89C51CC02 im plements a second data pointer for speeding up code execution

and reduc ing code size in case of intensive usage of external memo ry accesse s.

DPTR0 and DPTR1 are Seen by the CPU as DPTR and are ac cessed using the SFR

add resse s 83h and 84 h tha t are th e DPH and DP L add resse s. Th e DPS b it in A UXR 1

pointer 1 (See Figure 11).

Fi gure 11. Dual Data Pointer Implementation

Application Software can take advantage of the addition al data pointers to both increase speed and

reduc e code size, for e xam ple, blo ck operat ions (cop y, com pare… ) are w ell served by

using one data pointer as a “source” pointer and the other one as a “destination” pointer.

Hereafter is an example of block move implementation using the two pointers and coded

in assembler. The latest C compiler takes also adv antage of this feature by providing

enhanc ed algo rithm libraries.

The INC instruction is a short (2 Bytes) and fa st (6 m achine cycle) way to m anipulate the

DPS bit in the AUXR1 register. However, note that the INC instruction does not directly

force the DP S bit to a particul ar state, but simpl y toggles it. In sim ple routines, s uch as

the block move exam ple, only the fact th at DPS is tog gled in the p roper sequence mat-

ters, not its actual value. In other words, the block move routine works the same whether

DPS is 0 or 1 on entry.

; ASCII block move using dual data pointers

; Modifies DPTR0, DPTR1, A and PSW

; Ends when encountering NULL character

; Note: DPS exits opposite to the entry state unless an extra INC AUXR1 is

added

AUXR1EQU0A2h

move:movDPTR,#SOURCE ; address of SOURCE

incAUXR1 ; switch data pointers

movDPTR,#DEST ; address of DEST

mv_loop:incAUXR1; switch data pointers

movxA,@DPTR; get a byte from SOURCE

incDPTR; increment SOURCE address

incAUXR1; switch data pointers

movx@DPTR,A; write the byte to DEST

incDPTR; increment DEST address

jnzmv_loop; check for NULL terminator

end_move:

DPH0

DPH1

DPL0

DPS AUXR1.0

DPH

DPL

DPL1

DPTR

DPTR0

DPTR1

T89C51CC02

4126F–CAN–12/03

Registers Table 17. PSW Regi s ter

PSW (S:D0h)

Program Status Word Register

Rese t Value = 0000 0000b

76543210

CY AC F0 RS1 RS0 OV F1 P

Bit

Number Bit

Mnemonic Description

7CY

Carry Flag

Carry out from bit 1 of ALU operands.

6AC

Auxiliary Carry Flag

Car ry out from bit 1 of addition operands.

5F0User Definable Flag 0

4 - 3 RS1: 0 Re gis ter Bank Sele ct bits

Re fer to Ta bl e 16 for bits desc ri pti on .

2OV

Overflow Flag

Overflow set by arithmet ic operations.

1F1User Definable Flag 1

Parity bit

Set when ACC contains an odd number of 1’s.

Cleared when ACC contains an even number of 1’s.

T89C51CC02

4126F–CAN–12/03

Table 18. AUXR1 Regi ster

AUXR 1 (S:A2h)

Auxiliary Control Register 1

Reset Value = XXXX 00X0b

Note: 1. ENBOOT is initialized with the invert BLJB at reset. See In-System Programming

section.

76543210

- - ENBOOT - GF3 0 - DPS

Bit

Number Bit

Mnemonic Description

7 - 6 - Reserved

The value read fr om these bits is indeterminate. Do not set th ese bi ts.

5ENBOOT

(1) Enable Boot Flash

Set thi s bit to map the boot Flash betw een F800h - FFFFh

Clear this bit to disable boot Flash.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

3GF3General Purpose Flag 3

Always Zero

This bit is stuck to logi c 0 to allow IN C AU XR1 in st ruc tio n wit ho ut affecti ng GF3

flag.

1-Reserved for Data Pointer Extension

0DPS

Data Pointer Select bit

Set to se lect second dual data pointer: DPTR1 .

Clear to select first dual data pointer: DPTR0.

T89C51CC02

4126F–CAN–12/03

EEPROM Data

Memory T he 2K bytes on-chip EEPROM memory block is located at add re sses 0000h t o 07FF h

of the XRAM/XRAM memory space and is selected by setting control bits in the EECON

A physical write in the EEPROM memory is done in two steps: write data in the column

latches and transfer of all data latches into an EEP ROM memo ry row (programming).

The number of data written on the page may vary from 1 up to 128 Bytes (the page

size). W hen programm in g, only the data writ ten i n t he col um n latc h i s program m ed and

a ninth bit is used to obtain this feature. This provides the capability to program the

whole memory by Bytes, by page or by a number of Bytes in a page. Indeed, each ninth

bit is set when the writing the c orresponding byte in a row and all these ninth bits are

reset after the writ ing of the complete EEPROM row.

W rite Dat a in the Column

Latches Data is written by byte to the column latches as for an external RAM memory. Out of the

11 addres s bits of the data pointer, the 4 MSB s are us ed for pa ge select ion (row) and 7

are used for byte selection. Between two EEPROM programming sessions , all the

addres ses in the c olumn latches must stay on t he same page, meaning that the 4 MSB

must no be changed.

The following proced ure is used to writ e to the column latches:

• Save and disable interrupt

• Set bit EEE o f EEC ON re g ister

• Load DPTR with the address to write

• Store A register with the data to be written

• Execute a MOVX @DPTR, A

• If needed loop the three last instructions until the end of a 128 Bytes page

• Res tore interrupt

Note: The last page address used when loading the column latch is the one used to select the

page programming address.

Programming T he EEP ROM program mi ng cons ists of the following actions:

• Write one or more Bytes of one page in the column latches. Normally , all Bytes must

belong to the same page; if not, the last page address will be latched and the others

discarded.

• Launch programming by writing the control sequence (50h followed by A0h) to the

EECON register.

• EEBU SY flag in EECON is t hen set by hardware to indicate that programming is in

progress and that the EEPROM segment is not available for reading.

• The end of programm ing is indicated by a hardware clear of the EEBUSY flag.

Note: The sequence 5xh and Axh must be executed without instructions between then other-

wise the programming is abor ted.

Read Data The following procedure is used to read the data stored in the EEPROM memory:

• Save and disable interrupt

• Set bit EEE o f EEC ON re g ister

• Load DPTR with the address to read

• Execute a MOVX A, @DPTR

• Res tore interrupt

T89C51CC02

4126F–CAN–12/03

Examples ;*F*************************************************************************

;* NAME: api_rd_eeprom_byte

;* DPTR contain address to read.

;* Acc contain the reading value

;* NOTE: before execute this function, be sure the EEPROM is not BUSY

;***************************************************************************

api_rd_eeprom_byte:

; Save and clear EA

MOV EECON, #02h; map EEPROM in XRAM space

MOVX A, @DPTR

MOV EECON, #00h; unmap EEPROM

; Restore EA

ret

;*F*************************************************************************

;* NAME: api_ld_eeprom_cl

;* DPTR contain address to load

;* Acc contain value to load

;* NOTE: in this example we load only 1 byte, but it is possible upto

;* 128 Bytes.

;* before execute this function, be sure the EEPROM is not BUSY

;***************************************************************************

api_ld_eeprom_cl:

; Save and clear EA

MOV EECON, #02h ; map EEPROM in XRAM space

MOVX @DPTR, A

MOVEECON, #00h; unmap EEPROM

; Restore EA

ret

;*F*************************************************************************

;* NAME: api_wr_eeprom

;* NOTE: before execute this function, be sure the EEPROM is not BUSY

;***************************************************************************

api_wr_eeprom:

; Save and clear EA

MOV EECON, #050h

MOV EECON, #0A0h

; Restore EA

ret

T89C51CC02

4126F–CAN–12/03

Registers Table 19. EECON Regist er

EECON (S:0D2h)

EEPROM Control Register

Reset Value = XXXX XX00b

Not bit addressable

76543210

EEPL3 EEPL2 EEPL1 EEPL0 - - EEE EEBUSY

Bit Number Bit

Mnemonic Description

7 - 4 EEPL3-0 Programm ing Lau nch Comma nd bits

Write 5Xh followed by AXh to EEPL to launch the programming.

Reserved

The value read from this bit is indeterminate. Do not set this bit .

Reserved

The value read from this bit is indeterminate. Do not set this bit .

1 EEE

Enable EEPROM Space bit

Set to map the EEPROM space during MOVX instructions (Write in the column

latches)

Clear to map the XRAM space during MOV X.

0 EEBUSY

Progr a mming Busy Flag

Set by hardware when programming is in progress.

Cleared by hardware when programming is done.

Can not be set or cleared by software.

T89C51CC02

4126F–CAN–12/03

Program/Code

Memory The T89C51CC02 implement 16K Bytes of on-chip program/code memory.

The F lash m em ory increases E PR OM and ROM f uncti onality by in -circui t electrical era-

sure and programming. Thanks to the internal charge pump, the high voltage needed for

programming or erasing Flash cells is generated on-chip using the standard VDD vo lt -

age. Thus, the Flash memory can be programmed using only one voltage and allows In-

Syst em Program min g (ISP ). Hardw are program ming mod e is also av ailable usin g spe-

cific programmi ng tool.

Fi gure 1 2. Program /C ode Memory Organizat ion

Flash Memo ry

Architecture T 89C51CC02 features two on-chip Flash memories:

• Flash memory FM0:

containing 16K Bytes of program memory (user space) organized into 128 bytes

pages,

• Flash memory FM1:

2K By tes for boot loader and Application Programm ing Interfaces (API).

The FM0 can be program by both parallel programming and Serial ISP whereas FM1

supports only parallel pr ogramming by programmers. The IS P mode is detailed in the

’In-System Programming ’ section.

All Read/Write access operations on Flash memory by user application are managed by

a set of API described in the ’In-System Programming’ section.

Figu re 13. Flash Memory Arc hi tecture

0000h

16K Bytes

3FFFh

Internal

Flash

3FFFh

16K Bytes

Flash Mem ory

FM0

0000h

Hardware Security (1 byte)

Column Latches (128 Bytes)

User Space

Extra Row (128 Bytes)

2K Bytes

Flash Memory

FM1

Boot Space

FFFFh

F800h

FM1 mapped between F800h and

FFFFh when bit ENBOOT is set in

AUXR1 register

T89C51CC02

4126F–CAN–12/03

FM0 Me mory Arch itec ture The Flas h m em ory is made up of 4 blocks (S ee Figure 13):

1. The memory array (user space) 16K Bytes

2. T he Extra Row

3. T h e Hardware security bits

4. T he column latch registers

User Space Thi s spa ce is c ompo sed of a 16K Bytes F lash m em ory o rganize d in 12 8 p ages of 128

Bytes. It contains the user’s application code.

Extra Row (XRow) This row i s a part of FM0 and has a s ize of 1 28 By tes. Th e extra row ma y contain infor-

mation fo r boot loader usage.

Hardware Security Byt e The Hardware sec urity Byte space is a part of FM 0 and has a size of 1 b yte.

The 4 MSB can be read/written by software, the 4 LSB can only be read by software and

written by hardware in parallel mode.

Column Latches The column latches, also part of FM0, have a size of full page (128 Bytes).

The column latches are the entrance buffers of the t hree previous memory locations

(user array, XROW and Hardware security byte).

Cross Flash Me mory Access

Description The F M0 memory can be programm ed as describe on Table 20. Programming FM 0

from FM0 is impossible.

The FM 1 memory can be program only by parallel programming.

Table 20 s how all software Flash acces s allowed.

Table 20. Cross Flash Memory Access

Code executing from

Action FM0

(user Flash) FM1

(boot Flash)

FM0

(user Flash)

Read ok -

Load column latch ok -

Write - -

FM1

(boo t Fl as h)

Read ok ok

Load column latch ok -

Write ok -

T89C51CC02

4126F–CAN–12/03

Overview of FM0

Operations The CPU interfaces the Flash memory through the FCON register and AUXR1 register.

These re gisters are used to:

• Map the memory spaces in the adressable space

• Launch the programming of the memory spaces

• Get the status of the Flash mem ory (busy/not busy)

Ma ppin g of the Mem ory Space By def ault, the u se r space is ac cesse d by MOVC instructio n fo r read only . The colum n

latches s pa ce is ma de accessible by s etting the FPS bit in FC ON register. W riting is

possible from 0000h to 3FFFh, address bits 6 to 0 are used to select an address within a

page while bits 14 to 7 are us ed to select the programm ing address of the page.

Setting FP S bit takes precedence on the EEE bit in EECON register.

The o ther mem ory space s (u ser, ext ra row, hard ware security ) are made ac cessible in

the code segm ent by programm ing bits FMOD0 and FMO D1 in FCO N register in accor-

danc e with Table 21. A MOVC instruc tion is then used for reading these spaces.

Table 21. FM0 blocks Select bit s

Lau nchin g P rogram m i ng FPL3:0 bi ts i n F CON register are us ed to sec ure the laun ch of programming. A spec ific

se quence m ust be written i n these b its to unl ock the wri te pro te ction a nd to la unch th e

programming. This sequence is 5xh followed by Axh. Table 22 summarizes the memory

spaces to program according to FMOD 1:0 bits.

Table 22. Programming Spaces

Note: The sequence 5xh and Axh must be executi ng without instructions between them other-

wise the programming is abor ted.

Interrupts that may occur during programming time must be disabled to avoid any spuri-

ous exit of the programming mode.

FMO D1 FMO D0 FM0 Adressable Space

0 0 User (0000h-3FFFh)

0 1 Extra Row(FF80h-FFFFh)

1 0 Hardware Security Byte (0000h)

11Reserved

Write to FCON

OperationFPL3:0 FPS FMOD1 FMOD0

User

5 x 0 0 No action

Ax00

Write the column latches in user

space

Extra Row

5 x 0 1 No action

Ax01

Write the column latches in extra row

space

Hardware

Security

Byte

5 x 1 0 No action

A x 1 0 Write the fuse bits space

Reserved 5 x 1 1 No action

A x 1 1 No action

T89C51CC02

4126F–CAN–12/03

Status of the Flash Memory The bit FBUSY in FCON register is used to indicate the status of programming.

FBUSY is set when programming is in progress.

Selecting FM1 The bit E NB OO T in AUXR1 register is used to map FM1 from F800 h to FFFFh.

Loading the Column Latches Any number o f da ta from 1 byte to 1 28 By tes can be load ed in the column latches . This

provides the capability to program the whole memory by byte, by page or by any number

of Bytes in a page.

W hen progra mming i s launched , an aut oma ti c erase o f the locatio ns loade d in the c ol-

um n latc hes is f irst per form ed, th en program ming is e ff ect ively d one. Thus n o page or

bloc k erase is ne eded an d on ly the loa ded da ta are p rogram med i n the correspon ding

page.

The following procedure is used to load the column latches and is summarized in

Figure 14:

• Sa ve then d isabl e interrupt and map the column latch space by setting FPS bit.

• Load the DPTR with the address to load.

• Load A ccumula tor register with th e data to load.

• Execu te th e MOVX @DPT R, A instructi o n.

• If needed loop the three last i ns tructions until the page is com pletely loaded.

• unm ap the column latch and Restore Interrupt

T89C51CC02

4126F–CAN–12/03

Fi gure 1 4. Column Latches Loading Procedure(1)

Note: 1. The last page address used when loading the column l atch is the one used to select

the page programming address.

Programming the Flash Sp aces

User Th e following procedure is used to progra m the User space a nd is summarized in

Figure 15:

• Load up to one page of data in t he colum n latches from address 0000h to 3FFFh .

• Save then disable the interrupts.

• Launc h the programm ing by writing the data sequence 50h followed by A0h in

FCON register.This step mus t be executed from FM1.

The end of the programming indicated by the FBUSY flag cleared.

• Res tore t he interrupts.

Extra Row The f ollowing proc edure is us ed to program the E xt ra Row spac e and is s um m arized i n

Figure 15:

• Load data in the column latches from address FF80h to FFFFh.

• Sa ve then disable t he interrupts.

• Launc h the programm ing by writing the data sequence 52h followed by A2h in

FCON register. This step of the procedure must be executed from FM1.

The end of the programming indicated by the FBUSY flag cleared.

• Res tore t he interrupts.

Co lum n Lat che s

Data Load

DPTR = Address

ACC = Data

Exec: MOVX @DPTR, A

Last Byte

to load?

Column Latches Mapping

FCON = 08h (FPS = 1)

Data Memory Mapping

FCON = 00h (FPS = 0)

Save & Disable IT

EA = 0

Restore IT

T89C51CC02

4126F–CAN–12/03

Fi gure 1 5. Flash and Extra row Programming Procedure

Hardware Security Byt e T he following procedure is used to program the Hardware Security Byte space

and is sum m ariz ed in Fi gure 16:

• Se t FPS and map Hardware byte (FCON = 0x0C)

• Save then disable the interrupts.

• Load DPTR at address 0000h.

• Load A ccumula tor register with th e data to load.

• Execu te th e MOVX @DPT R, A instructi o n.

• Launc h the programm ing by writing the data sequence 54h followed by A4h in

FCON register. This step of the procedure must be executed from FM1.

The end of the programming indicated by the FBusy flag cleare d.

• Res tore the interrupts

Flash Spaces

Programming

Save & Disable IT

EA = 0

Launch Programming

FCON = 5xh

FCON = Axh

End Programming

Restore IT

Column La tches Loading

See Figure 14

FBusy

Cleared?

Clear Mode

FCON = 00h

T89C51CC02

4126F–CAN–12/03

Fi gure 1 6. Hardware Programming Procedure

Reading the Flash Spa ces

User The following procedure is used to read the User space:

• Read one by te in Accumulator by executing MO VC A,@A+ DPTR with A + DPTR is

the address of the code byte to read.

Note: FCON must be cleared (00h) when not used.

Extra Row The following procedure is used to read the Extra Row space and is summarized in

Figure 17:

• Map the Extra Row space by writing 02h in FCON register.

• Read one by te in Accumulato r by executing MOVC A,@ A+D PTR with A = 0 &

DPTR= FF80h to FFFFh.

• Clear FCO N to unmap the Extra Row.

Hardware Security Byt e T he f ollow ing proc edure is us ed t o read t he Hardw are Security B yte and is sum-

ma riz ed in F igure 17:

• Map the Hardware Security space by writing 04h in FCON register.

• Read the byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 &

DPTR= 0000h.

• Clear FCO N to unmap the Hardware Security Byte.

Flash Spaces

Programming

Save & Disable IT

EA = 0

Launch Programming

FCON = 54h

FCO N = A4h

End Programming

RestoreIT

FBusy

Cleared?

Clear Mode

FCON = 00h

Data Load

DPTR = 00h

ACC = Data

Exec : MOVX @DP TR, A

FCON = 0Ch

Save & Disable IT

EA = 0

End Loading

Restore IT

T89C51CC02

4126F–CAN–12/03

Fi gure 1 7. Reading Pr ocedure

Note: aa = 10 for the Hardware Security Byte.

Flash Protection from Parallel

Programming Th e thre e loc k bit s in Hardw are S ecu rity By te (Se e ’In-S ystem Progra mmi ng’ sect ion)

are programmed according to Table 23 provide different level of protection for the on-

chip code and data located in FM0 and FM1.

The only way to write this bits are the parallel mode. They are set by default t o level 3.

Table 23. Progra m Lock bit

Note: 1. Program Lock bits

U: unprogrammed

P: programmed

WARNING: Security level 2 and 3 should only be programmed after F lash and Core

verification.

Preventing Flash Corruption See Sec tion “Power M anagem ent”.

Flash S paces R eading

Flash Spaces Mapping

FCON = 00000aa0b

Data Read

DPTR = Address

ACC= 0

Exec: MOVC A, @A+DPTR

Clear Mode

FCON = 00h

Progr am Lock bits

Protection Description

Security

Level LB0 LB1 LB2

1UUU

No program lock features enabled. MOVC instruction executed from

external program memory returns code data.

2 P U U Par allel programming of the Flas h is disabled.

3UPU

Same as 2, also verify thr ough parallel programmi ng interface is

disabled. This is the factory defaul programming.

T89C51CC02

4126F–CAN–12/03

Registers Table 24. FCON Register

FCON Register FCON (S :D1h)

Flash Control Register

Rese t Value = 0000 0000b

76543210

FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY

Bit

Number Bit

Mnemonic Description

7 - 4 FPL3 :0 Pro gram m ing Launc h Com ma nd bits

Write 5Xh fol lowed by AXh to laun ch the pr ogramming accordi ng to FMOD1:0.

(See Table 22.)

3FPS

Flash Map Program Space

Set to map the column latch space in the data memory space.

Clear to r e-map the data memory space.

2 - 1 FM OD 1: 0 Flash Mode

Se e Ta bl e 21 or Ta bl e 22 .

0 FBUSY

Flash Busy

Set by hardware when programming is in progress.

Clear b y hardw are when programming is done.

Can not b e changed by s oftware.

T89C51CC02

4126F–CAN–12/03

Operation Cross

Memory Access Space addressable in read and write are:

•RAM

• ERAM (Expanded RAM access by movx)

• EEPROM DATA

• FM 0 ( user flash )

• Hardware by te

•XROW

•Boot Flash

• Flash C o lumn lat c h

The tab le below provides t he diffe rent kind of memory which can be accessed f rom dif-

ferent code location.

Table 25. Cross Memory Access

Action RAM ERAM Boot FLAS H F M0 E² Data Hardware

Byte XROW

boot FLASH Read OK OK OK OK -

Write - OK (RWW) OK (RWW) OK (RWW) OK (RWW)

FM0 Read OK

(confidential) OK OK -OK -

Write - OK (idle) OK(RWW) - -OK

T89C51CC02

4126F–CAN–12/03

Sharing Instructions Table 26. Instructions shared

Note: by cl : using Colum n Latch

Table 27. Read MOV X A, @DPTR

Table 28. Wri te MOVX @DPTR,A

Action RAM ERAM EEPROM

DATA Boot

FLASH FM0 Hardware

Byte XROW

Read MOV MOVX MOVX MOVC MOVC MOVC MOVC

Wr ite MOV MOVX MOVX - by cl by cl b y cl

EEE bit in

EECON

FCON Registe r ENBOOT ERAM EEPROM

DATA

Flash

Column

Latch

00Xwinner

01Xwinner

10X winner

11Xwinner

EEE bit in

EECON

FCON Register ENB OOT ERAM EEPROM

Data

Flash

Column

Latch

00Xwinner

01X winner

1 0 X winner

11X winner

T89C51CC02

4126F–CAN–12/03

Table 29. Read MOVC A, @DPTR

Code Execution

FCO N Register

ENBOOT DPTR FM1 FM0 XROW Hardware

ByteFMOD1 FMOD0 FPS

From FM0

00X

0 0000h to 3FFFh winner

10000h to 3FFFh winner

F800h to FFFFh Do not use this configuration

01X X

0000 to 007Fh

See (1 ) winner

10X X X winner

11X

0 000h to 3FFFh winner

10000h to 3FFFh winner

F800h to FFFFh Do not use this configuration

From FM1

(ENBOOT =1

010000h t o 3F FF win ne r

F800h to FFFFh winner

0X NA

11 X winner

0X NA

01X 10000h to 007h

See (2 )

winner

0NA

10X 1Xwinner

0NA

11X 1000h to 3FFFh winner

0NA

1. For DPTR higher than 007Fh only lowe st 7 bi ts are decoded, t hus the behavior is the same a s for ad dresses f rom

0000h to 007Fh

2. For DPTR higher than 007Fh only lowe st 7 bi ts are decoded, t hus the behavior is the same a s for ad dresses f rom

0000h to 007Fh

T89C51CC02

4126F–CAN–12/03

In-System

Programming (ISP) With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flash

technolog y the T89C51C C02 allows the syste m engineer the developmen t of applica-

tions with a very h igh level of f lexibility. This fl exibility is ba sed on the possibility to alter

the customer program at any stages of a product’s life:

• Be fore mounting the chip on the PCB, FM0 flash can be programmed with the

application code. FM1 is always preprogramm ed by Atme l with a bootloader (chip

can be ordered with CAN bootloader or UART bootloader).(1)

• Once the chip is mounted on the PCB, it can be programmed by serial mode via the

CAN bus or UART.

Note: 1. The use r can al so program his own boot loader in FM1.

This ISP allows code modification over the total lifetime of the product.

Besides the default Bootloaders Atmel provide customers all the needed Application-

Program m ing-Interfaces (A PI) which a re needed for the IS P. The A PI are lo cated in the

Boot memory.

This allow the customer to have a full us e of the 16-Kb yte user memory .

Flash Programming and

Erasure There are three methods for programming the Flash memory:

• The Atmel bootloader located in FM1 is activated by the application. Low level API

routines (located in FM1)will be used to program FM0. The interface used for serial

downloading to FM0 is the UART or the CAN. API can be called also by user ’s

bootloade r located in FM0 at [SBV]00h.

• A further method exist in activating the Atmel boot loader by hardwa re activation.

See the Sect ion “Hardware Secur ity Byte”.

• The FM0 c an be programmed also by the parallel m ode us ing a programmer.

Fi gure 1 8. Flash Memory Map ping

F800h

3FFFh

16K Bytes

Flash Memory

2K Bytes IAP

Bootloader

FM0

FM1

Custom

Bootloader

[SBV]00h

FFFFh

FM1 Mapped between F800h and FFFF

when API Called

0000h

T89C51CC02

4126F–CAN–12/03

Bo ot Pr oce s s

Software Boot Process

Example M any algorit hms can be u sed for the software boo t proce ss. Belo w are des criptio ns of

the different flags and Bytes.

Boot Loader Jump bit (BLJB):

- This bit indicates if on RESE T the user wants to jump to this applic ation at address

@ 0000h on FM0 or execute the boot loader at address @F800h on FM1.

- BLJB = 0 (i.e. bootloader FM1 executed after a reset) is the default Atmel factory pro-

gramming.

-To read or modify this bit, the APIs are used.

Boot Vector Address (SBV):

- This byte contains the MSB of the user boot loader address in FM0.

- The default value of SBV is FFh (no user boot lo ader in FM0).

- To read or m odi fy this byte, the APIs are used.

Extr a Byt e (EB ) & Boot Sta tu s Byte (BSB):

- These Bytes are reserved for c ust om er use.

- To read or m odi fy these Bytes, the APIs are used.

Figu re 19. Hardware Boot Process Algorithm

Application-

Programming-Interface S everal Appli cation Program Interface (API) calls are available for use by an application

program to permit selective erasing and programming of Flash pages. All calls are made

by functio ns.

All these APIs are described in detail in the following documents on the Atmel web site.

– Datasheet Bootloader CAN T89C51CC02.

– Datasheet Bootloader UART T89C51CC02.

RESET

BLJB == 0

Hardware

Software

Bootloader

in FM1

Application

in FM0

b it ENBOOT in AUXR1 Register

Is Initialize d wit h BLJB Inver t e d.

ENBOOT = 0

PC = 0000h

ENBOOT = 1

PC = F800 h

Example, if BLJB=0, ENBOOT

is set (=1) dur ing reset, thus the

bootload er is executed after the

reset.

T89C51CC02

4126F–CAN–12/03

XROW Bytes The E XTRA ROW (XRO W) in cludes 128 byt es. Some of thes e byt es are used f or spe-

cific purpose in conjonction with the bootloader.

Table 30. XROW Ma pping

Hardwa re Conditio ns It is possible to force the controller to execute the bootloader after a Reset with hard-

ware conditions.

D urin g the f irst pr og rammi ng, the us er c an defin e a con fig urat ion on Por t1 tha t wi ll be

r ecog n ize d by th e chi p as t he hard w are co ndi ti ons du rin g a R eset . I f th is co ndi ti on i s

met, the chip will start exec uting the bootloader at the end of the Reset.

See a detailed description in the applicable Docume nt.

– Datasheet Bootloader CAN T89C51CC02.

– Datasheet Bootloader UART T89C51CC02.

Description Default Value Address

Copy of the Manufacturer Code 58h 30h

Copy of the Device ID#1: Family code D7h 31h

Copy of the Device ID#2: Memories size and type BBh 60h

Copy of the Device ID#3: Name and Revision FFh 61h

T89C51CC02

4126F–CAN–12/03

Hardware Security Byte Table 31. Hardware Security byte

Default value after erasing chip: FFh

Notes: 1. Only the 4 MSB bits can be accessed by software.

2. The 4 LSB bits can only be accessed by parallel mode.

76543210

X2B BLJB - - - LB2 LB1 LB0

Bit

Number Bit

Mnemonic Description

7X2B

X2 bit

Set this bit to start in standard mode

Clear this bit to start in X2 Mode.

6BLJB

Boot Loader Jump bit

- 1: To start the user’s application on next RESET (@0000h) located in FM 0,

- 0: To start the boot loader(@F800h) lo cated in FM1.

5 - 3 - Reserved

The va lue read from these bits are indeterm inate.

2 - 0 L B 2 :0 Lock bits (see Ta bl e 22 )

T89C51CC02

4126F–CAN–12/03

Serial I/O Port The T89C5 1CC02 I/O serial port is compatible with the I /O serial port in the 80C52.

It provides both synchronous and asynchronous communication modes. It operates as a

Universal Asynchronous Receiver and Transmitter (UA RT) in three full-duplex modes

(Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously

and at different baud rates

Serial I/O port includes the following enhancements:

• Framing error detection

• Automatic address recognition

Figu re 20. Serial I/ O Port Block Diagram

Framing Error Detection Framing bit error detection is provided for the three asynchronous modes. To enable the

framing bit error detection feature, set SMOD0 bit in PCON register.

Fi gure 2 1. Framing Error Block Diagram

W hen this feature is enabl ed, the receiver chec ks each incom ing data frame for a valid

stop bit. An invalid stop bit may result f rom noise on the serial l ines or f rom simultaneous

tran smissio n by two C PUs . If a valid st op bit is n ot found, t he Fram ing Error bit (FE) i n

SCON register bit is set.

The software may examine the FE bit after each recep tion to check for data errors.

Onc e set , only software o r a reset clears t he F E bit. Subsequent ly received f ram es with

va lid s top bits cannot clear the FE bi t. When t he FE feat ure is enabl ed, RI rises o n the

stop bit instead of the last data bit (See Fi gure 22 and F igure 23).

W rite SBUF

RI TI

SBUF

Transmitter

SBUF

Receiver

IB Bus

Mode 0 Tran smit

Receive

Shift register

Load SBUF

Read SBUF

SCON reg

Interrupt Request

Serial Port

TXD

RXD

RITIRB8TB8RENSM2SM1

SM0/FE

IDLPDGF0GF1POF-SMOD0

SMOD1

To UART Framing Error Control

SM0 to UART Mode Control

Set FE bit if Stop bit is 0 (Framing Error)

T89C51CC02

4126F–CAN–12/03

Fi gure 2 2. UART Timing in Mode 1

Fi gure 2 3. UART Timing in Modes 2 and 3

Automatic Address

Recognition The automat ic address recognition feat ure is e nabled when t he multiproce ssor com m u-

nication feature is enabled (SM2 bit in SC O N register is set).

Implemented in the hardware, automatic address recognition enhances the multiproces-

sor communication feature by allowing the serial port to examine the address of each

incomi ng command fram e. Only when the serial port recognizes its own a ddress will the

receiver set the RI bit i n the SCON register to g enerate an interru pt. Th is ensure s that

the CPU is not interrupted by command frames addres sed to other devices.

If necessary, t he user can enable the autom atic ad dress recogn iti on feature in mode 1.

In this conf igur ation, the s top b it ta kes th e p lace o f the nint h da ta b it. bit RI is s et onl y

when the received comm and frame addres s m atches th e device’s address and is termi-

nated by a valid stop bit.

To support aut om atic addres s rec ognition, a device is identified b y a given ad dres s and

a broadca st address.

Note: The multiprocessor communication and automatic address recognition features cannot

be enabled in mode 0 (i.e. setting SM2 bit in SCO N register in mode 0 has no effect).

Given Address Each device has an individual address that is specified in the SADDR register; the

SAD EN reg ister i s a mask b yte t hat con tains don ’t-ca re bits (defined by zero s) to form

the device’ s give n address . The d on’t -care bits provide the fle xibility to a ddre ss one or

more slaves at a time. The following example illustrates how a given address is formed.

To address a device by its individual address, the SADEN mask byte must be 1111

1111b.

For example:

SADDR0101 0110b

SADEN1111 1100b

Given0101 01XXb

Dat a Byte

SMOD0 = x

Stop

bit

Start

bit

RXD D7D6D5D4D3D2D1D0

SMOD0 = 1

SMOD0 = 0

Data Byte Ninth

bit Stop

bit

Start

bit

RXD D8D7D6D5D4D3D2D1D0

SMOD0 = 1

T89C51CC02

4126F–CAN–12/03

Here is an example of how to use given addresses to address different slaves:

Slave A:SADDR1111 0001b

SADEN1111 1010b

Given1111 0X0Xb

Slave B:SADDR1111 0011b

SADEN1111 1001b

Given1111 0XX1b

Slave C:SADDR1111 0011b

SADEN1111 1101b

Given1111 00X1b

The SADEN by te is selected so that each slave may be addressed separately.

For slave A , bit 0 (t he LSB) is a don ’t-care bit; for slaves B and C, bit 0 is a 1. To com-

mun icate with slav e A o nly, the m aster must send an add ress where bit 0 is clear (e.g.

1111 0000b).

For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don’t care bit. To communicate with

slaves A and B, but not slave C, the master must send an address with bits 0 and 1 both

set (e.g . 1111 0011b).

To communicate with slaves A, B and C, the master must send an address with bit 0 set,

bit 1 clear, and bit 2 cle ar (e.g. 1111 0001b).

Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers

with zeros defined as don’t-care bits, e.g.:

SADDR 0101 0110b

SADEN 1111 1100b

SADDR OR SADEN1111 111Xb

The use of don’t-care bits provides flexibility in defining the broadcast address, however

in m ost applicat ions, a broa dcast addre ss is FFh. The f ollowing is an e xample of us ing

broadc ast addresses :

Slave A:SADDR1111 0001b

SADEN1111 1010b

Given1111 1X11b,

Slave B:SADDR1111 0011b

SADEN1111 1001b

Given1111 1X11B,

Slave C:SADDR=1111 0010b

SADEN1111 1101b

Given1111 1111b

For slaves A and B, bit 2 i s a don’t care bit; f or slave C, bit 2 is set. To communicate with

all o f the s laves, the m as ter must send an address FF h. To c om mu nicate with slav es A

and B, but not slave C, the master can send and address FBh.

T89C51CC02

4126F–CAN–12/03

Registers Table 32. SCO N Register

SCON (S:98h)

Serial Control Register

Rese t Value = 0000 0000b

bit addressabl e

76543210

FE/SM0 SM1 SM2 REN TB8 RB8 TI RI

Bit

Number Bit

Mnemonic Description

FE Framing Error bit (SMOD0 = 1)

Clear to reset the error state, not cleared by a valid stop bit.

Set by hardware when an invalid stop bit is detected.

SM0 Serial port Mode bit 0 (SMOD0 = 0)

Re fer to SM1 for se ria l po rt mod e sele c tio n.

6SM1

Serial port Mode bit 1

SM0 SM1 Mode Baud Rate

0 0 Shift Register FXTAL/12 (or FXTAL/6 in mode X2)

0 1 8-bit UART V ariable

1 0 9bit UART FXTAL/6 4 or FXTAL/32

1 1 9bit UART Variable

5SM2

Serial port Mode 2 bit/Multiprocessor Communication Enable bit

Clear to disable multiprocessor communication fea ture.

Set to en able multiproce ssor communication fe ature in mode 2 an d 3.

4REN

Reception Enable bit

Clear to disable serial reception.

Set to en able serial reception.

3TB8

Transmitter bit 8/Nint h bit to T ransmit in Mod es 2 and 3

Clear to transmit a logic 0 in the 9th bit.

Set to transmit a logic 1 in the 9th bit.

2RB8

Receiver bit 8/Ninth bit Received in Modes 2 and 3

Cleared by hardware if 9t h bit received is a logic 0.

Set by hardware if 9th bit received is a logic 1.

1TI

Transmit Interrupt Fl ag

Clear to acknowledge interrupt.

Set by ha rdw are at the e nd of the 8 t h bi t ti me in mod e 0 or at the beg i nni n g of t he

stop bit in the other modes.

0RI

Receive Interrupt Flag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0, See Figure 22. and

Figure 23. in the other modes.

T89C51CC02

4126F–CAN–12/03

Table 33. SADEN Register

SADEN (S:B9h)

Slave Address Mask Register

Rese t Value = 0000 0000b

Not bit addressable

Table 34. SADDR Register

SADDR (S:A9h)

Slave Address Register

Rese t Value = 0000 0000b

Not bit addressable

Table 35. SBUF Register

SBUF (S:99h )

Serial Data Buffer

Rese t Value = 0000 0000b

Not bit addressable

76543210

Bit

Number Bit

Mnemonic Description

7 - 0 Mask Data for Slave Indivi dual Address

76543210

Bit

Number Bit

Mnemonic Description

7 - 0 Slave In dividual Address

76543210

Bit

Number Bit

Mnemonic Description

7 - 0 Data sent/received by Serial I/O Port

T89C51CC02

4126F–CAN–12/03

Table 36. PCON Regist er

PCON (S:87h)

Power Control Register

Rese t Value = 00X1 0000b

Not bit addressable

76543210

SMOD1 SMOD0 - POF GF1 GF0 PD IDL

Bit

Number Bit

Mnemonic Description

7SMOD1

Serial port Mode bit 1

Set to select double baud rate in mode 1, 2 or 3.

6SMOD0

Serial port Mode bit 0

Clear to select SM0 bit in SCON register.

Set to select FE bit in SCON register.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

4POF

Power-off Flag

Clear to recognize next reset type.

Set by ha rdw are whe n V CC rises f rom 0 to it s nomi na l vo lt ag e. Can al so be s et by

software.

3GF1

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

2GF0

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

1PD

Power-down Mode bit

Cleared by hardware when reset occurs.

Set to en ter power-down mode.

0IDL

Idle Mo de bit

Clear by hardware when interrupt or reset occurs.

Set to enter idle mode.

T89C51CC02

4126F–CAN–12/03

Timers/Counters The T 89C 51CC02 implem ents two g ene ral-purpo se, 16-b it Timers/ Counters . Such are

ident ified as Timer 0 and Ti mer 1, and can be independe ntly confi gured to operate i n a

variety of modes as a Ti me r or an event Counter. Whe n operating as a Timer, the

Time r/Cou nter ru ns for a prog ramm ed len gth of ti me, then i ssues an interru pt req uest.

When operating as a Counter, the Timer/Counter counts negative transitions on an

external pin. After a preset number of counts, the Counter iss ue s an interrupt request.

The various operating modes of each Timer/Coun ter are described in the following

sections.

Timer/Counter

Operations A basic operation is Timer registers THx and TLx (x = 0, 1) connected in casc ade to

for m a 16-b it Timer. Se tting the run co ntrol bi t (TRx) in T CON reg ister (Se e Figure 37)

turns the Timer on by allowing the selected input to increment TLx. When TLx overflows

it i n crem ent s TH x; w h en T Hx over flo ws it se ts t he T ime r o verf low flag ( TFx ) in TCO N

regi ster. S etting t he TR x does not c lear the THx and TLx T imer registers . Time r reg is-

ters can be ac cess ed to obt ain the current count or to ent er pres et v alu es. They can be

read at any time but TRx bit must be cleared to preset their values, otherwise the behav-

ior of the Timer/Counter is unpredictable.

The C/ Tx# control bit selects T imer operation or Cou nter o peration by selecting t he

divided-down peripheral clock or external pin Tx as the source for the counted signal.

TRx bit must be cleared when cha nging the m ode of ope rati on, otherwi se the beha vior

of the Timer/Coun ter is unpredictable.

For Time r operation (C/Tx# = 0), the Timer register count s t he divided-down pe ripheral

clock. The Time r register is incremented once every peripheral cycle (6 peripheral clock

periods). The Timer clock rate is fPER/6, i.e. fOSC/12 in standard mode or fOSC/6 in X 2

Mode.

For Counter operat ion (C/Tx# = 1), the Timer register co unts the negative t ransitions on

the Tx externa l in put pin. The external input is sampled every periphera l cycle s. When

the sample is high in one cycle and low in the nex t one, the Counter is incremented.

Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transiti on,

the maximu m count rate is fPER/1 2, i.e. fOSC/24 in standard mode or fOSC/12 in X2 Mode.

There are no restrictions on the duty cycle of the external input signal, but to ensure that

a given lev el is sampled at least once before it changes, it should be held for at least

one full peripheral cycle.

Timer 0 Timer 0 functions as either a Timer or event Counter in four modes of operation.

Figure 24 th rough Figu re 27 show the logical configuration of each mode.

Timer 0 is c ontrolled b y the four lowe r bits of TMOD reg ister (See F igure 38) and bits 0,

1, 4 and 5 of TCON register (See Figure 37). T MOD register selec ts the m ethod of

Timer gating (GATE0), Timer or Counter operation (T/C0#) and mode of operation (M10

and M00). TCON register provides Timer 0 control functions: ov erflow flag (TF0), run

control bit (TR0), int errupt flag (IE0) and interrupt t ype control bit (I T 0).

For normal T im er op eration (GA TE0 = 0), setting TR0 al lows TL0 to be in crement ed by

th e select ed in put. Set ting G ATE0 and T R0 all ows ex te rna l pin INT 0# to c ontrol Timer

operation.

Timer 0 overflow (count rolls over f rom all 1s to all 0s ) sets TF0 flag generating an inter-

rupt request.

It is important to s top Timer/Co unt er before changing mode .

T89C51CC02

4126F–CAN–12/03

Mode 0 (13-bit Timer) Mode 0 configures Timer 0 as an 13-bit Timer which is set up as an 8-bit Timer (TH0

(S ee Fi gure 24). Th e uppe r thre e bits o f TL 0 regi ster a re ind etermina te a nd sh ould be

ignored. Prescaler overflow increme nts TH0 register.

Figu re 24. Ti mer/Counter x (x= 0 or 1) in Mode 0

Mode 1 (16-bit Timer) Mode 1 config ures Timer 0 a s a 16 -bit Time r with TH0 and TL 0 regist ers co nnected i n

cascade (S ee Figure 25). The selected input incremen ts TL0 register.

Figu re 25. Ti mer/Counter x (x= 0 or 1) in Mode 1

Mode 2 (8-bit Timer with Auto-

Reload) Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads

from TH0 register (See Figure 26). TL0 overflow sets TF0 flag in TCON regis ter and

r eloa ds TL0 with th e co nte nts o f TH0, whi ch is p rese t by soft ware . Wh en t he in te rru pt

reques t is se rv iced, hardware clears TF0. The reload lea ve s TH0 unchanged. The next

reload value ma y be changed at any time by writing it t o TH0 register.

FTx

CLOCK

TRx

TCON Reg

TFx

TCON Reg

GATEx

TMOD Reg

÷ 6 Overflow Timer x

Interrupt

Request

C/Tx#

TMOD Reg

TLx

(5 bits)

THx

(8 bits)

INTx#

See section “Clock”

TRx

TCON Reg

TFx

TCON Reg

GATEx

TMOD Reg

Overflow Tim er x

Interrupt

Request

C/Tx#

TMOD Reg

TLx

(8 bits)

THx

(8 bits)

INTx#

FTx

CLOCK ÷ 6

See section “Clock”

T89C51CC02

4126F–CAN–12/03

Figu re 26. Ti mer/Counter x (x= 0 or 1) in Mode 2

Mode 3 (Two 8-bit Timers) Mo de 3 con figu res Ti mer 0 su ch tha t reg isters TL 0 an d TH0 operate a s sep arat e 8-bit

Timers (See Figure 27). This mode is provided for applications requiring an additional 8-

bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD reg-

ister, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a

Timer function (count ing FPER /6) and takes over use of t he Timer 1 interrupt (TF1) a nd

run con trol (T R1) b its . Thus, operation of Timer 1 is restricted when T imer 0 is i n mode

Figu re 27. Ti mer/Counter 0 in Mode 3: Two 8-bit Counters

Timer 1 Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hol d-c ount mode. Fol low-

ing comments help to understand the differences:

• Timer 1 functions as either a Timer or event Counter in three modes of operation.

Figure 24 to Figure 26 show the logical configuration for modes 0, 1, and 2. Timer

1’s mo de 3 is a hold-count mode.

• Timer 1 is controlled by the four high-order bits of TMO D registe r (See Figure 38)

and bits 2 , 3, 6 and 7 of TCO N register (See Figure 37). TMOD re gister selects the

method of Timer gating (GATE1), Timer or Counter operation (C/T1#) and mode of

operation (M11 and M01). TCON register provides Timer 1 control functions:

overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and interrupt type

control bit (IT1).

• Timer 1 can serve as t he Baud Rat e Generator for the Serial Port. Mode 2 is best

suited for this purpose.

TRx

TCON Reg

TFx

TCON Reg

GATEx

TMOD Reg

Overflow Tim er x

Interrup

Reques

C/Tx#

TMOD Reg

TLx

(8 bits)

THx

(8 bits)

INTx#

FTx

CLOCK ÷ 6

See section “Clock”

TR0

TCON.4

TF0

TCON.5

INT0#

GATE0

TMOD.3

Overflow Tim er 0

Interrup

Reques

C/T0#

TMOD.2

TL0

(8 bits)

TR1

TCON.6

TH0

(8 bits) TF1

TCON.7

Overflow Tim er 1

Interrup

Reques

FTx

CLOCK ÷ 6

FTx

CLOCK ÷ 6

See section “Clock”

T89C51CC02

4126F–CAN–12/03

• For normal Timer operation (GATE1= 0), setting TR1 allows TL1 to be incremented

by the selecte d input. Setting GAT E1 and T R1 allows external pin INT1# to control

Timer o p erat i on.

• Tim er 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating

an interrupt request.

• When Timer 0 is in mode 3, it uses Timer 1’s overf low flag (TF1) and run control bit

(TR1). For t his situation, use Time r 1 only for applications that do not require an

interrupt (such as a Baud Rate Generator for the Serial Port) and swi tch Tim er 1 in

and out of mode 3 to turn it off and on.

• It is important to stop Timer/ Counter before changi ng mod e.

Mode 0 (13-bit Timer) Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Ti mer (TH1 reg-

ist er) with a modu lo-32 pre scal er implemen ted wi th the lowe r 5 bits o f the TL1 regi ster

(See Figure 24). T he upper 3 bits of TL1 register are ign ored. Prescaler overflow incre-

ments TH1 register.

Mode 1 (16-bit Timer) Mode 1 config ures Timer 1 a s a 16 -bit Time r with TH1 and TL 1 regist ers co nnected i n

cascade (S ee Figure 25). The selected input incremen ts TL1 register.

Mode 2 (8-bit Timer with Auto-

Reload) Mo de 2 co nfigures T ime r 1 as an 8-bi t Timer (TL 1 regist er) with au tomat ic reload f rom

TH1 regi ster on overflow (Se e Fig ure 26). TL1 overf low sets TF1 flag in T CON regist er

and rel oads TL1 with the contents of TH1 , which is preset by software. The reload

leaves TH1 unchanged.

Mode 3 (Halt) Pla ci ng Time r 1 in m ode 3 cau se s it to halt and hold its count. This c an be used to halt

Timer 1 when TR1 run control bit is not available i.e. when Timer 0 is in mode 3.

Interrupt Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This

flag is set every time an overf low occurs. Flags are cleared when vectoring to the Timer

interrupt routine. Interrupts are enabled by setting ETx bit in IEN0 register. This assumes

interrupts are globally enabled by setting EA bit in IEN0 register.

Fi gure 2 8. Timer Interrupt System

TF0

TCON.5

ET0

IEN0.1

Timer 0

Interrupt Request

TF1

TCON.7

ET1

IEN0.3

Timer 1

Interrupt Request

T89C51CC02

4126F–CAN–12/03

Registers Table 37. TCON Register

TCON (S :88h)

Timer/Co unter Control Register

Rese t Value = 0000 0000b

76543210

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Bit

Number Bit

Mnemonic Description

7TF1

Timer 1 Overflow Flag

Cleared by hardware when processor vectors to interrupt rou tine.

Set by hardware on Timer /Cou nter overflow, wh en Timer 1 register overflows.

6TR1

Timer 1 Run Control bit

Clear to turn off Timer/Counter 1.

Set to turn on Timer/Counter 1.

5TF0

Timer 0 Overflow Flag

Cleared by hardware when processor vectors to interrupt rou tine.

Set by hardware on Timer /Cou nter overflow, wh en Timer 0 register overflows.

4TR0

Timer 0 Run Control bit

Clear to turn off Timer/Counter 0.

Set to turn on Timer/Counter 0.

3IE1

Interrupt 1 Edge Flag

Cleared by ha rdware when interrupt is processed if edge- triggered (See IT1).

Set by har dware when external interrupt is detect ed on INT1# pin.

2IT1

Interrupt 1 Type Control bi t

Clear to select low level active (level trigg ered) for external int erru pt 1 (INT1#).

Set to select falling edge active (edge triggered) for external interrupt 1.

1IE0

Interrupt 0 Edge Flag

Cleared by ha rdware when interrupt is processed if edge- triggered (See IT0).

Set by har dware when external interrupt is detect ed on INT0# pin.

0IT0

Interrupt 0 Type Control bi t

Clear to select low level active (level trigg ered) for external int erru pt 0 (INT0#).

Set to select falling edge active (edge triggered) for external interrupt 0.

T89C51CC02

4126F–CAN–12/03

Table 38. TMOD Register

TMOD (S:89h)

Timer/Co unter Mode Control Register

Rese t Value = 0000 0000b

Notes: 1. Reloaded fr om TH1 at overf low.

2. Reloaded fr om TH0 at overf low.

Table 39. TH0 Register

TH0 (S:8Ch)

Timer 0 High Byte Register

Rese t Value = 0000 0000b

76543210

GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00

Bit

Number Bit

Mnemonic Description

7GATE1

Timer 1 Gating Control bit

Clear to enable Timer 1 whenever TR1 bit is set.

Set to en able Timer 1 onl y while INT1# pin is high and TR1 bit is set.

6C/T1#

Timer 1 Counter/Timer Select bit

Clear for Timer operation: Timer 1 counts the divid ed-down sy stem clock.

Set fo r Count e r oper a tio n: T i mer 1 cou nt s neg at i ve tr ans it ion s on ex te r nal pi n T1 .

5M11Timer 1 Mode Select bits

M11 M01 Operating mode

0 0 Mode 0: 8-bit Timer/Counte r (TH1) with 5bi t prescaler (TL1).

0 1 Mode 1: 16-bit Timer/Counter.

1 1 Mode 3: Timer 1 halted. Retains count.

1 0 Mode 2: 8- b it au t o -r el oa d Timer / C ou nte r (TL1) .(1)

4M01

3GATE0

Timer 0 Gating Control bit

Clear to enable Timer 0 whenever TR0 bit is set.

Set to en able Timer/Counter 0 only while INT0# pin is high and TR0 bit is set.

2C/T0#

Timer 0 Counter/Timer Select bit

Clear for Timer operation: Timer 0 counts the divid ed-down sy stem clock.

Set fo r Count e r oper a tio n: T i mer 0 cou nt s neg at i ve tr ans it ion s on ex te r nal pi n T0 .

1M10

Timer 0 Mode Select bit

M10 M00 Operating mode

0 0 Mode 0: 8-bit Timer/Counte r (TH0) with 5bi t prescaler (TL0).

0 1 Mode 1: 16-bit Timer/Counter.

1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL0).(2)

1 1 Mode 3: TL0 is an 8-bit Timer/Counter .

TH0 is an 8-bit Timer using Timer 1’s TR0 and TF0 bits.

0M00

76543210

Bit

Number Bit

Mnemonic Description

7:0 Hi gh Byte of Timer 0

T89C51CC02

4126F–CAN–12/03

Table 40. TL0 Register

TL0 (S:8Ah)

Timer 0 Low Byte Register

Rese t Value = 0000 0000b

Table 41. TH1 Register

TH1 (S:8Dh)

Timer 1 High Byte Register

Rese t Value = 0000 0000b

Table 42. TL1 Register

TL1 (S:8Bh)

Timer 1 Low Byte Register

Rese t Value = 0000 0000b

76543210

Bit

Number Bit

Mnemonic Description

7:0 Low Byte of Timer 0

76543210

Bit

Number Bit

Mnemonic Description

7:0 Hi gh Byte of Timer 1

76543210

Bit

Number Bit

Mnemonic Description

7:0 Low Byte of Timer 1

T89C51CC02

4126F–CAN–12/03

Timer 2 The T89C5 1CC02 Timer 2 is compatible with Timer 2 in the 80C52.

It is a 16-bit time r/coun ter: the co un t i s mai ntained by two eight bit ti mer re giste rs, TH 2

and TL2 that are cas cade-c onn ec ted. It is cont rolled by T 2CON registe r (Se e Ta ble 44)

and T 2MOD re gister (See T able 45). Timer 2 op eration is simil ar to Timer 0 an d Timer

1. C/T2 sel ect s F T2 clock/6 (timer operation) or external pin T2 (counter operation) as

timer clock. Setting TR2 allows TL2 to be incremented by the selected input.

Timer 2 includes the following enhancements:

• Au to-reload mode (up or down counter)

• Programmable clock-output

Auto-Reload Mode The aut o-relo ad mod e configu res Tim er 2 as a 16 -bit time r or event counte r with auto-

ma tic reload. T his fe ature is cont rolled by t he DCEN b it in T 2MO D register (Se e Tabl e

44). S etting the DCEN bit enables Timer 2 to count up or down as shown in Figure 29. In

this mode the T2EX pin controls the counting direction.

W hen T 2EX is hi gh, Timer 2 counts up. Timer ov erflow occurs at FFFFh which set s t he

TF2 f lag and gen erates an interrupt reque st. The overflo w a lso causes t he 16-bit value

in RCAP2H and RCAP 2L registers to be loaded i nto the timer registers TH2 and TL2.

When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the

timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers.

The underf low sets TF2 flag and reloads FFFFh into the timer registers.

The EXF2 bit toggles when Timer 2 overf low or underflow, depending on the direction of

th e count . EXF 2 does not ge ner ate a n interru pt. Th is bit c an be use d to prov ide 1 7-bit

resolution.

Figu re 29. Auto-Reload Mode Up/Down Counter

(DOWN COUNTING RELOAD VALUE)

TF2

EXF2

TH2

(8-bit)

TL2

(8-bit)

RCAP2H

(8-bit)

RCAP2L

(8-bit)

FFh

(8-bit) FFh

(8-bit)

TOGGLE

(UP COUNTING RELOAD VALUE)

TIMER 2

INTERRUPT

T2CON Reg

T2EX:

1=UP

2=DOWN

CT/2

T2CON.1

TR2

T2CON.2

FT2

CLOCK

See secti on “Clock”

T89C51CC02

4126F–CAN–12/03

Programmable Clock -

Output In clock-out m ode, Timer 2 operat es as a 5 0%-duty-cycle, programma ble clock genera-

tor (Figure 30). The input clock increments TL2 at frequency fOSC/2. The timer

repeatedly counts to overflow f rom a loaded value. At overflow, the c ontents of RCAP2H

and RCAP2L registers are loaded into TH2 and TL2. In this mode, Timer 2 overflows do

not generate interrupts. The formula gives the clock-out frequency depending on the

system oscillat or frequency and the value in the RCAP 2H and R CA P2 L registers:

For a 16 M Hz syste m clock in x1 mode, Tim er 2 has a programm able frequency rang e

of 61 Hz (fOSC/216) to 4 MHz (fOSC/4). The generated clock signal is brought out to T2 pin

(P1.0).

Timer 2 is programmed for the clock-out mode as follows:

• Se t T2OE bit in T2MOD register.

• Clear C/T 2 bit in T2CON register.

• Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L

registers.

• En ter a 16-bit in itial value in timer registers TH2/TL2. It can be the s am e as the

reload value or diffe rent depe nding on the application.

• To start the timer, set TR2 run control bit in T2CON register.

It is possible to use Timer 2 as a baud rate generator and a clock generator simulta-

neously. For this configuration, the baud rates and clock frequencies are not

independent since both functions use the values in the RCAP2H and RCAP2L registers.

Fi gure 3 0. Clock-Out Mode

Clock OutFrequency

–

clock

4 65536

RCAP

–

RCAP

⁄()×

-----------------------------------------------------------------------------------------

EXEN2

EXF2

OVERFLOW

T2EX

TH2

(8-bit)

TL2

(8-bit)

TIMER 2

RCAP2H

(8-bit)

RCAP2L

(8-bit)

T2OE

T2CON Reg

T2MOD Reg

C/T2

T2CON reg

INTERRUPT

CT/2

T2CON.1

TR2

T2CON.2

FT2

CLOCK

T89C51CC02

4126F–CAN–12/03

Registers Table 43. T 2 CON Register

T2CON (S:C8h)

Timer 2 Control Register

Rese t Value = 0000 0000b

bit addressabl e

76543210

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#

Bit

Number Bit

Mnemonic Description

7TF2

Timer 2 Overflow Flag

TF2 is not set if RCLK=1 or TCLK = 1.

Must be cleared by software.

Set by hardware on Timer 2 overflow.

6EXF2

Timer 2 External Flag

Set when a capture or a reload is caused by a negative transition on T2EX pin if

EXEN2=1.

Set to cause the CPU to vector to Ti mer 2 interrupt routine when Timer 2

interrupt is enabled.

Must be cleared by software.

5RCLK

Receive Clock bit

Clear to use timer 1 ov erfl ow as re ceive clock for serial port in mode 1 or 3.

Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.

4TCLK

Transmit Clock bit

Clear to use timer 1 o verflow as transmit clock for serial port in mode 1 o r 3.

Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.

3 EXEN2

Timer 2 External Enable bit

Clear to ignore events on T2EX pin for Timer 2 operation.

Set to ca use a capture or rel oad when a nega tive transition on T2EX pin is

detected, if Timer 2 is not used to clock the serial port.

2TR2

Timer 2 Run Control bit

Clear to turn off Timer 2.

Set to turn on Timer 2.

1C/T2#

Timer/Counter 2 Select bit

Clear for timer operation (input from internal clock system: fOSC).

Set for counter operation (i nput from T2 input pin).

0CP/RL2#

Timer 2 Capture/Relo ad bit

If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on

Timer 2 overflow .

Clear to auto-reload on Timer 2 overflows or negative transitions on T2EX pin if

EXEN2=1.

Set to capture on negative transitions on T2EX pin if EXEN2=1.

T89C51CC02

4126F–CAN–12/03

Table 44. T2MOD Register

T2M OD (S:C9h)

Timer 2 Mode Control Register

Reset Value = XXXX XX00b

Not bit addressable

Table 45. TH2 Register

TH2 (S:CDh)

Timer 2 High Byte Register

Rese t Value = 0000 0000b

Not bit addressable

76543210

------T2OEDCEN

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

1T2OE

Timer 2 Output Enable bit

Clear to program P1.0/T2 as clock input or I/O port.

Set to program P1.0/T2 as clock output.

0 DCEN Down Counter Enable bit

Clear to disable Timer 2 as up/down counter.

Set to en able Timer 2 as up/down counter.

76543210

--------

Bit

Number Bit

Mnemonic Description

7 - 0 Hig h By t e of Timer 2

T89C51CC02

4126F–CAN–12/03

Table 46. TL2 Register

TL2 (S:CCh)

Timer 2 Low Byte Register

Rese t Value = 0000 0000b

Not bit addressable

Table 47. RCAP2H Register

RCAP2H (S:CBh)

Timer 2 Reload/Capture High Byte Register

Rese t Value = 0000 0000b

Not bit addressable

Table 48. RCAP2L Register

RCAP2L (S:CAh) Timer 2 Reload/Capture Low Byte Register

Rese t Value = 0000 0000b

Not bit addressable

76543210

--------

Bit

Number Bit

Mnemonic Description

7 - 0 Low Byte of Timer 2

76543210

--------

Bit

Number Bit

Mnemonic Description

7 - 0 Hig h By t e of Timer 2 Rel oa d/Cap ture .

76543210

--------

Bit

Number Bit

Mnemonic Description

7 - 0 Low By te of Time r 2 Reload/C apture.

T89C51CC02

4126F–CAN–12/03

Watchdog Timer T89C51CC02 contains a powerful programmable hardware Watchdog Timer (WDT) that

automati cal ly resets the chip if it soft ware fail s to reset the WDT before the se lected time

interval has elaps ed. It permits large Timeout ranging from 16m s to 2s @fOSC = 12 MH z

in X1 mode.

Thi s WDT c onsists of a 14 -bit cou nter plus a 7-bit progra mmable coun ter, a Watc hdog

Timer reset reg ister (WDTRST) and a Wat chdog T im er programmi ng (WDT PRG) regis-

ter. When exiting reset, the WDT is -b y default- disable.

To enable the WDT, the user has to write the sequence 1EH and E1H into WDTRST

enabled, it will increment every machine cycle while the oscillator is running and there is

no w ay to dis abl e the W DT exce pt t hrou gh res et (e ither ha rdware re set or WDT over-

flow re set). When WD T overflow s, it will generate an output RESET pulse a t the RST

pin. The RESET pulse duration is 96xTOSC, where TOSC=1/fOSC. To make the best use of

the WDT, it should be serviced in those s ections of code that will periodically be exe-

cuted within the time required to prevent a WDT reset

Note: When the watchdog is enable it is impossible to change it s period.

Figu re 31. Watchdog Timer

÷ 6

÷ PS CPU and Peripheral

Clock

Fwd

Clock

WDTPRG

RESET Decoder

Control

WDTRST

Enable

14-bit Counter 7-bit Co unter

Outputs

Fwd Clock

RESET

- - -

- - 2 1 0

T89C51CC02

4126F–CAN–12/03

Watchdog Programming The thre e lower bits (S 0, S1, S2 ) located into W DTPR G register perm it to program the

W DT duration.

Table 49. Machine Cycle Count

To compute WD Timeout, the following f orm ula is applied:

Note: Svalue represents the decimal value of (S2 S1 S0)

Find Hereafter computed Timeout values for fOSCXTAL = 12 MHz in X1 mode

Table 50. Timeout Com puta tion

S2 S1 S0 Machine Cycle Count

000 2

14 - 1

001 2

15 - 1

010 2

16 - 1

011 2

17 - 1

100 2

18 - 1

101 2

19 - 1

110 2

20 - 1

111 2

21 - 1

S2 S1 S0 fOSC=12 MHz fOSC=16MHz fOSC=20 M Hz

0 0 0 16.38 ms 12.28 ms 9.82 ms

0 0 1 32.77 ms 24.57 ms 19.66 ms

0 1 0 65.54 ms 49.14 ms 39.32 ms

0 1 1 131.07 ms 98.28 ms 78.64 ms

1 0 0 262.14 ms 196.56 m s 157.28 ms

1 0 1 524.29 ms 393.12 m s 314.56 ms

1 1 0 1.05 s 786.24 ms 629.12 ms

1 1 1 2.10 s 1.57 s 1.25 ms

FTime Out F

12 214 2

Svalue

×()1

–

()×

-----------------------------------------------------------------

=–

T89C51CC02

4126F–CAN–12/03

Watchdog Timer

During Power-down

Mode and Idle

In Powe r- down mo de t he osc illato r s top s, w hich me ans the WDT al so s tops . Wh ile in

Power-down mode, the user does not need to service the WDT. There are 2 methods of

exiting Power-down mode: by a hardware reset or via a level activated external interrupt

which is enab led prior to entering Power-down mode. When P ower-down is exited with

hardware reset, the watchdog is disabled. Exiting Power-down with an interrupt is signif-

icantly different. The interrupt shall be held low long enough for the oscillator to stabilize.

W hen the interru pt is brough t hi gh, the interru pt is serviced . To preven t the W DT from

res etti ng the d evi ce whi le the i nte rrupt pin is held low , th e WDT is no t sta rted until th e

interrupt is pulled high. It i s suggested that the WDT be reset during the interrupt service

for the interrupt used to exit Power-down.

To ensure that the WDT does not overflow within a few states of exiting powerdown, it is

best to reset the WDT just before entering powerdown.

In the I dle mode, the oscillator continues to run. To prevent the WDT from resetting

T89C51CC02 while in Idle m ode, the user s hould alw ays set up a timer that will per iodi-

cally exit Idle, service t he WDT , and re-enter Idle mode.

WDTPRG (S: A7h) – Watchdog Timer Duration Programming register

Reset Value = XXXX X000b

76543210

- - - - - S2 S1 S0

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

2S2

Watchdog Timer Duration selection bit 2

Work in conjunction with bit 1 and bit 0.

1S1

Watchdog Timer Duration selection bit 1

Work in conjunction with bit 2 and bit 0.

0S0

Watchdog Timer Duration selection bit 0

Work in conjunction with bit 1 and bit 2.

T89C51CC02

4126F–CAN–12/03

Table 52. WDTRST Register

W DTRST (S:A6h Write Only) – Watchd og Timer Enable register

Rese t Value = 1111 1111b

Note: The WDRST register is used to reset/enable the WDT by writing 1EH then E1H in

sequence without instruction bet ween these two sequences.

76543210

--------

Bit

Number Bit

Mnemonic Description

7 - Watchdog Control Value

T89C51CC02

4126F–CAN–12/03

CAN Controller The CAN Con troller provides al l the f eatures required to i mplement the seri al commu ni-

cation protocol CAN as defined by BOSCH GmbH. The CAN specification as referred to

by ISO/1 18 98 (2.0A & 2. 0B) for high spe ed an d ISO /115 19-2 f or lo w speed . T he CA N

Controller i s able t o handle all t ypes of f ram es (Data, Rem ote, E rror and Ov erl oad) a nd

achieves a bitrate of 1-Mbit/s at 8 MHz1 Crystal frequenc y in X2 Mode.

Note: 1. At BRP = 1 sampling point will be fixed.

CAN Controller

Description The CAN controller accesses are made through SFR.

Several ope rations are possible by SFR:

• arithmetic and logic operations, transfers and program control (SFR is accessible by

direct addressing).

• 4 indepen dent message objects are implem ented, a pagination system manages

th eir acce sses.

Any m ess age object can be program m ed i n a rec ep tion buf f er block (ev en non-c onsec -

utiv e buffers). For the rec eption of def ined mes sages one or s everal receive r messag e

objects can be masked without partic ipating in the buffer feature. An IT is generated

when the b uff e r is full. T h e fr ames follo w i n g the bu ffe r -full in t er r up t w ill n ot b e t a k en into

account until at least one of the buffer message objects is re-enab led in reception.

Higher priority of a mes sage object for reception or transmission is given to the lower

mess age obje ct number.

The program mable 16-bit Timer (CANTIMER) is used to stamp each received and sent

message in the CA NSTMP register. T his timer starts counting as soon as the CAN con-

troller is enabled by the E NA bit in the CANGCON register.

The Time Trigger Comm unication (TTC) protocol is supported by the T89C51CC02.

Figu re 32. CAN Controller Block Diagram

bit

Stuffin g /De s tu ffin g

Cyclic

Redundancy Check

Receive Transmit

Error

Counter

Rec/Tec

bit

Timing

Logic

Page

Encoder

µC-Core Interface

Core

Control

Interface

Bus

TxDC

RxDC

T89C51CC02

4126F–CAN–12/03

CAN Controller Mailbox

and Registers

Organization

The pagination allows management of the 91 registers including 80(4 x 20) Bytes of

mailbox via 32 SFRs.

All ac tions o n the m ess age o bje ct wi ndow SF Rs ap ply t o the co rres pond ing mess ag e

object registers pointed by the message object number find in the Page message object

Figu re 33. CAN Controller Memory Organization

Ch.3 - ID Tag - 1

Ch.3 - ID Tag - 2

Ch.3 - ID Tag - 4

Ch.3 - ID Tag - 3

Ch.3 - ID Mask - 1

Ch.3 - ID Mask - 2

Ch.3 - ID Mask - 4

Ch.3 - ID Mask - 3

Ch.3 - Message Data - byte 0

General Control

General Status

bit Timing - 1

bit Timing - 2

bit Timing - 3

Enable Inter rupt

Enable Interrupt message object

Page message object

message object Status

message object Control & DLC

Message Data

ID Tag - 1

ID Tag - 2

ID Tag - 4

ID Tag - 3

ID Mask - 1

ID Mask - 2

ID Mask - 4

ID Mask - 3

message object 0 - Status

message object 0 - Control & DLC

Ch.0 - ID Tag - 1

Ch.0 - ID Tag - 2

Ch.0 - ID Tag - 4

Ch.0 - ID Tag - 3

Ch.0 - Message Data - byte 0

message object 3 - Status

message object 3 - Con trol & DLC

Status Interrupt message object

(message object number)(Data offs et)

SFRs On-chip CAN Controller Registers

4 Mess age Ob jects

8 Byt es

TimStmp High

TimStmp Low

Ch.0 - ID Mask- 1

Ch.0 - ID Mask- 2

Ch.0 - ID Mask - 4

Ch.0 - ID Mask- 3

CANTimer High

CANTimer Low

TimTTC High

TimTTC Low

TEC count er

REC count e r

Timer Control

Enable message object

message object Window SFRs

Ch.0 TimStmp High

Ch.0 TimStmp Low

Ch.3 TimStmp High

Ch.3 TimStmp Low

General Interrupt

T89C51CC02

4126F–CAN–12/03

Working on Message Objects T he Page message object register (CANPAG E) is used t o sel ect one of th e 4 m essage

obj ects. Then , messag e object Control (CANC ONCH ) and m essage object Status

(CANSTCH) are available for this selected message object number in the corresponding

SFRs. A single register (CANMSG) is used for the message. The mailbox pointer is

managed by the Page message object register with an auto-incrementation at the end of

each access. The range of this counter is 8.

Note that the maibo x is a pure RAM , dedicat ed to one message object, without overlap.

In m ost cases, it is n ot nece ssar y to tr ansf er the receiv ed m essage into the s tandard

mem ory. Th e message t o be transmitted can be bui lt directly in the maibox. Mos t calcu-

lations or tests can be executed in the mailbox area which provide quicker access.

CAN Controller

Management In order to enable the CAN Controller correctly the following registers have to be

initialized:

• General Control (CANGCON),

• bit Timing (CANBT 1, 2 & 3),

• And for each page of 15 message objects:

– Message object Control (CANCONCH),

– Message object Status (CANSTCH).

During operation, the CAN Enable message object registers (CANEN) gives a fast over-

view of the message objects availability.

The CAN messages can be handled by interrupt or polling modes.

A me ssage object can be configured as follow s:

• Transmit message object

• Rec eive message object

• Rec eive buffer message object

• Disable

This configuration is made in the CONCH field of the CANCONCH register (See

Table 53).

When a m e ssa ge object is config ured, th e correspondi ng ENCH bit of CANEN re gister

is set.

Table 53. Configuration for CONCH1:2

When a Transmitter or Receiv er action of a message objec t is completed, the corre-

sponding ENCH bit of the CANEN register is cleared. In order to re-enable the message

object, it is necess ary to re-write the configuration in CANCONCH register.

N on-con sec utiv e me ssag e obj ects c an b e us ed f or all t hree types of m es sage o bjec ts

(Transmi tter, Receiver and Receiver buffer).

CONCH 1 CONCH 2 Type of Message Object

00Disable

0 1 Transmitter

10Receiver

1 1 Receiv er bu ffer

T89C51CC02

4126F–CAN–12/03

Buffer Mode Any m essag e object can be used to d efine one buf fer, including non-con secutive m es-

sage objects, and with no limitation in number of message objects used up to 4.

Each message object of the buffer must be initialized CO NCH2 = 1 and CONCH1 = 1;

Fi gure 3 4. Buffer Mode

The same acceptance filter must be defined for each message objects of the buffer.

W hen there is no mask on the identifier or the IDE, all messages are accepted.

A rec eiv ed fram e will alw a ys be s tored in the lowes t free message object.

W hen th e fl ag RxO k i s set o n one of th e b uffer messa ge obje cts, this m ess age o bject

can then be read by the appli cation. T his flag m ust then be c lea red by the s oftware a nd

the messag e object re-enab led in buffer reception in order to free the message object.

The OVRBUF flag in the CANGIT register is set when the buffer is full. This flag can

generate an interrupt.

The frames following the buffer-full interrupt will not be stored and no status will be over-

written in the CANST CH regis te rs involved in th e buffer until at least on e of the buffer

mess age obje cts is re-enabled in reception.

This flag must be cleared by the software in order to acknowledge the interrupt.

IT CAN Management T he different interrupts are:

• Transmission interrupt

• Rec eption interrupt

• Interrupt on error (bit error, stuff error, crc error, form error, acknowledge error)

• Interrupt when Buffer receive is full

• Interrupt on overrun of CAN Ti mer

mess age object 0

mess age object 1

mess age object 2

mess age object 3

Block buffer

buffe r 0

buffe r 1

T89C51CC02

4126F–CAN–12/03

Figu re 35. CAN Controller Interrupt Structure

To enable a transmission interrupt:

• Enable Gen eral CAN IT in the interrupt syste m register

• En able interrupt by message object, EICHi

• En able transmission interrupt, ENTX

To enable a reception interrupt:

• Enable Gen eral CAN IT in the interrupt syste m register

• En able interrupt by message object, EICHi

• En able reception interrupt, ENRX

To enable an interrupt on message object error:

• Enable Gen eral CAN IT in the interrupt syste m register

• En able interrupt by message object, EICHi

• En able interrupt on error, ENER CH

To enable an interrupt on general error:

• Enable Gen eral CAN IT in the interrupt syste m register

• En able interrupt on error, ENERG

SIT i

i=0

i=4

OVRIT

ENRX

CANGIE.5 ENTX

CANGIE.4 ENERCH

CANGIE.3

ENBUF

CANGIE.2 ECAN

IEN1.0

RXOK i

CANSTCH.5

TXOK i

CANSTCH.6

BERR i

CANSTCH.4

SERR i

CANSTCH.3

FERR i

CANSTCH.1

CERR i

CANSTCH.2

AERR i

CANSTCH.0

EICH i

CANIE

OVRTIM

CANGIT.5

OVRBUF

CANGIT.4

FERG

CANGIT.1

AERG

CANGIT.0

SERG

CANGIT.3

CERG

CANGIT.2

ENERG

CANGIE.1

ETIM

IEN1.2

SIT i

CANSIT

CANIT

CANGIT.7

CAN

T89C51CC02

4126F–CAN–12/03

To enable an interrupt on Buffer-full condition:

• Enable Gen eral CAN IT in the interrupt syste m register

• En able interrupt on Buffer full, E NB UF

To enable an interrupt when Timer overruns:

• Enable Overrun IT in the interrupt system register

When an interrupt occurs, the corresponding message object bit is set in the SIT

To ack nowledge an interrupt, the corresponding CANSTCH bits (RXOK, TXOK,...) or

CANGIT bits (OVRTIM, OVRBUF,...), must be cleared by the software application.

W hen the CAN node is in transmission and det ects a Form Error in its frame, a bit Error

will also be raised. Cons equently, two c onsecut ive i nterrupts can occur, bot h du e t o the

same error.

When a message ob ject error oc curs and is set in CANS TC H regi s ter, n o g eneral error

are set in CANGIE register.

bit Timing and Baud Rate

Figu re 36. Sample and Transmission Point

The baud rate selection is made by Tbit calculation:

Tbit = Tsyns + Tprs + Tphs1 + Tphs 2

1. Tsyns = Tscl = (BRP[5..0]+ 1)/Fcan = 1TQ

2. Tprs = (1 to 8) * Tscl = (PRS[2..0]+ 1) * Tscl

3. Tph s1 = (1 to 8) * Tscl = (PHS1[2..0]+ 1) * Tscl

4. Tph s2 = (1 to 8) * Tscl = (PHS2[2..0]+ 1) * Tscl

5. Tsjw = (1 to 4) * Tscl = (SJW[1..0]+ 1) * Tscl

Th e to tal nu mbe r of T scl (T im e Qua nta) i n a bi t time mus t be c omp rise d betw ee n 8 t o

25.

FCAN

CLOCK Prescaler BRP

PRS 3bit length

PHS1 3bit length

PHS2 3bit length

SJW 2-bit le ngth

bit Timing

System Clock Tscl

Time Quantum

Sample Point

Transmission Poin

T89C51CC02

4126F–CAN–12/03

Figu re 37. General Structure of a bit Period

example of bit timing determination for CAN baudrate of 500 kbit/s:

FOSC = 12 MHz in X1 mode => FCAN = 6MHz

Verify that the CAN baud rate you want is an integer division of FCAN clock.

FCAN/CANbaudrate = 6 MHz/500 kHz = 12

The time quanta TQ must be comprised between 8 and 25: TQ = 12 and BRP = 0

Define the various timing parameters: Tbit = Tsyns + Tprs + Tphs1 + Tphs2 =

12TQ

Tsyns = 1TQ and Tsjw =1TQ => SJW = 0

If we chose a sample point at 66.6% => Tphs2 = 4TQ => PHS2 = 3

Tbit = 12 = 4 + 1 + Tphs1 + Tprs, let us choose Tprs = 3 Tphs1 = 4

PHS1 = 3 and PRS = 2

BRP = 0 so CANBT1 = 00h

SJW = 0 and PRS = 2 so CANBT2 = 04h

PHS2 = 3 and PHS1 = 3 so CANBT3 = 36h

bit Rate Prescaler

Oscillator

1/ Fc an

Tscl

System Clock

One N omi nal bit

Tsyns (*) Tprs

Sample Point

(*) Synchronization Segment: SYNS

Tbit

Tsyns = 1xTscl (fixed)

Data

Tbit Tsyns Tprs Tphs1Tphs2++ +=

Tbit calculation:

Transmission Poi

Tphs1 + Tsjw (3) Tphs2 - Tsjw (4)

(

1) Phase error ≤ 0

(

2) Phase error ≥ 0

(

3) Phase error > 0

(

4) Phase error < 0

Tp hs 2 (2)

Tp hs 1 (1)

T89C51CC02

4126F–CAN–12/03

Fault Confinement W ith respect to fault confinement, a unit may be in one of the three following status:

• Error active

• Error passive

•Bus off

An error active unit takes part in bus communication and can send an active error frame

when the CAN macro detects an error.

An error passive unit cannot send an active error frame. It takes part in bus communica-

tion, but when an error is detected, a passive error frame is sent. Also, after a

transm ission, an error passive unit wil l wait before initiat ing further transmission.

A bus off unit is not all owed to have any influence on the bus.

For fault confinement, two error counters (TEC and REC) are implemented.

See CAN Specification for details on Fault confinement.

Fi gure 3 8. Line Error Mode

TEC>255

Error

Active

Error

Passive Bus

Off

Init.

TEC<127

and

REC<127

TEC>127

REC>127 128 Occurrences

11 Consecutive

Recessive

bit

TEC: T ransmit Error Cou nter

REC: Receive E rro r Counter

T89C51CC02

4126F–CAN–12/03

Acceptance Filter Upon a reception hit (i.e., a good comparison between the ID+RTR+RB+IDE received

and an ID+ RTR+RB +IDE specified w hile taking the comparison m ask into account) the

ID+RTR+RB+IDE received are written over the ID TAG Registers.

ID => IDT0-29

RTR => RTRTAG

RB => RB0-1TAG

IDE => IDE in CANCONCH register

Fi gure 3 9. Acceptance Filter Block Diagram

example:

To accept only ID = 318h in part A.

ID MSK = 111 1111 1111 b

ID TAG = 011 0001 1000 b

13/32

RxDC

13/32

Write

13/32

Hit

13/32

ID MSK Registers (Ch i)

ID & RB RTR IDE

Rx Shift Register (internal)

ID & RB RTR IDE

Enable (Ch i)

ID TAG Registers (Ch i) & CanConch

ID & RB RTR

IDE

T89C51CC02

4126F–CAN–12/03

Data and Rem ote Frame Description of the different steps for:

• Data frame

• Rem ote frame, with automatic reply

• Rem ote frame

u uu uu

0 1 x 0 0 u uu uu

ENCH

RTR

RPLV

TXOK

RXOK

0 1 x 0 0

c uc uu

0 0 x 1 0 u cc uu

0 0 x 0 1

DATA FRAME

Node A Node B

ENCH

RTR

RPLV

TXOK

RXOK

message object in reception

message object stay in receptio

message object in transmission

message object stay in

transmission

u uu uu

1 1 x 0 0

c uu uc

0 1 x 1 0

ucc uu

0 0 x 0 1

REMOTE FRAME

DATA FRAME

u uu uu

1 1 1 0 0

u uu cc

0 1 0 0 0

c uc cu

0 0 0 1 0

ENCH

RTR

RPLV

TXOK

RXOK

ENCH

RTR

RPLV

TXOK

RXOK

(immediate)

message object in reception

message object in transmission

message object stay in transmission

message object in transmission

message object in reception

message object stay in

by CAN controller by CAN controller

reception

u uu uu

1 1 x 0 0 u uu uu

ENCH

RTR

RPLV

TXOK

RXOK

1 1 0 0 0

c uu uc

0 1 x 1 0 u cc uu

1 0 0 0 1

REMOTE FRAME

ENCH

RTR

RPLV

TXOK

RXOK

u uu uu

0 1 x 0 0

c uc uu

0 0 x 1 0

u cc uc

0 0 x 0 1

DATA FRAME

(deferred)

u: modified by user

ic: modified by CAN

message object in reception

message object in transmission by use

message object stay in transmission

message object stay in reception

message object in transmission

message object in reception

by CAN controlle r

by user

T89C51CC02

4126F–CAN–12/03

Time Trigge r

Communication (TTC)

and Message Stamping

The T89C51CC02 has a programmable 16-bit Timer (CANTIMH&CANTIML) for mes-

sage stamp and TTC.

This CAN Timer starts after the CAN controller is enabl ed by the ENA bit in the CANG-

CON register.

Two mod es in the tim er are implem ented:

• Tim e T ri gger Communication:

– Capture of this timer value in the CANTTCH & CANTTCL registers on St art

Of Frame (SOF) or End Of Frame (EOF), depending on the SYNCTTC bit in

the CANGCON register, when t he network is configured in TT C by the TTC

bit in the CANGCON register.

Note: In this mode, CAN only sends the frame once, even if an error occurs.

• Message St amping

– Capture of this timer value in the CANSTMPH & CANSTMPL registers of the

message object which received or s en t the frame.

– All messages can be stamps.

– The stamping of a received frame occurs when the RxOk flag is set.

– The stamping of a sent frame occurs when the TxO k flag is s et.

The CAN Timer works in a roll-over from FFFFh to 0000h which serves as a time base.

W hen the timer roll-over from FFFF h to 0000h, an interrupt is g enerated if the ETIM bit

in the interrupt enable register IEN1 is set.

Figu re 40. B lock Diagram of CAN Timer

EOF on CAN frame

ENA

CANGCON.1

CANTCON

RXOK i

CANSTCH.5

TXOK i

CANSTCH.4

÷ 6

Fcan

CLOCK

SOF on CAN frame

TTC

CANGCON.5 SYNCTTC

CANGCON.4

CANTTCH & CANTTCL

CANSTMPH & CANSTMPL

CANTIMH & CANTIML

OVRTIM

CANGIT.5

When 0xFFFF to 0x0000

T89C51CC02

4126F–CAN–12/03

CAN Autobaud and

Listening Mode To acti vate the A utobau d fe ature, the A UTO BAU D b it in th e CA NGCO N regi ster must

be s et. In this m ode, the CA N cont roller is only listening to the line without ack nowl edg-

ing the re ceived m es sages . It canno t send an y messag e. T he error f lags a re upda ted.

The bit timing can be adjusted until no error occurs (good c onfiguration find).

In this mode, the error c oun ters are frozen.

To go back to the standard mode, the AUTOBAUD bit must be cleared.

Fi gure 4 1. Autobaud M ode

Routine Examples 1. Init of CAN macro

// Reset the CAN macro

CANGCON = 01h;

// Disable CAN interrupts

ECAN = 0;

ETIM = 0;

// Init the Mailbox

for num_page =0; num_page <4; num_page++

{

CANPAGE = num_channel << 4;

CANCONCH = 00h

CANSTCH = 00h;

CANIDT1 = 00h;

CANIDT2 = 00h;

CANIDT3 = 00h;

CANIDT4 = 00h;

CANIDM1 = 00h;

CANIDM2 = 00h;

CANIDM3 = 00h;

CANIDM4 = 00h;

for num_data =0; num_data <8; num_data++)

{

CANMSG = 00h;

}

// Configure the bit timing

CANBT1 = xxh

CANBT2 = xxh

CANBT3 = xxh

TxDC

RxDC

AUTOBAUD

CANGCON.3 RxDC

TxDC

T89C51CC02

4126F–CAN–12/03

// Enable the CAN macro

CANGCON = 02h

2. Configure message object 3 in reception to receive only standard (11bit

identifier) message 100h

// Select the message object 3

CANPAGE = 30h

// Enable the interrupt on this message object

CANIE = 08h

// Clear the status and control register

CANSTCH = 00h

CANCONCH= 00h

// Init the acceptance filter to accept only message 100h in standard mode

CANIDT1 = 20h

CANIDT2 = 00h

CANIDT3 = 00h

CANIDT4 = 00h

CANIDM1 = FFh

CANIDM2 = FFh

CANIDM3 = FFh

CANIDM4 = FFh

// Enable channel in reception

CANCONCH = 88h // enable reception

Note: to enable the CAN interrupt in reception:

EA = 1

ECAN = 1

CANGIE = 20h

3. Send a message on the message object 0

// Select the message object 0

CANPAGE = 00h

// Enable the interrupt on this message object

CANIE = 01h

// Clear the Status register

CANSTCH = 00h;

// load the identifier to send (ex: 555h)

CANIDT1 = AAh;

CANIDT2 = A0h;

// load data to send

CANMSG = 00h

CANMSG = 01h

CANMSG = 02h

CANMSG = 03h

CANMSG = 04h

CANMSG = 05h

CANMSG = 06h

CANMSG = 07h

// configure the control register

CANCONCH = 18h

4. Interrupt routine

// Save the current CANPAGE

T89C51CC02

4126F–CAN–12/03

// Find the first message object which generate an interrupt in CANSIT

// Select the corresponding message object

// Analyse the CANSTCH register to identify which kind of interrupt is

generated

// Manage the interrupt

// Clear the status register CANSTCH = 00h;

// if it is not a channel interrupt but a general interrupt

// Manage the general interrupt and clear CANGIT register

// restore the old CANPAGE

T89C51CC02

4126F–CAN–12/03

CAN SFRs

Table 54. S FR Mappin g

0/8(1) 1/9 2/A 3/B 4/C 5/D 6/E 7/F

F8h IPL1

xxxx x000 CH

0000 0000 CCAP0H

0000 0000 CCAP1H

0000 0000 FFh

F0h B

0000 0000 ADCLK

xxx0 0000 ADCON

x000 0000 ADDL

0000 0000 ADDH

0000 0000 ADCF

0000 0000 IPH1

xxxx x000 F7h

E8h IEN1

xxxx x000 CL

0000 0000 CCAP0L

0000 0000 CCAP1L

0000 0000 EFh

E0h ACC

0000 0000 E7h

D8h CCON

0000 0000 CMOD

0xxx x000 CCAPM0

x000 0000 CCAPM1

x000 0000 DFh

D0h PSW

0000 0000 FCON

0000 0000 EECON

xxxx xx00 D7h

C8h T2CON

0000 0000 T2MOD

xxxx xx00 RCAP2L

0000 0000 RCAP2H

0000 0000 TL2

0000 0000 TH2

0000 0000 CANEN

xxxx 0000 CFh

C0h P4

xxxx xx11 CANGIE

1100 0000 CANIE

1111 0000 CANIDM1

xxxx xxxx CANIDM2

xxxx xxxx CANIDM3

xxxx xxxx CANIDM4

xxxx xxxx C7h

B8h IPL0

x000 0000 SADEN

0000 0000 CANSIT

xxxx 0000 CANIDT1

xxxx xxxx CANIDT2

xxxx xxxx CANIDT3

xxxx xxxx CANIDT4

xxxx xxxx BFh

B0h P3

1111 1111 CANPAGE

1100 0000 CANSTCH

xxxx xxxx CANCONCH

xxxx xxxx CANBT1

xxxx xxxx CANBT2

xxxx xxxx CANBT3

xxxx xxxx IPH0

x000 0000 B7h

A8h IEN0

0000 0000 SADDR

0000 0000 CANGSTA

1010 0000 CANGCON

0000 0000 CANTIML

0000 0000 CANTIMH

0000 0000 CANSTMPL

xxxx xxxx CANSTMPH

xxxx xxxx AFh

A0h P2

xxxx xx11 CANTCON

0000 0000 AUXR1(2)

xxxx 00x0 CANMSG

xxxx xxxx CANTTCL

0000 0000 CANTTCH

0000 0000 WDTRST

1111 1111 WDTPRG

xxxx x000 A7h

98h SCON

0000 0000 SBUF

0000 0000 CANGIT

0x00 0000 CANTEC

0000 0000 CANREC

0000 0000 9Fh

90h P1

1111 1111 97h

88h TCON

0000 0000 TMOD

0000 0000 TL0

0000 0000 TL1

0000 0000 TH0

0000 0000 TH1

0000 0000 CKCON

0000 0000 8Fh

80h SP

0000 0111 DPL

0000 0000 DPH

0000 0000 PCON

00x1 0000 87h

0/8(1) 1/9 2/A 3/B 4/C 5/D 6/E 7/F

T89C51CC02

4126F–CAN–12/03

Registers Table 55. CAN GCON Register

CANGCON (S:ABh)

CAN General Control Register

Rese t Value = 0000 0000b

7654 3210

ABRQ OVRQ TTC SYNCTTC AUTOBAUD TEST ENA GRES

Bit Number Bit Mnemonic Des cription

7 ABRQ

Abort Request

Not an auto-resetable bit. A reset of the ENCH bit (message object

cont rol & DLC re g is ter) is don e for ea ch me ss age obje ct. The

pen di ng tra ns mis sion co mmu ni cati on s a re i mme diat e ly ab ort ed bu t

the on-going commun ication wi ll be terminated normally, setting

the appropriate status flags, TxOk or RxOk.

6OVRQ

Overload Frame Request (Initiator).

Auto-resetable bit.

Set to send an overload frame after the next received message.

Cleared by the hardware at the beginning of transmission of the

overload frame.

5TTC

Network in Timer Trigger Communication

set to select node in TTC.

clear to disable TTC featu res.

4 SYNCTTC

Synchronization of TTC

When this bit is set the TTC timer is caught on the last bit of the

End Of Frame.

When this bit is clear the TTC timer is caught on the Start Of

Frame.

This bit is only used in the TTC mode.

3AUTOBAUD

AUTOBAUD

set to ac tiv e listening mo de.

Cle ar to disa ble lis t e ni ng mod e

2TEST

Test mode. The test mode is intended for factory testing and not for

customer use.

1ENA/STB

Enable/Standby CAN Con troller

When this bit is set, it enables the CAN controller and its input

clock.

When this bit is clear, the on-going communication is terminated

normally and the CAN controller state of the machine is frozen (the

ENCH bit of each message object does not change).

In the standby mode, the transmitter constantly provides a

recessive level; the re ceiver is not activat ed and the input clock is

stopped in the CAN controller. During the disable mode, the

registers and the mailbox remain accessible.

Note that two clock periods are needed to start the CAN controller

state of the machine.

0GRES

General Reset (Software Reset).

Auto-resetable bit. This reset command is ‘ORed’ with the

hardware reset in order to reset the controller. After a reset, the

controller is disabled.

T89C51CC02

4126F–CAN–12/03

Table 56. CANGS TA Register

CANGS TA (S: AAh )

CAN General Status Reg ister

Note: 1. These fields are Read Only.

Rese t Value = x0x0 0000b

76543210

- OVFG - TBSY RBSY ENFG BOFF ERRP

Bit Number Bit Mnemonic Des cription

Reserved

The values read from this bit is indeterminate. Do not set this bit.

6OVFG

Ove r load f rame f lag(1)

This status bit is s et by the har dware as long as the pr oduced

overload frame is sent.

This flag does not generate an interrupt

Reserved

The values read from this bit is indeterminate. Do not set this bit.

4 TBSY

Transmitter busy(1)

This status bit is set by the har dware as long as the CAN

transmitter generates a frame (remote, data, overload or error

frame) or an ack field. This bit is also active during an InterFrame

Spacing if a frame must be sent.

This flag does not generate an interrupt.

3RBSY

Receiver busy(1)

This status b it is set by the hardware as long as the CAN receiver

ac quires or mo nitors a frame.

This flag does not generate an interrupt.

2ENFG

Enable on-chip CAN controller flag(1)

Because an enable/disa ble command is not effec tive immediately,

this status bit gives the true state of a chose n mode.

This flag does not generate an interrupt.

1BOFF

Bus off mode(1)

See Figure 38

0 ERRP Error pa ssive mode(1)

See Figure 38

T89C51CC02

4126F–CAN–12/03

Table 57. CANGIT Register

CANGIT (S:9Bh)

CAN General Interrupt

Note: 1. These fields are Read Only.

Rese t Value = 0x00 0000b

76543210

CANIT - OVRTIM OVRBUF SERG CERG FERG AERG

Bit Number Bit Mnemonic Des cription

7CANIT

General interrupt flag(1)

This status bit is the image of all the CAN controller interrupts sent

to the interrupt controller.

It can be used in the case of the polling method.

Reserved

The values read from this bit is indeterminate. Do not set this bit.

5OVRTIM

Overrun CAN Timer

This status bit is set when the CAN timer switches 0xFFFF to

0x0000.

If the bit ETIM in the IE1 register is set, an interrupt is generated.

Clear this bit in order to reset the interrupt.

4 OVRBUF

Ove rrun B UFF E R

0 - no interrupt.

1 - IT turned on

This bit is set when the buffer is full.

bit rese table by user.

See Figure 35.

3 SERG Stuff Error General

Detection of more than five consecutive bits with the same polarity.

This flag can generate an interrupt. resetable by user.

2CERG

CRC Error General

The receiver performs a CRC check on each destuf fed received

message from the st art of frame up to the data field.

If this checking does not match with the destuffed CRC field, a

CRC error is set.

This flag can generate an interrupt. resetable by user.

1FERG

Form Error General

The for m erro r results from one or more violations of the fixed form

in th e fol lo w in g bit fields :

CRC delimiter

acknowledgment delimiter

end_of_frame

This flag can generate an interrupt. resetable by user.

0 AERG Acknowledgment Error General

No detect ion of the dominant bit in the acknowledge slot.

This flag can generate an interrupt. resetable by user.

T89C51CC02

4126F–CAN–12/03

Table 58. CANTEC Register

CANTEC (S:9Ch Read Only) – CAN Transmit Error Counter

Rese t Value = 00h

Table 59. CANREC Regi ster

CANREC (S:9Dh Read On ly) – CAN Reception Error Counter

Rese t Value = 00h

76543210

TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0

Bit Number Bit Mnemonic Des cription

7 - 0 TEC7:0 Tran smit E rror Counter

See Figure 38

76543210

REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0

Bit Number Bit Mnemonic Des cription

7 - 0 REC7:0 Reception Error Counter

See Figure 38

T89C51CC02

4126F–CAN–12/03

Table 60. CANGIE Register

CANGIE (S:C1h) – CAN

Rese t Value = xx00 000xb

76543210

- - ENRX ENTX ENERCH ENBUF ENERG -

Bit Number Bit Mnemonic Des cription

7 - 6 - Reserved

The values read from these bits are indeterminate. Do not set these

bits.

5 ENRX Enable Receive Interrupt

0 - Disa ble

1 - Enab le

4ENTX

Enable Transmit Interrupt

0 - Disa ble

1 - Enab le

3 ENERCH Enable Message Object Error Interrupt

0 - Disa ble

1 - Enab le

2ENBUF

Enable BUF Interrupt

0 - Disa ble

1 - Enab le

1 ENERG Enable General Error Interrupt

0 - Disa ble

1 - Enab le

Reserved

The value read from this bit is indeterminate. Do not set this bit.

See Figure 35.

T89C51CC02

4126F–CAN–12/03

Table 61. CANEN Register

CANEN (S:CFh Read Only)

CAN Enable M essage Obje ct Registers 2

Reset Value = xxxx 0 000b

Table 62. CANSIT Register

CANSIT (S:BBh Read Only) – CAN Status Interrupt Message Object Registers 2

Rese t Value = xxxx0000b

76543210

- - - - ENCH3 ENCH2 ENCH1 ENCH0

Bit Number Bit Mnemonic Des cription

7 - 4 - Reserved

The values read from these bits are indeterminate. Do not set these

bits.

3 - 0 ENCH3:0

Enable Message Object

0 - message obje ct is disabled => the message object is f ree fo r a

new emission or reception.

1 - message object is enabled.

This bit is resetable by re-writing the CANCONCH of the

corresponding message object.

76543210

- - - - SIT3 SIT2 SIT1 SIT0

Bit Number Bit Mnemonic Des cription

7 - 4 - Reserved

The values read from these bits are indeterminate. Do not set these

bits.

3 - 0 SIT3:0

Status of Interrupt by Message Object

0 - no interrupt.

1 - IT turned on. Reset when interrupt condition is cleared by user.

SIT3:0 = 0b 0000 1001 -> I T’s on messag e objects 3 & 0.

See Figure 35.

T89C51CC02

4126F–CAN–12/03

Table 63. CANIE Register

CANIE (S:C3h) – CAN Enable Interrupt message object Registers 2

Reset Value = xxxx 0 000b

Table 64. CANBT1 Register

CANBT1 (S:B4h) – CAN bit Timing Registers 1

Note: 1. The CAN co ntr oller bit timing registers must be accessed only if the CAN contr oller is

disabled with the ENA bit of the CANGCON register set t o 0.

See Figure 37.

No default value after res et.

76543210

- - - - IECH 3 I ECH 2 IECH 1 IECH 0

Bit Number Bit Mnemonic Des cription

7 - 4 - Reserved

The values read from these bits are indeterminate. Do not set these

bits.

3 - 0 IECH3:0

Enable Interrupt by Message Object

0 - disable IT.

1 - enable IT.

IECH3: 0 = 0b 0000 1100 -> Enable IT’s of message objects 3 & 2.

76543210

- BRP 5 BRP 4 BRP 3 BRP 2 BRP 1 BRP 0 -

Bit Number Bit Mnemonic Des cription

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6 - 1 BRP5:0

Baud Rate Prescaler

The period of the CAN controller syst em clock Tscl is

programmable and determ ines the individual bi t timing.(1)

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Tscl = BRP[5..0] + 1

FCAN

T89C51CC02

4126F–CAN–12/03

Table 65. CANBT2 Register

CANBT2 (S:B5h) – CAN bit Timing Registers 2

Note: 1. The CAN co ntr oller bit timing registers must be accessed only if the CAN contr oller is

disabled with the ENA bit of the CANGCON register set t o 0.

See Figure 37.

No default value after res et.

76543210

- SJW 1 SJW 0 - PRS 2 PRS 1 PRS 0 -

Bit Number Bit Mnemonic Des cription

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6 - 5 SJW1:0

Re-sync hroniza tion Jum p Width

To compensate for phase shifts between clock oscillators of

different bus controllers, the controller must re-synchronize on any

relevant signal edge of the current transmission.

The synchronization jump width defines the m aximum number of

clock cycles. A bit period may be shor tened or lengthened by a re-

synchronization.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

3 - 1 PRS2:0

Prog ram m ing Time Segm en t

This part of the bit time is used to compensate for the physical

delay times within the network. It is twice the sum of the signal

propagation time on the bus line, the input comparator delay and

the output dr iver delay.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Tsjw = Tscl x (SJW [1..0] +1)

Tprs = Tscl x (PRS[2..0] + 1)

T89C51CC02

4126F–CAN–12/03

Table 66. CANBT3 Register

CANBT3 (S:B6h)

CAN bit Timing Registers 3

Note: 1. The CAN co ntr oller bit timing registers must be accessed only if the CAN contr oller is

disabled with the ENA bit of the CANGCON register set t o 0.

See Figure 37.

No default value after res et.

76543210

- PHS2 2 PHS2 1 PHS2 0 PHS1 2 PHS1 1 PHS1 0 SMP

Bit Number Bit Mnemonic Des cription

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6 - 4 P H S2 2:0

Phase Se gment 2

This phase is used to compensate for pha se edge errors. This

segment can be shortened by the re-synchroni zation jump wi dth.

3 - 1 P H S1 2:0

Phase Se gment 1

This phase is used to compensate for pha se edge errors. This

segment can be lengthened by the re-sy nchronizat ion jump wid th.

0SMP

Samp le Type

0 - once, at the sample point.

1 - three times, the thr eefold sampling of the bus is the sample

point and twice over a dist ance of a 1/2 period of the Tscl. The

result corresponds to the majority decision of the three values.

Tphs2 = Tscl x (PHS2[2..0] + 1)

Tphs1 = Tscl x (P HS1[2..0] + 1)

T89C51CC02

4126F–CAN–12/03

Table 67. CANPAGE Register

CANPAGE (S:B1h) – CAN Message Object Page Register

Rese t Value = xx00 0000b

Table 68. CANCONCH Register

CANCO NCH (S:B3h) – CAN Message Object Control and DLC Register

No default value after res et

76543210

- - CHNB 1 CHNB 0 AINC INDX2 INDX1 INDX0

Bit Number Bit Mnemonic Des cription

7 - 6 - Reserved

The values read from these bits are indeterminate. Do not set these

bits.

5 - 4 CHNB3:0 Selection of Message Object Number

The available numbers are: 0 to 3(See Figure 33).

3AINC

Auto Increment of the Index (Active Low)

0 - auto-increment of the index (default value).

1 - non-a uto-increment of the index.

2 - 0 INDX2:0 Index

Byte location of the data field for the defined message object (See

Figure 33).

76543210

CONCH 1 CONCH 0 RPLV IDE DLC 3 DLC 2 DLC 1 DLC 0

Bit Number Bit Mnemonic Des cription

7 - 6 CONCH1:0

Configuration of Message Object

CONCH1 CONCH0

0 0: disable

0 1: Launch transmission

1 0: Ena bl e R ec ep tio n

1 1: Enable Reception Buffer

NOTE: The user must re-write the configuration to enable the

corres ponding bit in t he CANEN1:2 registers.

5RPLV

Reply valid

Used in the automatic reply mode after receiving a remote frame

0 - reply not ready.

1 - reply ready & valid.

4IDE

Identifier Extension

0 - C AN st andard rev 2.0 A (ident = 11 bits).

1 - C AN st andard rev 2.0 B (ident = 29 bits).

3 - 0 DLC3:0

Data Length Code

Number of Bytes in the data field of the message.

The range of DLC i s from 0 up to 8.

This value is updated when a frame is received (data or remote

frame).

If the expected DLC differs from the incoming DLC, a war ning

appears in the CANSTCH register.

T89C51CC02

4126F–CAN–12/03

Table 69. CANSTCH Register

CANSTC H (S:B2h) – CAN Message Object Status Register

Note: See Figure 35.

No default value after res et.

76543210

DLCW TXOK RXOK BERR SERR CERR FERR AERR

Bit Number Bit Mnemonic Des cription

7DLCW

Data Length Code Warning

Th e inc o mi ng mes s age do es n ot ha ve th e DLC ex pe cted.

Whatever the frame type, the DLC field of the CANCONCH register

is updated by the received DLC.

6TXOK

Transmit OK

The communication enabled by transmission is completed.

When the controller is ready to send a frame, if two or more

message objects are enabled a s producers , the lower index

message object (0 to 13) is suppli ed fir s t. Must be cl eared by

software.

This flag can generate an interrupt.

5RXOK

Receive OK

The communication enabled by reception is completed.

In the case of two or more message object reception hits, the lower

index message object (0 to 13) is updated first. Must be cleared by

software.

This flag can generate an interrupt.

4BERR

bit Error (only in transmission)

The bit value monitored is different from the bit value sent.

Exceptions:

the monitored recessive bit se nt as a dominant bit during the

arbitration field and the acknowledge slot detecting a dominant bit

during the sending of an error frame. Must be cleared by software.

This flag can generate an interrupt.

3SERR

Stuff Error

Detection of more than five consecutive bits with the same polarity.

Must be cleared by software.

This flag can generate an interrupt.

2CERR

CRC Error

The receiver performs a CRC check on each destuf fed received

message from the st art of frame up to the data field.

If t his checking does not mat ch with t he destuffed CRC field, a CRC

error is set. Must be cleared by software.

This flag can generate an interrupt.

1FERR

Form Error

The for m erro r results from one or more violations of the fixed form

in th e fol lo w in g bit fields :

CRC delimiter

acknowledgment delimiter

end_of_frame

Must be cleared by software.

This flag can generate an interrupt.

0AERR

Acknowledgment Error

No detect ion of the dominant bit in the acknowledge slot. Must be

cleared by software.

This flag can generate an interrupt.

T89C51CC02

4126F–CAN–12/03

Table 70. CANIDT1 Regist er for V2.0 part A

CANIDT1 for V2.0 part A (S:BCh) – CAN Identifier Tag Registers 1

No default value after res et.

Table 71. CANIDT2 Regist er for V2.0 part A

CANIDT2 for V2.0 p a rt A ( S:BDh) – CAN Ident ifier Tag Registers 2

No default value after res et.

Table 72. CANIDT3 Regist er for V2.0 part A

CANIDT3 for V2.0 part A (S:BEh) –CAN Identifier Tag Registers 3

No default value after res et.

76543210

IDT 10 IDT 9 IDT 8 IDT 7 IDT 6 IDT 5 IDT 4 IDT 3

Bit Number Bit Mnemonic Des cription

7 - 0 IDT10:3 IDentifier Tag Value

See Figure 39.

76543210

IDT 2 IDT 1 IDT 0 - - - - -

Bit Number Bit Mnemonic Des cription

7 - 5 IDT2:0 IDentifier Tag Value

See Figure 39.

4-0 - Reserved

The values read from these bits are indeterminate. Do not set these

bits.

76543210

--------

Bit Number Bit Mnemonic Des cription

7 - 0 - Reserved

The values read from these bits are indeterminate. Do not set these

bits.

T89C51CC02

4126F–CAN–12/03

Table 73. CANIDT1 for V2.0 part A

CANIDT4 for V2.0 p a r t A (S:BFh)

CAN Identifier Tag Registers 4

No default value after res et.

Table 74. CANIDT2Register for V2.0 part A

CANIDT1 for V2.0 Part B (S:BCh)

CAN Identifier Tag Registers 1

No default value after res et.

Table 75. CANIDT2 Regist er for V2.0 Part B

CANIDT2 for V2.0 Part B (S:BDh)

CAN Identifier Tag Registers 2

No default value after res et.

76543210

- - - - - RTRTAG - RB0TAG

Bit Number Bit Mnemonic Des cription

7 - 3 - Reserved

The values read from these bits are indeterminate. Do not set these

bits.

2 RTRTAG Remote transmission request tag value.

Reserved

The values read from this bit are indeterminate. Do not set these

bit.

0 RB0TAG Reserved bit 0 tag value.

76543210

IDT 28 IDT 27 IDT 26 IDT 25 IDT 24 IDT 23 IDT 22 IDT 21

Bit Number Bit Mnemonic Des cription

7 - 0 IDT28:21 IDentifier Tag Value

See Figure 39.

76543210

IDT 20 IDT 19 IDT 18 IDT 17 IDT 16 IDT 15 IDT 14 IDT 13

Bit Number Bit Mnemonic Des cription

7 - 0 IDT20:13 IDentifier Tag Value

See Figure 39.

T89C51CC02

4126F–CAN–12/03

Table 76. CANIDT3 Regist er for V2.0 Part B

CANIDT 3 for V2.0 Pa rt B (S :BEh )

CAN Identifier Tag Registers 3

No default value after res et.

Table 77. CANIDT4 Regist er for V2.0 Part B

CANIDT4 for V2.0 Part B (S:BFh)

CAN Identifier Tag Registers 4

No default value after res et.

76543210

IDT 12 IDT 11 IDT 10 IDT 9 IDT 8 IDT 7 IDT 6 IDT 5

Bit Number Bit Mnemonic Des cription

7 - 0 IDT12:5 IDentifier Tag Value

See Figure 39.

76543210

IDT 4 IDT 3 IDT 2 IDT 1 IDT 0 RTRTAG RB1TAG RB0TAG

Bit Number Bit Mnemonic Des cription

7 - 3 IDT4:0 IDentifier Tag Value

See Figure 39.

2RTRTAGRemote Transmission Request Tag Value

1 RB1TAG Reserv ed bit 1 tag value.

0 RB0TAG Reserved bit 0 tag value.

100

T89C51CC02

4126F–CAN–12/03

Table 78. CANIDM1 Register for V2.0 part A

CANIDM1 for V2.0 p a r t A (S:C4 h)

CAN Identifi er Mask Registe rs 1

No default value after res et.

Table 79. CANIDM2 Register for V2.0 part A

CANIDM2 for V2.0 p a r t A (S:C5 h)

CAN Identifi er Mask Registe rs 2

No default value after res et.

Table 80. CANIDM3 Register for V2.0 part A

CANIDM3 for V2.0 p a r t A (S:C6 h)

CAN Identifi er Mask Registe rs 3

No default value after res et.

76543210

IDMSK 10 IDMSK 9 IDMSK 8 IDMSK 7 IDMSK 6 IDMSK 5 IDMSK 4 IDMSK 3

Bit Number Bit Mnemonic Des cription

7 - 0 IDTMSK10:3

IDe ntif ier Mask Valu e

0 - comparison true forced .

1 - bit compar ison enabled.

See Figure 39.

76543210

IDMSK 2 IDMSK 1 IDMSK 0 - - - - -

Bit Number Bit Mnemonic Des cription

7 - 5 IDTMSK2:0

IDe ntif ier Mask Valu e

0 - comparison true forced .

1 - bit compar ison enabled.

See Figure 39.

4 -0 - Reserved

The values read from these bits are indeterminate. Do not set these

bits.

76543210

--------

Bit Number Bit Mnemonic Des cription

7 - 0 - Reserved

The values read from these bits are indeterminate.

101

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4126F–CAN–12/03

Table 81. CANIDM4 Register for V2.0 part A

CANIDM4 for V2.0 p a r t A (S:C7 h)

CAN Identifi er Mask Registe rs 4

Note: The ID Mask is only used for reception.

No default value after res et.

Table 82. CANIDM1 Register for V 2.0 Pa rt B

CANIDM1 for V 2.0 Part B (S :C4h)

CAN Identifi er Mask Registe rs 1

Note: The ID Mask is only used for reception.

No default value after res et.

76543210

- - - - - RTRMSK - IDEMSK

Bit Number Bit Mnemonic Des cription

7 - 3 - Reserved

The values read from these bits are indeterminate. Do not set these

bits.

2RTRMSK

Remote transmission reques t Mask Value

0 - comparison true forced .

1 - bit compar ison enabled.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

0IDEMSK

IDe ntif ier Exte ns ion Mask Va lue

0 - comparison true forced .

1 - bit compar ison enabled.

76543210

IDMSK 28 IDMSK 27 IDMSK 26 IDMSK 25 IDMSK 24 IDMSK 23 IDMSK 22 IDMSK 21

Bit Number Bit Mnemonic Des cription

7 - 0 IDMSK28:21

IDe ntif ier Mask Valu e

0 - comparison true forced .

1 - bit compar ison enabled.

See Figure 39.

102

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4126F–CAN–12/03

Table 83. CANIDM2 Register for V 2.0 Pa rt B

CANIDM2 for V 2.0 Part B (S :C5h)

CAN Identifi er Mask Registe rs 2

Note: 1. The ID Mask is only used for reception.

No default value after res et.

Table 84. CANIDM3 Register for V 2.0 Pa rt B

CANIDM3 for V 2.0 Part B (S :C6h)

CAN Identifi er Mask Registe rs 3

Note: The ID Mask is only used for reception.

No default value after res et.

76543210

IDMSK 20 IDMSK 19 IDMSK 18 IDMSK 17 IDMSK 16 IDMSK 15 IDMSK 14 IDMSK 13

Bit Number Bit Mnemonic Des cription

7 - 0 IDMSK20:13

IDe ntif ier Mask Valu e(1)

0 - comparison true forced .

1 - bit compar ison enabled.

See Figure 39.

76543210

IDMSK 12 IDMSK 11 IDMSK 10 IDMSK 9 IDMSK 8 IDMSK 7 IDMSK 6 IDMSK 5

Bit Number Bit Mnemonic Des cription

7 - 0 IDMSK12:5

IDe ntif ier Mask Valu e

0 - comparison true forced .

1 - bit compar ison enabled.

See Figure 39.

103

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4126F–CAN–12/03

Table 85. CANIDM4 Register for V 2.0 Pa rt B

CANIDM4 for V 2.0 Part B (S :C7h)

CAN Identifi er Mask Registe rs 4

Note: The ID Mask is only used for reception.

No default value after res et.

Table 86. CANMSG Regi ster

CANMSG (S:A3h)

CAN Messag e Data Register

No default value after res et.

76543210

IDMSK 4 IDMSK 3 IDMSK 2 IDMSK 1 IDMSK 0 RTRMSK - IDEMSK

Bit Number Bit Mnemonic Des cription

7 - 3 IDMSK4:0

IDe ntif ier Mask Valu e

0 - comparison true forced .

1 - bit compar ison enabled.

See Figure 39.

2RTRMSK

Remote transmission reques t Mask Value

0 - comparison true forced .

1 - bit compar ison enabled.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

0IDEMSK

IDe ntif ier Exte ns ion Mask Va lue

0 - comparison true forced .

1 - bit compar ison enabled.

76543210

MSG 7 MSG 6 MSG 5 MSG 4 MSG 3 MSG 2 MSG 1 MSG 0

Bit Number Bit Mnemonic Des cription

7 - 0 MSG7:0

Message D ata

This register contains the mailbox data byte pointed at the page

message object register.

After writing in the page message object register, this byte is equal

to the sp ec ified me ssag e locat io n (i n the ma ilbox) of th e p re-

defined identifier + index. If auto-incrementation is used, at the end

of the data register writing or reading cycle, the mailbox pointer is

auto-incremented. The range of the count ing is 8 with no end loop

(0, 1,..., 7, 0,...)

104

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Table 87. CANTCON Register

CANTCON (S:A1h)

CAN Timer ClockControl

Rese t Value = 00h

Table 88. CANTIMH Register

CANTIMH (S:ADh Read Only)

CAN Timer High

Rese t Value = 0000 0000b

Table 89. CANTIML Regi ster

CANTIML (S:ACh R ead Only)

CAN Timer Low

Rese t Value = 0000 0000b

76543210

TPRESC 7 TPRESC 6 TPRESC 5 TPRESC 4 TPRESC 3 TPRESC 2 TPRESC 1 TPRESC 0

Bit Number Bit Mnemonic Des cription

7 - 0 T PRESC7:0

Timer Prescaler of CAN Timer

This register is a prescaler for the main timer upper counter

range = 0 to 255.

See Figure 40.

76543210

CANGTIM

15 CANGTIM

14 CANGTIM

13 CANGTIM

12 CANGTIM

11 CANGTIM

10 CANGTIM

9CANGTIM

Bit Number Bit Mnemonic Des cription

7 - 0 CANGTIM15:8 High by te of M e ssage Timer

See Figure 40.

76543210

CANGTIM

7CANGTIM

6CANGTIM

5CANGTIM

4CANGTIM

3CANGTIM

2CANGTIM

1CANGTIM

Bit Number Bit Mnemonic Des cription

7 - 0 CANGTIM7:0 Low byte of Message Timer

See Figure 40.

105

T89C51CC02

4126F–CAN–12/03

Table 90. CANSTMPH Regi ster

CANSTMP H (S:AFh Read Onl y)

CAN Stamp Timer High

No default value after res et

Table 91. CANSTMPL Regi ster

CANSTMPL (S:AEh Read Only)

CAN Stamp Timer Low

No default value after res et

Table 92. CANTTCH Register

CANTTCH (S:A5h Read Onl y)

CAN TTC Timer High

Rese t Value = 0000 0000b

Table 93. CANTTCL Register

CANT TCL (S:A4h Read Only )

CAN TTC Timer Low

Rese t Value = 0000 0000b

76543210

TIMSTMP

15 TIMSTMP

14 TIMSTMP

13 TIMSTMP

12 TIMSTMP

11 TIMSTMP

10 T IMSTMP 9 TIMS TMP 8

Bit Number Bit Mnemonic Des cription

7 - 0 TIMSTMP15:8 High byte of T i me Stamp

See Figure 40.

76543210

TIMSTMP 7 TIMSTMP 6 TIMSTMP 5 TIMSTMP 4 TIMSTMP 3 TIMSTMP 2 TIMSTMP 1 TIMSTMP 0

Bit Number Bit Mnemonic Des cription

7 - 0 TIMSTMP7:0 Low byte of Time Stamp

See Figure 40.

76543210

TIMTTC 15 TIMTTC 14 TIMTTC 13 TIMTTC 12 TIMTTC 11 TIMTTC 10 TIMTTC 9 TIMTTC 8

Bit Number Bit Mnemonic Des cription

7 - 0 TIMTTC15:8 High byte of TTC Timer

See Figure 40.

76543210

TIMTTC 7 TIMTTC 6 TIMTTC 5 TIMTTC 4 TIMTTC 3 TIMTTC 2 TIMTTC 1 TIMTTC 0

Bit Number Bit Mnemonic Des cription

7 - 0 TIMTTC7:0 Low Byte of TTC Timer

See Figure 40.

106

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4126F–CAN–12/03

Programma ble

Counter Array (PCA) The PCA provides more timing capabilities with less CPU intervention than the standard

timer/c ounters. I ts advant ages include re duced s oftware ove rhead a nd impro ve d accu-

racy. The PCA con si sts of a dedic ated timer/count er which serves as the t ime base for

an array of two com pare/ca pture modu les. Its clock i nput can b e program med to co unt

any of the following signals:

• PCA clock frequency/6 (See “clock” section)

• PCA clock frequency/2

• Timer 0 overflow

• External input on ECI (P1.2)

Each compare/capture modules can be programmed in any one of the foll owing modes:

• Rising and/or falling edge capture,

• So ftware timer

• High-speed output

• Pulse width m odula t or

W hen the compare/ capture modul es are programm ed in capture mode , software timer,

or high speed output mode, an interrupt can be generated when the module executes its

function. Both modules and the PCA timer overf low share one interrupt vector.

The PCA timer/counter and compare/capture modules share Port 1 for external I/Os.

These pins are listed below. If the pin is not used for the P CA , it can still be used for

standard I /O.

PCA Timer The PCA timer is a common time base for both modules (See Figure 9). The timer count

source is determined from the CPS1 and CPS0 bits in the CMO D SF R (See Table 8)

and can be programm ed to run at:

• 1/6 the PCA clock frequency.

• 1/2 the PCA clock frequency.

• The Ti mer 0 overflow.

• The inp ut on the ECI pin (P 1.2).

PCA Component External I/O Pin

16-bit Counter P1.2/ECI

16-bit Module 0 P1.3/CEX0

16-bit Module 1 P1.4/CEX1

107

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4126F–CAN–12/03

Figu re 42. PCA Timer/Counter

The CMO D register includes three additional bits ass ociated with the PCA.

• The CIDL bit which allows the PCA to stop during idle mode.

• The ECF bit which when set causes an interrupt and the PCA overflow flag CF in

CCON register to be set when the PCA timer overflows.

The CCON register contains the run control bit for the PCA and the flags for the PCA

timer and each module.

• The CR bit must be set to run the PCA. The PCA is shut off by clearing this bi t.

• The CF bit is set when the PCA counter overflows and an interrupt will be generated

if the ECF b it in CMOD register is set. T he CF bit can only be cleared by software.

• The CCF0:1 bits are the flags for the modules (CCF0 for module0...) and are set by

hardware when either a match or a capture occurs. These flags also can be c leared

by software.

CIDL CPS1 CPS0 ECF

CH CL

16-bit up counter

To PCA

modules

FPca/6

FPca/2

T0 OVF

P1.2

Idle

CMOD

0xD9

CF CR CCON

0xD8

CCF1 CCF0

overflow

108

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4126F–CAN–12/03

PCA Modules Each one of the two compare/capture modules has six possible functions. It can

perform:

• 16-bit Capture, positive-edge triggered

• 16-bit Capture, negative-edge triggered

• 16-bit Capture, both positive and neg ative-edge triggered

• 16-bit Software Timer

• 16-bit High Speed Out put

• 8-bit Pulse Width Modulator.

Each m odu le in the P CA has a speci al f unction regi ster assoc iated with it (CCAPM 0 for

modu le 0 ...). The CCAPM0:1 reg isters contain the bits t hat control the mode that each

module will operat e in.

• The ECCF bit enables the CCF flag in the CCON register to generate an interrupt

when a match or compare occurs in the associated module.

• The PWM bi t enables the pulse width modulation mode.

• The TOG bit when set causes the CEX output associated with the module to toggle

when there is a match between the PCA counter and the module’s capture/compare

• The match bit MAT when set will cause the CCFn bit in the CCON register to be set

when there is a match between the PCA counter and the module’s capture/compare

• The two bits CAPN and CAPP in CCAPMn register determine the edge that a

capture input will be active on. The CAPN bit enables the negative edge, and the

CAPP bit enables the positive edge. If both bits are s et both edges will be enabled.

• The bit ECO M in CCAPM register when set enables the comparator function.

109

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4126F–CAN–12/03

PCA Interrupt

Figu re 43. PC A Inter r u p t Sy st e m

PCA Capture Mode T o use one of the PCA modul es in ca pture mode either one or bot h of the CCAPM bits

CAPN and CAPP for that module must be set. The external CEX input for the module

(on port 1) is sampled f or a transition. When a valid transition occurs the PCA ha rdware

loads the value of the PCA counter registers (CH and CL) into the module’s capture reg-

isters (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the

ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated.

Figu re 44. PCA Capture Mode

CF CR CCON

0xD8

CCF1 CCF0

Module 1

Module 0

PCA Time r/Co un ter

To Interrupt

IEN0.6 EA

IEN0.7

ECF

CMOD.0 ECCFn

CCAPMn.0

CEXn

n = 0, 1

PCA Counter

(8-bits) CL

(8-bits)

CCAPnH CCAPnL

CCFn

CCON Reg

PCA

Interrup

Reques

- 0CAPPnCAPNn000ECCFn

CCAPMn Register (n = 0, 1) 0

110

T89C51CC02

4126F–CAN–12/03

16-bit Software Timer

Mode The P CA modules can be used a s software timers by setting both the ECOM and MAT

bits in the modules CCAPMn regist er. Th e PCA timer will b e compared to the m odule’s

ca pture r egi ster s and w he n a m atch o ccurs an in terrup t wil l occu r if th e CC Fn (C CON

SF R) and the ECCFn (CCAPMn SFR) bits for the modu le are both set.

Figu re 45. PCA 16-bit Software Timer and High Speed Out put Mode

CCAPnL

(8 bits)

CCAPnH

(8 bits)

ECOMn0 0MATn TOGn0 ECCFn

70 CCAPMn Reg ister

(n = 0, 1)

(8 bits)

16-bit Comparator Match

Enable CCFn

CCON reg

PCA

Interrupt

Request

CEXn

Compare/Capture Module

PCA Counter

“0”

“1”

Reset

Write to

CCAPnL

Write to CCAPnH

For software Timer mode, set ECOMn and MA Tn.

F or high spee d out p ut mode , se t ECO M n , MATn and TOG n .

Toggle

(8 bits)

111

T89C51CC02

4126F–CAN–12/03

High Speed Output Mode In t his mode the CEX output (on port 1) associated with the PCA module will toggle

each time a match occurs between the PCA counter and the module’s capture registers.

To activate t his mode the TOG, MAT, and ECOM bits in the module’s CCAPM n SFR

must be set.

Figu re 46. PCA High Speed Output Mod e

Pulse Width Modulator

Mode Al l the PCA m odul es can b e used as PWM ou tput s. The out put freq uen cy dep ends on

the sou rce fo r the PCA timer. All the modules will have the same output frequency

because t hey all share the PC A t imer. The duty cycle of each mod ule is indep endent ly

va riab le u sing t he m odu le’ s ca pture r eg iste r CC APL n. W hen the value of the PCA C L

SF R is less t han the value in t he m odu le’s C CAPLn S FR the out put wi ll be l ow, when it

is equal to or greater than it, the output wi ll be high. When CL overflows from FF t o 00,

CCAPLn is reloaded with the value in CCAPHn. the allows the PWM to be updated with-

out glitches. The PWM and ECOM bits in the module’s CCAPMn register must be set to

enable th e PWM mo de.

CH CL

CCAPnH CCAPnL

ECOMn CC APMn, n = 0 to 1

0xDA to 0xDE

CAPNn MATn TOGn PWMn ECCFnCAPPn

16 bit comparator Match

CF CR CCON

0xD8

CCF1 CCF0

PCA IT

Enable

CEXn

PCA co unter/tim er

“1”“0”

Write to

CCAPnL

Reset

Write to

CCAPnH

112

T89C51CC02

4126F–CAN–12/03

Figu re 47. PCA PWM Mode

CL rolls over from FFh TO 00h loads

CCAPnH contents into CCAPnL

CCAPnL

CCAPnH

8-bit

Comparator

CL ( 8 bits )

“0”

“1”

CL < CCAPnL

CL >= CCAPnL CEX

PWMn

CCAPMn.1

ECOMn

CCAPMn.6

113

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4126F–CAN–12/03

PCA Registers Table 94. CMOD Register

CMOD (S:D9h)

PCA Count er Mode Register

Reset Value = 0X XX X000 b

76543210

CIDL - - - - CPS1 CPS0 ECF

Bit Number Bit

Mnemonic Description

7CIDL

PCA Counter Idle Control bit

Clear to let the PCA run during Idle mode.

Set to stop the PCA when Idle mode is invoked.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

2-1 CPS1:0

EWC Count Pulse Select bits

CPS1 CPS0 Cl oc k so u rce

0 0 Internal Clock, FPca/6

0 1 Internal Clock, FPca/2

1 0 Timer 0 overflow

1 1 External clock at ECI/P1.2 pin (Max. Rate = FPca/4)

0ECF

Enable PCA Coun t er Ove rf low Inte r rupt bit

Clear to disable C F bit in CCON register to generate an interrupt.

Set to enable CF bit in CCON register to generate an interrupt.

114

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4126F–CAN–12/03

Table 95. CCON Register

CCON (S:D8h)

PCA Count er Control Register

Rese t Value = 00xx xx00b

76543210

CF CR - - - - CCF1 CCF0

Bit Number Bit Mnemonic Descri ption

7CF

PCA Tim er/Cou nter Overflow flag

Set by har dware when the PCA Timer/Cou nter rolls over. This

generates a PCA interrupt request if the ECF bit in CMOD register

is set.

Must be cleare d by software.

6CR

PCA Timer/Counter Run Control bit

Clear to tur n the PCA Tim e r/C ount er off.

Set to turn the PCA Timer/Counter on.

5-2 - Reserved

The value re ad from the s e bist are i ndeterminate . D o not set these

bits.

1 CCF1

PC A Module 1 Compare/Ca pture Flag

Set by hardware when a match or capture occurs. This generates a

PCA interrupt request if the ECCF 1 bit in CCAPM 1 register is set.

Must be cleare d by software.

0 CCF0

PC A Module 0 Compare/Ca pture Flag

Set by hardware when a match or capture occurs. This generates a

PCA interrupt request if the ECCF 0 bit in CCAPM 0 register is set.

Must be cleare d by software.

115

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4126F–CAN–12/03

Table 96. CCAPnH Registers

CCAP0H (S:FAh)

CCAP1H (S:FBh)

PCA High Byte Com pare/C apture Module n Register (n=0..1)

Rese t Value = 0000 0000b

Table 97. CCAPnL Registers

CCAP0L (S:EAh)

CCAP1L (S:EBh)

PCA Low Byte Compa re/Cap ture Module n Register (n=0..1)

Rese t Value = 0000 0000b

76543210

CCAPnH 7 CCAPnH 6 CCAPnH 5 CCAPnH 4 CCAPnH 3 CCAPnH 2 CCAPnH 1 CCAPnH 0

Bit Number Bit Mnemonic Descri ption

7:0 CCAPnH 7:0 High byt e of EWC- PCA comparison or capture v alues

76543210

CCAPnL 7 CCAPnL 6 CCAPnL 5 CCAPnL 4 CCAPnL 3 CCAPnL 2 CCAPnL 1 CCAPnL 0

Bit Number Bit Mnemonic Descri ption

7:0 CCAPnL 7:0 Low byte of EWC-PCA comparis on or captu re values

116

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4126F–CAN–12/03

Table 98. CCAPMn Registers

CCAPM0 ( S:D Ah)

CCAPM1 ( S:D Bh)

PCA Comp are/Ca pture Module n Mode registers (n=0..1)

Rese t Value = X000 0000b

76543210

- ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

Bit Number Bit Mnemonic Descri ption

Reserved

The Value read from this bit is indeterminate. Do not set this bit.

6ECOMn

Enable Compar e Mode Mo dule x bit

Cle ar to di sable the Co mpa r e func t i on .

Set to enable the Compare fun c tion.

The Compare function is used to implement the software Timer , the

high-speed output, the Pulse Width Modulator (PWM) and the

W atc hdog Timer (WDT).

5 CAPPn

Capture Mode (Positive) Module x bit

Cle ar to di sable th e Capt u re fu nc tio n tri gg er e d by a positive edge

on CEXx pin.

Set to enable the Capture function triggered by a positive edge on

CEXx pin

4 CAPNn

Capture Mode (Negative) Module x bit

Cle ar to di sa ble t he Ca ptu r e func tion tri gg er e d by a nega t i ve edg e

on CEXx pin.

Set to enab le the Ca pture fun c tion tr iggered by a negative e dge on

CE Xx pin.

3MATn

Match Modu le x bit

Set when a match of the PCA Counter with the Compare/Capture

2 TOGn

Toggle Module x bit

The toggle mode is configured by setting ECOMx, MATx and TOGx

bits.

Set when a match of the PCA Counter with the Compare/Capture

1PWMn

Pulse Width Modulation Module x Mode bit

Set to configure the module x as an 8-bit Pulse W idth Modulator

with output waveform on CEXx pin.

0 ECCFn

Enable CCFx Interrupt bit

Clear to disable CCFx bit in CCON register to generate an interrupt

request.

Set to enable CCFx bit in CCON register to generate an interrupt

request.

117

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4126F–CAN–12/03

Table 99. CH Regist er

CH (S:F9h)

PCA Count er Register High value

Rese t Value = 0000 00000 b

Table 100. CL Register

CL (S:E9h)

PCA counte r Register Low value

Rese t Value = 0000 00000 b

76543210

CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0

Bit Number Bit Mnemonic Descri ption

7: 0 CH 7: 0 High by te of Time r/C o un ter

76543210

CL 7 CL 6 CL 5 CL 4 CL 3 CL 2 CL 1 CL 0

Bit Number Bit Mnemonic Descri ption

7:0 CL0 7: 0 Low byte of Ti mer/Counter

118

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4126F–CAN–12/03

Analog-to-Digital

Converter (ADC) This section describes the on-chip 10-bit analog-to-digital converter of the

T89C51CC02. Eight ADC channels are available for sampling of the external sources

AN0 t o AN7. An an alog mu ltiplexer allows the sin gle ADC convert er to s elect one fr om

the 8 ADC chan nels as AD C input voltag e (ADCIN). AD CIN is conve rte d by the 10 -bit-

cascaded potentiometric ADC.

Two modes of conversion are available:

- Standard conversion (8 bits).

- Precision conversion (10 bits).

Fo r the preci sion c onv ersio n, se t bit PSIDL E in A DC ON re gister a nd sta rt conv ersio n.

The device is in a pseudo-idle mode, the CPU does not run but the peripherals are

always run ning. This mode allows digital noise to be as low as possible, to ensure high

precision con version.

For this mode it is necessary to work with e nd of conversion interrupt, which is th e only

way to wake the device up.

If another interrupt occ urs during the precision c onvers ion, it will be served only after

this conversion is completed.

Features • 8 channels with multiplexed inputs

• 10-bit cascaded potentiometric ADC

• Conv ersion time 16 micro-seco nds (typ.)

• Zero Error (offset ) ± 2 LSB m ax

• Po sitive External Reference Voltage Range (VA REF) 2.4 to 3.0-volt (t yp.)

• ADC IN Range 0 to 3-volt

• Integral non-linearity typical 1 LSB, max. 2 LSB

• Differential non-linearity typical 0.5 LSB, max. 1 LS B

• Conv ersion Complete Flag or Conversion Complete Interrupt

• Selectable ADC Clock

ADC Port1 I/O Functions Port 1 pi ns are ge neral I/O tha t are shared w ith the A DC channel s. The cha nnel select

bit in ADCF register define whic h ADC channel/port1 pin will be used as ADCIN. The

remain ing ADC channel s/port1 pins c an be used as gen eral purpose I /O or as the alter-

nate function that is available.

A conversion launched on a channel which are not selected on ADCF register will not

have any effect.

VAREF V AREF should be connected to a low impedance point and must remain in the range

speci fied VAREF absolute maximum range (See section “AC-DC”).

. If the ADC is not used, it is recommended to tie VAREF to VAGND.

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Figu re 48. A DC Description

Figure 49 s hows the timing diagra m of a c omplete conversio n. For s implicity, the figure

depi cts th e wavefo rms in idea lized f orm and do not pro vide pre cise tim ing inf ormati on.

For ADC c haract eristics and timing parameters refer to the section “AC Characte ristics”

of this datasheet.

Figu re 49. Ti ming Diagram

Note: Tset up min, s ee the AC Parameter for A/D conversion.

Tconv = 11 clock ADC = 1sample and hold + 10-bit conversion

The user must ensure that Tsetup time bet ween setting ADEN and the st art of the fi rst conversion.

ADC Converte r

Operation A start of si ngle A/D convers ion is triggered by setting bit ADSST (ADCON.3).

After completion of the A/D conversion, the ADSST bit is cleared by hardware.

The end-of -conv ersion flag A DEO C (ADC ON.4) is se t when the va lue of convers ion is

available in A DDH and ADDL, it must be cleared by software. If the bit EADC (IEN1.1) is

s et, an i nterru pt occur w hen flag AD EO C is s et (S ee F igure 51). Cl ear th is fla g for r e-

arming the interrupt.

Note: Always leave Tsetup time before st arting a conversi on unless ADEN is perm anently high.

In this case one should wait Tsetup only befo re the first conversion

Rai

AN0/P1.0

AN1/P1.1

AN2/P1.2

AN3/P1.3

AN4/P1.4

AN5/P1.5

AN6/P1.6

AN7/P1.7

000

001

010

011

100

101

110

111

SCH2

ADCON.2 SCH0

ADCON.0

SCH1

ADCON.1

ADC

CLOCK

ADEN

ADCON.5 ADSST

ADCON.3

ADEOC

ADCON.4 ADC

Interrupt

Request

EADC

IEN1.1

CONTROL

AVSS

Sample and Hold

ADDH

VAREF

R/2R DAC

VAGND

-ADDL

SAR

ADCIN

Cai

ADEN

ADSST

ADEOC

TSETUP

TCONV

CLK

120

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Th e bits SC H0 to SC H2 in ADCON register are used for the analog input chan nel

selection.

Table 101. Selected Analog input

Voltage Conversion When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If

the input voltage equals VA GND, the ADC converts it to 000h. Input voltage between

VARE F and VAGND a re a straight-line linear conversio n. All other voltages will result in

3FFh if greater than VAREF and 000h if less than VAGND.

Note that ADCIN should not exceed VAREF absolute maximum range (See section

“AC-DC”).

Clock Selection T he ADC clock is t he same as CPU.

The m axim um c lock f reque nc y is define d in th e DC parme ter for A/D convert er. A pres-

caler is fe atured (ADCCLK) to generate the ADC cl ock from the oscillator frequency.

fADC = fcpu clock/ (4 (or 2 in X2 mode)* PRS )

Figu re 50. A/ D Converter Clock

ADC Standby Mode When t he ADC is no t u sed, it is pos sibl e to s et it in stan dby mode by clearing bit A DE N

in ADCON register. In this mode the power dissipation is reduced.

IT ADC management An interrup t end-o f-conversio n will occurs when the bit AD EOC is act ivated and t he bit

EADC is set. For re-arming the interrupt the bit ADEO C must be cleared by software.

SCH2 SCH1 SCH0 S elected Analog Input

000AN0

001AN1

010AN2

011AN3

100AN4

101AN5

110AN6

111AN7

Prescaler ADCLK A/D

Converter

ADC Clock

CPU

CLOCK

CPU Core Clock Symbol

÷ 2

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Fi gure 5 1. ADC interrupt struc ture

Routine Examples 1. Configure P1.2 and P1.3 in ADC channels

// configure channel P1.2 and P1.3 for ADC

ADCF = 0Ch

// Enable the ADC

ADCON = 20h

2. Start a standard conversion

// The variable ’channel’ contains the channel to convert

// The variable ’value_converted’ is an unsigned int

// Clear the field SCH[2:0]

ADCON &= F8h

// Select channel

ADCON |= channel

// Start conversion in standard mode

ADCON |= 08h

// Wait flag End of conversion

while((ADCON & 01h)!= 01h)

// Clear the End of conversion flag

ADCON &= EFh

// read the value

value_converted = (ADDH << 2)+(ADDL)

3. Start a precision conversion (need interrupt ADC)

// The variable ’channel’ contains the channel to convert

// Enable ADC

EADC = 1

// clear the field SCH[2:0]

ADCON &= F8h

// Select the channel

ADCON |= channel

// Start conversion in precision mode

ADCON |= 48h

Note: To enable the ADC interrupt: EA = 1

ADEOC

ADCON.2

EADC

IEN1.1

ADCI

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Registers Table 102. ADCF Register

ADCF (S:F6h)

ADC Configuration

Rese t Value = 0000 0000b

Table 103. ADCON Register

ADCON (S:F3h)

ADC Control Register

Rese t Value = X00 0 0000b

76543210

CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0

Bit

Number Bit

Mnemonic Description

7 - 0 CH 0:7 Cha nn el C onf igura t io n

Set to use P1.x as ADC input.

Clear to use P1.x as standart I/O port.

76543210

- PSIDLE ADEN ADEOC ADSST SCH2 SCH1 SCH0

Bit

Number Bit

Mnemonic Description

Reserved

The value read from these bits are inde terminate. Do not set these bits.

6 PSIDLE Pseudo Idle Mode (Best Precision)

Set to put in idle mode during conversion

Clear to convert without idle mode.

5ADEN

Enabl e/Stand by Mode

Set to enable ADC

Clear for Standb y mode.

4ADEOC

End Of Conversion

Set by hardware when ADC result is ready to be read. This flag can generate an

interrupt.

Must be cleared by software.

3 ADSST S tart and Stat us

Set to start an A/D conversion.

Cleared by hardware after comp letion of th e conversion

2-0 SCH2:0 Selection of Channel to Convert

See Table 101

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Table 104. ADCLK Register

ADCLK (S:F2h)

ADC Clock Prescaler

Rese t Value = XXX0 0000b

Table 105. ADDH Register

ADDH (S:F5h Read Only)

ADC Data High Byte R egister

Rese t Value = 00h

Table 106. ADDL Register

ADDL (S:F4h Read Only)

ADC Data Low Byte Register

Rese t Value = 00h

76543210

- - - PRS 4 PRS 3 PRS 2 PRS 1 PRS 0

Bit

Number Bit

Mnemonic Description

7 - 5 - Reserved

The value read from these bits are inde terminate. Do not set these bits.

4-0 PRS4:0 Clock Prescaler

Fadc = Fcpuclock/(4*PRS)) in X1 mode

Fadc=Fcpuclock/(2*PRS) in X2 mode

76543210

ADAT 9 ADAT 8 ADAT 7 ADAT 6 ADAT 5 ADAT 4 ADAT 3 ADA T 2

Bit

Number Bit

Mnemonic Description

7 - 0 ADAT9:2 ADC result

bit s 9-2

76543210

- - - - - - ADAT 1 ADAT 0

Bit

Number Bit

Mnemonic Description

7 - 2 - Reserved

The value read from these bits are inde terminate. Do not set these bits.

1-0 ADAT1:0 ADC result

bit s 1-0

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Inter r upt S yst em

Introduction The CAN Controller has a total of 10 interrupt vectors: two external interrupts (INT0 and

INT1), three timer interrupts (timers 0, 1 and 2), a s erial port interrupt, a PCA, a CAN

interrupt, a timer overrun interrupt and an ADC. These interrupts are shown below.

Figu re 52. I nterrupt Control System

ECAN

IEN1.0

EX0

IEN0.0

External

In terrupt 0

INT0#

IEN0.7

EX1

IEN0.2

External

In terrupt 1

INT1#

ET0

IEN0.1

Timer 0

IEN0.6

PCA

ET1

IEN0.3

Timer 1

IEN0.4

UART

EADC

IEN1.1

A to D

Converter

ETIM

IEN1.2

CAN Timer

CAN

Interrup t Enab le Lowe st Prio rity Int erru pt s

Highest

Priority Enable

Priority

Interrup

TxDC

RxDC

AIN1:0

IPH/L

Controller

Timer 2

ET2

IEN0.5

TxD

RxD

CEX0:1

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Each of the interrupt sources can be individually enabled or disabled by setting or clear-

ing a bit in the In terrupt E nable r egis ter. This re gister a lso cont ains a glo bal disa ble bit

which must be cleared to disable all the interrupts at the same time.

Each in terrupt source can also be individ ually programmed t o one of four priority levels

by setting or clearing a bit in the Inte rrup t Priority regist ers. The Table below shows the

bit values and priority levels associa ted with each combination.

Table 107. Priority Level bit Values

A l ow-priorit y i nterru pt can be inte rrupted by a high p rior ity interrupt but not b y another

low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt

source.

If two interrupt requests of different priority levels are received simultan eously, the

requ est o f the h igher p riori ty lev el is se rviced. If int errupt re qu ests o f the sa me pr iority

level are received simultaneously, an internal polling sequence determines which

r equ est is se rv iced . T hus wi thi n ea ch pri ority l evel th ere is a se co nd p rior it y str uc tur e

determined by the polling sequenc e, See Tabl e 10 8.

Table 108. Interrupt Priority Within Level

IPH.x IPL.x Interrupt Level Priority

0 0 0 (Lowe s t)

011

102

113 (Highest)

Interrupt Name Interrupt Address Vector Interrupt Number Polling Priority

Exte rna l in terr up t (IN T0) 000 3h 1 1

T imer0 (TF0) 000Bh 2 2

Exte rna l in terr up t (IN T1) 001 3h 3 3

T i mer 1 (TF1) 001Bh 4 4

PCA (CF or CCFn) 0033h 7 5

UART (RI or TI) 0023h 5 6

T i mer 2 (TF2) 002Bh 6 7

CAN (Txok, Rxok, Err or OvrB uf) 003Bh 8 8

ADC (ADCI) 0043h 9 9

CA N T imer Overfl ow (OVRTIM) 004Bh 10 10

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Registers Figure 53. IEN0 Register

IEN0 (S:A 8h)

Interrupt Enable Register

Rese t Value = 0000 0000b

bit addressable

76543210

EA EC ET2 ES ET1 EX1 ET0 EX0

Bit

Number Bit

Mnemonic Description

7EA

Enable All Interrupt bit

Clear to disable all interrupts.

Set to enable all interrupts.

If EA=1, each interrupt source is individually enabled or disabled by setting or

clearing its inter rupt enabl e bit.

6EC

PCA Interrupt Ena ble

Clear to disable the PCA interrupt.

Set to enable the PCA interrupt.

5ET2

Timer 2 Overflow Interrupt Enable bit

Clear to disable Timer 2 overflow interrupt.

Set to enable Timer 2 overflow interrupt.

4ES

Serial port Enable bit

Clear to disable serial port interrupt.

Set to enable ser ial port interrupt .

3ET1

Timer 1 Overflow Interrupt Enable bit

Clear to disable timer 1 overflow interrupt.

Set to enable timer 1 overflow interrupt.

2EX1

External Inte rr up t 1 Enable bit

Clear to disable external interrupt 1.

Set to enable external interrupt 1.

1ET0

Timer 0 Overflow Interrupt Enable bit

Clear to disable timer 0 overflow interrupt.

Set to enable timer 0 overflow interrupt.

0EX0

External Inte rr up t 0 Enable bit

Clear to disable external interrupt 0.

Set to enable external interrupt 0.

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Fi gure 5 4. IEN1 Regist er

IEN1 (S:E 8h)

Interrupt Enable Register

Reset Va lue = xxxx x00 0b

bit addressabl e

76543210

- - - - ETIM EADC ECAN

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

2ETIM

TImer overrun Interrupt Enable bit

Clear to disable the timer overrun interrupt.

Set to enable the timer overrun interrupt.

1 EADC ADC Interrupt Enable bit

Clear to disable the ADC interrupt.

Set to enable the ADC interrupt.

0ECAN

CAN Interrupt Enable bit

Clear to disable the CAN interrupt.

Set to enable the CAN interrupt.

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Table 109. IPL0 Register

IPL0 (S:B 8h)

Interrupt Enable Register

Rese t Value = X00 0 0000b

bit addressabl e

76543210

- PPC PT2 PS PT1 PX1 PT0 PX0

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6 PPC PCA Interrupt Priority bit

Re fer to PPCH for pri ori ty leve l

5PT2

Timer 2 Overflow Interrupt Priority bit

Re fer to PT2H for pri ori ty level.

4PS

Serial Port Priority bit

Re fer to PSH for pri ori ty level.

3PT1

Timer 1 Overflow Interrupt Priority bit

Re fer to PT1H for pri ori ty level.

2PX1

External Interrupt 1 Priority bit

Refer to PX1H for priority level.

1PT0

Timer 0 Overflow Interrupt Priority bit

Re fer to PT0H for pri ori ty level.

0PX0

External Interrupt 0 Priority bit

Refer to PX0H for priority level.

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Table 11 0. IPL1 Register

IPL1 (S:F8h )

Interrupt Priority Low Register 1

Reset Value = XXXX X000b

bit addressabl e

76543210

- - - - POVRL PADCL PCANL

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

2POVRL

Timer Overrun Interrupt Priority Level Less Significant bit

Refer to PI2CH for priority level.

1 PADCL ADC Interrupt Priority Level Less Significant bit

Refer to PSPIH for priority level.

0 PCANL CAN Interrupt Priority Level Less Significant bit

Refer to PKBH for priority level .

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Table 111. IPH0 Register

IPH0 (B7h)

Interrupt High Priority Register

Rese t Value = X00 0 0000b

76543210

- PPCH PT2H PSH PT1H PX1H PT0H PX0H

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6 PPCH

PCA Interrupt Priority Level Most Significant bit

PPCH PPC Priori ty lev el

00Lowest

1 1 Highest priority

5PT2H

Timer 2 Overflow Interrupt High Priority bit

PT2H PT2 Priority Level

00Lowest

1 1 Highest

4 PSH

Serial Port High Priority bit

PSH PS Priori ty Level

00Lowest

1 1 Highest

3PT1H

Timer 1 Overflow Interrupt High Priority bit

PT1H PT1 Priority Level

00Lowest

1 1 Highest

2PX1H

External Interrupt 1 High Priority bit

PX1H PX1 Prior i ty Level

00Lowest

1 1 Highest

1PT0H

Timer 0 Overflow Interrupt High Priority bit

PT0H PT0 Priority Level

00Lowest

1 1 Highest

0PX0H

External Interrupt 0 High Priority bit

PX0H PX0 Prior i ty Level

00Lowest

1 1 Highest

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Table 11 2. IPH1 Register

IPH1 (S:F7 h )

Interrupt high priority Register 1

Reset Value = XXXX X000b

76543210

- - - - POVRH PADCH PCANH

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

2POVRH

Timer Overrun Interrupt Priority Level Most Significant bit

POVRH POVRLPriority level

00Lowest

1 1 Highest

1 PADCH

ADC Interrupt Priority Level Most Significant bit

PADCH PADCLPr io rity lev e l

00Lowest

1 1 Highest

0 PCANH

CAN Interrupt Priority Level Most Significant bit

PCANH PCANLPriority level

00Lowest

1 1 Highest

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Electrical Characteristics

DC Parameters for

Standard Voltage

TA = -40°C to +85°C; VSS = 0 V; VCC = 3 vo lts to 5.5 volts; F = 0 to 40 MHz

Notes: 1. T ypicals are based on a li mited number of samp les and are not guaranteed. The values listed are at room temp erature.

2. Flash ret ention is guarant eed with the same formula for VCC min down to 0V.

3. Under steady state (non-transient) conditi ons, IOL must be externally limited as fol lows:

Maximum IOL per port pin : 10 mA

Ab solu te Maximum Rati ngs

I = industrial ............ ........................................... - 40°C t o 85°C

Sto r ag e Te m p e ra t ur e .... ..... ......... .......... ....... - 6 5°C to + 150°C

Voltage on VCC fr o m VSS .....................................-0.5V to + 6V

Voltage on Any Pin from V SS .....................-0.5V to VCC + 0. 2V

Power Dissipation ............................................................. 1 W

Note: Stresses at or above those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a st ress rating only and functi onal

operation of the device at these or any other condi-

tions above those indicated in the operational

sections of this specification is not im plied. Exposure

to absolute maximum rating conditions may affect

device reliability.

Power Dissipation value is based on the maximum

allowable die tem perature and the thermal resistance

of the package.

Table 113. DC Parameters in Standard Voltage

Symbol Parameter Min Typ(1) Max Unit Test Conditions

VIL Inpu t Low Vol tage -0.5 0 .2 Vc c - 0.1 V

VIH Input High Vol tage except XTAL1, RST 0.2 V CC + 0 .9 VCC + 0.5 V

VIH1(2) Input High Voltage, XTAL1, RST 0.7 VCC VCC + 0.5 V

VOL Output Low Vo ltage, por ts 1, 2, 3 and 4(3) 0.3

0.45

1.0

IOL = 100 µA

IOL = 1.6 mA

IOL = 3.5 mA

VOH Output High Voltage, ports 1, 2, 3, 4 and 5 VCC - 0.3

VCC - 0.7

VCC - 1.5

IOH = -10 µA

IOH = -30 µA

IOH = -60 µA

VCC = 5V ± 10%

RRST RST Pulldown Resistor 50 9 0 200 kΩ

IIL Logical 0 Input Current ports 1, 2, 3 and 4 -50 µA Vin = 0.45V

ILI Input Leakage Current ±10 µA0.45V < Vin < V

ITL L ogical 1 to 0 Transition Current, port s 1, 2, 3

and 4 -650 µA Vin = 2.0V

CIO Capacitance of I/O Buffer 10 pF Fc = 1 MHz

TA = 25°C

IPD Power-down Current 160 400 µA3V < V

CC < 5.5 V(4)

ICC

Power Supply Current

ICCOP(6) = 0.7 Freq (MHz) + 3 mA

ICCIDLE (5)= 0.6 Fr eq (MH z ) + 2 mA

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Maximum IOL per 8-bit port:

Ports 1, 2 and 3: 15 mA

Maximum total IOL for all output pins: 71 mA

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test conditions.

4. Power-down ICC is measured with all output pins disconnected; XTAL2 NC.; RST = VSS (See Figure 57. ).

5. Idle ICC is measured with all output pins disconnected; XTAL1 driven wit h TCLCH, TCHCL = 5 ns, V IL = VSS + 0.5V, VIH = VCC -

0.5V; XTAL2 N.C; RST = VSS (See Figure 56.).

6. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (See Figure 58.), VIL =

VSS + 0.5V, VIH = V CC - 0.5V; XTAL2 N.C.; RST = VCC. ICC would be slightly higher if a crystal oscillator used (See Figure

55.).

Fi gure 5 5. ICC Test Condition, Active Mode

Fi gure 5 6. ICC Test Condition, Idle Mode

VaVcc

VCC

ICC

(NC)

CLOCK

SIGNAL

VCC

All other pins are disconnecte

RST

XTAL2

XTAL1

VSS

VCC

VAGND

RST

XTAL2

XTAL1

VCC

ICC

(NC)

VaVcc

VCC

All other pins are disconnecte

CLOCK

SIGNAL

VSS

VAGND

134

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4126F–CAN–12/03

Fi gure 5 7. ICC Test Condition, Power-down Mode

Fi gure 5 8. Clock Signal Waveform for ICC Tests in Active and Idle Modes

DC Parameters for A/D

Converter Table 114. DC Parameters for AD Converter in P recision Conversion

Notes: 1. Typicals are based on a lim ited number of samples and are not guaranteed.

2. With ADC enabl ed.

VaVcc

RST

XTAL2

XTAL1

VSS

VCC

ICC

(NC)

VCC

All othe r pins ar e disconnected.

VAGND

VCC-0.5V

0.45V 0.7VCC

0.2VCC-0.1

TCLCH

TCHCL

TCLCH = TCHCL = 5ns.

Symbol Parameter Min Typ(1) Max Unit Test Conditions

AVin Analog input voltage Vss- 0.2 Max Vref

+ 0.6 V

VaV cc Ana lo g supply voltag e Vref Vcc Vcc +

10% V

Rref(2) Resistance between Varef and Vss 12 16 24 KΩ

Varef Reference voltage 2.40 3.00 V

Cai Analog input Capacitance 60 pF During sampling

Rai Ana lo g inp ut Re si stor 400 ΩDuring sampling

INL Integral non linearity 1 2 lsb

DNL Differential non linearity 0.5 1 lsb

OE Offset error -2 2 lsb

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AC Parameters

Serial Port Timing - Shift

Table 11 7. AC Parameters for a Va riable Clock

Symbol Parameter

TXLXL Serial port cloc k cycle time

TQVHX Output data set-up to clock rising edge

TXHQX Output data hold after clock rising edge

TXHDX Input data ho ld after c lock rising edge

TXHDV Clock rising edge to input data valid

Table 11 6. AC Parameters for a Fix Clock (F = 40 M Hz)

Symbol Min Max Units

TXLXL 300 ns

TQVHX 200 ns

TXHQX 30 ns

TXHDX 0ns

TXHDV 117 ns

Symbol Type Standard

Clock X2 Clock x parameter

for -M range Units

TXLXL Min 12 T 6 T ns

TQVHX Min 10 T - x 5 T - x 50 n s

TXHQX Min 2 T - x T - x 20 ns

TXHDX Min x x 0 ns

TXHDV Max 10 T - x 5 T - x 133 ns

136

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Shift Register Timing Wave form s

Externa l Clock Drive

Characteristics (XTAL1) Table 118. AC Parameters

Externa l Clock Drive

Waveforms

AC Testing Input/Output Waveforms

AC in puts during testin g are driven at VCC - 0.5 fo r a logic “1” and 0.45V fo r a logic “0”.

Timing m easurem ent are made at VIH min for a logic “1” and VIL max for a logic “0”.

Float Wavefor ms

VALID VALID VALIDVALID VALID

VALID

INPUT DATA VALID

0123456 87

CLOCK

OUTPUT DATA

WRITE to SBUF

CLEAR RI

TXLXL

TQVXH TXHQX

TXHDV TXHDX SET TI

SET RI

INSTRUCTION

01234567

VALID

Symbol Parameter Min Max Units

TCLCL Oscillator Peri od 25 ns

TCHCX High Time 5 ns

TCLCX Low Time 5 ns

TCLCH Rise Time 5 ns

TCHCL Fall Time 5 ns

TCHCX/TCLCX Cyclic ratio in X2 Mode 40 60 %

VCC-0.5V

0.45V

0.7VCC

0.2VCC-0.1

TCHCL TCLCX TCLCL

TCLCH

TCHCX

INPUT/OUTPUT 0.2 VCC + 0.9

0.2 VCC - 0.1

VCC -0.5V

0.45 V

FLOAT

VOH - 0.1V

VOL + 0.1V

VLOAD VLOAD + 0.1V

VLOAD - 0.1V

137

T89C51CC02

4126F–CAN–12/03

For t iming pu rposes a s port pi n is no lon ger float ing whe n a 100 m V c hang e from load

voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL lev el

occurs. IOL/IOH ≥ ± 20mA.

Clock Wavefor m s Valid in normal clock mode. In X2 Mode XTAL2 must be changed to XTAL2/2.

Flash Memory Table 119. Me mory AC Tim in g

Vcc = 3.0V to 5.5V, T A = - 40°C to +85°C

Fi gure 5 9. Flash Memory - I nternal B usy Waveforms

A/D Converter Table 120. AC Parameters for A/D Conversion

Symbol Parameter Min Typ Max Unit

TBHBL Flas h Internal Busy (Programming) Time 13 17 ms

NFCY Num ber of Flash Erase/ Wri te Cycles 100 000 cycles

TFDR Flash Data Retention Time 10 years

FBUSY bit TBHBL

Symbol Parameter Min Typ Max Unit

TSETUP 4µs

ADC Clock Frequency 700 KHz

138

T89C51CC02

4126F–CAN–12/03

Ordering Information

Factory default programming for T89C51CC02CA-xxxx is Bootloader CAN and

HSB = BBh:

• X1 mode

• BL JB = 0 : jump to Bootloader

• LB 2 = 0 : S ecurity Level 3.(1)

Factor y defaul t p rogram mi n g for T89C51CC02UA-xxxx is Bootl o ader UART and

HSB = BBh:

• X1 mode

• BL JB = 0 : jump to Bootloader

• LB 2 = 0 : S ecurity Level 3.(1)

Notes: 1. LB2 = 0 is not described in Table 22 Program load bi t. LB2 = 0 is equivalent to LB1 =

0: Security Level 3.

2. Customer can change these modes by re-programming with a parallel programmer,

this can be done by an Atmel distri butor .

Part Number Bootloader Temperature

Range Package Packing Product Marking

T89C51CC02CA-RATIM CAN(2) Industrial VQFP32 Tray 89C51CC02CA-IM

T89C51CC02CA-SISIM CAN(2) Industrial PLCC28 Stick 89C51CC02CA-IM

T89C51CC02CA-TDSIM CAN(2) Industrial SOIC24 Stick 89C51CC02CA-IM

T89C51CC02CA-TISIM CAN(2) Industrial SOIC28 Stick 89C51CC02CA-IM

T89C51CC02UA-RATIM UART(2) Industrial VQFP32 Tray 89C51CC02UA-IM

T89C51CC02UA-SISIM UART(2) Industrial PLCC28 Stick 89C51CC02UA-IM

T89C51CC02UA-TDSIM UART(2) Industrial SOIC24 Stick 89C51CC02UA-IM

T89C51CC02UA-TISIM UART(2) Industrial SOIC28 Stick 89C51CC02UA-IM

139

T89C51CC02

4126F–CAN–12/03

Pac kag e Dra win g s

VQFP32

140

T89C51CC02

4126F–CAN–12/03

PLCC28

141

T89C51CC02

4126F–CAN–12/03

SOIC24

142

T89C51CC02

4126F–CAN–12/03

SOIC28

143

T89C51CC02

4126F–CAN–12/03

Datasheet Change

Log for T89C51CC02

Changes from 4126C-

10/02 to 4126D-04/03 1. Changed the endurance of Flash to 100, 000 Wri te/Erase cycles.

2. A dded note on Flash retention formula for VIH1, in Se ction "D C Pa ra me ters for

Sta ndard Voltage ", page 141.Changes from 4129F -11/02 to 4129G-04/0 3

1. Changed the endurance of Flash to 100, 000 Write/Erase cycles.

2. A dded note on Flash retention formula for VIH1, in Se ction "D C Pa ra me ters for

Sta ndard Voltage ", page 141.

Changes from 4126D-

05/03 to 4126E - 10/03 1. Updated “Electrical Characteristics” on page 132.

2. Correc ted F igure 35 on page 75.

Changes from 4126E -

10/03 to 4126F - 12/03 1. Changed value of IPDMAX to 400, Section "A bsolute Ma ximu m Ratings" ,

page 132.

2. P CA , CPS0, register c orrect ion, Section "PCA Registers" , page 11 3.

3. Cross Mem ory section added. S ect ion "Operation Cross M em ory Access",

page 42.

Table of Contents
i
Table of 
Contents Features .................................................................................................1
Description ............................................................................................ 2
Block Diagram .......................................................................................2
Pin Configura tions .............. .......... ......... ............................ ...................3
Pin Descript ion... ......... ......... ............................ ..................................... 5
I/O Configurati o n s .............................................................................. ...................7
Port Structure............................................... ........................................................ 7
Read-Mo dify-W rite Instructions............................................................................ 8
Quas i Bi-directional Port Operation............. ............................ . .................. . ......... 8
SFR Mapping .......................................................................................10
Clock .................................................................................................... 16
Description ......................................................................................................... 16
Register.............................................................................................................. 19
Power Management ............................................................................20
Reset Pin  ..............................................................................................20
At Power-up (cold reset)..................................................................................... 20
During a Normal Operation (W arm Reset)......................................................... 21
Watch d og Res et... ........................................................... ................................... 21
Reset Recommendation to Prevent Flash Co rrup tion.........................................22
Idle Mode ............................................................................................................ 22
Power- d own Mod e ................................ ............................................................. 22
Registers .............................................................................................................24
Data Memory  .......................................................................................25
Internal Space .................................................................................................... 25
Dual Data Pointer............................................................................................... 27
Registers ............................................................................................................ 28
EEPROM Data Memory .......................................................................30
Write Data in the Column Latches...................................................................... 30
Programming...................................................................................................... 30
Read Data..... ........................................ ....................................................... ...... 30
Examples............................................................................................................ 31
Registers ............................................................................................................ 32

ii
Program/Co de Memory  ......................................................................33
Flash Memory Architecture ................................................................................ 33
Overview of FM0 Operations.............................................................................. 35
Registers ............................................................................................................ 41
Operation Cross Memory Access  .....................................................42
Sharing Instructions........................................................................... 43
In-System Programming (ISP) ...........................................................45
Flash  Pr ogra mming and Erasur e ... ........................................................... ......... 45
Boot Process...................................................................................................... 46
Application-Program ming-Interface.................................................................... 46
XROW Bytes................................ ...................................................................... 47
Hardware Cond itions... .................................... ................................................. .. 47
Hardware Se cu r ity Byte................................................. ..................................... 48
Serial I/O Port ......................................................................................49
 Framin g Error  Det e ction.......................... .......................................................... 49
Automatic Address Reco gnition......................................................................... 50
Given Address.................................................................................................... 50
Broadcast Address.................. ............ ......... ....... ............ ............ ............ ......... .. 51
Registers .............................................................................................................52
Timers/Counters .................................................................................55
Timer/Counter Operations.................................................................................. 55
Timer 0............ .............................................................................. ..................... 55
Timer 1............ .............................................................................. ..................... 57
Interrupt.............................................................................................................. 58
Registers ............................................................................................................ 59
Timer 2 .................................................................................................62
Auto- Re load Mode . .................................... ........................................................ 62
Programmable Clock-Output.............................................................................. 63
Registers ............................................................................................................ 64
Watchdog Timer ..................................................................................67
Watch d og Pro g r a mmin g... ................................................................ ...................68
Watchdo g Timer During Power-down Mode and Idle ......................69
Register.............................................................................................................. 69
CAN Controller .................................................................................... 71

Table of Contents
iii
CAN Controller Description................................................................................ 71
CAN Controller Mailbox and Registers Organization . ............. ................... ........ 72
CAN Controller Management .............................................................73
IT CAN Management.......................................................................................... 74
bit  Timing and Baud Ra te... ................................................................ ................ 76
Faul t Confinement.. .......................................................................... .................. 78
Accepta n ce  Fi lter.... ............................................................ ................................ 79
Data and Remot e Frame... ................... ..................... ................... ................... ... 80
Time Trigger Com m unication (TTC ) and Message Stam ping.................... ........ 81
CAN Autob aud and Listening M ode.............. .......................... ........................ ... 82
Routine  Exa mples .. .................................... ........................................................ 82
CAN SFRs.......................................................................................................... 85
Registers ............................................................................................................ 86
Programm able Counter Array (PCA) ...............................................106
PCA Timer........................................................................................................ 106
PCA Mod ules ................................................................................................... 108
PCA Interrupt.................................................................................................... 109
PCA Capture Mode .......................................................................................... 109
16-bit Software Ti mer Mode............................................................................. 110
High Speed Outp u t Mod e.................................... ............................................. 111
Pulse Wi dth Modula tor Mode ............................... . ....................... .................... 111
PCA Registers.................................................................................................. 113
Analog-to-Digital Converter (ADC) ..................................................118
Features........................................................................................................... 118
ADC Port1 I/O Functions.................................................................................. 118
VAREF ............................................................................................................. 118
ADC Converter O peration ................................................................................ 119
Vol ta g e Conve r sion.............................................................. ............................ 120
Clock Selection................................................................................................. 120
ADC Standby Mode.......................................................................................... 120
IT ADC management........................................................................................ 120
Routine  Exa mples .. .................................... ...................................................... 121
Registers ...........................................................................................................122
Interrupt System  ............................................................................... 124
Introduction....................................................................................................... 124
Registers .......................................................................................................... 126
Electrical Characteristics ................................................................. 132
Absolu te Maximum Ratings .............................................................................. 132

iv
DC Paramete rs for Standard Voltage............. ................ ................ .................. 132
DC Parameters for A/D Converter.................................................................... 134
AC Parameters................................................................................................. 135
Ordering Information........................................................................ 138
Package  Drawings............................................................................ 139
VQFP32 ............................................................................................................ 139
PLCC28............................................................................................................ 140
SOIC24............................................................................................................. 141
SOIC28............................................................................................................. 142
Datasheet Change Log for T89C51CC02........................................ 143
Changes  from 4126C - 10/02 to 4126D - 04/03............... ........................ ........ 143
Changes  from 4126D - 05/03 to 4126E - 10/03 . ..................... ......................... 143
Changes  from 4126E  - 10/03 to 4126F - 12/03.............. ............................ . ..... 143
Table of Contents ...................................................................................i

Pr inted o n rec ycled paper.

Disclaimer: A tmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard

warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibilit y for any

erro r s whic h m ay ap pear in this doc um ent, res er ve s th e r i gh t to c hange dev ic es or s pe ci fic at io ns d eta iled he r ei n at an y tim e w it hout no tice, and

does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are

gra nted by th e Co mpany in c on nect ion w ith th e sa le of Atme l p roduc ts, ex pre ssl y or by imp lica tio n. A tmel ’s pr oduc ts are n ot authorized for use

as c rit ic al c om po ne nts i n l ife s up po rt de vi ce s or sys tem s .

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4126F–CAN–12/03 /0M

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