IC42S32200 IC42S32200L Document Title 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM Revision History Revision No History Draft Date Remark 0A Initial Draft September 26,2002 Preliminary The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. DR036-0A 09/26/2002 1 IC42S32200 IC42S32200L 512K Words x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM FEATURES DESCRIPTION * Partial refresh * Concurrent auto precharge * Clock rate:200/166/143/125 MHz * Fully synchronous operation * Internal pipelined architecture * Four internal banks (512K x 32bit x 4bank) * Programmable Mode -CAS#Latency:2 or 3 -Burst Length:1,2,4,8,or full page -Burst Type:interleaved or linear burst -Burst-Read-Single-Write * Burst stop function * Individual byte controlled by DQM0-3 * Auto Refresh and Self Refresh * 4096 refresh cycles/64ms * Single +3.3V 0.3V power supply * Interface:LVTTL * Package:400 x 875 mil,86 Pin TSOP-2,0.50mm Pin Pitch and 11x13mm, 90 Ball BGA, Ball pitch 0.8mm * Pb-free package is available. The ICSI IC42S32200 and IC42S32200L is a high-speed CMOS configured as a quad 512K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal,CLK). Each of the 512K x 32 bit banks is organized as 2048 rows by 256 columns by 32 bits.Read and write accesses start at a selected locations in a programmed sequence. Accesses begin with the registration of a BankActive command which is then followed by a Read or Write command The ICSI IC42S32200 and IC42S32200L provides for programmable Read or Write burst lengths of 1,2,4,8,or full page, with a burst termination operation. An auto precharge function may be enable to provide a self-timed row precharge that is initiated at the end of the burst sequence.The refresh functions,either Auto or Self Refresh are easy to use. By having a programmable mode register,the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth. ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Circuit Solution Inc. 2 Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L FUNCTIONAL BLOCK DIAGRAM Row Decoder Column Decoder CLK CLOCK BUFFER 2048 X 256 X 32 C E L L A R R AY (BANK #0) Sense Amplifier Sense Amplifier CONTROL SIGNAL G E N E R AT O R CS# RAS# CAS# WE# COMMAND DECODER MODE REGISTER Row Decoder CKE 2048 X 256 X 32 C E L L A R R AY (BANK #1) Col um n Decoder COLUMN C O U N TE R A10/AP Row Decoder Column Decoder ADDRESS BUFFER A0 A9 BS0 BS1 2048 X 256 X 32 CELL ARRAY (BANK #2) Sense Amplifier REFRESH COUNTER DQ BUFFER Row DQ0 Decoder Sense D Q 31 Amplifier 2048 X 256 X 32 CELL ARRAY (BANK #3) Column Decoder DQM0~3 Integrated Circuit Solution Inc. DR036-0A 09/26/2002 3 IC42S32200 IC42S32200L PIN DESCRIPTIONS Table 1.Pin Details of IC42S32200 and IC42S32200L Symbol Type Description CLK Input Clock:CLK is driven by the system clock.All SDRAM input signals are sampled on the positive edge of CLK.CLK also increments the internal burst counter and controls the output registers. CKE Input Clock Enable:CKE activates(HIGH)and deactivates(LOW)the CLK signal.If CKE goes low synchronously with clock(set-up and hold time same as other inputs),the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low.When all banks are in the idle state,deactivating the clock controls the entry to the Power Down and Self Refresh modes.CKE is synchronous except after the device enters Power Down and Self Refresh modes,where CKE becomes asynchronous until exiting the same mode. The input buffers,including CLK,are disabled during Power Down and Self Refresh modes,providing low standby power. Bank Select:BS0 and BS1 defines to which bank the BankActivate,Read,Write,or BankPrecharge command is being applied.BS0, BS1 is used to program the partial refresh. Address Inputs:A0-A10 are sampled during the BankActivate command (row address A0-A10)and Read/Write command (column address A0-A7 with A10 defining Auto Precharge) to select one location out of the 256K available in the respective bank.During a Precharge command,A10 is sampled to determine if all banks are to be precharged (A10 =HIGH). BS0,BS1 Input A0-A10 Input The address inputs also provide the op-code during a Mode Register Set or Special Mode Register Set command. CS# Input Chip Select:CS#enables (sampled LOW)and disables (sampled HIGH)the command decoder.All commands are masked when CS#is sampled HIGH.CS#provides for external bank selection on systems with multiple banks.It is considered part of the command code. RAS# Input Row Address Strobe:The RAS#signal defines the operation commands in conjunction with the CAS#and WE#signals and is latched at the positive edges of CLK.When RAS# and CS#are asserted "LOW"and CAS#is asserted "HIGH,"either the BankActivate command or the Precharge command is selected by the WE#signal.When the WE#is asserted "HIGH,"the BankActivate command is selected and the bank designated by BS is turned on to the active state.When the WE#is asserted "LOW,"the Precharge command is selected and the bank designated by BS is switched to the idle state after the precharge operation. CAS# Input Column Address Strobe:The CAS#signal defines the operation commands in conjunction with the RAS#and WE#signals and is latched at the positive edges of CLK. When RAS#is held "HIGH"and CS#is asserted "LOW,"the column access is started by asserting CAS#"LOW."Then,the Read or Write command is selected by asserting WE# "LOW"or "HIGH." WE# Input Write Enable:The WE#signal defines the operation commands in conjunction with the RAS#and CAS#signals and is latched at the positive edges of CLK.The WE#input is used to select the BankActivate or Precharge command and Read or Write command. DQM0-3 Input Data Input/Output Mask:DQM0-DQM3 are byte specific,nonpersistent I/O buffer controls. The I/O buffers are placed in a high-z state when DQM is sampled HIGH.Input data is masked when DQM is sampled HIGH during a write cycle.Output data is masked (two-clock latency)when DQM is sampled HIGH during a read cycle.DQM3 masks DQ31-DQ24,DQM2 masks DQ23-DQ16,DQM1 masks DQ15-DQ8,and DQM0 masks DQ7-DQ0. DQ0-31 Input/Output Data I/O:The DQ0-31 input and output data are synchronized with the positive edges of CLK.The I/Os are byte-maskable during Reads and Writes. 4 Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L PIN FUNCTION NC - No Connect:These pins should be left unconnected. VDDQ Supply DQ Power:Provide isolated power to DQs for improved noise immunity. VSSQ Supply DQ Ground:Provide isolated ground to DQs for improved noise immunity. VDD Supply Power Supply:+3.3V 0.3V VSS Supply Ground PIN CONFIGURATIONS 86-Pin TSOP 2 90-Ball FBGA 1 2 3 7 8 9 A DQ26 DQ24 Vss VDD DQ23 DQ21 B DQ28 VDDQ VSSQ VDDQ VSSQ DQ19 C VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ D VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ E VDDQ DQ31 NC NC DQ16 VSSQ F VSS DQM3 A3 A2 DQM2 VDD G A4 A5 A6 A10 A0 A1 H A7 A8 NC NC BA1 NC J CLK CKE A9 BA0 CS RAS K DQM1 NC NC CAS WE DQM0 L VDDQ DQ8 VSS VDD DQ7 VSSQ M VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ N VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ P DQ11 VDDQ VSSQ VDDQ VSSQ DQ4 R DQ13 DQ15 VSS VDD DQ0 DQ2 Pin Assignment (Top View) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM 0 /WE /CAS /RAS /CS NC BS0 BS1 A10/AP A0 A1 A2 DQM 2 VDD NC DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS DQM1 NC NC CL K CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS Integrated Circuit Solution Inc. DR036-0A 09/26/2002 4 5 6 (Top View) 5 IC42S32200 IC42S32200L Operation Mode Fully synchronous operations are performed to latch the commands at the positive edges of CLK.Table 2 shows the truth table for the operation commands. Table 2.Truth Table (Note (1),(2)) Command State BankActivate Idle H X X V Row address L L H H BankPrecharge Any H X X V L X L L H L PrechargeAll Any H X X X H X Write Active (3) H X X V L Write and Auto Precharge Active (3) H X X V H Read Active (3) H X X V L Read and Autoprecharge Active (3) H X X V H Mode Register Set Idle H X X No-Operation Any H X X Burst Stop Active(4) H X X Device Deselect Any H X AutoRefresh Idle H H (3) CKEn-1 CKE DQM(6) BS0,1 A10 A9-0 CS# RAS# CAS# WE# L L H L Column address (A0 ~A7) L H L L L H L L Column address (A0 ~A7) L H L H L H L H OP code L L L L X X X L H H H X X X L H H L X X X X H X X X X X X X L L L H SelfRefresh Entry Idle H L X X X X L L L H SelfRefresh Exit Idle L H X X X X H X X X L H H H Clock Suspend Mode Entry Active H L X X X X X X X X Power Down Mode Entry H L X X X X H X X X L H H H (SelfRefresh) Any(5) Clock Suspend Mode Exit Active L H X X X X X X X X Power Down Mode Exit L H X X X X H X X X L H H H Data Write/Output Enable Active H X L X X X X X X X Data Mask/Output Disable Active H X H X X X X X X X Any (PowerDown) Note: 1. V =Valid,X =Don 't care,L =Logic low,H =Logic high 2. CKEn signal is input level when commands are provided. CKEn-1 signal is input level one clock cycle before the commands are provided. 3. These are states of bank designated by BS signal. 4. Device state is 1,2,4,8,and full page burst operation. 5. Power Down Mode can not enter in the burst operation. When this command is asserted in the burst cycle,device state is clock suspend mode. 6. DQM0-3 6 Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L Commands 1 BankActivate (RAS#="L",CAS#="H",WE#="H",BS =Bank,A0-A10 =Row Address) The BankActivate command activates the idle bank designated by the BS0,1 (Bank Select) signal.By latching the row address on A0 to A10 at the time of this command,the selected row access is initiated.The read or write operation in the same bank can occur after a time delay of tRCD(min.)from the time of bank activation.A subsequent BankActivate command to a different row in the same bank can only be issued after the previous active row has been precharged (refer to the following figure).The minimum time interval between successive BankActivate commands to the same bank is defined by tRC(min.).The SDRAM has four internal banks on the same chip and shares part of the internal circuitry to reduce chip area;therefore it restricts the back-to-back activation of the four banks.tRRD(min.)specifies the minimum time required between activating different banks. After this command is used,the Write command and the Block Write command perform the no mask write operation. T0 T1 T2 T3 Tn+3 CLK Tn+4 Tn+5 Tn+6 .............. ADDRESS Bank A Row Addr. Bank A Col Addr. .............. Bank B Row Addr. R/W A with AutoPrecharge .............. Bank B Activate RAS#- RAS# delay time (tRRD) RAS# - CAS# delay (tRCD) COMMAND Bank A Activate NOP NOP Bank A Row Addr . NOP NOP Bank A Activate RAS# Cycle time (tRC) :"H" or "L" Bank Auto Precharge Begin 2 Partial refresh: During MRS, use BS1/BS0 to set partial refresh mode so that only the selected bank(s) will be refreshed to save power. The other bank(s) not selected will never be rereshed. BA1/BA0=0/0 =>4 bank refresh. (All 4 bank 0/1/2/3 will be refreshed.) BA1/BA0=0/1 =>2 bank refresh. (Only banks 0/1 will be refreshed.) BA1/BA0=1/0, 1/1 =>1 bank refresh. (Only bank 0 will be reshed.) 3 BankPrecharge command (RAS#="L",CAS#="H",WE#="L",BS =Bank,A10 ="L",A0-A9 =Don 't care) The BankPrecharge command precharges the bank disignated by BS0,1 signal.The precharged bank is switched from the active state to the idle state.This command can be asserted anytime after tRAS(min.)is satisfied from the BankActivate command in the desired bank.The maximum time any bank can be active is specified by tRAS(max.).Therefore,the precharge function must be performed in any active bank within tRAS(max.).At the end of precharge,the precharged bank is still in the idle state and is ready to be activated again. Integrated Circuit Solution Inc. DR036-0A 09/26/2002 7 IC42S32200 IC42S32200L 8 4 PrechargeAll command (RAS#="L",CAS#="H",WE#="L",BS =Don t care,A10 ="H",A0-A9 =Don 't care) The PrechargeAll command precharges all the four banks simultaneously and can be issued even if all banks are not in the active state.All banks are then switched to the idle state. 5 Read command (RAS#="H",CAS#="L",WE#="H",BS =Bank,A10 ="L",A0-A7 =Column Address) The Read command is used to read a burst of data on consecutive clock cycles from an active row in an active bank.The bank must be active for at least tRCD(min.)before the Read command is issued.During read bursts,the valid data-out element from the starting column address will be available following the CAS#latency after the issue of the Read command.Each subsequent data- out element will be valid by the next positive clock edge (refer to the following figure).The DQs go into high-impedance at the end of the burst unless other command is initiated.The burst length,burst sequence,and CAS#latency are determined by the mode register which is already programmed.A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L T0 T1 READ A NOP T2 T3 T4 T5 T6 NOP NOP NOP DOUT A1 DOUT A2 T7 T8 CLK COMMAND NOP DOUT A0 CAS# latency=2 t CK2 , DQ s DOUT A0 CAS# latency=3 t CK3 , DQ s DOUT A1 NOP NOP NOP DOUT A3 DOUT A2 DOUT A3 Burst Read Operation(Burst Length =4,CAS#Latency =2,3) The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier (i.e.DQM latency is two clocks for output buffers).A read burst without the auto precharge function may be interrupted by a subsequent Read or Write command to the same bank or the other active bank before the end of the burst length.It may be interrupted by a BankPrecharge/PrechargeAll command to the same bank too.The interrupt coming from the Read command can occur on any clock cycle following a previous Read command (refer to the following figure). T0 T1 T2 T3 T4 NOP NOP DOUT B0 DOUT B1 T5 T6 NOP NOP T7 T8 CLK COMMAND READ A READ B CAS# latency=2 t CK2 , DQ s CAS# latency=3 t CK3 , DQ s NOP DOUT A0 DOUT A 0 DOUT B0 DOUT B2 DOUT B1 NOP NOP DOUT B3 DOUT B2 DOUT B3 Read Interrupted by a Read (Burst Length =4,CAS#Latency =2,3) The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from a Write command.The DQMs must be asserted (HIGH)at least two clocks prior to the Write command to suppress data-out on the DQ pins.To guarantee the DQ pins against I/O contention,a single cycle with high-impedance on the DQ pins must occur between the last read data and the Write command (refer to the following three figures).If the data output of the burst read occurs at the second clock of the burst write,the DQMs must be asserted (HIGH)at least one clock prior to the Write command to avoid internal bus contention. Integrated Circuit Solution Inc. DR036-0A 09/26/2002 9 IC42S32200 IC42S32200L T0 T1 T2 T3 T4 NOP NOP T5 T6 T7 T8 CLK DQM COMMAND NOP READ A DQs NOP NOP DOUT A WRITE B DINB 0 NOP DINB 1 NOP DINB 2 Must be Hi-Z before the Write Command : "H" or "L" Read to Write Interval (Burst Length = 4,CAS#Latency =3) T0 T1 T2 T3 T4 CLK T5 T6 T7 T8 1 Clk Interval DQM COMMAND NOP NOP BANKA ACTIVAT E NOP READ A WRITEA NOP DIN A0 DIN A1 CAS# latency=2 tCK2, DQS NOP NOP DIN A2 DIN A3 : "H" or "L" Read to Write Interval (Burst Length = 4,CAS#Latency =2) T0 T1 NOP NOP T2 T3 T4 T5 T6 T7 T8 CLK DQM COMMAND CAS# latency=2 t CK2 , DQs READ A NOP NOP WRITEB NOP DIN B0 DIN B1 NOP NOP DIN B2 DIN B3 : "H" or "L" Read to Write Interval (Burst Length = 4,CAS#Latency =2) A read burst without the auto precharge function may be interrupted by a BankPrecharge/ PrechargeAll command to the same bank.The following figure shows the optimum time that BankPrecharge/PrechargeAll command is issued in different CAS#latency. 10 Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK ADDRESS Bank, Col A Bank, Row Bank(s) tRP COMMAND READ A NOP CAS# latency=2 t CK2 , DQ s NOP DOUT A 0 CAS# latency=3 t CK3 , DQ s NOP Precharge NOP DOUT A 1 DOUT A 2 DOUT A 3 DOUT A 0 DOUT A 1 DOUT A 2 NOP Activate NOP DOUT A 3 Read to Precharge (CAS#Latency =2,3) 6 Write command (RAS#="H",CAS#="L",WE#="L",BS =Bank,A10 ="L",A0-A7 =Column Address) The Write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank.The bank must be active for at least tRCD(min.)before the Write command is issued.During write bursts, the first valid data-in element will be registered coincident with the Write command.Subsequent data elements will be registered on each successive positive clock edge (refer to the following figure).The DQs remain with highimpedance at the end of the burst unless another command is initiated.The burst length and burst sequence are determined by the mode register,which is already programmed.A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). T0 T1 T2 T3 T4 T5 T6 T7 T8 WRITEA I NOP NOP NOP NOP NOP NOP NOP DIN A 0 DIN A1 DIN A 2 DIN A 3 don't care CLK COMMAND DQ0 - DQ3 NOP The first data element and the write are registered on the same clock edge. Extra data is masked. Burst Write Operation (Burst Length =4,CAS#Latency =2,3) A write burst without the AutoPrecharge function may be interrupted by a subsequent Write, BankPrecharge/ PrechargeAll,or Read command before the end of the burst length.An interrupt coming from Write command can occur on any clock cycle following the previous Write command (refer to the following figure). Integrated Circuit Solution Inc. DR036-0A 09/26/2002 11 IC42S32200 IC42S32200L T0 T1 T2 T3 T4 T5 T6 T8 T7 CLK NOP COMMAND WRITEA WRITEB NOP NOP NOP DIN B1 DIN B2 DIN B3 NOP NOP NOP 1 Clk Interval DIN A0 DQ's DIN B0 Write Interrupted by a Write (Burst Length =4,CAS#Latency =2,3) The Read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock edge in which the last data-in element is registered.In order to avoid data contention,input data must be removed from the DQs at least one clock cycle before the first read data appears on the outputs (refer to the following figure).Once the Read command is registered,the data inputs will be ignored and writes will not be executed. T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK NOP COMMAND WRITEA NOP READ B CAS# latency=2 t CK2 , DQ's DIN A0 don't care CAS# latency=3 t CK3 , DQ's DIN A0 don't care NOP DOUT B0 DOUT B2 DOUT B1 DOUT B0 don't care Input data for the write is masked. NOP NOP NOP NOP DOUT B3 DOUT B1 DOUT B2 DOUT B3 Input data must be removed from the DQs at least one clock cycle before the Read data appears on the outputs to avoid data contention. DI N Write Interrupted by a Read (Burst Length =4,CAS#Latency =2,3) The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge function should be issued m cycles after the clock edge in which the last data-in element is registered,where m equals tWR/ tCK rounded up to the next whole number.In addition,the DQM signals must be used to mask input data,starting with the clock edge following the last data-in element and ending with the clock edge on which the BankPrecharge/ PrechargeAll command is entered (refer to the following figure). T0 T1 T2 T3 T4 T5 T6 Activate NOP CLK DQM t RP COMMAND WRITE ADDRESS BANK COL n NOP Precharge NOP NOP BANK (S) ROW t WR DIN n DQ n+1 : don t care Note:The DQMs can remain low in this example if the length of the write burst is 1 or 2. Write to Precharge 12 Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L 7 Concurrent Auto Precharge An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. ICIS SDRAMs support CONCURRENT AUTO PRECHARGE. Four cases where CONCURRENT AUTO PRECHARGE occurs are defined below. READ with Auto Precharge * Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is regis-tered. READ With Auto Precharge Interrupted by a READ T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND NOP BANK n Internal States READ - AP BANK n Page Active READ - AP BANK m NOP READ with Burst of 4 NOP NOP NOP NOP Idle Interrupt Burst, Precharge t RP - BANK m t RP - BANK n Page Active BANK m BANK n, COL a ADDRESS Precharge READ with Burst of 4 BANK m, COL d DOUT a+1 DOUT a DQ DOUT d DOUT d+1 CAS Latency = 3 (BANK n) CAS Latency = 3 (BANK m) NOTE: DQM is LOW. DON T CARE * Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered. READ With Auto Precharge Interrupted by a WRITE T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND BANK n Internal States READ - AP BANK n Page Active NOP NOP NOP WRITE - AP BANK m READ with Burst of 4 NOP NOP Interrupt Burst, Precharge Idle t RP - BANK n Page Active BANK m ADDRESS DQM NOP Write-Back WRITE with Burst of 4 BANK n, COL a t WR - BANK m BANK m, COL d 1 DOUT a DQ DIN d DIN d+1 DIN d+2 DIN d+3 CAS Latency = 3 (BANK n) NOTE: 1. DQM is HIGH at T2 to prevent D OUT-a+1 from contending with D IN-d at T4. DON'T CARE Integrated Circuit Solution Inc. DR036-0A 09/26/2002 13 IC42S32200 IC42S32200L WRITE with Auto Precharge * Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out ap- pearing CAS latency later. The PRECHARGE to bank n will begin after t WR is met, where t WR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. WRITE With Auto Precharge Interrupted by a READ T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND BANK n Internal States WRITE - AP BANK n NOP Page Active NOP READ - AP BANK m WRITE with Burst of 4 NOP NOP Interrupt Burst, Write-Back BANK m t RP - BANK m BANK m, COL d DIN a DQ Precharge READ with Burst of 4 BANK n, COL a ADDRESS NOP t RP - BANK n t WR - BANK n Page Active NOP DOUT d+1 DOUT d DIN a+1 CAS Latency = 3 (BANK m) NOTE: 1. DQM is LOW. DON'T CARE * Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on bank n when registered. The PRECHARGE to bank n will begin after t WR is met, where t WR begins when the WRITE to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m. WRITE With Auto Precharge Interrupted by a WRITE T0 COMMAND BANK n Internal States NOP Page Active T1 WRITE - AP BANK n T3 T4 T5 WRITE - AP BANK m NOP WRITE with Burst of 4 NOP Interrupt Burst, Write-Back t WR - BANK n BANK m ADDRESS Page Active NOTE: 1. DQM is LOW. T6 T7 NOP NOP Precharge t RP - BANK n t WR - BANK m Write-Back WRITE with Burst of 4 BANK n, COL a DIN a 14 T2 BANK m, COL d DIN a+1 DIN a+2 DIN d DIN d+1 DIN d+2 DIN d+3 DON'T CARE Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L 8 Mode Register Set command (RAS#="L",CAS#="L",WE#="L",BS0,1 and A10-A0 =Register Data) The mode register stores the data for controlling the various operating modes of SDRAM.The Mode Register Set command programs the values of CAS#latency,Addressing Mode and Burst Length in the Mode register to make SDRAM useful for a variety of different applications.The default values of the Mode Register after powerup are undefined;therefore this command must be issued at the power-up sequence.The state of pins BS0,1 and A10~A0 in the same cycle is the data written to the mode register.One clock cycle is required to complete the write in the mode register (refer to the following figure).The contents of the mode register can be changed using the same command and the clock cycle requirements during operation as long as all banks are in the idle state. Integrated Circuit Solution Inc. DR036-0A 09/26/2002 15 IC42S32200 IC42S32200L T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCK2 CKE Clock min. CS# RAS# CAS# WE# Address Key ADDR. DQM DQ tRP Hi-Z Precharge All Mode Register Set Command Any Command Mode Register Set Cycle The mode register is divided into various fields depending on functionality. Address BS0.1 Function Partial Refresh* * A10/Ap RFU** A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 WBL Test ModeCas Latency BT Burst Length *Please refer to "Partial Refresh" in Page 7. **Note:RFU (Reserved for future use)should stay 0 during MRS cycle. Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2, 4,8,or full page. 16 A2 0 0 0 A1 0 0 1 A0 0 1 0 Burst Length 1 2 4 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 8 Reserved Reserved Reserved Full Page Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L * Burst Type Field (A3) The Burst Type can be one of two modes,Interleave Mode or Sequential Mode. A3 0 1 Burst Type Sequential Interleave --Addressing Sequence of Sequential Mode An internal column address is performed by increasing the address from the column address which is input to the device.The internal column address is varied by the Burst Length as shown in the following table.When the value of column address,(n +m),in the table is larger than 255,only the least significant 8 bits are effective. Data n 0 1 2 3 4 5 6 7 - 255 256 257 - Column Address n n+1 n+2 n+3 n+4 n+5 n+6 n+7 - n+255 n n+1 - 2 words: Burst Length 4 words: 8 words: Full Page: Column address is repeated until terminated. * Addressing Sequence of Interleave Mode A column access is started in the input column address and is performed by inverting the address bits in the sequence shown in the following table. Data n Column Address Burst Length Data 0 Data 1 A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 A0# Data 2 Data 3 A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 A1# A1# A0 A0# Data 4 Data 5 A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2# A2# A1 A1 A0 A0# Data 6 Data 7 A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2# A2# A1# A1# A0 A0# 4 words 8 words * CAS#Latency Field (A6~A4) This field specifies the number of clock cycles from the assertion of the Read command to the first read data.The minimum whole value of CAS#Latency depends on the frequency of CLK.The minimum whole value satisfying the following formula must be programmed into this field. tCAC(min)<=CAS#Latency X tCK A6 0 0 0 0 1 A5 0 0 1 1 X A4 0 1 0 1 X CAS#Latency Reserved Reserved 2 clocks 3 clocks Reserved Integrated Circuit Solution Inc. DR036-0A 09/26/2002 17 IC42S32200 IC42S32200L * Test Mode field (A8~A7) These two bits are used to enter the test mode and must be programmed to "00"in normal operation. A8 0 0 1 A7 0 1 X Test Mode normal mode Vendor Use Only Vendor Use Only * Write Burst Length (A9) This bit is used to select the burst write length. A9 0 1 9 10 Write Burst Length Burst Single Bit No-Operation command (RAS#="H",CAS#="H",WE#="H") The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS# is Low).This prevents unwanted commands from being registered during idle or wait states. Burst Stop command (RAS#="H",CAS#="H",WE#="L") The Burst Stop command is used to terminate either fixed-length or full-page bursts.This command is only effective in a read/write burst without the auto precharge function.The terminated read burst ends after a delay equal to the CAS#latency (refer to the following figure).The termination of a write burst is shown in the following figure. Termination of a Burst Read Operation (Burst Length > 4,CAS#Latency =2,3) Termination of a Burst Write Operation (Burst Length =X) 18 Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L 11 12 13 14 15 16 17 Device Deselect command (CS#="H") The Device Deselect command disables the command decoder so that the RAS#,CAS#,WE# and Address inputs are ignored,regardless of whether the CLK is enabled.This command is similar to the No Operation command. AutoRefresh command (RAS#="L",CAS#="L",WE#="H",CKE ="H",BS0,1 =Don t care,A0-A10 =Don 't care) The AutoRefresh command is used during normal operation of the SDRAM and is analogous to CAS#-beforeRAS#(CBR)Refresh in conventional DRAMs.This command is non-persistent,so it must be issued each time a refresh is required.The addressing is generated by the internal refresh controller.This makes the address bits a "don 't care"during an AutoRefresh command.The internal refresh counter increments automatically on every auto refresh cycle to all of the rows.The refresh operation must be performed 4096 times within 64ms.The time required to complete the auto refresh operation is specified by tRC(min.).To provide the AutoRefresh command, all banks need to be in the idle state and the device must not be in power down mode (CKE is high in the previous cycle).This command must be followed by NOPs until the auto refresh operation is completed.The precharge time requirement,tRP(min),must be met before successive auto refresh operations are performed. SelfRefresh Entry command (RAS#="L",CAS#="L",WE#="H",CKE ="L",A0-A10 =Don 't care) The SelfRefresh is another refresh mode available in the SDRAM.It is the preferred refresh mode for data retention and low power operation.Once the SelfRefresh command is registered,all the inputs to the SDRAM become "don 't care"with the exception of CKE,which must remain LOW.The refresh addressing and timing is internally generated to reduce power consumption.The SDRAM may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited by restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command). SelfRefresh Exit command (CKE ="H",CS#="H"or CKE ="H",RAS#="H",CAS#="H",WE#="H") This command is used to exit from the SelfRefresh mode.Once this command is registered, NOP or Device Deselect commands must be issued for tRC(min.)because time is required for the completion of any bank currently being internally refreshed.If auto refresh cycles in bursts are performed during normal operation,a burst of 4096 auto refresh cycles should be completed just prior to entering and just after exiting the SelfRefresh mode. Clock Suspend Mode Entry /PowerDown Mode Entry command (CKE ="L") When the SDRAM is operating the burst cycle,the internal CLK is suspended(masked)from the subsequent cycle by issuing this command (asserting CKE "LOW").The device operation is held intact while CLK is suspended.On the other hand,when all banks are in the idle state,this command performs entry into the PowerDown mode.All input and output buffers (except the CKE buffer)are turned off in the PowerDown mode.The device may not remain in the Clock Suspend or PowerDown state longer than the refresh period (64ms)since the command does not perform any refresh operations. Clock Suspend Mode Exit /PowerDown Mode Exit command When the internal CLK has been suspended,the operation of the internal CLK is einitiated from the subsequent cycle by providing this command (asserting CKE "HIGH").When the device is in the PowerDown mode,the device exits this mode and all disabled buffers are turned on to the active state.tPDE(min.)is required when the device exits from the PowerDown mode.Any subsequent commands can be issued after one clock cycle from the end of this command. Data Write /Output Enable,Data Mask /Output Disable command (DQM ="L","H") During a write cycle,the DQM signal functions as a Data Mask and can control every word of the input data.During a read cycle,the DQM functions as the controller of output buffers.DQM is also used for device selection,byte selection and bus control in a memory system. Integrated Circuit Solution Inc. DR036-0A 09/26/2002 19 IC42S32200 IC42S32200L Absolute Maximum Rating Symbol VIN,VOUT VDD,VDDQ TOPR TSTG TSOLDER PD IOUT Item Input,Output Voltage Power Supply Operating Temperature Storage Temperature Soldering Temperature (10s) Power Dissipation Short Circuit Output Current Rating -0.3~VDD +0.3 -0.3~4.6 0~70 -55~150 260 1 50 Unit V V C C C W mA Note 1 1 1 1 1 1 1 Unit V V Note 2 2 Recommended D.C.Operating Conditions (Ta =0~70 C) Symbol VDD VDDQ Parameter Power Supply Voltage Power Supply Voltage(for I/O Buffer) Min. 3.0 3.0 Typ. 3.3 3.3 Max. 3.6 3.6 VIH VIL LVTTL Input High Voltage LVTTL Input Low Voltage 2.0 -0.3 VDDQ +0.3 0.8 Min. Max. 4.5 6.5 V V 2 2 Capacitance (VDD =3.3V,f =1MHz,Ta =25 C) Symbol CI CI/O Parameter Input Capacitance Input/Output Capacitance Unit pF pF Note:These parameters are periodically sampled and are not 100% tested. 20 Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L Recommended D.C.Operating Conditions (VDD =3.3V 0.3V,Ta =0~70 C) Description/Test condition Operating Current 1 bank tRC tRC(min), Outputs Open, Input operation signal one transition per one cycle Precharge Standby Current in power down mode tCK = 15ns, CKE VIL(max) Precharge Standby Current in power down mode tCK = , CKE VIL(max) Precharge Standby Current in non-power down mode tCK = 15ns, CS# VIH(min), CKE VIH nput signals are changed once during 30ns. Precharge Standby Current in non-power down mode tCK = , CLK VIL(max), CKE VIH Active Standby Current in power down mode C KE VIL(max), tCK = 15ns Active Standby Current in power down mode CKE& CLK VIL(max), tCK = Active Standby Current in non-power down mode CKE VIH(min), CS# VIH(min), tCK = 15ns Active Standby Current in non-power down mode CKE VIH(min), CLK VIL(max), tCK = Operating Current (Burst mode) tCK =tCK(min), Outputs Open, Multi-bank interleave Refresh Current tRC TrC(min) Self Refresh Current C KE 0.2V Symbol - 5/6/7/8 Max. ICC1 145/140/130/130 3 ICC2P 2 3 ICC2PS 2 ICC2N 20 ICC2NS 10 ICC3P 3 ICC3PS 3 ICC3N 30 ICC3NS 20 ICC4 225/200/180/150 3, 4 ICC5 220/200/180/160 3 ICC6 0.4 (L-Version) 1 Parameter Description IIL Input Leakage Current (0V VIN VDD, All other pins not under test = 0V ) VOH LVTTL Output "H" Level Voltage ( IOUT = -2mA ) LVTTL Output "L" Level Voltage ( IOUT = 2mA ) VOL Integrated Circuit Solution Inc. DR036-0A 09/26/2002 Min. -5 Unit Note 3 mA 3 3 Max. Unit Note +5 2.4 V 0.4 V 21 IC42S32200 IC42S32200L Electrical Characteristics and Recommended A.C.Operating Conditions (VDD =3.3V 0.3V,Ta =0~70 C)(Note:5,6,7,8) - 5/6/7/8 Symbol A.C. Parameter Min. 50/60/70/70 9 10/12/14/16 9 15/18/21/20 9 15/18/21/20 9 tCK2 Row cycle time (same bank) Row activate to row activate delay (different banks) RAS# to CAS# delay (same bank) Precharge to refresh/row activate command (same bank) Row activate to precharge time (same bank) Clock cycle time CL* = 2 tCK3 CL* = 3 tRC tRRD tRCD tRP tRAS tAC2 Access time from CLK CL* = 2 tAC3 (positive edge) CL* = 3 tOH Data output hold time tCH 35/42/49/48 Max. Unit 100,000 Note 9 - / - / - /10 ns 5/6/7/8 - / - / - /6 9 4.5/5.5/5.5/6 2/2/2.5/2.5 9 Clock high time 2/2/3/3 10 tCL Clock low time 2/2/3/3 10 tIS Data/Address/Control Input set-up time 1.5/1.5/1.75/2 10 tIH Data/Address/Control Input hold time 1 10 tLZ Data output low impedance 1 9 tHZ Data output high impedance tRDL Last data in to row precharge 2 tCCD CAS# to CAS# Delay time 1 tMRS Mode Register Set cycle time 2 4.5/5.5/5.5/6 8 CLK * CL is CAS# Latency. Note: 1. Stress greater than those listed under "Absolute Maximum Ratings"may cause permanent damage to the device. 2. All voltages are referenced to VSS. 3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC.Input signals are changed one time during tCK. 4. These parameters depend on the output loading.Specified values are obtained with the output open. 5. Power-up sequence is described in Note 11. 22 Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L 6. A.C.Test Conditions LVTTL Interface Reference Level of Output Signals Output Load Input Signal Levels Transition Time (Rise and Fall)of Input Signals Reference Level of Input Signals 1.4V /1.4V Reference to the Under Output Load (B) 2.4V /0.4V 1ns 1.4V 1.4V 3.3V 50 1.2k Output Output 30pF LVTTL D.C. Test Load (A) Z0=50 30pF 870 LVTTL A.C. Test Load (B) 7. 8. 9. 10. Transition times are measured between VIH and VIL.Transition(rise and fall)of input signals are in a fixed slope (1 ns). tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels. If clock rising time is longer than 1 ns,(tR /2 -0.5)ns should be added to the parameter. Assumed input rise and fall time tT (tR &tF )=1 ns If tR or tF is longer than 1 ns,transient time compensation should be considered,i.e.,[(tr +tf)/2 -1 ]ns should be added to the parameter. 11. Power up Sequence Power up must be performed in the following sequence. 1) Power must be applied to VDD and VDDQ(simultaneously)when all input signals are held "NOP"state and both CKE ="H"and DQM ="H."The CLK signals must be started at the same time. 2) After power-up,a pause of 200) seconds minimum is required.Then,it is recom mended that DQM is held "HIGH"(VDD levels)to ensure DQ output is in high impedance. 3) All banks must be precharged. 4) Mode Register Set command must be asserted to initialize the Mode register. 5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the device. Integrated Circuit Solution Inc. DR036-0A 09/26/2002 23 IC42S32200 IC42S32200L Timing Waveforms Figure 1.AC Parameters for Write Timing (Burst Length=4,CAS#Latency=2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCL tCH tCK2 tIS CKE tIS Begin Auto Precharge Bank A tIH Begin Auto Precharge Bank B tIS CS# RAS# CAS# WE# -5 , , -7 , x x BS0,1 tIH tIS ADDR. CAx RBx RBx CBx RAy RAz CAy RBy DQM tRCD tRC tDAL tIS DQ Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Activate Write with Activate Write with Activate Command Auto Precharge Command Auto Precharge Command Bank A Command Bank B Command Bank A Bank A Bank B 24 tWR tRP tIH Hi-Z Ay0 Write Command Bank A Ay1 Ay2 tRRD Ay3 Precharge Activate Command Command Bank A Bank A Activate Command Bank B Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L Figure 2.AC Parameters for Read Timing (Burst Length=2,CAS#Latency=2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CLK tCK2 tCH tCL CKE Begin AutoPrecharge Bank B tIS tIH tIH tIS CS# RAS# CAS# WE# BS0,1 tIH A10 RBx RAx RAy tIS A0-A9 RAx CAx CBx RBx tRRD RAy tRAS tRC DQM tAC2 tLZ tRCD Hi-Z DQ tAC2 Ax0 tRP tHZ Ax1 Bx0 t HZ t OH Activate Command Bank A Integrated Circuit Solution Inc. DR036-0A 09/26/2002 Read Command Bank A Activate Command Bank B Bx1 Read with Auto Precharge Command Bank B Precharge Command Bank A Activate Command Bank A 25 IC42S32200 IC42S32200L Figure 3.Auto Refresh (CBR)(Burst Length=4,CAS#Latency=2) 26 Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L Figure 4.Power on Sequene and Auto Refresh (CBR) Integrated Circuit Solution Inc. DR036-0A 09/26/2002 27 IC42S32200 IC42S32200L Figure 5.Self Refresh Entry &Exit Cycle Note:To Enter SelfRefresh Mode 1. CS#,RAS#&CAS#with CKE should be low at the same clock cycle. 2. After 1 clock cycle,all the inputs including the system clock can be don 't care except for CKE. 3. The device remains in SelfRefresh mode as long as CKE stays "low". Once the device enters SelfRefresh mode,minimum tRAS is required before exit from SelfRefresh. To Exit SelfRefresh Mode 1. System clock restart and be stable before returning CKE high. 2. Enable CKE and CKE should be set high for minimum time of tSRX. 3. CS#starts from high. 4. Minimum tRC is required after CKE going high to complete SelfRefresh exit. 5. 2048 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the system uses burst refresh. 28 Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L Figure 6.1.Clock Suspension During Burst Read (Using CKE) (Burst Length=4,CAS#Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx CAx DQM tHZ DQ Hi-Z Ax0 Activate Command Bank A Read Command Bank A Ax1 Clock Suspend 1 Cycle Ax2 Ax3 Clock Suspend 2 Cycle Clock Suspend 3 Cycle Note:CKE to CLK disable/enable =1 clock Integrated Circuit Solution Inc. DR036-0A 09/26/2002 29 IC42S32200 IC42S32200L Figure 6.2.Clock Suspension During Burst Read (Using CKE) (Burst Length=4,CAS#Latency=3) T0 T 1 T 2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE CS# RAS# CAS# WE# BS0,1 A10 A0-A9 RAx RAx CAx DQM tHZ DQ Hi-Z Ax0 Activate Command Bank A Read Command Bank A Ax1 Ax2 Clock Suspend Clock Suspend 1 Cycle 2 Cycle Ax3 Clock Suspend 3 Cycle Note:CKE to CLK disable/enable =1 clock 30 Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L Figure 7.1.Clock Suspension During Burst Write (Using CKE) (Burst Length=4,CAS#Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx CAx DQM DQ Hi-Z DAx0 Activate Command Bank A DAx1 DAx2 Clock Suspend Clock Suspend 1 Cycle 2 Cycle DAx3 Clock Suspend 3 Cycle Write Command Bank A Note:CKE to CLK disable/enable =1 clock Integrated Circuit Solution Inc. DR036-0A 09/26/2002 31 IC42S32200 IC42S32200L Figure 7.2.Clock Suspension During Burst Write (Using CKE) (Burst Length=4,CAS#Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE CS# RAS# CAS# WE# BS0,1 A10 A0-A9 RAx RAx CAx DQM DQ Hi-Z DAx0 Activate Command Bank A DAx1 DAx2 Clock Suspend Clock Suspend 2 Cycle 1 Cycle DAx3 Clock Suspend 3 Cycle Write Command Bank A Note:CKE to CLK disable/enable =1 clock 32 Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L Figure 8.Power Down Mode and Clock Mask (Burst Lenght=4, CAS#Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 tPDE t IS CKE Valid CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx CAx DQM t HZ Hi-Z Ax0 DQ ACTIVE STANDBY Read Activate Command Command Bank A Bank A Power Down Power Down Mode Exit Mode Entry Integrated Circuit Solution Inc. DR036-0A 09/26/2002 Ax1 Clock Mask Start Ax2 Clock Mask End Ax3 Precharge Command Bank A PRECHARGE STANDBY Power Down Mode Exit Any Command Power Down Mode Entry 33 IC42S32200 IC42S32200L Figure 9.1.Random Column Read (Page within same Bank) (Burst Length=4,CAS#Latency=2) 34 Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L Figure 9.2.Random Column Read (Page within same Bank) (Burst Length=4,CAS#Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAz RAw A0-A9 RAw CAw CAx RAz CAy CAz DQM Hi-Z Aw0 Aw1 Aw2 DQ Activate Command Bank A Read Command Bank A Integrated Circuit Solution Inc. DR036-0A 09/26/2002 Read Command Bank A Aw3 Read Command Bank A Ax0 Ax1 Ay0 Ay1 Precharge Command Bank A Ay2 Az0 Ay3 Activate Command Bank A Read Command Bank A 35 IC42S32200 IC42S32200L Figure 10.1.Random Column Write (Page within same Bank) (Burst Length=4,CAS#Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BS0,1 RBw A10 A0-A9 RBw RBz CBw CBx CBy RBz CBz DQM DQ Hi-Z Activate Command Bank A 36 DBz0 DBz1 DBz2 DBz3 DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 Write Command Bank A Write Command Bank B Write Command Bank B Precharge Command Bank B Activate Command Bank B Write Command Bank B Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L Figure 10.2.Random Column Write (Page within same Bank) (Burst Length=4,CAS#Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RBw A0-A9 RBw RBz CBw CBx CBy RBz CBz DQM Hi-Z DQ Activate Command Bank A Write Command Bank A Integrated Circuit Solution Inc. DR036-0A 09/26/2002 DBz0 DBz1 DBz2 DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 Write Command Bank B Write Command Bank B Precharge Command Bank B Activate Command Bank B Write Command Bank B 37 IC42S32200 IC42S32200L Figure 11.1.Random Row Read (Interleaving Banks) (Burst Length=8,CAS#Latency=2) 38 Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L Figure 11.2.Random Row Read (Interleaving Banks) (Burst Length=8,CAS#Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE High CS# RAS# CAS# WE# BS0,1 A10 A0-A9 RBx RBy RAx RBx RAx CBx tRCD RBy CAx tAC3 CBy tRP DQM DQ Hi-Z Bx0 Activate Command Bank B Read Command Bank B Integrated Circuit Solution Inc. DR036-0A 09/26/2002 Bx1 Bx2 Activate Command Bank A Bx3 Bx4 Bx5 Read Command Bank A Bx6 Bx7 Precharge Command Bank B Ax0 Ax1 Ax2 Activate Command Bank B Ax3 Ax4 Ax5 Read Command Bank B Ax6 Ax7 By0 Precharge Command Bank A 39 IC42S32200 IC42S32200L Figure 12.1.Random Row Write (Interleaving Banks) (Burst Length=8,CAS#Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx RAy RBx CAx RBx tRCD RAy CBx tWR* t RP CAy tWR* DQM DQ Hi-Z Activate Command Bank A DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 DAy4 Write Command Bank A Activate Command Bank B Write Command Bank B Precharge Command Bank A Activate Command Bank A Write Command Bank A Precharge Command Bank B * tWR > tWR(min.) 40 Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L Figure 12.2.Random Row Write (Interleaving Banks) (Burst Length=8,CAS#Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx RBx CAx RBx tRCD RAy RAy CBx tWR* tRP CAy tWR* DQM DQ Hi-Z Activate Command Bank A DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 Write Command Bank A Activate Command Bank B Write Command Bank B Precharge Command Bank A Activate Command Bank A Write Command Bank A Precharge Command Bank B * tWR > tWR(min.) Integrated Circuit Solution Inc. DR036-0A 09/26/2002 41 IC42S32200 IC42S32200L Figure 13.1.Read and Write Cycle (Burst Length=4,CAS#Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx CAx CAz CAy DQM DQ Hi-Z Ax0 Activate Command Bank A 42 Read Command Bank A Ax1 Ax2 Ax3 DAy0 DAy1 Write Command Bank A DAy3 The Write Data is Masked with a Zero Clock Latency Az0 Read Command Bank A Az1 Az3 The Read Data is Masked with a Two Clock Latency Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L Figure 13.2.Read and Write Cycle (Burst Length=4,CAS#Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx CAy CAx CAz DQM DQ Hi-Z Ax0 Activate Command Bank A Read Command Bank A Integrated Circuit Solution Inc. DR036-0A 09/26/2002 Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 Write The Write Data Command is Masked with a Bank A Zero Clock Latency Az0 Read Command Bank A Az1 Az3 The Read Data is Masked with a Two Clock Latency 43 IC42S32200 IC42S32200L Figure 14.1.Interleaving Column Read Cycle (Burst Length=4,CAS#Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx CAy tRCD DQM DQ RAx Hi-Z Read Command Bank A CBw CBx CBy Bw0 Bw1 Bx0 CBz CAy tAC2 Ax0 Activate Command Bank A 44 RAx Activate Command Bank B Ax1 Ax2 Read Command Bank B Ax3 Read Command Bank B Read Command Bank B Bx1 By0 Read Command Bank A By1 Ay0 Ay1 Bz0 Bz1 Read Command Bank B Precharge Command Bank A Bz2 Bz3 Precharge Command Bank B Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L Figure 14.2.Interleaved Column Read Cycle (Burst Length=4,CAS#Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx RBx CAx CBx CBz CBy CAy tAC3 tRCD DQM RBx DQ Hi-Z Ax0 Activate Command Bank A Read Command Bank A Activate Command Bank B Integrated Circuit Solution Inc. DR036-0A 09/26/2002 Ax1 Read Command Bank B Ax2 Ax3 Read Command Bank B Bx0 Bx1 Read Command Bank B By0 By1 Read Command Bank A Bz0 Bz1 Ay0 Precharge Command Bank B Ay1 Ay2 Ay3 Precharge Command Bank A 45 IC42S32200 IC42S32200L Figure 15.1.Interleaved Column Write Cycle (Burst Length=4,CAS#Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx RBw CAx RBw CBw CBx CBy CAy tRCD CBz tRP t WR tRP DQM tRRD Hi-Z DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3 DQ Activate Command Bank A 46 Write Command Bank A Activate Command Bank B Write Command Bank B Write Command Bank B Write Command Bank B Write Command Bank A Write Command Bank B Precharge Command Bank A Precharge Command Bank B Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L Figure 15.2.Interleaved Column Write Cycle (Burst Length=4,CAS#Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE CS# RAS# CAS# WE# BS0,1 A10 A0-A9 RAx RBw RAx CAx RBw CBw CBx CBy CAy tRCD DQM CBz tWR tRP tWR(min) tRRD > tRRD(min) DQ Hi-Z DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3 Activate Command Bank A Activate Command Bank B Write Command Bank A Integrated Circuit Solution Inc. DR036-0A 09/26/2002 Write Command Bank B Write Command Bank B Write Command Bank B Write Command Bank A Write Command Bank B Precharge Command Bank A Precharge Command Bank B 47 IC42S32200 IC42S32200L Figure 16.1.Auto Precharge after Read Burst (Burst Length=4,CAS#Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx RBx CAx RAz RBy RBx CBx Ax0 Ax1 Ax2 RAy RBy Bx1 Bx2 Bx3 Ay0 CBy RAz Ay2 Ay3 By0 CAz DQM DQ Hi-Z Activate Command Bank A 48 Read Command Bank A Activate Command Bank B Ax3 Read with Auto Precharge Command Bank B Bx0 Ay1 By1 By2 By3 Az0 Az1 Az2 Activate Activate Read with Read with Read with Auto Precharge Command Auto Precharge Command Auto Precharge Bank B Bank A Command Command Command Bank B Bank A Bank A Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L Figure 16.2.Auto Precharge after Read Burst (Burst Length=4,CAS#Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx RBy RBx CAx CBx RBx CAy CBy RBy DQM DQ Hi-Z Activate Command Bank A Ax0 Activate Command Bank B Read Command Bank A Integrated Circuit Solution Inc. DR036-0A 09/26/2002 Ax1 Ax2 Read with Auto Precharge Command Bank B Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Activate Command Bank B Read with Auto Precharge Command Bank A Ay1 Ay2 Ay3 By0 By1 By2 By3 Read with Auto Precharge Command Bank B 49 IC42S32200 IC42S32200L Figure 17.1.Auto Precharge after Write Burst (Burst Length=4,CAS#Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx RBx CAx RBx RAz RBy CBx CAy RBy CBy RAz CAz DQM DQ Hi-Z Activate Command Bank A DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3 Write Command Bank A Write with Activate Command Auto Precharge Bank B Command Bank B 50 Write with Auto Precharge Command Bank A DBy0 DBy1 DBy2 DBy3 DAz0 DAz1 DAz2 DAz3 Write with Write with Activate Activate Command Auto Precharge Command Auto Precharge Bank B Bank A Command Command Bank B Bank A Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L Figure 17.2.Auto Precharge after Write Burst (Burst Length=4,CAS#Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE High CS# RAS# CAS# WE# ` BS0,1 A9 RAx A0-A9 RAx RBx RBx CAx RBy CBx CAy RBy CBy DQM DQ Hi-Z Activate Command Bank A DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3 Activate Command Bank B Write Command Bank A Integrated Circuit Solution Inc. DR036-0A 09/26/2002 Write with Auto Precharge Command Bank B Write with Auto Precharge Command Bank A Activate Command Bank B DBy0 DBy1 DBy2 DBy3 Write with Auto Precharge Command Bank B 51 IC42S32200 IC42S32200L Figure 18.1.Full Page Read Cycle (Burst Length=Full Page,CAS#Latency=2) 52 Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L Figure 18.2.Full Page Read Cycle (Burst Length=Full Page,CAS#Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE High CS# RAS# CAS# WE# BS0,1 A10 A0-A9 RBx RAx RAx CAx RBy RBy CBx RBx tRP DQM DQ Hi-Z Ax Activate Command Bank A Read Command Bank A Integrated Circuit Solution Inc. DR036-0A 09/26/2002 Activate Command Bank B Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Read Command Full Page burst operation does not Bank B terminate when the burst length is satisfied; the burst counter The burst counter wraps increments and continues from the highest order page address back to zero bursting beginning with the starting address. during this time interval Precharge Command Bank B Activate Command Bank B Burst Stop Command 53 IC42S32200 IC42S32200L Figure 19.1.Full Page Write Cycle (Burst Length=Full Page,CAS#Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE High CS# RAS# CAS# WE# BS0,1 A10 A0-A9 RAx RAx RBx CAx RBy CBx RBx RBy DQM DQ Hi-Z Activate Command Bank A DAx DAx+1 DAx+2 DAx+3 DAx-1 Write Command Bank A DAx Activate Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval 54 DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+55DBx+6 Write Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. Data is ignored Precharge Command Bank B Activate Command Bank B Burst Stop Command Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L Figure 19.2.Full Page Write Cycle (Burst Length=Full Page,CAS#Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx RBy RBx CAx RBx RBy CBx DQM Data is ignored DQ Hi-Z Activate Command Bank A DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx Write Command Bank A Activate Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval Integrated Circuit Solution Inc. DR036-0A 09/26/2002 DAx+1 DBx DBx+1 DBx+3 DBx+4 DBx+5 Write Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. Precharge Command Bank B Activate Command Bank B Burst Stop Command 55 IC42S32200 IC42S32200L Figure 20.Byte Write Operation (Burst Length=4,CAS#Latency=2) 56 Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L Figure 21.Full Page Random Column Read (Burst Length=Full Page,CAS#Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RBx A0-A9 RAx RBx CAx RBw CBx CAy CBy CAz CBz RBw t RP DQM t RRD tRCD DQ Ax0 Activate Command Bank A Read Activate Command Bank B Command Bank B Read Command Bank A Integrated Circuit Solution Inc. DR036-0A 09/26/2002 Read Command Bank A Bx0 Ay0 Read Command Bank B Ay1 By0 Read Command Bank A By1 Az0 Az1 Read Command Bank B Az2 Bz0 Bz1 Bz2 Precharge Command Bank B (Precharge Temination) Activate Command Bank B 57 IC42S32200 IC42S32200L Figure 22.Full Page Random Column Write (Burst Length=Full Page,CAS#Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BS0,1 A10 A0-A9 RAx RBx RAx RBx RBw CAx CBx CAy CBy CAz CBz RBw t WR t RP DQM tRRD t RCD DQ DAx0 DBx0 DAy0 DAy1 DBy0 DBy1 DAz0 DAz1 DAz2 DBz0 DBz1 DBz2 Activate Command Bank A 58 Write Command Bank B Write Write Command Command Bank A Bank A Activate Command Bank B Write Command Bank B Write Command Bank A Write Command Bank B Precharge Command Bank B (Precharge Temination) Write Data is masked Activate Command Bank B Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L Figure 23.1.Precharge Termination of a Burst (Burst Length=8 or Full Page,CAS#Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High CS# RAS# CAS# WE# BS0,1 A10 A0-A9 RAx RAx RAz RAy CAx RAy RAz CAy tWR tRP CAz tRP tRP DQM DQ Ay0 DAx0 DAx1 DAx2 DAx3 Activate Command Bank A Write Command Bank A Precharge Command Bank A Precharge Termination of a Write Burst. Write data is masked. Integrated Circuit Solution Inc. DR036-0A 09/26/2002 Activate Command Bank A Read Command Bank A Ay1 Precharge Command Bank A Ay2 Activate Command Bank A Az0 Read Command Bank A Az1 Az2 Precharge Command Bank A Precharge Termination of a Read Burst. 59 IC42S32200 IC42S32200L Figure 23.2.Precharge Termination of a Burst (Burst Length=4,8 or Full Page,CAS#Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE High CS# RAS# CAS# WE# BS0,1 RAx A0-A9 RAx RAz RAy A10 RAy CAx t WR RAz CAy t RP tRP DQM DQ Activate Command Bank A Write Command Bank A Write Data is masked 60 Ay0 DAx0 DAx1 Precharge Command Bank A Activate Command Bank A Read Command Bank A Precharge Command Bank A Ay1 Ay2 Activate Command Bank A Precharge Termination of a Read Burst Precharge Termination of a Write Burst Integrated Circuit Solution Inc. DR036-0A 09/26/2002 IC42S32200 IC42S32200L ORDERING INFORMATION Commercial Range: 0C to 70C Frequency Speed (ns) 200MHz 200MHz 166MHz 166MHz 143MHz 143MHz 125MHz 125MHz 5 5 6 6 7 7 8 8 Order Part No. IC42S32200/L-5T IC42S32200/L-5B IC42S32200/L-6T IC42S32200/L-6B IC42S32200/L-7T IC42S32200/L-7B IC42S32200/L-8T IC42S32200/L-8B Package 400mil TSOP-2 11*13mm BGA 400mil TSOP-2 11*13mm BGA 400mil TSOP-2 11*13mm BGA 400mil TSOP-2 11*13mm BGA ORDERING INFORMATION Industrial Temperature Range: -40C to 85C Frequency Speed (ns) 200MHz 200MHz 166MHz 166MHz 143MHz 143MHz 125MHz 125MHz 5 5 6 6 7 7 8 8 Order Part No. IC42S32200/L-5TI IC42S32200/L-5BI IC42S32200/L-6TI IC42S32200/L-6BI IC42S32200/L-7TI IC42S32200/L-7BI IC42S32200/L-8TI IC42S32200/L-8BI Integrated Circuit Solution Inc. DR036-0A 09/26/2002 Package 400mil TSOP-2 11*13mm BGA 400mil TSOP-2 11*13mm BGA 400mil TSOP-2 11*13mm BGA 400mil TSOP-2 11*13mm BGA 61 IC42S32200 IC42S32200L ORDERING INFORMATION (Pb-free Package) Commercial Range: 0C to 70C Frequency Speed (ns) 200MHz 200MHz 166MHz 166MHz 143MHz 143MHz 125MHz 125MHz 5 5 6 6 7 7 8 8 Order Part No. IC42S32200/L-5TG IC42S32200/L-5BG IC42S32200/L-6TG IC42S32200/L-6BG IC42S32200/L-7TG IC42S32200/L-7BG IC42S32200/L-8TG IC42S32200/L-8BG Package 400mil TSOP-2 11*13mm BGA 400mil TSOP-2 11*13mm BGA 400mil TSOP-2 11*13mm BGA 400mil TSOP-2 11*13mm BGA ORDERING INFORMATION (Pb-free Package) Industrial Temperature Range: -40C to 85C Frequency Speed (ns) 200MHz 200MHz 166MHz 166MHz 143MHz 143MHz 125MHz 125MHz 5 5 6 6 7 7 8 8 Order Part No. Package IC42S32200/L-5TIG 400mil TSOP-2 IC42S32200/L-5BIG 11*13mm BGA IC42S32200/L-6TIG 400mil TSOP-2 IC42S32200/L-6BIG 11*13mm BGA IC42S32200/L-7TIG 400mil TSOP-2 IC42S32200/L-7BIG 11*13mm BGA IC42S32200/L-8TIG 400mil TSOP-2 IC42S32200/L-8BIG 11*13mm BGA Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw 62 Integrated Circuit Solution Inc. DR036-0A 09/26/2002