IL510/IL511/IL514/IL515/IL516
10
NVE Corporation 11409 Valley View Road, Eden Prairie, MN 55344-3617 Phone: (952) 829-9217 Fax: (952) 829-9189 www.IsoLoop.com ©NVE Corporation
Application Information
Electrostatic Discharge Sensitivity
This product has been tested for electrostatic sensitivity to the
limits stated in the specifications. However, NVE recommends that
all integrated circuits be handled with appropriate care to avoid
damage. Damage caused by inappropriate handling or storage could
range from performance degradation to complete failure.
Electromagnetic Compatibility
IsoLoop Isolators have the lowest EMC footprint of any isolation
technology. IsoLoop Isolators’ Wheatstone bridge configuration
and differential magnetic field signaling ensure excellent EMC
performance against all relevant standards.
Additionally, on the IL510 and IL515, the internal clock can be
disabled for even better EMC performance.
These isolators are fully compliant with generic EMC standards
EN50081, EN50082-1 and the umbrella line-voltage standard for
Information Technology Equipment (ITE) EN61000. NVE has
completed compliance tests in the categories below:
EN50081-1
Residential, Commercial & Light Industrial
Methods EN55022, EN55014
EN50082-2: Industrial Environment
Methods EN61000-4-2 (ESD), EN61000-4-3 (Electromagnetic
Field Immunity), EN61000-4-4 (Electrical Transient Immunity),
EN61000-4-6 (RFI Immunity), EN61000-4-8 (Power Frequency
Magnetic Field Immunity), EN61000-4-9 (Pulsed Magnetic
Field), EN61000-4-10 (Damped Oscillatory Magnetic Field)
ENV50204
Radiated Field from Digital Telephones (Immunity Test)
Immunity to external magnetic fields is even higher if the field
direction is “end-to-end” rather than to “pin-to-pin” as shown in the
diagram below:
Cross-axis Field Direction
Power Supply Decoupling
Both power supplies to these devices should be decoupled with low
ESR ceramic capacitors of at least 47 nF. Capacitors must be
located as close as possible to the VDD pins.
Maintaining Creepage
Creepage distances are often critical in isolated circuits. In addition to
meeting JEDEC standards, NVE isolator packages have unique creepage
specifications. Standard pad libraries often extend under the package,
compromising creepage and clearance. Similarly, ground planes, if used,
should be spaced to avoid compromising clearance. Package drawings
and recommended pad layouts are included in this datasheet.
Dynamic Power Consumption
IsoLoop Isolators achieve their low power consumption from the
way they transmit data across the isolation barrier. A magnetic field
is created around the GMR Wheatstone bridge by detecting the
edge transitions of the input logic signal and converting them to
narrow current pulses. Depending on the direction of the magnetic
field, the bridge causes the output comparator to switch following
the input logic signal. Since the current pulses are narrow, about
2.5 ns, the power consumption is independent of mark-to-space
ratio and solely dependent on frequency. This has obvious
advantages over optocouplers, which have power consumption
heavily dependent on mark-to-space ratio.
DC Correctness, EMC, and the SYNC Function
NVE digital isolators have the lowest EMC noise signature of any
high-speed digital isolator on the market today because of the dc
nature of the GMR sensors used. It is perhaps fair to include opto-
couplers in that dc category too, but their limited parametric
performance, physically large size, and wear-out problems
effectively limit side by side comparisons between NVE’s isolators
and isolators coupled with RF, matched capacitors, or transformers.
IL500-Series isolators has an internal refresh clock which ensure
the synchronization of input and output within 9 μs of the supply
passing the 1.5 V threshold. The IL510 and IL515 allow external
control of the refresh clock through the SYNC pin thereby further
lowering the EMC footprint. This can be advantageous in
applications such as hi-fi, motor control and power conversion.
The isolators can be used with Power on Reset (POR) circuits
common in microcontroller applications, as the means of ensuring
the output of the device is in the same state as the input a short time
after power up. Figure 1 shows a practical Power on Reset circuit:
POR
SET
OUT
SYNC
IN
1
2
3
4
8
6
5
IL510
V
OE
7
V
dd1
V
dd2
Fig. 1. Typical Power On Reset Circuit for IL510
After POR, the SYNC line goes high, the internal clock is disabled,
and the EMC signature is optimized. Decoupling capacitors are
omitted for clarity.