REFH OUT
REFH
Digital
(2.0 V to 5.5 V)
Analog
(7V to 18 V)
REFLAOLD
SCL
SDA
REFL OUT
OUT 18
OUT 17
DAC Registers
OUT 1
OUT 2
18 Output Channels plus
Two VCOM Channels
BUF20800-Q1
DAC Registers
DAC Registers
VCOM OUT1
VCOM OUT2
Control IFControl IF
BUF20800-Q1
www.ti.com
SBOS571 –AUGUST 2011
18-CHANNEL GAMMA VOLTAGE GENERATOR
WITH TWO PROGRAMMABLE V
COM
CHANNELS
Check for Samples: BUF20800-Q1
1FEATURES APPLICATIONS
2•Qualified for Automotive Applications •Replaces Resistor-Based Gamma Solutions
•18-Channel Gamma Correction •TFT-LCD Reference Drivers
•2-Channel Programmable VCOM: 50 mA IOUT •Dynamic Gamma Control
•10-Bit Resolution DESCRIPTION
•Rail-to-Rail Output The BUF20800-Q1 is a programmable voltage
•Low Supply Current: 900 μA/ch reference generator designed for gamma correction
•Supply Voltage: 7 V to 18 V in TFT-LCD panels. It provides 18 programmable
outputs for gamma correction and two channels for
•Digital Supply: 2.0 V to 5.5 V VCOM adjustment, each with 10-bit resolution.
•Industry-Standard, Two-Wire Interface: 3.4
MHz High-Speed Mode This programmability replaces the traditional, time
consuming process of changing resistor values to
•Demo Board and Software Available optimize the various gamma voltages and allows
designers to determine the correct gamma voltages
for a panel very quickly. Required changes can also
be easily implemented without hardware changes.
The BUF20800-Q1 uses TI’s latest, small-geometry
analog CMOS process, which makes it a very
competitive choice for full production, not just
evaluation.
Programming of each output occurs through an
industry standard, two-wire serial interface. Unlike
existing programmable buffers, the BUF20800-Q1
offers a high-speed mode that allows clock speeds up
to 3.4 MHz.
For lower channel count, please contact your local
sales or marketing representative.
The BUF20800-Q1 is available in an HTSSOP-38
PowerPAD™package. It is specified from −40°C to
+105°C.
RELATED PRODUCTS
FEATURES PRODUCT
18-Channel Programmable, Two VCOM + OTP Memory BUF20820
12-Channel Programmable Buffer, 10-Bit BUF12800
Programmable VCOM BUF01900
11-, 6-, 4-Channel Gamma Correction Buffer, 18V BUFxx704
Supply
High-Speed VCOM, 1 and 2 Channels SN10501
Complete LCD DC/DC Solution TPS65100
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright ©2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
BUF20800-Q1
SBOS571 –AUGUST 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT PACKAGE PACKAGE DESIGNATOR PACKAGE MARKING
BUF20800-Q1 HTSSOP-38 DCP BUF20800Q
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted).
PARAMETER VALUE UNIT
VSSupply voltage 19 V
VSD Supply voltage 6 V
Voltage –0.5 to 6 V
Signal input terminals, SCL, SDA, AO, LD Current ±10 mA
Output Short-Circuit(2) Continuous
TAOperating temperature –40 to +105 °C
Tstg Storage temperature –65 to +150 °C
TJJunction temperature 125 °C
Latch-up per JESD78B Class 1
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) Short-circuit to ground, one channel at a time.
2Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
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BUF20800-Q1
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SBOS571 –AUGUST 2011
ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, TA=–40°C to +105°C.
At TA= 25°C, VS= 18 V, VSD = 5 V, RL= 1.5 kΩconnected to ground, and CL= 200 pF, unless otherwise noted.
BUF20800-Q1
PARAMETER CONDITIONS MIN TYP MAX UNIT
ANALOG
OUT 1−9, Sourcing 10 mA, VREFH = 17.8 V, Code 1023 17.7 17.8
Gamma Output Swing: High V
OUT 10−18, Sourcing 10 mA, VREFH = 17.8 V, Code 1023 17.0 17.2
OUT 1−9, Sinking 10 mA, VREFL = 0.2 V, Code 00 0.6 1.0
Gamma Output Swing: Low V
OUT 10−18, Sinking 10 mA, VREFL = 0.2 V, Code 00 0.2 0.3
VCOM Buffer Output Swing: High VCOM, Sourcing 50 mA, VREFH = 17.8 V 13 15.5 V
VCOM Buffer Output Swing: Low VCOM, Sinking 50 mA, VREFL = 0.2 V 1 2.0 V
Output Current(1) IOAll Channels, Code 512, Sinking/Sourcing 40 45 mA
REFH Input Range(2) 4 VSV
REFL Input Range(2) GND VS- 4 V
Integral Nonlinearity INL No Load, VREFH = 17 V, VREFL = 1 V 0.3 1.5 Bits
Differential Nonlinearity DNL No Load, VREFH = 17 V, VREFL = 1 V 0.3 1 Bits
Gain Error 0.12 %
Program to Out Delay tD5μs
Output Accuracy No Load, VREFH = 17 V, VREFL = 1 V ±20 ±50 mV
Over Temperature ±25 mV
Input Resistance at VREFH and RINH 100 MΩ
VREFL
Load Regulation, All References REG VOUT = VS/2, IOUT = 5 mA to –5 mA Step 0.5 1.5 mV/mA
40 mA, All Channels VOUT = VS/2, ISINKING = 40 mA, ISOURCING = 40 mA 0.5 1.5 mV/mA
ANALOG POWER SUPPLY
Operating Range VS7 18 V
Total Analog Supply Current ISNo Load 18 28 mA
Over Temperature 28 mA
DIGITAL
Logic 1 Input Voltage VIH 0.7 ×VSD V
Logic 0 Input Voltage VIL 0.3 ×VSD V
Logic 0 Output Voltage VOL ISINK = 3 mA 0.15 0.4 V
Input Leakage ±0.01 ±10 μA
Clock Frequency fCLK Standard/Fast Mode 400 kHz
High-Speed Mode 3.4 MHz
DIGITAL POWER SUPPLY
Operating Range VSD 2.0 5.5 V
Digital Supply Current(3) ISD Outputs at Reset Values, No Load, Two-Wire Bus Inactive 25 50 μA
Over Temperature 100 μA
TEMPERATURE RANGE
Operating Temperature Range Junction Temperature <+125°C–40 +105 °C
Storage Temperature Range –65 +150 °C
Thermal Resistance, HTSSOP-38
Junction-to-Ambient θJA 30 °C/W
Junction-to-Case θJC 15 °C/W
(1) See typical characteristic graph Output Voltage vs Output Current.
(2) See application information section REFH and REFL Input Range.
(3) See typical characteristic graph Digital Supply Current vs Temperature.
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): BUF20800-Q1
VCOM OUT2
REFH
NC(1)
NC(1)
OUT 1
OUT 2
OUT 3
OUT 4
OUT 5
OUT 6
GNDA(2)
VS
OUT 7
OUT 8
OUT 9
REFH OUT
VSD
SCL
SDA
VCOM OUT1
REFL
NC(1)
NC(1)
REFL OUT
OUT 18
OUT 17
OUT 16
OUT 15
OUT 14
GNDA(2)
VS
OUT 13
OUT 12
OUT 11
OUT 10
GNDD(2)
LD
AO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
PowerPAD
LeadFrame
Die Pad
Exposed on
Underside
BUF20800-Q1
SBOS571 –AUGUST 2011
www.ti.com
PIN CONFIGURATION
BUF20800-Q1
HTSSOP-38
(TOP VIEW)
(1) NC denotes no connection
(2) GNDDand GNDAare internally connected and must be at the same voltage potential.
4Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): BUF20800-Q1
16
14
12
10
8
6
4
2
0
Analog IQ(mA)
−40 −20 402010 60 80 100
Temperature ( C)°
VS= 18V
VS= 10V
−40 −20 402010 60 80 100
Temperature ( C)°
30
25
20
15
10
5
0
Digital IQ(mA)
VS= 3. 3 V
VS= 5V
Output Voltage (5V/div)
Time (1ms/div)
REFH =17V
REFL =1V
Code 3FF →
000
Code 000 →
3FF
0
10 403020 50 60 70 80 90 100
18
17
16
15
3
2
1
0
Output Voltage (V)
Output Current (mA)
OUT19, V COM12 (sinking)
Code =000h
VREF L = 1V, V
REF H = 17..8V
RLOAD
OUT1018 (sourcing), Code =3FFh
VREFL REFH = 17 V
RLOAD Connected to GND
OUT1018 (sin king) , Code =000 h
VREFL REFH = 17V
RLOAD Connected to 18V
OUT19, V COM12 (sourcing)
Code =3FFh
VREFL= 1 V, V
REFH = 17..8V
RLOAD Connected to GND
Connected to 18V
= 0.2 V, V
= 0.2 V, V
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
INL Error (LSB)
0 200 400 600 800 1000
Input Code
0 200 400 600 800 1000
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
DNL Error (LSB)
Input Code
BUF20800-Q1
www.ti.com
SBOS571 –AUGUST 2011
TYPICAL CHARACTERISTICS
At TA= 25°C, VS= 18 V, VSD = 5 V, VREFH = 17 V, VREFL = 1V, RL= 1.5 kΩconnected to ground, and CL= 200pF, unless
otherwise noted.
ANALOG SUPPLY CURRENT vs TEMPERATURE DIGITAL SUPPLY CURRENT vs TEMPERATURE
Figure 1. Figure 2.
FULL−SCALE OUTPUT SWING OUTPUT VOLTAGE vs OUTPUT CURRENT
Figure 3. Figure 4.
INTEGRAL NONLINEARITY ERROR vs INPUT CODE DIFFERENTIAL NONLINEARITY ERROR vs INPUT CODE
Figure 5. Figure 6.
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): BUF20800-Q1
BUF20800-Q1
SBOS571 –AUGUST 2011
www.ti.com
APPLICATION INFORMATION
The BUF20800-Q1 programmable voltage reference allows fast, easy adjustment of 18 programmable reference
outputs and two channels for VCOM adjustment, each with 10-bit resolution. It offers very simple, time-efficient
adjustment of the gamma reference and VCOM voltages. The BUF20800-Q1 is programmed through a
high-speed, standard, two-wire interface. The BUF20800-Q1 features a double-register structure for each DAC
channel to simplify the implementation of dynamic gamma control. This structure allows pre-loading of register
data and rapid updating of all channels simultaneously.
Buffers 1−9 are able to swing to within 200mV of the positive supply rail, and to within 0.6V of the negative
supply rail. Buffers 10−18 are able to swing to within 0.8V of the positive supply rail and to within 200mV of the
negative supply rail.
The BUF20800-Q1 can be powered using an analog supply voltage from 7V to 18V, and a digital supply from 2V
to 5.5V. The digital supply must be applied prior to or simultaneously with the analog supply to avoid excessive
current and power consumption; damage to the device may occur if it is left connected only to the analog supply
for extended periods of time. Figure 7 shows the power supply timing requirements.
Figure 7. Power Supply Timing Requirements
Figure 8 shows the BUF20800-Q1 in a typical configuration. In this configuration, the BUF20800-Q1 device
address is 74h. The output of each digital-to-analog converter (DAC) is immediately updated as soon as data are
received in the corresponding register (LD = 0).
For maximum dynamic range, set VREFH = VS−0.2 V and VREFL = GND + 0.2 V.
TWO-WIRE BUS OVERVIEW
The BUF20800-Q1 communicates through an industry standard, two-wire interface to receive data in slave
mode. This standard uses a two-wire, open-drain interface that supports multiple devices on a single bus. Bus
lines are driven to a logic low level only. The device that initiates the communication is called a master, and the
devices controlled by the master are slaves. The master generates the serial clock on the clock signal line (SCL),
controls the bus access, and generates the START and STOP conditions.
To address a specific device, the master initiates a START condition by pulling the data signal line (SDA) from a
HIGH to a LOW logic level while SCL is HIGH. All slaves on the bus shift in the slave address byte, with the last
bit indicating whether a read or write operation is intended. During the 9th clock pulse, the slave being addressed
responds to the master by generating an Acknowledge and pulling SDA LOW.
Data transfer is then initiated and eight bits of data are sent followed by an Acknowledge Bit. During data
transfer, SDA must remain stable while SCL is HIGH. Any change in SDA while SCL is HIGH will be interpreted
as a START or STOP condition.
Once all data has been transferred, the master generates a STOP condition indicated by pulling SDA from LOW
to HIGH while SCL is HIGH.
The BUF20800-Q1 can act only as a slave device; therefore, it never drives SCL. SCL is only an input for the
BUF20800-Q1. Table 1 and Table 2 summarize the address and command codes, respectively, for the
BUF20800-Q1.
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Product Folder Link(s): BUF20800-Q1
BUF20800-Q1
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SBOS571 –AUGUST 2011
ADDRESSING THE BUF20800-Q1
The address of the BUF20800-Q1 is 111010x, where x is the state of the A0 pin. When the A0 pin is LOW, the
device will acknowledge on address 74h (1110100). If the A0 pin is HIGH, the device will acknowledge on
address 75h (1110101).
Other valid addresses are possible through a simple mask change. Contact your TI representative for
information.
Table 1. Quick-Reference Table of BUF20800-Q1
Addresses
DEVICE/COMPONENT
BUF20800-Q1 Address: ADDRESS
A0 pin is LOW 1110100
(device acknowledges on address 74h)
A0 pin is HIGH 1110101
(device acknowledges on address 75h)
Table 2. Quick-Reference Table of Command Codes
COMMAND CODE
General Call Reset Address byte of 00h followed by a data byte of
06h.
High-Speed Mode 00001xxx, with SCL ≤400kHz; where xxx are
bits unique to the Hs-capable master. This byte
is called the Hs master code.
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): BUF20800-Q1
(1) RC combination optional.
(2) GNDAand GNDDmust be connected together.
(3) Connecting a capacitor to this node is not recommended.
VCOM OUT2
REFH (3)
NC
NC
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
GNDA(2)
VS
OUT7
OUT8
OUT9
REFH OUT
VSD
SCL
SDA
VCOM OUT1
REFL(3)
NC
NC
REFL OUT
OUT18
OUT17
OUT16
OUT15
OUT14
GNDA(2)
VS
OUT13
OUT12
OUT11
OUT10
GNDD(2)
LD
AO
BUF20800-Q1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
VCOM1 VCOM2
VS
VS
VS
(1)
(1)
(1)
(1)
(1)
Timing
Controller
3.3V
100nF
1mF
(1)
(1)
(1)
(1)
100nF 10mF
Source
Driver
Source
Driver
VS
(1)
(1)
(1)(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
100nF 10mF
Source
Driver
Source
Driver
BUF20800-Q1
SBOS571 –AUGUST 2011
www.ti.com
Figure 8. Typical Application Configuration
8Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): BUF20800-Q1
REFH REFL
OUT REFL
V V
V =[ Decimal Value of Code]+ V
1024
-´
BUF20800-Q1
www.ti.com
SBOS571 –AUGUST 2011
DATA RATES
The two-wire bus operates in one of three speed modes:
•Standard: allows a clock frequency of up to 100kHz;
•Fast: allows a clock frequency of up to 400kHz; and
•High-speed mode (also called Hs mode): allows a clock frequency of up to 3.4MHz.
The BUF20800-Q1 is fully compatible with all three modes. No special action is required to use the device in
Standard or Fast modes, but High-speed mode must be activated. To activate High-speed mode, send a special
address byte of 00001xxx, with SCL = 400kHz, following the START condition; xxx are bits unique to the
Hs-capable master, which can be any value. This byte is called the Hs master code. (Note that this is different
from normal address bytes—the low bit does not indicate read/write status.) The BUF20800-Q1 will respond to
the High-speed command regardless of the value of these last three bits. The BUF20800-Q1 will not
acknowledge this byte; the communication protocol prohibits acknowledgment of the Hs master code. On
receiving a master code, the BUF20800-Q1 will switch on its Hs mode filters, and communicate at up to 3.4MHz.
Additional high-speed transfers may be initiated without resending the Hs mode byte by generating a repeat
START without a STOP. The BUF20800-Q1 will switch out of Hs mode with the next STOP condition.
GENERAL-CALL RESET AND POWER-UP
The BUF20800-Q1 responds to a General Call Reset, which is an address byte of 00h (0000 0000) followed by a
data byte of 06h (0000 0110). The BUF20800-Q1 acknowledges both bytes. Upon receiving a General Call
Reset, the BUF20800-Q1 performs a full internal reset, as though it had been powered off and then on. It always
acknowledges the General Call address byte of 00h (0000 0000), but does not acknowledge any General Call
data bytes other than 06h (0000 0110).
The BUF20800-Q1 automatically performs a reset upon power up. As part of the reset, all outputs are set to
(VREFH −VREFL)/2. Other reset values are available as a custom modification—contact your TI representative for
details.
The BUF20800-Q1 resets all outputs to (VREFH −VREFL)/2 after sending the device address, if a valid DAC
address is sent with bits D7 to D5 set to ‘100’. If these bits are set to ‘010’, only the DAC being addressed in this
most significant byte (MSB) and the following least significant byte (LSB) will be reset.
OUTPUT VOLTAGE
Buffer output values are determined by the reference voltages (VREFH and VREFL) and the decimal value of the
binary input code used to program that buffer. The value is calculated using Equation 1:
(1)
The valid voltage ranges for the reference voltages are:
4V ≤VREFH –VS≤0.2 V and 0.2 V ≤VREFL ≤VS–4 V (2)
The BUF20800-Q1 outputs are capable of a full-scale voltage output change in typically 5 μs—no intermediate
steps are required.
OUTPUT LATCH
Updating the DAC register is not the same as updating the DAC output voltage, because the BUF20800-Q1
features a double-buffered register structure. There are three methods for latching transferred data from the
storage registers into the DACs to update the DAC output voltages.
Method 1 requires externally setting the latch pin (LD) LOW, LD = LOW, which will update each DAC output
voltage whenever its corresponding register is updated.
Method 2 externally sets LD = HIGH to allow all DAC output voltages to retain their values during data transfer
and until LD = LOW, which will then simultaneously update the output voltages of all DACs to the new register
values. Use this method to transfer a future data set in advance to prepare for a very fast output voltage update.
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 9
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SBOS571 –AUGUST 2011
www.ti.com
Method 3 uses software control. LD is maintained HIGH, and all DACs are updated when the master writes a 1
in bit 15 of any DAC register. The update will occur after receiving the 16-bit data for the currently-written
register.
The General Call Reset and the power-up reset will update the DAC regardless of the state of the latch pin.
READ/WRITE OPERATIONS
The BUF20800-Q1 is able to read from a single DAC, or multiple DACs, or write to the register of a single DAC,
or multiple DACs in a single communication transaction. DAC addresses begin with 0000 0000, which
corresponds to DAC_1, through 0001 0011, which corresponds to VCOM OUT2.
Write commands are performed by setting the read/write bit LOW. Setting the read/write bit HIGH will perform a
read transaction.
Writing
To write to a single DAC register
1. 1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW. The BUF20800-Q1 will acknowledge this byte.
3. Send a DAC address byte. Bits D7−D5 must be set to 0. Bits D4−D0 are the DAC address. Only DAC
addresses 00000 to 10011 are valid and will be acknowledged. Table 3 shows the DAC addresses.
4. Send two bytes of data for the specified DAC register. Begin by sending the most significant byte first (bits
D15−D8, of which only bits D9 and D8 are used, and bits D15−D14 must not be 01), followed by the least
significant byte (bits D7−D0). The register is updated after receiving the second byte.
5. Send a STOP condition on the bus
Table 3. DAC Addresses
DAC ADDRESS
DAC_1 0000 0000
DAC_2 0000 0001
DAC_3 0000 0010
DAC_4 0000 0011
DAC_5 0000 0100
DAC_6 0000 0101
DAC_7 0000 0110
DAC_8 0000 0111
DAC_9 0000 1000
DAC_10 0000 1001
DAC_11 0000 1010
DAC_12 0000 1011
DAC_13 0000 1100
DAC_14 0000 1101
DAC_15 0000 1110
DAC_16 0000 1111
DAC_17 0001 0000
DAC_18 0001 0001
VCOM OUT1 0001 0010
VCOM OUT2 0001 0011
10 Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): BUF20800-Q1
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SBOS571 –AUGUST 2011
The BUF20800-Q1 will acknowledge each data byte. If the master terminates communication early by sending a
STOP or START condition on the bus, the specified register will not be updated. Updating the DAC register is not
the same as updating the DAC output voltage. See the Output Latch section.
The process of updating multiple DAC registers begins the same as when updating a single register. However,
instead of sending a STOP condition after writing the addressed register, the master continues to send data for
the next register. The BUF20800-Q1 automatically and sequentially steps through subsequent registers as
additional data is sent. The process continues until all desired registers have been updated or a STOP condition
is sent.
To write to multiple DAC registers:
1. 1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW. The BUF20800-Q1 will acknowledge this byte.
3. Send either the DAC_1 address byte to start at the first DAC, or send the address byte for whichever DAC
will be the first in the sequence of DACs to be updated. The BUF20800-Q1 will begin with this DAC and step
through subsequent DACs in sequential order.
4. Send the bytes of data; begin by sending the most significant byte (bits D15−D8, of which only bits D9 and
D8 have meaning), followed by the least significant byte (bits D7−D0). The first two bytes are for the DAC
addressed in step 3 above. Its register is automatically updated after receiving the second byte. The next two
bytes are for the following DAC. That DAC register is updated after receiving the fourth byte. This process
continues until the registers of all following DACs have been updated.
5. Send a STOP condition on the bus.
The BUF20800-Q1 will acknowledge each byte. To terminate communication, send a STOP or START condition
on the bus. Only DAC registers that have received both bytes of data will be updated.
Reading
Reading a DAC register will return the data stored in the DAC. This data can differ from the data stored in the
DAC register. See the Output Latch section.
To read the DAC value:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW. The BUF20800-Q1 will acknowledge this byte.
3. Send the DAC address byte. Bits D7−D5 must be set to 0; Bits D4−D0 are the DAC address. Only DAC
addresses 00000 to 10011 are valid and will be acknowledged.
4. Send a START or STOP/START condition on the bus.
5. Send correct device address and read/write bit = HIGH. The BUF20800-Q1 will acknowledge this byte.
6. Receive two bytes of data. They are for the specified DAC. The first received byte is the most significant byte
(bits D15−D8; only bits D9 and D8 have meaning); the next byte is the least significant byte (bits D7−D0).
7. Acknowledge after receiving the first byte.
8. Do not acknowledge the second byte to end the read transaction.
Communication may be terminated by sending a premature STOP or START condition on the bus, or by not
sending the acknowledge.
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 11
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SBOS571 –AUGUST 2011
www.ti.com
To Read Multiple DACs:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW. The BUF20800-Q1 will acknowledge this byte.
3. Send either the DAC_1 address byte to start at the first DAC, or send the address byte for whichever DAC
will be the first in the sequence of DACs to be read. The BUF20800-Q1 will begin with this DAC and step
through subsequent DACs in sequential order.
4. Send a START or STOP/START condition on the bus.
5. Send correct device address and read/write bit = HIGH. The BUF20800-Q1 will acknowledge this byte.
6. Receive two bytes of data. They are for the specified DAC. The first received byte is the most significant byte
(bits D15−D8, only bits D9 and D8 have meaning); the next byte is the least significant byte (bits D7−D0).
7. Acknowledge after receiving each byte of data except for the last byte. The acknowledge bit of the last byte
should be HIGH to end the read operation.
8. When all desired DACs have been read, send a STOP or repeated START condition on the bus.
Communication may be terminated by sending a premature STOP or START condition on the bus, or by not
sending the acknowledge.
12 Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): BUF20800-Q1
SDA_in
Start
Write single DAC register. P4- P0 specify DAC address.
If D15 = 0, the DACs are updated on the Latch pin.
If D15 = 0, the DACs are updated on the Latch pin.
If D15 = 0, the DACs are updated on the Latch pin.
If D15 = 1, all DACs are updated when the current DAC register is updated.
If D15 = 1, all DACs are updated when the current DAC register is updated.
If D15 = 1, all DACs are updated when the current DAC register is updated.
Write Operation
A6 A3
A5 A2
A4 A1 A0 W
A6 A3
A5 A2
A4 A1 A0 W
D7 P4
D6 P3
D5 P2 P1 P0 D15 D12
D14 D11
D13 D10 D9 D8 D7
D7
D4
D4
D6
D6
D3
D3
D5
D5
D2
D2
D1
D1
D0
D0
D7 D4
D6 D3
D5 D2 D15
D1 D14
D0 D13
D7 D4
D6 D3
D5 D2 D15
D1 D14
D0 D13
D15 D12
D14 D11
D13 D10 D9 D8
D15 D12
D14 D11
D13 D10 D9 D8
D15 D12
D14 D11
D13 D10 D9 D8
D7 P4
D6 P3
D5 P2 P1 P0
D7 P4
D6 P3
D5 P2 P1 P0
D7 P4
D6 P3
D5 P2 P1 P0
A6
A6
A3
A3
A5
A5
A2
A2
A4
A4
A1
A1
A0
A0
W
W
SCL
Device_out
SCL
SDA_in
Write Operation
Write multiple DAC registers. P4- P0 specify start DAC address.
Device_out
DAC 20 (V ) MSbyte. D14must be 0.
COM OUT2 Ackn Ackn Stop
DAC 20 LSbyte
a. Write Single DAC a. Write Multiple DACs
Device Address Write DAC MSbyte. D14 must be 0.
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
DAC LSbyte Ackn
Ackn
Ackn
DAC address pointer. D7- D5 must be 000. Stop
Start Device Address Write DAC MSbyte. D14 must be 0.
Ackn Ackn Ackn
Ackn
Ackn
Ackn Ackn
D7 D4
D6 D3
D5 D2 D1 D0
D15 D12
D14 D11
D13 D10 D9 D8 Ackn Ackn
D7 D4
D6 D3
D5 D2 D1 D0
D15 D12
D14 D11
D13 D10 D9 D8 Ackn Ackn
Ackn
Ackn Ackn
Ackn
DAC (pointer) LSbyte Ackn
Start DAC address pointer. D7- D5 must be 000. DAC (pointer + 1)MSbyte. D14 must be 0.
The entire DAC register D9-D0
is updated in this moment.
The entire DAC register D9-D0
is updated in this moment.
The entire DAC register D9-D0
is updated in this moment.
BUF20800-Q1
www.ti.com
SBOS571 –AUGUST 2011
Figure 9. Timing Diagram for Write DAC Register
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): BUF20800-Q1
D15 D12
D14 D11
D13 D10 D9 D8
D15 D12
D14 D11
D13 D10 D9 D8
Read multiple DAC registers. P4- P0 specify start DAC address.
Device Address Write Device Address
Ackn Ackn Read Ackn
Ackn
Ackn
D7 D4
D6 D3
D5 D2 D1 D0 Ackn
D7 D4
D6 D3
D5 D2 D1 D0
R
R
D15 D12
D14 D11
D13 D10 D9 D8
D15 D12
D14 D11
D13 D10 D9 D8
D7 P4
D6 P3
D5 P2 P1 P0
D7 P4
D6 P3
D5 P2 P1 P0
A6
A6
A6
A6
A3
A3
A3
A3
A5
A5
A5
A5
A2
A2
A2
A2
A4
A4
A4
A4
A1
A1
A1
A1
A0
A0
A0
A0
W
W
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
Start DAC address pointer. D7- D5 must be 000. DAC (pointer) MSbyte. D15- D10 have no meaning.
SCL
Start Start
Read Operation
DAC20(V ) MSbyte. D15-D10 ha ve no meaning.
COMOUT2 DAC20 LSbyte.
Ackn
Ackn
Ackn
No Ackn Stop
Device_out
b. Read Multiple DACs
Read single DAC register. P4- P0 specify DAC address.
A6
A6
A3
A3
A5
A5
A2
A2
A4
A4
A1
A1
A0
A0
W
WD7 P4
A4
A4
D6
A6
A6
P3
A3
A3
D5
A5
A5
P2
A2
A2
P1
A1
A1
P0
A0
A0
D7 P4
D6 P3D5 P2 P1 P0 D15 D7
D7
D15
D12 D4
D4
D12
D14 D6
D6
D14
D11 D3
D3
D11
D13 D5
D5
D13
D10 D2
D2
D10
D9 D1
D1
D9
D8 D0
D0
D8
Ackn Ackn
Ackn Ackn
SCL
SDA_in Ackn
Ackn
DAC Msbyte. D15-D10 ha ve no meaning. DAC LSbyte.
Ackn
Device_out
Start No Ack n St op
Start
Read Operation
a. Read Single DAC
Device Address Device Address
DAC address pointer. D7- D5 must be 000.
Write Ackn Ackn
Ackn
Ackn
Read
R
R
BUF20800-Q1
SBOS571 –AUGUST 2011
www.ti.com
Figure 10. Timing Diagram for Read DAC Register
14 Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): BUF20800-Q1
BUFxx704
a) Traditional b) SolutionBUF20800-Q1
PC
SDA
SCL
SDA
SCL
EEPROM
Timing
Controller
LCD Panel Electronics
BUF20800-Q1
Register
Control Interface
Gamma
References
OUT1
OUT2
OUT17
OUT18
VCOM
VCOM OUT1
VCOM OUT2
BUF20800-Q1
www.ti.com
SBOS571 –AUGUST 2011
REPLACEMENT OF TRADITIONAL GAMMA BUFFER
Traditional gamma buffers rely on a resistor string (often using expensive 0.1% resistors) to set the gamma
voltages. During development, the optimization of these gamma voltages can be time-consuming. Programming
these gamma voltages with the BUF20800-Q1 can significantly reduce the time required for gamma voltage
optimization. The final gamma values can be written into an external EEPROM to replace a traditional gamma
buffer solution. During power-up of the LCD panel, the timing controller reads the EEPROM and loads the values
into the BUF20800-Q1 to generate the desired gamma voltages. Figure 11a shows the traditional resistor string;
Figure 11b shows the more efficient alternative method using the BUF20800-Q1.
BUF20800-Q1 uses the most advanced high-voltage CMOS process available today, which allows it to be
competitive with traditional gamma buffers.
This technique offers significant advantages:
•It shortens development time significantly.
•It allows demonstration of various gamma curves to LCD monitor makers by simply uploading a different set
of gamma values.
•It allows simple adjustment of gamma curves during production to accommodate changes in the panel
manufacturing process or end-customer requirements.
•It decreases cost and space.
Figure 11. Replacement of the Traditional Gamma Buffer
PROGRAMMABLE VCOM
The VCOM channels of the BUF20800-Q1 can swing to 2V from the positive supply rail while sourcing 50 mA and
to 1 V above the negative rail while sinking 50 mA (see Figure 4, typical characteristic Output Voltage vs Output
Current). To store the gamma and the VCOM values, an external EEPROM is required. During power-up of the
LCD panel, the timing controller can then read the EEPROM and load the values into the BUF20800-Q1 to
generate the desired VCOM voltages, as illustrated in Figure 11 and Figure 12. The VCOM channels can be
programmed independently from the gamma channels.
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): BUF20800-Q1
BUF20800-Q1
SDA
SCL
Register
Control Interface
Gamma
References
OUT1
OUT2
OUT17
OUT18
VCOM
VCOM OUT1
VCOM OUT2
BUF20800-Q1
SBOS571 –AUGUST 2011
www.ti.com
Figure 12. BUF20800-Q1 Used for Programmable VCOM
REFH AND REFL INPUT RANGE
Best performance and output swing range of the BUF20800-Q1 are achieved by applying REFH and REFL
voltages that are slightly below the power-supply voltages. Most specifications have been tested at REFH = Vs−
200mV and REFL = GND + 200mV. The REFH internal buffer is designed to swing very closely to Vsand the
REFL internal buffer to GND. However, there is a finite limit on how close they can swing before saturating. To
avoid saturation of the internal REFH and REFL buffers, the REFH voltage should not be greater than Vs
−100mV and REFL voltage should not be lower than GND + 100mV. Figure 13 shows the swing capability of the
REFH and REFL buffers.
The other consideration when trying to maximize the output swing capability of the gamma buffers is the
limitation in the swing range of output buffers (OUT1−18, VCOM1, and VCOM2), which depends on the load current.
A typical load in the LCD application is 5−10mA. For example, if OUT1 is sourcing 10mA, the swing is typically
limited to about Vs−200mV. The same applies to OUT18, which typically limits at GND + 200mV when sinking
10mA. An increase in output swing can only be achieved for much lighter loads. For example, a 3mA load
typically allows the swing to be increased to approximately Vs−100mV and GND + 100mV.
Connecting REFH directly to Vsand REFL directly to GND does not damage the BUF20800-Q1. As discussed
above however, the output stages of the REFH and REFL buffers will saturate. This condition is not desirable
and can result in a small error in the measured output voltages of OUT1−18, VCOM1, and VCOM2. As described
above, this method of connecting REFH and REL does not help to maximize the output swing capability.
16 Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): BUF20800-Q1
18
17
16
15
3
2
1
0
Output Voltage (V)
REFL OUT (sinking), Code =000h
VREFL REFH = 17V
RLOAD Connected to 18V
= 0.2 V, V
= 1 V, V = 17.8 V
REFH OUT (sourcing), Code =3FFh
VREFL REFH
RLOAD Connected to GND
0
10 403020 50 60 70 80 90 100
Output Current (mA)
BUF20800-Q1
www.ti.com
SBOS571 –AUGUST 2011
Figure 13. Reference Buffer Output Voltage vs Output Current
CONFIGURATION FOR 20 GAMMA CHANNELS
The VCOM outputs can be used as additional gamma references in order to achieve two additional gamma
channels (20 total). The VCOM outputs will behave the same as the OUT1−9 outputs when sourcing or sinking
smaller currents (see Figure 4). The VCOM outputs are better able to swing to the positive rail than to the negative
rail. Therefore, it is better to use the VCOM outputs for higher reference voltages, as shown in Figure 14.
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): BUF20800-Q1
SDA
SCL
LD A0
AnalogDigita l REFH
OUT17
VCO M OUT1
REFL
DAC Registers
Control IF
OUT18
OUT1
OUT2
REFH OUT
REFL OUT
DAC Registers
14.8V
0.2V
15V
15V
0.2V
14.8V2V5.5V
GMA 3
GMA 4
GMA 19
GMA 20
VCO M OUT2
GMA 1
GMA 2
18 Gamma Channels
Source
Driver
BUF20800-Q1
BUF20800-Q1
SBOS571 –AUGUST 2011
www.ti.com
Figure 14. 20 Gamma Channel Solution −Two VCOM Channels Used as Additional Gamma Channels
CONFIGURATION FOR 22 GAMMA CHANNELS
In addition to the VCOM outputs, the REFH and REFL OUT outputs can also be used as fixed gamma references.
The output voltage will be set by the REFH and REFL input voltages, respectively. Therefore, REFH OUT should
be used for the highest voltage gamma reference, and REFL OUT for the lowest voltage gamma reference. A
22-channel solution can be created by using all 18 outputs, the two VCOM outputs, and both REFH/L OUT outputs
for gamma references—see Figure 15. However, the REFH and REFL OUT buffers were designed to only drive
light loads on the order of 5−10mA. Driving capacitive loads is not recommended with these buffers. In addition,
the REFH and REFL buffers must not be allowed to saturate from sourcing/sinking too much current from REFH
OUT or REFL OUT. Saturation of the REFH and REFL buffers results in errors in the voltages of OUT1−18 and
VCOM OUT1−2. The BUF01900 can be used to provide a programmable VCOM output.
18 Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): BUF20800-Q1
SDA
SCL
LD A0
Analo gDigi tal REFH
OUT 17
REFL
DAC Registers
Control IF
OUT18
OUT 1
OUT 2
REFL OUT
DAC Registers
REFH OUT
17V
0.2V
18V
18V
0.2V
17.8V
GMA 1
GMA 2
GMA 3
GMA 4
GMA 5
GMA 20
GMA 21
GMA 22
(REFH OUT
will be a
fixed voltage.)
Analog BIAS
18V
Digital
2V5. 5V
SDA
SCL
A0
Contro l IF
10Bit
DAC
4 x OT P
ROM
Switch
Control
Voltag e Regu la to r
Progra m Comm and
BUF01900(1)
VCOM
Buffer VCOM OUT
VCOM
Panel
Output of referenc e
buffer can be used
for an extra fixed
gam ma channel
2V5.5V
VCOM OUT 1
VCOM OUT 2
Source
Driver
BUF20800-Q1
Reference buffer
and VCOM OUT
outputs can be used
for extra gamma channels.
18 Output Channels
2 VCOM Channels plus
BUF20800-Q1
www.ti.com
SBOS571 –AUGUST 2011
Figure 15. 22-Channel Gamma Solution
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): BUF20800-Q1
Digital
Picture
Data
Histogram
Gamma
Adjustment
Algorithm
SDA BUF20800-Q1
Gamma References
Timing Controller/mController
1 through 18
SCL
Source Driver Source Driver VCOM
Black White
BUF20800-Q1
SBOS571 –AUGUST 2011
www.ti.com
DYNAMIC GAMMA CONTROL
Dynamic gamma control is a technique used to improve the picture quality in LCD TV applications. The
brightness in each picture frame is analyzed and the gamma curves are adjusted on a frame-by-frame basis. The
gamma curves are typically updated during the short vertical blanking period in the video signal. Figure 16 shows
a block diagram using the BUF20800-Q1 for dynamic gamma control and VCOM output.
The BUF20800-Q1 is ideally suited for rapidly changing the gamma curves because of its unique topology:
•double register input structure to the DAC;
•fast serial interface;
•simultaneous updating of all DACs by software. See the Read/Write Operations to write to all registers and
the Output Latch sections.
The double register input structure saves programming time by allowing updated DAC values to be pre-loaded
into the first register bank. Storage of this data can occur while a picture is still being displayed. Because the
data are only stored into the first register bank, the DAC output values remain unchanged—the display is
unaffected. During the vertical sync period, the DAC outputs (and therefore, the gamma voltages) can be quickly
updated either by using an additional control line connected to the LD pin, or through software—writing a ‘1’in bit
15 of any DAC register. For the details on the operation of the double register input structure, see the Output
Latch section.
Example: Update all 18 gamma registers simultaneously via software.
Step 1: Check if LD pin is placed in HIGH state.
Step 2: Write DAC Registers 1−18 with bit 15 always ‘0’.
Step 3: Write any DAC register a second time with identical data. Make sure that bit 15 is ‘1’. All DAC
channels will be updated simultaneously after receiving the last bit of data. (Note: this step may be
eliminated by setting bit 15 of DAC 18 to ‘1’in the previous step.)
Figure 16. Dynamic Gamma Control
TOTAL TI PANEL SOLUTION
In addition to the BUF20800-Q1 programmable voltage reference, TI offers a complete set of ICs for the LCD
panel market, including gamma correction buffers, various power-supply solutions, and audio power solutions.
See Figure 17 for the total IC solution from TI.
20 Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): BUF20800-Q1
2.7V5V
3.3V
n n
26V
−14V
15V
TPS651xx
LCD
Supply
TPA3005D2
TPA3008D2
Audio
Speaker
Driver
Logic and
Timing
Controller
High Resolution
TFTLCS Panel
Source Driver
Gamma Correction
BUF20800-Q1
VCOM
Gate Driver
BUF20800-Q1
www.ti.com
SBOS571 –AUGUST 2011
Figure 17. TI LCD Solution
THE BUF20800-Q1 IN INDUSTRIAL APPLICATIONS
The wide supply range, high output current, and very low cost make the BUF20800-Q1 attractive for a range of
medium accuracy industrial applications such as programmable power supplies, multi-channel data-acquisition
systems, data loggers, sensor excitation and linearization, power-supply generation, and other uses. Each DAC
channel features 1LSB DNL and INL.
Many systems require different levels of biasing and power supply for various components as well as sensor
excitation, control-loop set-points, voltage outputs, current outputs, and other functions. The BUF20800-Q1, with
its 20 total programmable DAC channels, provides great flexibility to the entire system by allowing the designer to
change all these parameters via software.
Figure 18 provides various ideas on how the BUF20800-Q1 can be used in applications. A micro-controller with
two-wire serial interface controls the various DACs of the BUF20800-Q1. The BUF20800-Q1 can be used for:
•sensor excitation
•programmable bias/reference voltages
•variable power-supplies
•high-current voltage output
•4-20mA output
•set-point generators for control loops
NOTE: The output voltages of the BUF20800-Q1 DACs will be set to (VREFH −VREFL)/2 at power-up or reset.
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): BUF20800-Q1
Sensor Excitation/Linearization
0.3V to17V
2V to 16V, 100mA
+18V +5V
Voltage
Output
High Current
Voltage Output
SDA SCL
mC
BU F 2 0 8 0 0 - Q 1
+5V
+5V
+2.5V Bias
Bias Voltage
Generator
LED Driver
+4.3V
+4V
+7.5V
Supply Voltage
Generator
Control Loop
Set Point
Offset
Adjustment
Ref
INA
MDAC
Comparator
Threshold
420 mA
420 mA
Generator
Reference
for MDAC
Ref
BUF20800-Q1
SBOS571 –AUGUST 2011
www.ti.com
Figure 18. Industrial Applications for the BUF20800-Q1
EVALUATION BOARD AND SOFTWARE
An evaluation board is available for the BUF20800-Q1. The evaluation board features easy-to-use software that
allows individual channel voltages to be set (see Figure 19). Configurations can be quickly evaluated to
determine optimal codes for a given application. Contact your local TI representative for more information
regarding the evaluation board.
22 Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): BUF20800-Q1
BUF20800-Q1
www.ti.com
SBOS571 –AUGUST 2011
Figure 19. Evaluation Board
GENERAL PowerPad DESIGN CONSIDERATIONS
The BUF20800-Q1 is available in a thermally-enhanced PowerPAD package. This package is constructed using
a downset leadframe upon which the die is mounted, see Figure 20(a) and Figure 20(b). This arrangement
results in the lead frame being exposed as a thermal pad on the underside of the package; see Figure 20(c).
This thermal pad has direct thermal contact with the die; thus, excellent thermal performance is achieved by
providing a good thermal path away from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat-dissipating device.
Soldering the PowerPAD to the printed circuit board (PCB) is always required, even with applications
that have low power dissipation. This provides the necessary thermal and mechanical connection between the
lead frame die pad and the PCB.
The PowerPAD must be connected to the most negative supply voltage on the device, GNDAand GNDD.
1. Prepare the PCB with a top-side etch pattern. There should be etching for the leads as well as etch for the
thermal pad.
2. Place recommended holes in the area of the thermal pad. Ideal thermal land size and thermal via patterns for
the HTSSOP-38 DCP package can be seen in the technical brief, PowerPAD Thermally-Enhanced Package
(SLMA002), available for download at www.ti.com. These holes should be 13 mils in diameter. Keep them
small, so that solder wicking through the holes is not a problem during reflow. An example thermal land
pattern mechanical drawing is attached to the end of this data sheet.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the BUF20800-Q1 IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered; thus, wicking is not a problem.
4. Connect all holes to the internal plane that is at the same voltage potential as the GND pins.
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): BUF20800-Q1
BUF20800-Q1
SBOS571 –AUGUST 2011
www.ti.com
5. When connecting these holes to the internal plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In
this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the
holes under the BUF20800-Q1 PowerPAD package should make their connection to the internal plane with a
complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its twelve
holes exposed. The bottom-side solder mask should cover the holes of the thermal pad area. This masking
prevents solder from being pulled away from the thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the BUF20800-Q1 IC is simply placed in position and run through the
solder reflow operation as any standard surfacemount component. This preparation results in a properly
installed part.
24 Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): BUF20800-Q1
DIE
Side View (a)
End View (b)
Bottom View (c)
DIE
The thermal pad is electrically isolated from all terminals in the package.
Thermal
Pad
P =
D
TMAX A
-T
qJA
( )
6
5
4
3
2
1
0
Maximum Power Dissipation (W)
TA, Free Air Temperature ( C)°
−40 −20 402010 60 80 100
BUF20800-Q1
www.ti.com
SBOS571 –AUGUST 2011
Figure 20. Views of Thermally-Enhanced DCP Package
For a given θJA (listed in the Electrical Characteristics
table), the maximum power dissipation is shown in
Figure 21, and is calculated by Equation 3:
(3)
Where:
PD= maximum power dissipation (W)
TMAX = absolute maximum junction temperature
(+125°C)
TA= free-ambient air temperature (°C)
Figure 21. Maximum Power Dissipation
vs Free-Air Temperature
(with PowerPAD soldered down)
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): BUF20800-Q1
PACKAGE OPTION ADDENDUM
www.ti.com 1-Oct-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
BUF20800ATDCPRQ1 ACTIVE HTSSOP DCP 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF BUF20800-Q1 :
•Catalog: BUF20800
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
BUF20800ATDCPRQ1 HTSSOP DCP 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BUF20800ATDCPRQ1 HTSSOP DCP 38 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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