M65608E
Rev. E – June 5, 2000 1
Introduction
The M65608E is a very low power CMOS static RAM
organized as 131072 × 8 bits.
Atmel Wireless & Microcontrollers brings the solution
to applications where fast computing is as mandatory as
low consumption, such as aerospace electronics,
portable instruments, or embarked systems.
Utilizing an array of six transistors (6T) memory cells,
the M65608E combines an extremely low standby
supply current (Typical value = 0.2 µA) with a fast
access time at 30 ns over the full military temperature
range. The high stability of the 6T cell provides
excellent protection against soft errors due to noise.
The M65608E is processed according to the methods of
the latest revision of the MIL STD 883 (class B or S),
ESA SCC 9000 or QML.
Features
DAccess time: 30, 45 ns
DVery low power consumption
active : 250 mW (Typ)
standby : 1 µW (Typ)
data retention : 0.5 µW (Typ)
DWide temperature Range : –55 To +125°C
D400 Mils width package
DTTL compatible inputs and outputs
DAsynchronous
DSingle 5 volt supply
DEqual cycle and access time
DGated inputs :
no pull-up/down
resistors are required
Interface
Block Diagram
128 K 8 Very Low Power CMOS SRAM Rad Tolerant
M65608E
Rev. E – June 5, 2000
2
Pin Configuration 32 pins DIL side-brazed 400 MILS
32 pins Flatpack 400 MILS
Pin Names
A0–A16 Address inputs
I/O0–I/O7 Data Input/Output
CS1Chip select 1
CS2Chip select 2
WWrite Enable
OE Output Enable
VCC Power
GND Ground
Truth Table
CS1CS2W OE INPUTS/
OUTPUTS MODE
H X X X Z Deselect/
Power-down
X L X X Z Deselect/
Power Down
L H H L Data Out Read
L H L X Data In Write
L H H H Z Output Disable
L = low, H = high, X = H or L, Z = high impedance.
M65608E
Rev. E – June 5, 2000 3
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage to GND potential : - 0.5 V + 7.0 V. . . . . . . . . . . . . . .
DC input voltage : GND – 0,3 V to VCC + 0,3. . . . . . . . . . . . . . . . .
DC output voltage high Z state : GND – 0,3 V to VCC + 0,3. . . . . .
Storage temperature : –65 °C to + 150 °C. . . . . . . . . . . . . . . . . . . . . .
Output current into outputs (low) : 20 mA. . . . . . . . . . . . . . . . . . . . . .
Electro statics discharge voltage : > 2 001 V. . . . . . . . . . . . . . . . . . .
(MIL STD 883D method 3015.3)
Operating Range
OPERATING VOLTAGE OPERATING TEMPERATURE
Military 5 V ± 10 % – 55 _C to + 125 _C
Recommended DC Operating Conditions
PARAMETER DESCRIPTION MINIMUM TYPICAL MAXIMUM UNIT
Vcc Supply voltage 4.5 5.0 5.5 V
Gnd Ground 0.0 0.0 0.0 V
VIL Input low voltage GND – 0.3 0.0 0.8 V
VIH Input high voltage 2.2 –VCC + 0.3 V
Capacitance
PARAMETER DESCRIPTION MINIMUM TYPICAL MAXIMUM UNIT
Cin (1) Input low voltage – – 8 pF
Cout (1) Output high volt – – 8 pF
Note : 1. Guaranteed but not tested.
DC Parameters
PARAMETER DESCRIPTION MINIMUM TYPICAL MAXIMUM UNIT
IIX (2) Input leakage current – 1 –1µA
IOZ (2) Output leakage current – 1 –1µA
VOL (3) Output low voltage – – 0.4 V
VOH (4) Output high voltage 2.4 – –
Notes : 2. Gnd < Vin < Vcc, Gnd < Vout < Vcc Output Disabled.
3. Vcc min. IOL = 8.0 mA.
4. Vcc min. IOH = –4.0 mA.
M65608E
Rev. E – June 5, 2000
4
Consumption
SYMBOL DESCRIPTION 65608
– 30 65608
– 45 UNIT VALUE
ICCSB (5) Standby supply current 2 2 mA max
ICCSB1 (6) Standby supply current 300 300 µA max
ICCOP (7) Dynamic operating current 130 100 mA max
Notes : 5. CS1 ≥ VIH or CS2 ≤ VIL and CS1 ≤ VIL.
6. CS1 ≥ Vcc – 0.3 V or, CS2 < Gnd + 0.3 V and CS1 ≤ 0.2 V
7. F = 1/TAVAV, Iout = 0 mA, W = OE = VIH, Vin = Gnd/Vcc, Vcc max.
AC Parameters
Input pulse levels : Gnd to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input rise : 5 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input timing reference levels : 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .
Output loading IOL/IOH (see figure 1a and 1b) : + 30 pF. . . . . . . . .
AC Test Loads Waveforms
Figure 1a Figure 1b Figure 2
Data Retention Mode
MHS CMOS RAM’s are designed with battery backup
in mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules insure
data retention :
1. During data retention chip select CS1 must be held. high within VCC to VCC -0.2 V or, chip select CS2
must be held low within GND to GND + 0.2 V.
2. Output Enable (OE) should be held high to keep the
RAM outputs high impedance, minimizing power
dissipation.
3. During power up and power down transitions CS1
and OE must be kept between VCC + 0.3 V and
70 % of VCC, or with CS2 between GND and GND
- 0.3 V.
4. The RAM can begin operation > TR ns after Vcc
reaches the minimum operation voltages (4.5 V).
M65608E
Rev. E – June 5, 2000 5
Timing
Data Retention Characteristics
PARAMETER DESCRIPTION MINIMUM TYPICAL
TA = 25 _CMAXIMUM UNIT
VCCDR Vcc for data retention 2.0 – – V
TCDR Chip deselect to data retention time 0.0 – – ns
TR Operation recovery time TAVAV (9) – – ns
ICCDR1 (10) Data retention current @ 2.0 V –0.1 150 µA
ICCDR2 (10) Data retention current @ 3.0 V –0.2 200 µA
Notes : 9. TAVAV = Read cycle time.
10. CS1 = Vcc or CS2 = CS1 = GND, Vin = Gnd/Vcc, this parameter is only tested at Vcc = 2 V.
M65608E
Rev. E – June 5, 2000
6
Write Cycle
SYMBOL PARAMETER 65608
– 30 65608
– 45 UNIT VALUE
TAVAW Write cycle time 30 45 ns min
TAVWL Address set-up time 0 0 ns min
TAVWH Address valid to end of write 22 35 ns min
TDVWH Data set-up time 18 25 ns min
TE1LWH CS1 low to write end 22 35 ns min
TE2HWH CS2 high to write end 22 35 ns min
TWLQZ Write low to high Z (11) 8 15 ns max
TWLWH Write pulse width 22 35 ns min
TWHAX Address hold from to end of write 0 0 ns min
TWHDX Data hold time 0 0 ns min
TWHQX Write high to low Z (11) 0 0 ns min
Read Cycle
SYMBOL PARAMETER 65608
– 30 65608
– 45 UNIT VALUE
TAVAV Read cycle time 30 45 ns min
TAVQV Address access time 30 45 ns max
TAVQX Address valid to low Z 5 5 ns min
TE1LQV Chip-select1 access time 30 45 ns max
TE1LQX CS1 low to low Z (11) 3 3 ns min
TE1HQZ CS1 high to high Z (11) 18 20 ns max
TE2HQV Chip-select2 access time 30 45 ns max
TE2HQX CS2 high to low Z (11) 3 3 ns min
TE2LQZ CS2 low to high Z (11) 18 20 ns max
TGLQV Output Enable access time 12 15 ns max
TGLQX OE low to low Z (11) 0 0 ns min
TGHQZ OE high to high Z (11) 8 15 ns max
Notes : 11. Parameters guaranteed, not tested, with output loading 5 pF. (see fig. 1.b.).
M65608E
Rev. E – June 5, 2000 7
Write Cycle 1. W Controlled. OE High During Write
TE1LWH
Write Cycle 2. W Controlled. OE Low
M65608E
Rev. E – June 5, 2000
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Write Cycle 3. CS1 or CS2 Controlled.
Note : 12. The internal write time of the memory is defined by the overlap of CS1 Low and CS2 HIGH and W LOW. Both signals must be
actived to initiate a write and either signal can terminate a write by going in actived. The data input setup and hold timing should be
referenced to the actived edge of the signal that terminates the write.
Data out is high impedance if OE = VIH.
M65608E
Rev. E – June 5, 2000 9
Read Cycle nb 1
Read Cycle nb 2
Read Cycle nb 3
M65608E
Rev. E – June 5, 2000
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Ordering Information
M = Military –55°to +125°C
S = Space –55°to +125°C
C9 = Side Brazed 32 pins 400 mils
DJ = Flat Package 32 pins 400 mils
0 = die
128K × 8
STATIC RAM
blank = MHS standards
/883 = MIL-STD 883 Class B or S
SB/SC = SCC 9000 level B/C
M– 65608EM DJ V
30 ns
45 ns
TEMPERATURE RANGE PACKAGE DEVICE SPEED FLOW*
– 45
V = Very low power
GRADE
/883
* For ordering in QML quality level, use the QML PIN according to SMD no 5962–89598.
The information contained herein is subject to change without notice. No r esponsibility is assumed by Atmel W ireless & Microcontrollers for using this
publication and/or circuits described herein : nor for any possible infringements of patents or other rights of thir d parties which may result from its use.
