PBA 313 01 BluetoothTM Radio PBA 313 01/2 (Bluetooth 1.0b), PBA 313 01/3 (Bluetooth 1.1) Key Features * RF output power Class 2 * Compliant to Bluetooth specification 1.0b or 1.1 * Forms a complete radio with: - an antenna - a crystal or existing 13 MHz - reference frequency - data and digital control - circuitry (baseband) * Small outline BGA-package (10.2 x 14.0 x 1.6 mm) * Requires no external shielding Suggested Applications * Mobile phones, PDA, Modems, Laptop computers, Handheld equipment Description PBA 313 01 is a short-range microwave frequency radio transceiver for Bluetooth communication links that are designed to operate in the globally available ISM frequency band, 2.4-2.5 GHz. Fast frequency hopping (1600 channel hops/s) with 79 channels available (2.402 to 2.480 GHz) and a maximum TX & RX bit rate of 1 Mbit/s exploits the maximum channel bandwidth allowed in the unlicensed ISM band. The implemented modulation technique is GFSK (Gaussian Frequency Shift Keying), with a BT product of 0.5. The design is based around a BiCMOS ASIC mounted on a LTCC (Low Temperature Co-fired Ceramic) substrate. The antenna filter, RX and TX baluns are all integrated into the substrate. Connection to the PCB is achieved by a non-collapsing BGA structure which gives a selfshielding design. The BLUETOOTH trademarks are owned by Bluetooth SIG, Inc., U.S.A. E PBA 313 01 RX_ON PX_ON Receiver RX Balun LNA Antenna filter BPF DISC Switch GLPF TX amp. TX Balun RX Data TX Data VCO Loop filter PLL TX_ON Synthesizer SYNTH_ON PHD_OFF Min Typ Figure 1. Block diagram. Absolute Maximum Ratings Parameter Condition Supply voltage Applied voltage to non supply pins Input RF Power Symbol VCC +3.3 VCC +0.3 -0.3 In-band Out-band Storage temperature Max 15 15 TStg -25 +100 Unit V V dBm dBm C Recommended Operating Conditions Parameter Condition Symbol Min Typ Max Reference clock frequency Reference clock amplitude Reference clock phase noise f = 15 kHz 1), 2) fEXT_CLK 12.99974 0.2 13 13.00026 0.5 -110 MHz V dBc/Hz Supply voltage Applied voltage to non-supply pins VCC_VCO 2.7 -0.3 +2.8 3.0 VCC+0.3 V V Output matching of ANT pin Antenna load VSWRTX Logical input high Logical input low VIH VIL Rise/Fall time of all digital inputs Clock frequency of SI_CLK Positive period of SI_CLK fSI_CLK tSI_CLK2 76 Ambient temperature TAmb -10 1) 2) 2 50 2:1 Unit 0.9xVCC -0.3 VCC+0.3 +0.3 2 20 4 ns MHz ns +75 C +23 V V If an external clock input is used the external clock should be AC coupled into the XO_N input and the XO_P input shall be left unconnected. The load capacitance on the XO_N input can be trimmed by 4 pF to allow frequency trimming when a crystal is used. Refer to the Design Considerations section for details on using the XO-trim register. EN/LZT 146 65 R3B (c) Ericsson Microelectronics AB, October 2001 PBA 313 01 Electrical Characteristics DC and low frequency Specifications Parameter Condition Current consumption Sleep mode3) SYNT_ON only Receive mode Transmit mode XO_N input capacitance XO_P output capacitance Capacitance of all digital inputs 4) Input leakage current Rise/Fall time of digital outputs Logical output high Logical output low 0.5 < VIN < (VCC -0.5) driving a 10 pF load Symbol Min CXO_N VOH VOL SYS_CLK frequency TX_CLK frequency Minimum LPO_CLK frequency Maximum LPO_CLK frequency 3) 4) 5) Typ Max Unit 65 21 40 32 200 30 52 44 A mA mA mA 11.5 33 7 pF pF pF 5 5 2.8 0 A ns V V MHz MHz fEXT_CLK fEXT_CLK /13 5) 3.3 2.0 4.7 3.1 kHz kHz Average after steady state. The XO_N input capacitance can be trimmed by 4 pF by writing a 6-bit value to the XO-Trim register. Refer to the Design Considerations section for further information. If used, the baseband must trim LPO_CLK to 3.2 kHz by writing to the LPO trim registers in the radio. Refer to the Design Considerations section for further information. RF Specifications (-10C - TA - +55C, VCC = 2.8 V, external frequency = 13 MHz 10 ppm, matching of antenna, max VSWRRX = 2:1. Recommended value in register according to table 5.) Radio performance without baseband. Parameter Condition General Frequency range Input and output impedance of ANT pin Receiver Performance (BER - 0.1%) Sensitivity level Symbol fRange Min 2.402 Typ 50 Max Unit 2.480 GHz -71.5 dBm 75 kHz offset (max), fMOD: 160kHz 0 kHz offset PIn, Min Max input level 75kHz offset (max), fMOD: 160kHz PIn, Max C/I (fC = 2441 MHz) C -4MHz 7), 8) C -3MHz 7), 8) C -2MHz 6), 7) C -1MHz 6) Co-channel 6) -37 -40 -24 -5 +7 -17 -17 -17 +4 +14 dB dB dB dB dB C +2MHz 6), 7) C +3MHz 7), 8) C +4MHz 8) -33 -41 -43 -17 -17 -40 dB dB dB Sensitivity level -78 0 C +1MHz 6) C/I Blocking, DC - 5 GHz Out-of-band blocking Intermodulation characteristics Spurious Emissions 6) 7) 8) see figure 3 30-1910 MHz 1910-2000 MHz 2000-2399 MHz 2484-2999 MHz 3000-3019 MHz 3.00-12.75 GHz 30 MHz - 1 GHz 1 GHz - 12.75 GHz 15 0 +4 -10 -27 -27 -11 -10 +13 +9 -39 -32 dBm +4 dBm dBm dBm dBm dBm dBm -14 -5 -5 -60 dB -57 -47 dBm dBm dBm Carrier signal level at -60 dBm, interferer Bluetooth modulated. Exception allowed in Bluetooth test specifications. Carrier signal level at -67 dBm, interferer Bluetooth modulated. EN/LZT 146 65 R3B (c) Ericsson Microelectronics AB, October 2001 3 PBA 313 01 RF Specifications, cont. Parameter Transmitter Performance Frequency modulation Condition Symbol Min Typ Max Unit Deviation from center frequency9) fMod 140 155 175 kHz -75 -4 0 +75 4.5 kHz dBm 25 40 40 kHz kHz kHz 1000 -36 -30 -47 -47 kHz dBm dBm dBm dBm Initial frequency error TX power 10) TX carrier drift 1 slot (366 s) 3 slots (1598 s) 5 slots (2862 s) 20 dB bandwidth Spurious Emissions Measured with RBW: 10 kHz and peak detector 30 MHz - 1GHz 1 GHz - 12.75 GHz 1.8 GHz - 1.9 GHz 5.15 GHz - 5.3 GHz -25 -40 -40 fDrift1 fDrift2 fDrift3 600 9) fMod = (FMod1-FMod0)/2. 10) The initial frequency is mainly affected by the tolerance of the reference frequency or crystal; for every 1Hz deviation from 12MHz, the TX carrier offset is altered by approximately 186Hz. C/I Blocking The blocking characteristics can be basically split into two regions: In-band and Out-of-band. Blocking is performed both on the chip and on the module level. * Out-of-band - - Antenna filter, DC to 1.9 GHz and 3:rd harmonic. Switch, low freq. and 2:nd harmonic. RX-balun, low freq. and 2:nd harmonic. On-chip IF filter. 0 m1 -10 dB(RX path) -30 m4 m3 -50 Example 1 Example 2 Interferenc e of +33 dBm a t 2015 MHz. Interferenc e of +33 dBm a t 1910 MHz. * Antenna isolation * Antenna filter, Antenna switch, RX-balun -20 -40 Figure 2 shows the combination blocking effect of the antenna switch, antenna filter and RX balun. In addition to the blocking characteristics shown in figure 2, there is antenna isolation and filtering on the chip. Marker 1 shows the region where the Bluetooth band is located. Markers 2 - 4 show the blocking at the telecom frequency bands. An example of total blocking characteristics can be seen in figure 3. 15 dB 27 dB * Interference level before -9 dBm IF filter +33-15-27= -60 * Antenna isolation * Antenna filter, Antenna switch, RX-balun 25 dB 36 dB * Interference level before -28 dBm IF filter +33-25-36= 0.1% BER requires a C/I of more than -40 dB at the IF filter. -70 m2 * 0.1% BER carrier level -40 + (-9)= -80 -90 -49 dBm * 0.1% BER carrier level -40 + (-28)= -68 dBm Figure 3. Blocking examples. -100 0.0 0.5 1.0 m1 freq=2.450GHz dB( RX path)= -3.529 m2 freq=900.0MHz dB(RX path) = -74.58 1.5 2.0 2.5 GH z 3.0 3.5 4.0 4.5 5.0 m3 freq=1.800GHz dB(RX path) = -47.426 m4 freq=1.900GHz dB(RX path ) = -36.537 Figure 2. Typical out-of-band blocking characteristics excluding antenna isolation and on chip filtering. 4 EN/LZT 146 65 R3B (c) Ericsson Microelectronics AB, October 2001 PBA 313 01 Mechanical specifications Top view 0.762 Bottom view 0.635 1.27 8.89 +0.2 10.2 -0.1 1.27 Side view 12.7 1.56 +0.04 14.0 0.2 RF ASIC Other components Coplanarity 0.1 mm (max) Tolerance on ball placement 0.2 mm All dimensions are in mm. Figure 4. Mechanical dimensions of PBA 313 01. Pin Description Pin no. Pin name Type Description Pin no. Pin name Type Description 1 Ground Common ground 18 Ground Common ground GND GND 2 TX_CLK D out 1 MHz clock 19 GND Ground Common ground 3 TX_ON D in Transmit power on 20 VCC_VCO Power VCO power supply 4 RX_DATA D out Received data output 21 PHD_OFF D in Open PLL 5 RX_ON D in Receiver power on 22 TX_DATA D in Transmit data 6 GND Ground Common ground 23 GND Ground Common ground 7 XO_P A in Crystal positive output 24 SYNT_ON D in Synt power up 8 XO_N A in Crystal negative input or external clock input 25 SI_CLK D in Serial interface clock 26 SI_CMS D in Serial interface control 9 POR_EXT D in External power on reset 10 GND Ground Common ground 11 VCC Power Common power supply 12 GND Ground Common ground 13 GND Ground Common ground 14 GND Ground Common ground 15 GND Ground Common ground 16 GND Ground Common ground 17 ANT 50 Antenna input/output Table 1. Pin description. 27 SI_CDI D in Serial data input 28 GND Ground Common ground 29 SI_CDO D out Serial data output 30 POR D out Power on reset 31 LPO_CLK D out 3.2 kHz clock 32 PX_ON D in Packet on 33 SYS_CLK_REQ D in System clock request 34 SYS_CLK D out System clock * A = Analog, D = Digital EN/LZT 146 65 R3B (c) Ericsson Microelectronics AB, October 2001 5 PBA 313 01 I/O Signal Description RX_ON Power supply There are two connections to supply the Bluetooth radio with power. VCC_VCO supplies the sensitive VCO circuitry with power, and VCC is for the remaining circuitry. Each of the two supplies should be low frequency decoupled. See figure 13 for example circuitry. Oscillator or external clock input Refer to the Design Considerations section. Oscillator or external clock input XO_N and XO_P connects to the crystal's inputs. The load capacitance to the crystal can be trimmed using the XO-Trim register. If an external clock is used, it should be AC coupled into the XO_N input and the XO_P input shall be left unconnected. Antenna The ANT pin should be connected to a 50 antenna interface, thereby supporting the best signal strength performance. Ericsson Microelectronics' partners can support application specific antennas. Input Control There are six digital inputs available for controlling the radio features of the PBA 313 01. The Bluetooth timing requirements for these are decribed in figure 6. In addition, there is a digital input signal for hardware reset of the radio, and a digital input signal for waking up the clock circuitry after a sleep mode period. Receive-on control is active 'high'. Activate this signal to enable reception of Bluetooth data on the RX_DATA pin. The transmit-on control (TX_ON) must be deactivated and the synthesiser (SYNT_ON) activated if data is to be received. PX_ON Packet switch on control is active 'high'. Activate this signal during reception of a Bluetooth payload. PX_ON is used to control the Dynamic Automatic Frequency Compensation (DAFC) of the receiver. Since the General Inquiry Access Code (GIAC), information in a Bluetooth packet header contains an equal number of one's (+FMOD) and zero's (-FMOD), the average frequency will always be centered on the carrier frequency. This provides the DAFC with the reference for the fast tuning. If the fast mode is not used during the header then the first bits could be interpreted incorrectly. The slow mode gives a more accurate FSK compensation of the thresholds for a one and a zero compared to the fast mode; therefore, the BER is less. The fast mode (time constant <2s) is used when PX_ON is deactived and the slow mode (time constant <50s) when it is activated. TX_ON Transmit-on control is active 'high'. Activate this signal to enable radio signal output on the ANT pin. The actual transfer of data that exists on the TX_DATA input occurs when PHD_OFF goes 'high'. The receive-on control, RX_ON, must also be 'low' if data is to be transmitted. SYNT_ON Synthesizer on control is active 'high'. Activate this signal to power up of the VCO section of the radio. SYNT_ON is used in both transmit and receive mode. VCC RX_ON RX_DATA PX_ON Serial interface 4 PINS tTO Input control tTD 6 PINS PBA 313 01 Output control 4 PINS Data interface 4 PINS POR_EXT XO_N CLOCK 13 MHz 11 PINS XO_P RX SLOT TX_ON PHD_OFF TX_DATA VCC_VCO ANTENNA TX SLOT SYNT_ON SI_CDI t PHD tD tR O tD tRD tS tS Baseband Symbol Parameter tS tS tS tTO tTD tPHD tD tD tD tRO tRD One Slot time Two Slot times Three Slot times Transmitter On delay Delay before transmitting data Phase Detector Off delay after tTO Data sending period, one slot Data sending period, two slots Data sending period, three slots Receiver On delay Delay before receiving data Min 203 Typical 102 213 104 175 213 Max 625 1875 3125 223 366 1598 2862 213 Unit s s s s s s s s s s s GROUND Figure 5. System overview. 6 Figure 6 and table 2. Timing sequence for data transmission. EN/LZT 146 65 R3B (c) Ericsson Microelectronics AB, October 2001 PBA 313 01 PHD_OFF TX_CLK Phase detector off control is active 'high'. Activate this signal in transmit mode to open the phase locked loop (PLL) employed in the VCO synthesizer section and enable modulation of the carrier using the TX_DATA digital input. PHD_OFF is activated after the initialization of the SYNT_ON signal and the TX_ON signal, see figure 6 and table 2. 1 MHz transmit clock digital output available for the baseband circuitry when the POR_EXT and SYS_CLK_REQ (see above) are both 'high'. TX_CLK changes value on rising edges of SYS_CLK. POR_EXT External power on reset is active 'high'. An external poweron-reset digital input signal that will reset the radio controller and its registers. A reset will occur on the positive edge of POR_EXT signal. SYS_CLK_REQ System clock request control is active 'high'. Once the crystal oscillator bit (XOCTR, control register, bit #2) has been set, use this control to switch off (sleep mode) and wake up (idle and operating modes) the reference clock circuitry and corresponding 13MHz and 1MHz clock output ports of the module. Output Control There are four digital output control signals available for controlling external baseband circuitry. POR Power-on-reset digital output is activated after the power has been applied to the Bluetooth radio or on a positive edge of the POR_EXT digital input. POR has a transition from 'low' to 'high' after four clock cycles have been delivered to the baseband chip, see figure 7. LPO_CLK 3.2 kHz low power oscillator clock digital output that is adjustable by setting the internal LPOHI and LPOLO registers (see Design Considerations). The clock output is available as soon as the power supply is applied and POR_EXT is 'high' (figure 7). The LPO is necessary for wake-up timing in the baseband circuitry, if the Ericsson baseband is used. LPO_CLK must be trimmed to 1/2 LSB from 3.2 kHz or calibrated within 230 ppm, using SYS_CLK or TX_CLK. Data Interface Two digital signals are used for data flow over the air interface. TX_DATA Transmit data digital control is active 'high'12). The radio module feeds Bluetooth data (1Mbit/s) directly to the radio frequency modulator when PHD_OFF is activated. The total delay from the TX_DATA pin to the ANT pin is typically 0.5s. RX_DATA Receive data digital output is active 'high'. The radio module latches out Bluetooth data (1 Mbit/s) on the RX_DATA pin on each falling edge of SYS_CLK when RX_ON is activated. The total delay from the ANT pin to the RX_DATA pin is typically 2.5s. SYS_CLK 13 MHz system clock digital output available for the baseband circuitry when the POR_EXT and SYS_CLK_REQ are both 'high'. SYS_CLK will also be available during startup, independent on the value of SYS_CLK_REQ, see figure 7. 0 0.5ms 1.0ms 1.5ms 12) Data on the TX_DATA pin is digitally buffered before it is fed to the radio frequency modulator. The polarity of this input can be set to normal by writing `1' or inverted by writing `0' to bit 0 of the Enable register. 2.0ms 2.5ms VCC Vcc POR_EXT '1' SYS_CLK_REQ 3.0ms 3.5ms 4.0ms '0' or '1 ' LPO_CLK Control Register 10000XX SYS_CLK POR Figure 7. Powering up the module. EN/LZT 146 65 R3B (c) Ericsson Microelectronics AB, October 2001 7 PBA 313 01 Serial Interface The serial control interface is a JTAG Boundary-Scan Architecture (IEEE Std 1149.1). Interconnection between the serial interface and the external controller (baseband circuit) consists of four 1-bit digital signals; control data input (SI_CDI), control mode select (SI_CMS), control clock (SI_CLK) and control data output (SI_CDO). The timing of these signals are defined in figure 8. State Diagram The serial interface (SI) is operational when POR is 'high'. The state diagram is shown in figure 9. Transitions from one state to another depend on the SI_CMS input at the rising edge of SI_CLK. The SI controller is normally kept in the RunControl/Idle state. SI_CMS and SI_CDI should change value at the falling edge of SI_CLK. The SI_CDO output will also change at the falling edge of SI_CLK. Four types of instruction registers (table 3) can be accessed in an IR-Scan. Performing an IR-Scan with IR=01YYYY selects one of the data register in the radio. Reference source not SI_ CLK SI_ CMS SI _CDI SI _CDO IR Description 00 EXTEST (no action) 01YYY Selection of a Data Register 10 SAMPLE/PRELOAD (no action) 11 BYPASS Table 3. Instruction registers. Data register scans (DR-Scan) transfer 8 bits data from the readable register at address 01YYYY to SI_TDO, and 8 bits of data from SI_TDI to the writable register at the same address, in one single operation. See figure 10. Table 5 lists the different registers in the radio controller, their read or write operation, address, and content after a reset. The functionality is described in table 4. Delay bit 7: bit 6: bit 5-3: Delay PHD_OFF negative edge 6 us. Delay SYNT_ON negative edge 6 us.. Reserved. Channel bit 7: bit 6-0: RX/TX - Receive (1) or Transmit (0) channel Channel value - 0 - 127 decimal RSSI bit 4-0: t1 t2 found. IR starting with the bit code 11 allows serial data to be by-passed from SI_CDI to SI_CDO. The EXTEST and SAMPLE/PRELOAD instructions have no action. t SI_CLK2 t SI_CLK Min 200 76 20 tSI_CLK tSI_CLK2 t1 t2 Typ 250 76 Max 20 XO-trim bit 5-0: Unit ns ns ns ns ID bit 7-4: bit 3-0: Figure 8. Timing diagram of the serial interface. LPOLO bit 7-0: 1 ControlLogic-Reset 0 Run Control/Idle LPOHI bit 0: 0 1 Select-DRScan 1 Select-IRScan 0 1 1 Capture-IR 0 0 Shift-DR Shift-IR 0 1 1 Exit1-IR Exit2-DR Pause-IR 0 0 Update-DR 0 1 0 Exit2-IR 1 1 Modulation bit 6-4: 1 0 1 0 0 1 0 Pause-DR Control bit 6-3: bit 2: 0 CaptureDR Exit1-DR 1 1 1 Update-IR 0 Figure 9. State machine for serial interface control. '0' denotes a logic level 'low' and '1' level 'high' level on the SI_CMS control pin. 8 bit 3-0: Current bit 7-5: Enable bit 7-6: bit 5-1: bit 0: Received signal strength indicator, lower input power gives lower RSSI value. Trim value for the internal capacitor load of the crystal (0 = 0 pF, 63 = 8 pF) Chip identity, Radio Controller = 0001. Chip version number. Eight least significant bits of the LPO frequency adjust value (LPO7-LPO0). LPO8:0 = 0 gives maximum fLPO and 511 mininum fLPO. Most significant bit of the LPO adjust value (LPO8). LPO coarse trimming, lower value gives higher fLPO. Crystal oscillator control. After POR has been activated, a 0 to 1 transition enables the SYS_CLK_REQ control pin. TX modulation amplitude. 0 gives 10% higher than the nominal value, 7 gives 10% lower. Reserved. Reserved. Reserved Amplifier power control. 00000=On, 11111=Off. Polarity of TX_DATA. 1 = positive, 0 = negative polarity. Table 4. Description of registers. EN/LZT 146 65 R3B (c) Ericsson Microelectronics AB, October 2001 PBA 313 01 Register name VCO/DAFC/Delay Channel RSSI XO-trim ID LPO-hi LPO-lo Control Modulation Current Enable # bits R or W Address Value at reset 8 8 5 6 8 1 8 7 8 3 8 W W R W R W W W W W W 0100012 = 1710 0100102 = 1810 00000X00 00000010 XXXUUUUU XX 0 0 0 0 0 0 0 0 0 1 VVVV XXXXXXX 0 00000000 X 1 0 0 0 0 XX 00000000 0 0 0 XXXXX UUUUUUUU 0100112 = 1910 0101012 = 2010 0101002 = 2110 0101102 = 2210 0101112 = 2310 0110002 = 2410 0110012 = 2510 Recommended value 1111 10112 = 25110 Bit two set to 1 to enable SYS_CLK_REQ 0100 00002 = 6410 0000 00002 = 010 1011 11112 = 19110 W = Writable, R = Readable, X = Not applicable, U = Undefined, V = Version number Table 5. Data registers in the radio controller. 1 5 10 15 20 5 SI_CLK SI_CMS i2 i3 i4 i5 Q0 Q1 Q2 Q3 D4 D5 Q4 Q5 D6 D7 Q6 Q7 Run Control/Idle D3 Update DR D2 Exit DR i1 JTAG controller state D1 Shift DR i0 Capture DR SI_CDO Select DR-Scan D0 Update IR I5 Exit IR I4 Shift IR I3 Capture IR I2 Select IR-Scan I1 Select DR-Scan I0 Run Control/Idle SI_CDI Figure 10. Reading and updating a data register. A data register is selected by entering the Shift IR state using SI_CMS, and transferring the appropriate bit code to the instruction register using SI_CDI (I[5:0]=01YYYY, where YYYY is the address of the register). Moving to the Shift-DR state, eight bits of register data can then be transferred on SI_CDI and SI_CDO. The data register selected by the instruction register is updated when the SI controller enters the Update-DR state. At the end of the data register access, the SI controller is once again held in the Run Control/Idle state. Serial interface example Writing the value 77 to the Channel register selects Bluetooth channel 75 (i.e. 2477 MHz) for transmission. This will simultaneously read the RSSI measurement for the latest received packet header. The normal operation sequence is: * Point out the Channel register, this is done by performing an IR-scan. The SI_CMS signal should be controlled as shown in figure 10. When in the Shift-IR state the value 010010 should be shifted in on the SI_CDI input (LSB first). When in the Run Control/Idle state the Instruction Register is updated. * Write the new channel value, this is done by performing a DR-scan. The SI_CMS signal should be controlled as shown in figure 10. When in the Shift-DR state, SI_CDI= 01001101 should be shifted in (LSB first). When in the Run Control/Idle state the Channel register is updated. EN/LZT 146 65 R3B (c) Ericsson Microelectronics AB, October 2001 If no other register has been addressed then the Channel register contents are still in the IR, therefore only a new DR-scan needs to be done to change to another frequency channel. Design Considerations Power-up sequence The start-up sequence is as follows, see figure 11 for typical timing: 1. The start-up sequence starts with a Power-On-Reset (POR_EXT) or by applying power to VCC. This resets all the registers in the radio controller. 2. The LPO_CLK starts to oscillate. 9 PBA 313 01 3. The 13 MHz clock circuitry stabilises and is output to the CLK_REF pin. POR is activated when four complete cycles have been delivered to the baseband. 4. The baseband should now initiate the XO-trim register, Control, Modulation and LPO registers. The XO-trim register should be set to the stored calibration value from the production calibration. The Control and Modulation register should be set to the recommended values for normal operation. 5. The LPO frequency must be adjusted to 3.2 kHz. This is done by comparing LPO_CLK with a fraction of the system clock frequency, SYS_CLK. The initial calibration of the LPO can use a successive approximation algorithm that adjusts the LPO register value from its mid value (256) in finer and finer steps until satisfied accuracy has been achieved. This compensates for oscillator frequency variations due to process variations of the resistors and capacitors. Thereafter, calibration of the LPO only has to be done due to temperature and voltage variations by increments or decrements of the LPO register value. 6. The Bluetooth radio and the baseband is now initialized up to the point that is normally called stand-by mode. 7. To activate the radio and be ready for transmission/ receive, write the value 111110112 = 25110 to the VCO/ DAFC control register and the value 101111112 = 19110 to the Enable register. 8. To enter sleep mode power down the crystal by resetting SYS_CLK_REQ. Bit 2 in the control register must be set to enable SYS_CLK_REQ. Ground Ground should be distributed with very low impedance as a ground plane. Connect all GND connections to the ground plane. It is critical to have a ground plane underneath the Bluetooth radio in order to shield the VCO tank from any electrical noise, see figure 12. The ground vias purpose is to connect the local ground plane to the main ground layer. Note: If a local ground plane cannot be directly placed underneath the radio, then no routing should be planned underneath the radio until a layer can be used as a local ground plane. The Bluetooth radio will be self shielding and no additional shields should be necessary for normal operating conditions. VCC VCC_IO V CC_IO TX_DATA V CC_IO RS232 RS232 Transceiver RX_DATA UART VCC SI_CMS SI_CMI Memory GND ADDR Baseband ASIC or DATA CTRL Data Interface SI_CLK GND Baseband functionality (DSP) VCC_VCO VCC VCC Bluetooth Radio PBA 313 01 Serial Interface SI_CDO POR_EXT TX_ON RX_ON PHD_OFF SYNT_ON ANT Input Control PX_ON SYS_CLK_REQ VCC CODEC TX_CLK PCM POR LPO_CLK GND XO_P Output Control XO_N SYS_CLK GND CRYSTAL GND GND Figure 11. Typical UART or PCM configuration. 10 EN/LZT 146 65 R3B (c) Ericsson Microelectronics AB, October 2001 PBA 313 01 Ground vias 1 34 33 32 31 30 29 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 11 19 12 13 14 15 16 17 18 Figure 12. Example of local ground plane underneath the Bluetooth Radio. Application schematic ANT POR SYS_CLK EXT INT1 EXT INT1 Bluetooth Radio PBA 313 01 POR Bluetooth Baseband Qualified for 1.0B or 1.1 Figure 13. Example of interface between Ericsson Bluetooth Baseband and Bluetooth Radio. EN/LZT 146 65 R3B (c) Ericsson Microelectronics AB, October 2001 11 Marking Packing Module marking All devices will be delivered in tape & reel protecting them from electrostatic discharges and mechanical shock (see figure 15). The tape width is 24 mm and the component centre to centre distance is 16 mm. The size of the reel is 13". The number of parts per reel is 1500 units. Each transceiver module is marked with the following information on the top side of the ceramic substrate (see figure 14): a) Ericsson logotype. b) Internal number. c) Ericsson Microelectronics product number and version. d) Manufacturing year and week, factory code and batch number. Reel marking Each reel is marked with the following information: a) Ericsson logotype. b) Internal number. c) Ericsson Microelectronics product number and version. d) Number of components on the reel. e) Manufacturing year and week, factory code and batch number. The marking is also printed in bar-code format. Figure 15. Carrier tape dimensions. ROK101002/1 PBA31301/2S 00W42 FFF BBB Pin 1 Figure 14. Top view with marking example and pin one indicator. Ericsson Microelectronics SE-164 81 Kista, Sweden Telephone: +46 8 757 50 00 Internet: www.ericsson.com/microelectronics For local sales contacts, please refer to our website or call: Int + 46 8 757 47 00, Fax: +46 8 757 47 76 Ordering Information BT Specification 1.0b 1.1 Part No. PBA 313 01/2S PBA 313 01/3S Information given in this data sheet is believed to be accurate and reliable. However no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Ericsson Microelectronics. These products are sold only according to Ericsson Microelectronics' general conditions of sale, unless otherwise confirmed in writing. Specifications subject to change without notice. The latest and most complete information can be found on our website Preliminary Data Sheet EN/LZT 146 65 R3B (c) Ericsson Microelectronics AB, October 2001