Utopia Level 2 Master Interface Macrocell For Quicklogic Eclipse and QuickSD ESP Product Brief Version 1.1 February 2001 Introduction The Utopia (Universal Test & Operations PHY Interface for ATM) interface is defined by the ATM Forum to provide a standard interface between ATM devices and ATM PHY or SAR (Segmentation and Re-Assembly) devices. The ATM forum has standardized the Utopia Level 2 (L2) which can handle aggregated throughputs of 622Mbps (OC-12 Rates). The Utopia L2 can be used in single or multi PHY applications. The Master polls the Slave device(s) to get cell availability status, selects and initiates data transfers to / from the Slave device(s). The Utopia Level 2 Master Macrocell from MorethanIP is designed for ease of use performance and provides the required flexibility to be used in a wide range of applications. * Packet rate decoupling with fully User programmable (Depth) FIFOs * Optional odd Parity checking / generation on the Utopia Ingress / Egress interfaces * Programmable Single PHY or Multi PHY (MPHY) operation with Out-Band addressing * Programmable number of PHY port from 1 (Single PHY operation) to 31 * Round robin Egress port arbitration when used in MPHY mode to guarantee fairness between the multiple PHYs * Advanced management options with error handling, Utopia protocol violation check and non compliant cell discard * Simple User application interface with a two signals handshake simplifying the user application design and integration * Delivered with a complete and programmable simulation environment * Scripts for Synplicity / Modelsim synthesis / simulation tools provided * Delivered in VHDL source code for easy integration and with a platform independent JAVA configuration utility * Optimized FIFO with Eclipse specific embedded memory blocks for high integration and speed Features * Compliant with ATM-Forum af-phy0039.000 * Programmable Utopia Level-2 data width (8, 16-Bit) * Meets 50MHz performance and 16-Bit interface operation supporting 800Mbps (Exceeding OC12 requirements) packet rate transfers * Selectable Octet Level or Cell Level transfers supported with Polled or Direct status indication and User programmable FIFO thresholds 1 Utopia Level 2 Master Interface Macrocell For Quicklogic Eclipse and QuickSD ESP Product Brief Version 1.1 February 2001 Application RxClav RxEnb* RxAddr[4:0] RxData[15:0] RxSoc RxClk MPHY Device 1 TxClav TxEnb* TxAddr[4:0] RxClav RxEnb* RxAddr[4:0] User Application TxData[15:0] TxSoc RxData[15:0] RxSoc RxClk TxClk TxClav TxEnb* TxAddr[4:0] TxData[15:0] TxSoc TxClk RxClav RxEnb* RxAddr[4:0] Eclipse / QuickSD RxData[15:0] RxSoc RxClk MPHY Device 2 TxClav TxEnb* TxAddr[4:0] TxData[15:0] TxSoc TxClk Application Example - L2 MPHY Polled Status Indication Block Diagram Port 0 Status Parity Generation Data POS Status Data Port N Control State-Machine Round Robin Arbiter Port Arbitration Direct Status Multiplexed Polling Port 0 Data Parity Check Status Data Status Control State-Machine Port N Block Diagram 2 Utopia Level 2 Master Interface Macrocell For Quicklogic Eclipse and QuickSD ESP Product Brief Version 1.1 February 2001 Design Kit Overview Design Files Language Simulation System Verification Technology optimized VHDL Configurable VHDL Testbench with 34 different simulation scenarios verifying the Macrocell features and simulating non Utopia compliance behavior The Testbench implements a Utopia model to exercise the Macrocell. Design Tools Simulation Modelsim Version 5.4d Scripts (do files) provided Synthesis Synplicity Synplify v6.1.3 Implementation Quickworks v9.0 References * * * ATM Forum, af-phy-0039.000 Quicklogic, Eclipse Family Datasheet (Preliminary, 8/24/2000) Quicklogic, QL82SD QuickSD Programmable Serdes (Preliminary, 8/25/2000) Contact MorethanIP Tel : +49 (0) 89 3219599 0 FAX : +49 (0) 89 3219599 1 E-Mail : info@morethanip.com Internet : www.morethanip.com QuickLogic Corp. Tel : 408 990 4000 (US) : + 44 1932 57 9011 (Europe) : + 49 89 930 86 170 (Germany) : + 852 8106 9091 (Asia) : + 81 45 470 5525 (Japan) E-mail : info@quicklogic.com Internet : www.quicklogic.com 3