1-Mbit (128K x 8) Static RAM
CY62128E
MoBL®
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05485 Rev. *D Revised November 02, 2006
Features
• Very high speed: 45 ns
• Voltage range: 4.5V–5.5V
• Pin-compatible with CY62128B
• Ultra-low standby power
—Typical standby current: 1 µA
—Maximum standby current: 4 µA
• Ultra-low active power
— Typical active current: 1.3 mA @ f = 1 MHz
• Easy memory expansion with CE1, CE2 and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Offered in standard lead-free 32-lead STSOP, 450 mil-wide
32-lead SOIC, and 32-lead TSOP-I packages
Functional Description[1]
The CY62128E is a high-performance CMOS static RAM
organized as 128K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption when addresses are not toggling.
The device can be put into standby mode reducing power
consumption by more than 99% when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE1) and Write Enable (WE) inputs LOW and Chip Enable
(CE2) input HIGH. Data on the eight I/O pins (I/O0 through
I/O7) is then written into the location specified on the address
pins (A0 through A16).
Reading from the device is accomplished by taking Chip
Enable (CE1) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable (CE2) HIGH. Under these
conditions, the contents of the memory location specified by
the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
The CY62128E is available in 32-lead STSOP, 450 mil-wide
32-lead SOIC, 32-lead TSOP-I, and 32-lead Reverse TSOP-I
packages
Logic Block Diagram
Note
1.For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
15
A1
A2
A3
A4
A
5
A6
A7
A8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
Data in Drivers
POWER
DOWN
WE
OE
I/O0
I/O1
I/O2
I/O3
128K x 8
ARRAY
I/O7
I/O6
I/O5
I/O4
A
0
A12
A14
A13
A
A16
A9
A10
A11
CE1
CE2
CY62128E
MoBL®
Document #: 38-05485 Rev. *D Page 2 of 12
Pin Configuration[2]
A6
A7
A16
A14
A12
WE
VCC
A4
A13
A8
A9
OE
STSOP
Top View
(not to scale)
30
28
29
31
24
19
23
22
21
20
18
13
17
16
15
14
11
12
I/O2
I/O1
GND
I/O7
I/O4
I/O5
I/O6
I/O0
CE1
A11
A59
10
32
1
2
3
4
5
6
7
8
CE2
A15
NC
A10
I/O3
A1
A0
A3
A2
26
25
26
27
A6
A7
A16
A14
A12
WE
VCC
A4
A13
A8
A9
OE
TSOP I
Top View
(not to scale)
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
I/O2
I/O1
GND
I/O7
I/O4
I/O5
I/O6
I/O0
CE1
A11
A517
18
8
9
10
11
12
13
14
15
16
CE2
A15
NC
A10
I/O3
A1
A0
A3
A2
1
2
3
4
5
6
7
8
9
10
11
14 19
20
24
23
22
21
25
28
27
26
Top View
SOIC
12
13
29
32
31
30
16
15
17
18
GND
A16
A14
A12
A7
A6
A5
A4
A3
WE
VCC
A15
A13
A8
A9
I/O7
I/O6
I/O5
I/O4
A2
NC
I/O0
I/O1
I/O2
CE1
OE
A10
I/O3
A1
A0
A11
CE2
Notes
2. NC pins are not connected on the die.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C
4. When used with a 100 pF capacitive load and resistive loads as shown on page 4, access times of 55 ns (tAA, tACE) and 25 ns (tDOE) are guaranteed.
5. Automotive product information is Preliminary.
Product Portfolio
Product VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC (mA) Standby ISB2 (µA)
f = 1MHz f = fmax
Min. Typ.[3] Max. Typ.[3] Max. Typ.[3] Max. Typ.[3] Max.
CY62128E-45LL 4.5 5.0 5.5 45 [4] 1.3 2 11 16 1 4
CY62128E-55LL 4.5 5.0 5.5 55 1.3 411 35 130
CY62128E
MoBL®
Document #: 38-05485 Rev. *D Page 3 of 12
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground
Potential..............................–0.5V to 6.0V (VCC(MAX) + 0.5V)
DC Voltage Applied to Outputs
in High-Z State[6, 7]...............–0.5V to 6.0V (VCC MAX + 0.5V)
DC Input Voltage[6, 7] ...........–0.5V to 6.0V (VCC MAX + 0.5V)
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range
Range Ambient
Temperature VCC[8] Speed
Industrial –40°C to +85°C 4.5V to 5.5V 45 ns
Automotive –40°C to +125°C 55 ns
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions 45 ns 55 ns Unit
Min. Typ.[3] Max. Min. Typ.[3] Max.
VOH Output HIGH
Voltage
IOH = –1 mA VCC = 4.5V 2.4 2.4 V
VOL Output LOW
Voltage
IOL = 2.1 mA VCC = 4.5V 0.4 0.4 V
VIH Input HIGH
Voltage
VCC = 4.5V to 5.5V 2.2 VCC + 0.5 2.2 VCC + 0.5 V
VIL Input LOW voltage VCC = 4.5V to 5.5V –0.5 0.8 –0.5 0.8 V
IIX Input Leakage
Current GND < VI < VCC –1 +1 –1 +1 µA
IOZ Output Leakage
Current GND < VO < VCC, Output
Disabled –1 +1 –1 +1 µA
ICC VCC Operating
Supply Current f = fMAX = 1/tRC VCC = VCCmax
IOUT = 0 mA
CMOS levels
11 16 11 35 mA
f = 1 MHz 1.3 2 1.3 4
ISB2 Automatic CE
Power-down
Current—CMOS
Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = VCCmax
14 130 µA
Capacitance (for all packages)[9]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
10 pF
COUT Output Capacitance 10 pF
Thermal Resistance
Parameter Description Test Conditions SOIC
Package
STSOP
Package
TSOP
Package Unit
ΘJA Thermal Resistance
(Junction to Ambient)[9] Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
48.67 32.56 33.01 °C/W
ΘJC Thermal Resistance
(Junction to Case)[9] 25.86 3.59 3.42 °C/W
Notes
6. VIL(min.) = –2.0V for pulse durations less than 20 ns.
7. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.
8. Full device AC operation assumes a 100-µs ramp time from 0 to VCC(min) and 200-µs wait time after VCC stabilization.
9. Tested initially and after any design or process changes that may affect these parameters.
CY62128E
MoBL®
Document #: 38-05485 Rev. *D Page 4 of 12
AC Test Loads and Waveforms
Parameters Value Unit
R1 1800 Ω
R2 990 Ω
RTH 639 Ω
VTH 1.77 V
Data Retention Characteristics (Over the Operating Range)[10]
Parameter Description Conditions Min. Typ.[3] Max. Unit
VDR VCC for Data Retention 2 V
ICCDR Data Retention Current VCC= VDR CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
Industrial 4 µA
Automotive 30 µA
tCDR[10] Chip Deselect to Data
Retention Time 0ns
tR[11] Operation Recovery Time tRC ns
3.0VVCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
Notes
10. When CE is LOW, CE1 is LOW and CE2 is HIGH. When CE is HIGH, CE1 is HIGH or CE2 is LOW.
11. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs.
Data Retention Waveform[10,11]
VCC(min)
VCC(min)
tCDR
VDR >2 V
DATA RETENTION MODE
tR
VCC
CE
CY62128E
MoBL®
Document #: 38-05485 Rev. *D Page 5 of 12
Notes
12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3ns (1V/ns) or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3V, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
14. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.
15. The internal Write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
Switching Characteristics Over the Operating Range[10, 12]
Parameter Description 45 ns 55 ns Unit
Min. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 45 55 ns
tAA Address to Data Valid 45 55 ns
tOHA Data Hold from Address Change 10 10 ns
tACE CE LOW to Data Valid 45 55 ns
tDOE OE LOW to Data Valid 22 25 ns
tLZOE OE LOW to LOW Z[13] 55ns
tHZOE OE HIGH to High Z[13, 14] 18 20 ns
tLZCE CE LOW to Low Z[13] 10 10 ns
tHZCE CE HIGH to High Z[13, 14] 18 20 ns
tPU CE LOW to Power-up 0 0ns
tPD CE HIGH to Power-down 45 55 ns
Write Cycle[15]
tWC Write Cycle Time 45 55 ns
tSCE CE LOW to Write End 35 40 ns
tAW Address Set-up to Write End 35 40 ns
tHA Address Hold from Write End 0 0ns
tSA Address Set-up to Write Start 0 0ns
tPWE WE Pulse Width 35 40 ns
tSD Data Set-up to Write End 25 25 ns
tHD Data Hold from Write End 0 0ns
tHZWE WE LOW to High-Z[13, 14] 18 20 ns
tLZWE WE HIGH to Low-Z[13] 10 10 ns
CY62128E
MoBL®
Document #: 38-05485 Rev. *D Page 6 of 12
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[16, 17]
Read Cycle No. 2 (OE Controlled)[10, 17, 18]
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
DATA OUT HIGH IMPEDANCE IMPEDANCE
I
CC
I
SB
t
HZOE
t
HZCE
t
PD
OE
CE
HIGH
V
CC
SUPPLY
CURRENT
ADDRESS
Notes
16. The device is continuously selected. OE, CE = VIL.
17. WE is HIGH for read cycle.
18. Address valid prior to or coincident with CE transition LOW.
CY62128E
MoBL®
Document #: 38-05485 Rev. *D Page 7 of 12
Write Cycle No. 1 (WE Controlled)[10, 15, 19, 20]
Write Cycle No. 2 (CE Controlled)[10, 15, 19, 20]
Switching Waveforms (continued)
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
DATA I/O
ADDRESS
CE
WE
OE
t
HZOE
DATA
IN
VALID
NOTE
21
t
SCE
t
WC
t
WC
DATA
IN
VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
CE
ADDRESS
WE
DATA I/O
OE
Notes
19. Data I/O is high impedance if OE = VIH
20. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state
21. During this period, the I/Os are in output state and input signals should not be applied.
CY62128E
MoBL®
Document #: 38-05485 Rev. *D Page 8 of 12
Write Cycle No. 3 (WE Controlled, OE LOW)[10, 20]
Switching Waveforms (continued)
DATA I/O
ADDRESS
t
HD
t
SD
t
LZWE
t
SA
t
HA
t
AW
t
WC
CE
WE
t
HZWE
DATA
IN
VALID
NOTE 21
t
PWE
t
SCE
Truth Table
CE1CE2WE OE Inputs/Outputs Mode Power
H X X X High Z Deselect/Power-down Standby (ISB)
X L X X High Z Deselect/Power-down Standby (ISB)
L H H L Data Out Read Active (ICC)
L H L X Data In Write Active (ICC)
L H H H High Z Selected, Outputs Disabled Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
45 CY62128ELL-45SXI 51-85081 32-Lead 450-Mil SOIC (Pb-Free) Industrial
CY62128ELL-45ZAXI 51-85094 32-Lead STSOP (Pb-Free)
CY62128ELL-45ZXI 51-85056 32-Lead TSOP Type I (Pb-Free)
55 CY62128ELL-55SXE 51-85081 32-Lead 450-Mil SOIC (Pb-Free) Automotive
CY62128ELL-55ZAXE 51-85094 32-Lead STSOP (Pb-Free)
CY62128ELL-55ZXE 51-85056 32-Lead TSOP Type I (Pb-Free)
Please contact your local Cypress sales representative for availability of these parts
CY62128E
MoBL®
Document #: 38-05485 Rev. *D Page 9 of 12
Package Diagrams
Figure 1. 32-Lead (450 Mil) Molded SOIC (51-85081)
0.546[13.868]
0.440[11.176]
0.101[2.565]
0.050[1.270]
0.014[0.355]
0.118[2.997]
0.004[0.102]
0.047[1.193]
0.006[0.152]
0.023[0.584]
0.793[20.142]
0.450[11.430]
0.566[14.376]
0.111[2.819]
0.817[20.751]
BSC.
0.020[0.508]
MIN.
MAX.
0.012[0.304]
0.039[0.990]
0.063[1.600]
SEATING PLANE
116
17 32
0.004[0.102]
51-85081-*B
CY62128E
MoBL®
Document #: 38-05485 Rev. *D Page 10 of 12
Figure 2. 32-Lead Shrunk Thin Small Outline Package (8 x 13.4 mm) (51-85094)
Package Diagrams (continued)
51-85094-*D
CY62128E
MoBL®
Document #: 38-05485 Rev. *D Page 11 of 12
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Figure 3. 32-Lead Thin Small Outline Package Type I (8 x 20 mm) (51-85056)
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names
mentioned in this document are the trademarks of their respective holders.
Package Diagrams (continued)
51-85056-*D
CY62128E
MoBL®
Document #: 38-05485 Rev. *D Page 12 of 12
Document History Page
Document Title: CY62128E MoBL® 1-Mbit (128K x 8) Static RAM
Document Number: 38-05485
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 203120 See ECN AJU New data sheet
*A 299472 See ECN SYT Converted from Advance Information to Preliminary
Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns, respectively
Changed tDOE from 15 ns to 18 ns for 35 ns speed bin
Changed tHZOE, tHZWE from 12 and 15 ns to 15 and 18 ns for the 35 and 45 ns
speed bins, respectively
Changed tHZCE from 12 and 15 ns to 18 and 22 ns for the 35 and 45 ns speed bins,
respectively
Changed tSCE from 25 and 40 ns to 30 and 35 ns for the 35 and 45 ns speed bins,
respectively
Changed tSD from 15 and 20 ns to 18 and 22 ns for the 35 and 45 ns speed bins,
respectively
Added lead-free package information
Added footnote #9
Changed operating range for SOIC package from Commercial to Industrial
Modified signal transition time from 5 ns to 3 ns in footnote #11
Changed max of ISB1, ISB2 and ICCDR from 1.0 µA to 1.5 µA
*B 461631 See ECN NXR Converted from Preliminary to Final
Included Automotive Range and 55 ns speed bin
Removed 35 ns speed bin
Removed “L” version of CY62128E
Removed Reverse TSOP I package from Product offering
Changed ICC (Typ) from 8 mA to 11 mA and ICC (Max) from 12 mA to 16 mA for f = fmax
Changed ICC (Max) from 1.5 mA to 2.0 mA for f = 1 MHz
Removed ISB1 DC Specs from Electrical characteristics table
Changed ISB2 (Max) from 1.5 µA to 4 µA
Changed ISB2 (Typ) from 0.5 µA to 1 µA
Changed ICCDR (Max) from 1.5 µA to 4 µA
Changed the AC Test load Capacitance value from 100 pF to 30 pF
Changed tLZOE from 3 to 5 ns
Changed tLZCE from 6 to 10 ns
Changed tHZCE from 22 to 18 ns
Changed tPWE from 30 to 35 ns
Changed tSD from 22 to 25 ns
Changed tLZWE from 6 to 10 ns
Updated the Ordering Information Table
*C 464721 See ECN NXR Updated the Block Diagram on page # 1
*D 563144 See ECN AJU Added footnote 4 on page 2
