© Semiconductor Components Industries, LLC, 2016
October, 2016 − Rev. 2 1Publication Order Number:
ESD7471/D
ESD7471, SZESD7471
Ultra-Low Capacitance ESD
Protection
Micro−Packaged Diodes for ESD Protection
The ESD7471 is designed to protect voltage sensitive components
that require ultra-low capacitance from ESD and transient voltage
events. Excellent clamping capability, low capacitance, high
breakdown voltage, high linearity, low leakage, and fast response time
make these parts ideal for ESD protection on designs where board
space is at a premium. It has industry leading capacitance linearity
over voltage making it ideal for RF applications. This capacitance
linearity combined with the extremely small package and low
insertion loss makes this part well suited for use in antenna line
applications for wireless handsets and terminals.
Features
•Industry Leading Capacitance Linearity Over Voltage
•Ultra−Low Capacitance: 0.35 pF Max
•Stand−off Voltage: 5.3 V
•Low Leakage: < 1 nA
•Low Dynamic Resistance: < 1 W
•IEC61000−4−2 Level 4 ESD Protection
•1000 ESD IEC61000−4−2 Strikes ±8 kV Contact / Air Discharged
•SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
•RF Signal ESD Protection
•RF Switching, PA, and Antenna ESD Protection
•Near Field Communications
•USB 2.0, USB 3.0
MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Rating Symbol Value Unit
IEC 61000−4−2 Contact (ESD) (Note 1)
IEC 61000−4−2 Air (ESD) (Note 1) ESD
ESD ±20
±20 KV
kV
IEC 61000−4−5 (ESD) (Note 2) ESD 2.2 A
Total Power Dissipation (Note 3) @ TA = 25°C
Thermal Resistance, Junction−to−Ambient °PD°
RqJA 300
400 mW
°C/W
Junction and Storage Temperature Range TJ, Tstg −55 to
+150 °C
Lead Solder Temperature − Maximum
(10 Second Duration) TL260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be af fected.
1. At least 10 discharges at TA = 25°C, per IEC61000−4−2 waveform.
2. Non−repetitive current pulse at TA = 25°C, per IEC61000−4−5 waveform.
3. Mounted with recommended minimum pad size, DC board FR−4
Device Package Shipping†
ORDERING INFORMATION
www.onsemi.com
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer t o our Tape and Reel Packaging Specification
s
Brochure, BRD8011/D.
ESD7471N2T5G XDFN2
(Pb−Free) 8000 / Tape &
Reel
MARKING
DIAGRAM
D = Specific Device Code
M = Date Code
G= Pb−Free Package
XDFN2
CASE 711AM D M
G
SZESD7471N2T5G XDFN2
(Pb−Free) 8000 / Tape &
Reel
ESD7471, SZESD7471
www.onsemi.com
2
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Symbol Parameter
IPP Maximum Reverse Peak Pulse Current
VCClamping Voltage @ IPP
VRWM Working Peak Reverse Voltage
IRMaximum Reverse Leakage Current @ VRWM
VBR Breakdown Voltage @ IT
ITTest Current
*See Application Note AND8308/D for detailed explanations of
datasheet parameters. Bi−Directional TVS
IPP
IPP
V
I
IR
IT
IT
IR
VRWM
VCVBR VRWM VC
VBR
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Parameter Symbol Condition Min Typ Max Unit
Reverse Working Voltage VRWM 5.3 V
Breakdown Voltage VBR IT = 1 mA (Note 4) 7.0 V
Reverse Leakage Current IRVRWM = 5.3 V < 1 50 nA
Clamping Voltage VCIPP = 1 A (Note 5) 13 15 V
Junction Capacitance CJVR = 0 V, f = 1 MHz
VR = 0 V, f = 1 GHz 0.24
0.24 0.35
0.35 pF
Dynamic Resistance RDYN TLP Pulse 0.8 W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1.
5. Non−repetitive current pulse at 25°C, per IEC61000−4−5 waveform.
TYPICAL CHARACTERISTICS
Figure 1. Typical IEC61000−4−2 + 8 kV Contact
ESD Clamping Voltage Figure 2. Typical IEC61000−4−2 − 8 kV Contact
ESD Clamping Voltage
TIME (ns) TIME (ns)
1501251007550250−25
−20
0
20
40
80
100
1501251007550250−25
−120
−100
−80
−60
−20
0
20
VOLTAGE (V)
VOLTAGE (V)
60
120
−40
ESD7471, SZESD7471
www.onsemi.com
3
IEC 61000−4−2 Spec.
Level Test Volt-
age (kV)
First Peak
Current
(A) Current at
30 ns (A) Current at
60 ns (A)
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
Ipeak
90%
10%
IEC61000−4−2 W aveform
100%
I @ 30 ns
I @ 60 ns
tP = 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
Figure 4. Diagram of ESD Clamping Voltage Test Setup
50 W
50 W
Cable
TVS Oscilloscope
ESD Gun
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD7471, SZESD7471
www.onsemi.com
4
Figure 5. Typical Positive TLP IV Curve Figure 6. Typical Negative TLP IV Curve
NOTE: TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns.
TLP CURRENT (A)
0
2
4
6
8
0
2
4
6
8
10
12
14
16
0 2 4 6 8 10 12 14 16 18 20 22 24 26
EQUIVALENT VIEC (kV)
VC, VOLTAGE (V)
0
2
4
6
8−16
−14
−12
−10
−8
−6
−4
−2
002468101214161820222426
TLP CURRENT (A)
EQUIVALENT VIEC (kV)
VC, VOLTAGE (V)
Transmission Line Pulse (TLP) Measurement
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 7. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 8 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
Figure 7. Simplified Schematic of a Typical TLP
System
DUT
LS÷
Oscilloscope
Attenuator
10 MW
VC
VM
IM
50 W Coax
Cable
50 W Coax
Cable
Figure 8. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
ESD7471, SZESD7471
www.onsemi.com
5
TYPICAL CHARACTERISTICS
Figure 9. IV Characteristics Figure 10. CV Characteristics
Figure 11. RF Insertion Loss Figure 12. Capacitance over Frequency
1.E−12
1.E−11
1.E−10
1.E−09
1.E−08
1.E−07
1.E−06
1.E−05
1.E−04
1.E−03
−12 −10 −8 −6 −4 −2 0 2 4 6 8 10 12
VOLTAGE (V)
I (A)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
−6 −5 −4 −3 −2 −1 0 1 2 3 4 5 6
Vbias (V)
CAPACITANCE (pF)
2
1E8 1E9 1E10 2E10
VOLTAGE (V)
0
−2
−4
−6
−8
−10
−12
−14
(dB)
2.0
0.5 FREQUENCY (GHz)
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
01.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5
ESD7471, SZESD7471
www.onsemi.com
6
PACKAGE DIMENSIONS
XDFN2 1.0x0.6, 0.65P (SOD−882)
CASE 711AM
ISSUE O
ÉÉ
ÉÉ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. EXPOSED COPPER ALLOWED AS SHOWN.
A B
E
D
BOTTOM VIEW
b
L
0.10 C
TOP VIEW
0.05 C
A
A1
0.10 C
0.10 C
CSEATING
PLANE
SIDE VIEW
DIM MIN MAX
MILLIMETERS
A0.34 0.44
A1 −−− 0.05
b0.43 0.53
D1.00 BSC
E0.60 BSC
SOLDER FOOTPRINT*
DIMENSIONS: MILLIMETERS
1.20
0.60
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
1
L0.20 0.30
0.47
RECOMMENDED
PIN 1
PIN 1
INDICATOR
e0.65 BSC
A
M
0.05 BC
A
M
0.05 BC
2X
e
e/2
2X 2X
NOTE 3
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ESD7471/D
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