AMP1600DMS3C - Advanced Micro Devices, Inc.

Preliminary Information

AMD Athlon MP

Processor Model 6

OPGA Data Sheet

for Multiprocessoultiprocessor

Platforms

Publication # 25480 Rev: D

Issue Date: June 2002

Preliminary Information

Trademarks

AMD, the AMD Arrow logo, AMD Athlon, AMD Duron, and combinations thereof, AMD-760, 3DNow!, and

QuantiSpeed are trademarks of Advanced Micro Devices, Inc.

HyperTransport is a trademark of the HyperTransport Technology Consortium

MMX is a trademark of Intel Corporation.

Other product names used in this publication are for identification purposes only and may be trademarks of

their respective companies.

The contents of this document are provided in connection with Advanced

Micro Devices, Inc. (“AMD”) products. AMD makes no representations or war-

ranties with respect to the accuracy or completeness of the contents of this

publication and reserves the right to make changes to specifications and prod-

uct descriptions at any time without notice. No license, whether express,

implied, arising by estoppel or otherwise, to any intellectual property rights is

granted by this publication. Except as set forth in AMD’s Standard Terms and

Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any

express or implied warranty, relating to its products including, but not limited

to, the implied warranty of merchantability, fitness for a particular purpose,

or infringement of any intellectual property right.

AMD’s products are not designed, intended, authorized or warranted for use

as components in systems intended for surgical implant into the body, or in

other applications intended to support or sustain life, or in any other applica-

tion in which the failure of AMD’s product could create a situation where per-

sonal injury, death, or severe property or environmental damage may occur.

AMD reserves the right to discontinue or make changes to its products at any

Table of Contents iii
25480D—June 2002 AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms
Preliminary Information
Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1
1.1 AMD Athlon™ MP Processor Model 6 Key 
Microarchitecture Summary  . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Interface Signals  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5
2.1 Overview  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Push-Pull (PP) Drivers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 AMD Athlon System Bus Signals   . . . . . . . . . . . . . . . . . . . . . . . 6
3 Logic Symbol Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7
4 Power Management   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9
4.1 Power Management States   . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Working State  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Stop Grant States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Probe State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Connect and Disconnect Protocol . . . . . . . . . . . . . . . . . . . . . . 12
Connect Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 Clock Control   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 CPUID Support  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
6 Thermal Design  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  21
7 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23
7.1 Conventions   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2 Interface Signal Groupings  . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3 Voltage Identification (VID[4:0])  . . . . . . . . . . . . . . . . . . . . . . 24
7.4 Frequency Identification (FID[3:0]) . . . . . . . . . . . . . . . . . . . . 25
7.5 VCCA AC and DC Characteristics  . . . . . . . . . . . . . . . . . . . . . 25
7.6 Decoupling   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.7 VCC_CORE Characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.8 Absolute Ratings   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.9 VCC_CORE Voltage and Current . . . . . . . . . . . . . . . . . . . . . . 29
7.10 SYSCLK and SYSCLK# AC and DC Characteristics   . . . . . . 30
7.11 AMD Athlon System Bus AC and DC Characteristics   . . . . . 32
7.12 General AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . 34
7.13 Open Drain Test Circuit   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.14 Thermal Diode Characteristics  . . . . . . . . . . . . . . . . . . . . . . . . 37
Thermal Diode Electrical Characteristics. . . . . . . . . . . . . . . . 37
Thermal Protection Characterization . . . . . . . . . . . . . . . . . . . 38
7.15 APIC Pins AC and DC Characteristics  . . . . . . . . . . . . . . . . . . 39

iv Table of Contents
AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms 25480D—June 2002
Preliminary Information
8 Signal and Power-Up Requirements  . . . . . . . . . . . . . . . . . . . .  41
8.1 Power-Up Requirements  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Signal Sequence and Timing Description . . . . . . . . . . . . . . . . 41
Clock Multiplier Selection (FID[3:0]) . . . . . . . . . . . . . . . . . . . 44
8.2 Processor Warm Reset Requirements  . . . . . . . . . . . . . . . . . . 44
Northbridge Reset Pins  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9 Mechanical Data  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  45
9.1 Introduction   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.2 Die Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.3 OPGA Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10 Pin Descriptions   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  49
10.1 Pin Diagram and Pin Name Abbreviations  . . . . . . . . . . . . . . 49
10.2 Pin List   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.3 Detailed Pin Descriptions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
A20M# Pin  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
AMD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
AMD Athlon System Bus Pins  . . . . . . . . . . . . . . . . . . . . . . . . . 66
Analog Pin  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
APIC Pins, PICCLK, PICD[1:0]#  . . . . . . . . . . . . . . . . . . . . . . . 66
CLKFWDRST Pin  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
CLKIN, RSTCLK (SYSCLK) Pins. . . . . . . . . . . . . . . . . . . . . . . 66
CONNECT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
COREFB and COREFB# Pins. . . . . . . . . . . . . . . . . . . . . . . . . . 67
CPU_PRESENCE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
DBRDY and DBREQ# Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
FERR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
FID[3:0] Pins  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
FLUSH# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
IGNNE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
INIT# Pin  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
INTR Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
K7CLKOUT and K7CLKOUT# Pins. . . . . . . . . . . . . . . . . . . . . 69
Key Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
NC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
NMI Pin  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
PGA Orientation Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
PLL Bypass and Test Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
PWROK Pin  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
SADDIN[1:0]# and SADDOUT[1:0]# Pins. . . . . . . . . . . . . . . . 70
Scan Pins  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
SCHECK[7:0]# Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
STPCLK# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SYSCLK and SYSCLK#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table of Contents v
25480D—June 2002 AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms
Preliminary Information
THERMDA and THERMDC Pins . . . . . . . . . . . . . . . . . . . . . . . 71
VCCA Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
VID[4:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
VREFSYS Pin  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
ZN and ZP Pins  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
11 Ordering Information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  73
Standard AMD Athlon MP Processor Model 6 Products. . . . . . . . . . 73
Appendix A  Conventions and Abbreviations . . . . . . . . . . . . . . . . . .  75
Signals and Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Data Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Abbreviations and Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

vi Table of Contents

AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms 25480D—June 2002

Preliminary Information

List of Figures vii
25480D—June 2002 AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms
Preliminary Information
List of Figures
Figure 1. Logic Symbol Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. AMD Athlon™ MP Processor Model 6 Power 
Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. AMD Athlon System Bus Disconnect Sequence 
in the Stop Grant State  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. Exiting the Stop Grant State and Bus Connect 
Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5. Northbridge Connect State Diagram . . . . . . . . . . . . . . . . . . . . . 16
Figure 6. Processor Connect State Diagram  . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. VCC_CORE Voltage Waveform  . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 8. SYSCLK and SYSCLK# Differential Clock Signals . . . . . . . . . 30
Figure 9. SYSCLK Waveform  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 10. General ATE Open-Drain Test Circuit. . . . . . . . . . . . . . . . . . . . 36
Figure 11. Signal Relationship Requirements During Power-Up 
Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 12. AMD Athlon MP Processor Model 6 OPGA Package . . . . . . . . 47
Figure 13. AMD Athlon MP Processor Model 6 Pin Diagram
—Topside View  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 14. AMD Athlon MP Processor Model 6 Pin Diagram
—Bottomside View  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 15. OPN Example for the AMD Athlon MP Processor 
Model 6, OPGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

viii List of Figures

AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms 25480D—June 2002

Preliminary Information

List of Tables ix
25480D—June 2002 AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms
Preliminary Information
List of Tables
Table 1. Maximum Thermal Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 2. Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 3. VID[4:0] DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 4. FID[3:0] DC Characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 5. VCCA AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 25
Table 6. VCC_CORE AC and DC Characteristics  . . . . . . . . . . . . . . . . . . 26
Table 7. Absolute Ratings  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 8. VCC_CORE Voltage and Current. . . . . . . . . . . . . . . . . . . . . . . . 29
Table 9. SYSCLK and SYSCLK# DC Characteristics  . . . . . . . . . . . . . . . 30
Table 10. SYSCLK and SYSCLK# AC Characteristics  . . . . . . . . . . . . . . . 31
Table 11. AMD Athlon™ System Bus DC Characteristics  . . . . . . . . . . . . 32
Table 12. AMD Athlon System Bus AC Characteristics  . . . . . . . . . . . . . . 33
Table 13. General AC and DC Characteristics. . . . . . . . . . . . . . . . . . . . . . 34
Table 14. Thermal Diode Electrical Characteristics . . . . . . . . . . . . . . . . . 37
Table 15. Guidelines for Platform Thermal Protection of 
the Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 16. APIC Pin AC and DC Characteristics. . . . . . . . . . . . . . . . . . . . . 39
Table 17. Mechanical Loading for the OPGA Package . . . . . . . . . . . . . . . 45
Table 18. Dimensions for the AMD Athlon MP Processor 
Model 6 OPGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 19. Pin Name Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 20. Cross-Reference by Pin Location . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 21. FID[3:0] Clock Multiplier Encodings . . . . . . . . . . . . . . . . . . . . . 68
Table 22. VID[4:0] Code to Voltage Definition . . . . . . . . . . . . . . . . . . . . . 72
Table 23. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 24. Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

xList of Tables

AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms 25480D—June 2002

Preliminary Information

Revision History xi
25480D—June 2002 AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms
Preliminary Information
Revision History
Date Rev Description
June 2002 D
Revision D of the AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor 
Platforms contains current, frequency, power, and voltage information for Model Number 
2100+ (1733 MHz) and changes to the following:
■In Chapter 6, revised Table 1, “Maximum Thermal Power,” on page 21. 
■In Chapter 7, revised Table 8, “VCC_CORE Voltage and Current,” on page 29 .
■In Chapter 11, revised Figure 15, “OPN Example for the AMD Athlon™ MP Processor Model
6, OPGA Package” on page 73.
March 2002 C
Revision C of the AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor 
Platforms contains current, frequency, power, and voltage information for Model Number 
2000+ (1667 MHz) and changes to the following:
■In Chapter 6, revised Table 1, “Maximum Thermal Power,” on page 21. 
■In Chapter 7, revised Table 8, “VCC_CORE Voltage and Current,” on page 29 and Table 10,
“SYSCLK and SYSCLK# AC Characteristics,” on page 31.
■In Chapter 10, updated table and notes for Table 21, “FID[3:0] Clock Multiplier Encodings,”
on page 68.
■In Chapter 11, revised Figure 15, “OPN Example for the AMD Athlon™ MP Processor Model
6, OPGA Package” on page 73.
December 2001 B
Revision B of the AMD Athlon™ MP Processor Model 6 Data Sheet for Multiprocessor 
Platforms contains current, frequency, power, and voltage information for Model Number 
1900+ (1600 MHz) and changes to the following:
■In Chapter 6, revised Table 1, “Maximum Thermal Power,” on page 21.
■In Chapter 7, revised Table 6, “VCC_CORE AC and DC Characteristics,” on page 26, Table 8,
“VCC_CORE Voltage and Current,” on page 29, revised Table 13, “General AC and DC
Characteristics,” on page 34, added new section, “Open Drain Test Circuit” on page 36,
added Figure 10, “General ATE Open-Drain Test Circuit” on page 36, added new section,
“Thermal Protection Characterization” on page 38, and added Table 15, “Guidelines for
Platform Thermal Protection of the Processor,” on page 39.
■In Chapter 11, revised Figure 15, “OPN Example for the AMD Athlon™ MP Processor Model
6, OPGA Package” on page 73.
October 2001 A Initial release of the AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor 
Platforms, order# 25480.

xii Revision History

AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms 25480D—June 2002

Preliminary Information

Chapter 1 Overview 1

25480D—June 2002 AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms

Preliminary Information

1 Overview

The AMD Athlon™ MP processor model 6 powers the next

generation in computing platforms, delivering compelling

performance for cutting-edge applications and an unprecedented

computing experience.

The AMD Athlon™ MP processor model 6 continues to deliver

breakthrough performance in the multiprocessing server and

workstation markets. This processor is designed to meet the

reliability and computation-intensive requirements of

cutting-edge software applications required by workstations

and servers.

Delivered in an OPGA package, the AMD Athlon MP processor

model 6 delivers the integer, floating-point, and 3D multimedia

performance for enterprise applications running on x86 system

platforms. The AMD Athlon MP processor model 6 offers

compelling performance for productivity software, including

workstation-class Digital Content Creation (DCC), Electronic

Design Automation (EDA), and Computer-Aided Design (CAD),

as well as infrastructure and collaborative server applications.

It also offers the scalability and reliability that IT managers and

business users require for mission-critical computing.

The AMD Athlon MP processor model 6 features the

seventh-generation microarchitecture, including a high-speed

execution core that includes multiple x86 instruction decoders;

a dual-ported, 128-Kbyte, split level-one (L1) cache; a 256-Kbyte

on-chip L2 cache; three independent integer pipelines, three

address calculation pipelines; and a superscalar, fully

pipelined, out-of-order, three-way floating-point engine. The

integrated L2 cache supports the growing processor and system

bandwidth requirements of emerging software, graphics, I/O,

and memory technologies. The processor also features the

advanced Modified Owner Exclusive Shared Invalid (MOESI)

cache coherency protocol to ensure efficient cache integrity in

a multiprocessing environment. The floating-point engine is

capable of delivering excellent performance on the numerically

complex applications typical of servers and workstations.

2Overview Chapter 1

AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms 25480D—June 2002

Preliminary Information

The key features of the AMD Athlon MP processor model 6

include QuantiSpeed™ architecture, a high-performance full-

speed cache, a 266-MHz, 2.1-Gigabyte per second system bus,

3DNow!™ Professional technology, and fully featured logic

implementation for the multiprocessor configuration.

The AMD Athlon system bus combines the latest technological

advances, such as point-to-point topology, source-synchronous

packet-based transfers, and low-voltage signaling. The point-to-

point front-side bus architecture provides a more efficient,

higher bandwidth bus that allows each processor, in a multi-

processor configuration, to communicate to the system chipset

through two, full-speed, independent buses rather than through

a common, shared bus. Combined with the AMD-760™ MPX

chipset, the processor and the system bus interface with

Double-Data Rate (DDR) memory subsystems, providing

scalable headroom for bandwidth-hungry applications such as

large databases, CAD/CAM modeling, and simulation engines.

The front-side bus of the AMD Athlon MP processor model 6

also provides multiple-bit error detection and single-bit error

correction with 8-bit Error Correction Code (ECC). The front-

side bus with 8-bit ECC delivers the high reliability and

consistency demanded by mission-critical applications.

The AMD Athlon MP processor model 6 is binary-compatible

with existing x86 software and backwards compatible with

applications optimized for MMX™ and 3DNow! technologies.

Using a data format and Single-Instruction Multiple-Data

(SIMD) operations based on the MMX instruction model, the

AMD Athlon MP processor model 6 can produce as many as

four, 32-bit, single-precision floating-point results per clock

cycle. The 3DNow! professional technology implemented in the

AMD Athlon MP processor model 6 includes new integer

multimedia instructions and software-directed data movement

instructions for optimizing such applications as digital content

creation and streaming video for the internet, as well as new

instructions for Digital Signal Processing

(DSP)/communications applications.

Chapter 1 Overview 3

25480D—June 2002 AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms

Preliminary Information

1.1 AMD Athlon™ MP Processor Model 6 Key Microarchitecture

Summary

The following features summarize the AMD Athlon MP

processor model 6 microarchitecture:

■QuantiSpeed™ architecture:

•An advanced nine-issue, superpipelined, superscalar x86

processor microarchitecture designed for increased

Instructions Per Clock cycle (IPC) and high clock

frequencies

•Fully pipelined floating-point unit that executes all x87

(floating-point), MMX and 3DNow! Professional

instructions

•Hardware data pre-fetch that increases and optimizes

performance on high-end software applications that

utilize high-bandwidth system capability

•Advanced two-level Translation Look-aside Buffer (TLB)

structures for enhanced data and instruction address

translation. The AMD Athlon MP processor with

QuantiSpeed architecture incorporates three TLB

optimizations: the L1 DTLB increases from 32 to 40

entries, the L2 ITLB and L2 DTLB both use exclusive

architecture, and the TLB entries can be speculatively

loaded.

■3DNow! Professional technology with new instructions to

enable improved integer-math calculations for speech or

video encoding and improved data movement for internet

plug-ins and other streaming applications

■A 266-MHz AMD Athlon system bus enabling leading-edge

system bandwidth for data movement-intensive applications

■Point-to-point front-side bus architecture allowing each

processor in a multi-processor configuration to communicate

to the system chipsets through two, full speed, independent

buses

■High-performance cache architecture featuring an

integrated 128-Kbyte L1 cache and a 16-way, 256-Kbyte on-

chip L2 cache for a total of 384 Kbytes of on-chip cache

■Multiple-bit error detection and single-bit error correction

with 8-bit Error Correction Code (ECC)

■Full featured MP Local APIC implementation

4Overview Chapter 1

AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms 25480D—June 2002

Preliminary Information

■Advanced MOESI cache coherency protocol to ensure

efficient cache integrity in a multiprocessing environment

The AMD Athlon MP processor model 6 delivers excellent

system performance in a cost-effective, industry-standard form

factor. The AMD Athlon MP processor model 6 is compatible

with motherboards based on Socket A.

Chapter 2 Interface Signals 5

25480D—June 2002 AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms

Preliminary Information

2 Interface Signals

2.1 Overview

The AMD Athlon™ system bus architecture is designed to

deliver superior data movement bandwidth for next-generation

x86 platforms as well as the high-performance required by

enterprise-class application software. The system bus

architecture consists of three high-speed channels (a

unidirectional processor request channel, a unidirectional

probe channel, and a 72-bit bidirectional data channel,

including 8-bit Error Correction Code [ECC] protection),

source-synchronous clocking, and a packet-based protocol. In

addition, the system bus supports several control, clock, and

legacy signals. The interface signals use an impedance

controlled push-pull, low-voltage, swing-signaling technology

contained within the Socket A socket.

For more information, see “AMD Athlon™ System Bus Signals”

on page 6, “Pin Descriptions” on page 49, and the

AMD Athlon™ System Bus Specification, order# 21902.

2.2 Signaling Technology

The AMD Athlon system bus uses a low-voltage, swing-signaling

technology, that has been enhanced to provide larger noise

margins, reduced ringing, and variable voltage levels. The

signals are push-pull and impedance compensated. The signal

inputs use differential receivers that require a reference

voltage (VREF). The reference signal is used by the receivers to

determine if a signal is asserted or deasserted by the source.

Termination resistors are not needed because the driver is

impedance-matched to the motherboard and a high impedance

reflection is used at the receiver to bring the signal past the

input threshold.

For more information about pins and signals, see Chapter 10,

“Pin Descriptions” on page 49.

6Interface Signals Chapter 2

AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms 25480D—June 2002

Preliminary Information

2.3 Push-Pull (PP) Drivers

The AMD Athlon MP processor model 6 supports Push-Pull

(PP) drivers. The system logic configures the processor with the

configuration parameter called SysPushPull (1=PP). The

impedance of the PP drivers is set to match the impedance of

the motherboard by two external resistors connected to the ZN

and ZP pins.

See “ZN and ZP Pins” on page 72 for more information.

2.4 AMD Athlon™ System Bus Signals

The AMD Athlon system bus is a clock-forwarded, point-to-

point interface with the following three point-to-point channels:

■A 13-bit unidirectional output address/command channel

■A 13-bit unidirectional input address/command channel

■A 72-bit bidirectional data channel

For more information, see Chapter 7, “Electrical Data” on page

23 and the AMD Athlon™ System Bus Specification, order#

21902.

Chapter 3 Logic Symbol Diagram 7

25480D—June 2002 AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms

Preliminary Information

3 Logic Symbol Diagram

Figure 1 is the logic symbol diagram of the processor. This

diagram shows the logical grouping of the input and output

signals.

Figure 1. Logic Symbol Diagram

SDATA[63:0]#

SDATAINCLK[3:0]#

SDATAOUTCLK[3:0]#

SCHECK[7:0]#

Data

SADDIN[14:2]#

SADDINCLK#

Probe/SysCMD

SADDOUT[14:2]#

SADDOUTCLK#

VID[4:0]

FID[3:0]

A20M#

CLKFWDRST

CONNECT

COREFB

COREFB#

FERR

IGNNE#

INIT#

INTR

NMI

PROCRDY

PWROK

RESET#

SFILLVALID#

SMI#

STPCLK#

SYSCLK#SYSCLK

Clock

Voltage

Control

Frequency

Control

Legacy

Request

AMD Athlon™ MP

Processor Model 6

SDATAINVALID#

SDATAOUTVALID#

Power

and Initialization

Management Thermal

Diode

THERMDA

THERMDC

FLUSH#

PICCLK

PICD[1:0] APIC

8Logic Symbol Diagram Chapter 3

AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms 25480D—June 2002

Preliminary Information

Chapter 4 Power Management 9

25480D—June 2002 AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms

Preliminary Information

4 Power Management

This chapter describes the power management control system

of the AMD Athlon™ MP processor model 6. The power

management features of the processor are compliant with the

ACPI 1.0b and ACPI 2.0 specifications.

4.1 Power Management States

The AMD Athlon MP processor model 6 supports low-power

Halt and Stop Grant states. These states are used by Advanced

Configuration and Power Interface (ACPI) enabled operating

systems for processor power management.

Figure 2 shows the power management states of the processor.

The figure includes the ACPI “Cx” naming convention for these

states.

Figure 2. AMD Athlon™ MP Processor Model 6 Power Management States

Halt

Working4

Execute HLT

SMI#, INTR, NMI, INIT#, RESET#

Incoming Probe

Probe Serviced

STPCLK# asserted

STPCLK# deasserted

Stop Grant

Cache Snoopable

Incoming Probe

Probe Serviced

Probe

State1

STPCLK# deasserted

(Read PLVL2 register

or throttling)

Stop Grant

Cache Not Snoopable

Sleep

STPCLK# asserted

STPCLK#deasserted

Note: The AMD AthlonTM System Bus is connected during the following states:

1) The Probe state

2) During transitions between the Halt state and the C2 Stop Grant state

3) During transitions between the C2 Stop Grant state and the Halt state

4) C0 Working state

Software transitions

Hardware transitions

Legend

10 Power Management Chapter 4

AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms 25480D—June 2002

Preliminary Information

The following sections provide an overview of the power

management states. For more details, refer to the

AMD Athlon™ System Bus Specification, order# 21902.

Note: In all power management states that the processor is

powered, the system must not stop the system clock

(SYSCLK/SYSCLK#) to the processor.

Working State The Working state is the state in which the processor is

executing instructions.

Halt State When the processor executes the HLT instruction, the processor

enters the Halt state and issues a Halt special cycle to the

AMD Athlon system bus. The processor only enters the low

power state dictated by the CLK_Ctl MSR if the system

controller (Northbridge) disconnects the AMD Athlon system

bus in response to the Halt special cycle.

If STPCLK# is asserted, the processor will exit the Halt state

and enter the Stop Grant state. The processor will initiate a

system bus connect, if it is disconnected, then issue a Stop

Grant special cycle. When STPCLK# is deasserted, the

processor will exit the Stop Grant state and re-enter the Halt

state. The processor will issue a Halt special cycle when

re-entering the Halt state.

The Halt state is exited when the processor detects the

assertion of INIT#, RESET#, SMI#, or an interrupt via the INTR

or NMI pins, or via a local APIC interrupt message. When the

Halt state is exited, the processor will initiate an AMD Athlon

system bus connect if it is disconnected.

Stop Grant States The processor enters the Stop Grant state upon recognition of

assertion of STPCLK# input. After entering the Stop Grant

state, the processor issues a Stop Grant special bus cycle on the

AMD Athlon system bus. The processor is not in a low-power

state at this time, because the AMD Athlon system bus is still

connected. After the Northbridge disconnects the AMD Athlon

system bus in response to the Stop Grant special bus cycle, the

processor enters a low-power state dictated by the CLK_Ctl

MSR. If the Northbridge needs to probe the processor during

the Stop Grant state while the system bus is disconnected, it

must first connect the system bus. Connecting the system bus

places the processor into the higher power probe state. After

Chapter 4 Power Management 11

25480D—June 2002 AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms

Preliminary Information

the Northbridge has completed all probes of the processor, the

Northbridge must disconnect the AMD Athlon system bus

again so that the processor can return to the low-power state.

During the Stop Grant states, the processor latches INIT#,

INTR, NMI, SMI#, or a local APIC interrupt message, if they are

asserted.

The Stop Grant state is exited upon the deassertion of

STPCLK# or the assertion of RESET#. When STPCLK# is

deasserted, the processor initiates a connect of the

AMD Athlon system bus if it is disconnected. After the

processor enters the Working state, any pending interrupts are

recognized and serviced and the processor resumes execution

at the instruction boundary where STPCLK# was initially

recognized. If RESET# is sampled asserted during the Stop

Grant state, the processor exits the Stop Grant state and the

reset process begins.

There are two mechanisms for asserting STPCLK#—hardware

and software.

The Southbridge can force STPCLK# assertion for throttling to

protect the processor from exceeding its maximum case

temperature. This is accomplished by asserting the THERM#

input to the Southbridge. Throttling asserts STPCLK# for a

percentage of a predefined throttling period: STPCLK# is

repetitively asserted and deasserted until THERM# is

deasserted.

Software can force the processor into the Stop Grant state by

accessing ACPI-defined registers typically located in the

Southbridge.

The operating system places the processor into the C2 Stop

Grant state by reading the P_LVL2 register in the Southbridge.

If an ACPI Thermal Zone is defined for the processor, the

operating system can initiate throttling with STPCLK# using

the ACPI defined P_CNT register in the Southbridge. The

Northbridge connects the AMD Athlon system bus, and the

processor enters the Probe state to service cache snoops during

Stop Grant for C2 or throttling.

In C2, probes are allowed, as shown in Figure 2 on page 9

12 Power Management Chapter 4

AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms 25480D—June 2002

Preliminary Information

The Stop Grant state is also entered for the S1, Powered On

Suspend, system sleep state based on a write to the SLP_TYP

and SLP_EN fields in the ACPI-defined Power Management 1

control register in the Southbridge. During the S1 Sleep state,

system software ensures no bus master or probe activity occurs.

The Southbridge deasserts STPCLK# and brings the processor

out of the S1 Stop Grant state when any enabled resume event

occurs.

Probe State The Probe state is entered when the Northbridge connects the

AMD Athlon system bus to probe the processor (for example, to

snoop the processor caches) when the processor is in the Halt or

Stop Grant state. When in the Probe state, the processor

responds to a probe cycle in the same manner as when it is in

the Working state. When the probe has been serviced, the

processor returns to the same state as when it entered the

Probe state (Halt or Stop Grant state). When probe activity is

completed the processor only returns to a low-power state after

the Northbridge disconnects the AMD Athlon system bus again.

4.2 Connect and Disconnect Protocol

Significant power savings of the processor only occur if the

processor is disconnected from the system bus by the

Northbridge while in the Halt or Stop Grant state. The

Northbridge can optionally initiate a bus disconnect upon the

receipt of a Halt or Stop Grant special cycle. The option of

disconnecting is controlled by an enable bit in the Northbridge.

If the Northbridge requires the processor to service a probe

after the system bus has been disconnected, it must first

initiate a system bus connect.

Connect Protocol In addition to the legacy STPCLK# signal and the Halt and Stop

Grant special cycles, the AMD Athlon system bus connect

protocol includes the CONNECT, PROCRDY, and CLKFWDRST

signals and a Connect special cycle.

AMD Athlon system bus disconnects are initiated by the

Northbridge in response to the receipt of a Halt or Stop Grant

special cycle. Reconnect is initiated by the processor in

response to an interrupt for Halt, STPCLK# deassertion, or by

the Northbridge to service a probe.

Chapter 4 Power Management 13

25480D—June 2002 AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms

Preliminary Information

The Northbridge contains BIOS programmable registers to

enable the system bus disconnect in response to Halt and Stop

Grant special cycles. When the Northbridge receives the Halt or

Stop Grant special cycle from the processor and, if there are no

outstanding probes or data movements, the Northbridge

deasserts CONNECT a minimum of eight SYSCLK periods after

the last command sent to the processor. The processor detects

the deassertion of CONNECT on a rising edge of SYSCLK and

deasserts PROCRDY to the Northbridge. In return, the

Northbridge asserts CLKFWDRST in anticipation of

reestablishing a connection at some later point.

Note: The Northbridge must disconnect the processor from the

AMD Athlon system bus before issuing the Stop Grant

special cycle to the PCI bus, or passing the Stop Grant

special cycle to the Southbridge for systems that connect to

the Southbridge with HyperTransport™ technology.

This note applies to current chipset implementation—

alternate chipset implementations that do not require this

are possible.

Note: In response to Halt special cycles, the Northbridge passes the

Halt special cycle to the PCI bus or Southbridge

immediately.

The processor can receive an interrupt after it sends a Halt

special cycle, or STPCLK# deassertion after it sends a Stop

Grant special cycle to the Northbridge but before the

disconnect actually occurs. In this case, the processor sends the

Connect special cycle to the Northbridge, rather than

continuing with the disconnect sequence. In response to the

Connect special cycle, the Northbridge cancels the disconnect

request.

The system is required to assert the CONNECT signal before

returning the C-bit for the connect special cycle (assuming

CONNECT has been deasserted).

For more information, see the AMD Athlon™ System Bus

Specification, order# 21902 for the definition of the C-bit and

the Connect special cycle.

14 Power Management Chapter 4

AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms 25480D—June 2002

Preliminary Information

Figure 3 shows STPCLK# assertion resulting in the processor in

the Stop Grant state and the AMD Athlon system bus

disconnected.

Figure 3. AMD Athlon™ System Bus Disconnect Sequence in the Stop Grant State

An example of the AMD Athlon system bus disconnect

sequence is as follows:

1. The peripheral controller (Southbridge) asserts STPCLK#

to place the processor in the Stop Grant state.

2. When the processor recognizes STPCLK# asserted, it enters

the Stop Grant state and then issues a Stop Grant special

cycle.

3. When the special cycle is received by the Northbridge, it

deasserts CONNECT, assuming no probes are pending,

initiating a bus disconnect to the processor.

4. The processor responds to the Northbridge by deasserting

PROCRDY.

5. The Northbridge asserts CLKFWDRST to complete the bus

disconnect sequence.

6. After the processor is disconnected from the bus, the

processor enters a low-power state. The Northbridge passes

the Stop Grant special cycle along to the Southbridge.

Stop Grant

STPCLK#

CONNECT

PROCRDY

CLKFWDRST

PCI Bus

AMD Athlon™

System Bus

Chapter 4 Power Management 15

25480D—June 2002 AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms

Preliminary Information

Figure 4 shows the signal sequence of events that takes the

processor out of the Stop Grant state, connects the processor to

the AMD Athlon system bus, and puts the processor into the

Working state.

Figure 4. Exiting the Stop Grant State and Bus Connect Sequence

The following sequence of events removes the processor from

the Stop Grant state and connects it to the system bus:

1. The Southbridge deasserts STPCLK#, informing the

processor of a wake event.

2. When the processor recognizes STPCLK# deassertion, it

exits the low-power state and asserts PROCRDY, notifying

the Northbridge to connect to the bus.

3. The Northbridge asserts CONNECT.

4. The Northbridge deasserts CLKFWDRST, synchronizing the

forwarded clocks between the processor and the

Northbridge.

5. The processor issues a Connect special cycle on the system

bus and resumes operating system and application code

execution.

STPCLK#

PROCRDY

CONNECT

CLKFWDRST

16 Power Management Chapter 4

AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms 25480D—June 2002

Preliminary Information

Figure 5 and Figure 6 on page 17 describe the Northbridge and

processor connect state diagrams, respectively.

Figure 5. Northbridge Connect State Diagram

Condition

1 A disconnect is requested and probes are still pending.

2 A disconnect is requested and no probes are pending.

3 A Connect special cycle from the processor.

4 No probes are pending.

5 PROCRDY is deasserted.

6 A probe needs service.

7 PROCRDY is asserted.

Three SYSCLK periods after CLKFWDRST is deasserted.

Although reconnected to the system interface, the

Northbridge must not issue any non-NOP SysDC

commands for a minimum of four SYSCLK periods after

deasserting CLKFWDRST.

Action

ADeassert CONNECT eight SYSCLK periods

after last SysDC sent.

BAssert CLKFWDRST.

C Assert CONNECT.

D Deassert CLKFWDRST.

Disconnect

Pending Connect Disconnect

Requested

Reconnect

Pending

Probe

Pending 2

Disconnect

Probe

Pending 1

2/A

4/A

5/B

3/C

7/D,C

6/C 7/D

Chapter 4 Power Management 17

25480D—June 2002 AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms

Preliminary Information

Figure 6. Processor Connect State Diagram

Condition

1CONNECT is deasserted by the Northbridge (for a

previously sent Halt or Stop Grant special cycle).

2Processor receives a wake-up event and must cancel

the disconnect request.

3 Deassert PROCRDY and slow down internal clocks.

4Processor wake-up event or CONNECT asserted by

Northbridge.

5 CLKFWDRST is deasserted by the Northbridge.

6Forward clocks start three SYSCLK periods after

CLKFWDRST is deasserted.

Action

A CLKFWDRST is asserted by the Northbridge.

B Issue a Connect special cycle.*

CReturn internal clocks to full speed and assert

PROCRDY.

Note:

* The Connect special cycle is only issued after a

processor wake-up event (interrupt or STPCLK#

deassertion) occurs. If the AMD Athlon™ system

bus is connected so the Northbridge can probe the

processor, a Connect special cycle is not issued at

that time (it is only issued after a subsequent

processor wake-up event).

Connect

Disconnect

Pending

Disconnect

Connect

Pending 1

Connect

Pending 2

3/A

4/C

6/B

2/B

18 Power Management Chapter 4

AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms 25480D—June 2002

Preliminary Information

4.3 Clock Control

The processor implements a Clock Control (CLK_Ctl) MSR

(address C001_001Bh) that determines the internal clock

divisor when the AMD Athlon system bus is disconnected.

Refer to the AMD Athlon™ and AMD Duron™ Processors BIOS,

Software, and Debug Developers Guide, order# 21656, for more

details on the CLK_Ctl register.

Chapter 5 CPUID Support 19

25480D—June 2002 AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms

Preliminary Information

5 CPUID Support

AMD Athlon™ and Duron™ Processor Recognition Application

Note Addendum version and feature set recognition can be

performed through the use of the CPUID instruction, that

provides complete information about the processor—vendor,

type, name, etc., and its capabilities. Software can make use of

this information to accurately tune the system for maximum

performance and benefit to users.

For information on the use of the CPUID instruction see the

following documents:

■AMD Processor Recognition Application Note, order# 20734

■AMD Athlon™ and Duron™ Processor Recognition Application

Note Addendum, order# 21922

■AMD Athlon™ and AMD Duron™ Processors BIOS, Software,

and Debug Developers Guide, order# 21656

20 CPUID Support Chapter 5

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Preliminary Information

Chapter 6 Thermal Design 21

25480D—June 2002 AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms

Preliminary Information

6 Thermal Design

The AMD Athlon™ MP processor model 6 provides a diode that

can be used in conjunction with an external temperature sensor

to determine the die temperature of the processor. The diode

anode (THERMDA) and cathode (THERMDC) are available as

pins on the processor.

Refer to “THERMDA and THERMDC Pins” on page 71 for

more details.

For information about thermal design for the AMD Athlon MP

processor model 6, including layout and airflow considerations,

see the AMD Processor Thermal, Mechanical, and Chassis Cooling

Design Guide, order# 23794, and the cooling guidelines on

http://www.amd.com.

Table 1 shows the thermal design power specifications.

Table 1. Maximum Thermal Power

Model Number Frequency

(MHz)

Nominal

Voltage

Maximum Thermal

Power*

Typical Thermal

Power

Maximum Die

Temperature

1500+ 1333

1.75 V

60.0 W 53.8 W

95°C

1600+ 1400 62.8 W 56.3 W

1800+ 1533

66.0 W 58.9 W

1900+ 1600

2000+ 1667

2100+ 1733

Notes:

* The maximum thermal power represents the maximum sustained power dissipated while executing publicly available software or

instruction sequences under normal system operation at nominal VCC_CORE. Thermal solutions must monitor the processor tem-

perature to prevent the processor from exceeding its maximum die temperature.

22 Thermal Design Chapter 6

AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms 25480D—June 2002

Preliminary Information

Chapter 7 Electrical Data 23
25480D—June 2002 AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms
Preliminary Information
7 Electrical Data
7.1 Conventions
The conventions used in this chapter are as follows:
■Current specified as being sourced by the processor is
negative.
■Current specified as being sunk by the processor is positive.
7.2 Interface Signal Groupings
The electrical data in this chapter is presented separately for
each signal group.
Table 2 defines each group and the signals contained in each
group.
Table 2. Interface Signal Groupings
Signal Group Signals Notes
Power VID[4:0], VCCA, VCC_CORE, COREFB, COREFB#
See “Absolute Ratings” on page 28, 
“Voltage Identification (VID[4:0])” 
on page 24, “VID[4:0] Pins” on page 
71, “VCCA AC and DC 
Characteristics” on page 25, “VCCA 
Pin” on page 71, and “COREFB and 
COREFB# Pins” on page 67.
Frequency FID[3:0]
See “Frequency Identification 
(FID[3:0])” on page 25 and 
“FID[3:0] Pins” on page 68.
System Clocks SYSCLK, SYSCLK# (Tied to CLKIN/CLKIN# and RSTCLK/RSTCLK#), 
PLLBYPASSCLK#, PLLBYPASSCLK
See Table 9, “SYSCLK and SYSCLK# 
DC Characteristics,” on page 30, 
Table 10, “SYSCLK and SYSCLK# AC 
Characteristics,” on page 31, Table , 
“SYSCLK and SYSCLK#,” on 
page 71, and Table , “PLL Bypass 
and Test Pins,” on page 70.
AMD Athlon™ 
System Bus
SADDIN[14:2]#, SADDOUT[14:2]#, SADDINCLK#, SADDOUTCLK#, 
SFILLVAL#, SDATAINVAL#, SDATAOUTVAL#, SDATA[63:0]#, 
SDATAINCLK[3:0]#, SDATAOUTCLK[3:0]#, SCHECK[7:0]#, 
CLKFWDRST, PROCRDY, CONNECT
See “AMD Athlon™ System Bus AC 
and DC Characteristics” on page 32, 
and “CLKFWDRST Pin” on page 66.

24 Electrical Data Chapter 7
AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms 25480D—June 2002
Preliminary Information
7.3 Voltage Identification (VID[4:0])
Table 3 shows the VID[4:0] DC Characteristics. For more infor-
mation on VID[4:0] DC Characteristics, see “VID[4:0] Pins” on 
page 71.
Southbridge RESET#, INTR, NMI, SMI#, INIT#, A20M#, FERR, IGNNE#, 
STPCLK#, FLUSH#
See “General AC and DC 
Characteristics” on page 34, “INTR 
Pin” on page 69, “NMI Pin” on page 
70, “SMI# Pin” on page 71, “INIT# 
Pin” on page 69, “A20M# Pin” on 
page 66, “FERR Pin” on page 67, 
“IGNNE# Pin” on page 69, 
“STPCLK# Pin” on page 71, and 
“FLUSH# Pin” on page 69.
JTAG TMS, TCK, TRST#, TDI, TDO See “General AC and DC 
Characteristics” on page 34.
Test PLLBYPASS#, PLLTEST#, PLLMON1, PLLMON2, SCANCLK1, 
SCANCLK2, SCANSHIFTEN, SCANINTEVAL, ANALOG
See “General AC and DC 
Characteristics” on page 34, “PLL 
Bypass and Test Pins” on page 70, 
“Scan Pins” on page 70, “Analog 
Pin” on page 66.
Miscellaneous DBREQ#, DBRDY, PWROK
See “General AC and DC 
Characteristics” on page 34, 
“DBRDY and DBREQ# Pins” on 
page 67, “PWROK Pin” on page 70.
APIC PICD[1:0]#, PICCLK
See “APIC Pins AC and DC 
Characteristics” on page 39, and 
“APIC Pins, PICCLK, PICD[1:0]#” on 
page 66.
Thermal THERMDA, THERMDC
Table 14, “Thermal Diode Electrical 
Characteristics,” on page 37, and 
“THERMDA and THERMDC Pins” 
on page 71.
Table 2. Interface Signal Groupings (Continued)
Signal Group Signals Notes
Table 3. VID[4:0] DC Characteristics
Parameter Description Min Max
IOL  Output Current Low 16 mA
VOH  Output High Voltage – 2.625 V*
Note:
* The VID pins must not be pulled above this voltage by an external pullup resistor.

Chapter 7 Electrical Data 25

25480D—June 2002 AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms

Preliminary Information

7.4 Frequency Identification (FID[3:0])

Table 4 shows the FID[3:0] DC characteristics. For more

information, see “FID[3:0] Pins” on page 68.

7.5 VCCA AC and DC Characteristics

Table 5 shows the AC and DC characteristics for VCCA. For

more information, see “VCCA Pin” on page 71.

7.6 Decoupling

See the AMD Athlon™ Processor-Based Motherboard Design

Guide, order# 24363, or contact your local AMD office for

information about the decoupling required on the motherboard

for use with the AMD Athlon™ MP processor model 6.

Table 4. FID[3:0] DC Characteristics

Parameter Description Min Max

IOL Output Current Low 16 mA

VOH Output High Voltage – 2.625 V *

Note:

* The FID pins must not be pulled above this voltage by an external pullup resistor.

Table 5. VCCA AC and DC Characteristics

Symbol Parameter Min Nominal Max Units Notes

VVCCA VCCA Pin Voltage 2.25 2.5 2.75 V 1

IVCCA VCCA Pin Current 0 50 mA/GHz 2

Notes:

1. Minimum and Maximum voltages are absolute. No transients below minimum nor above maximum voltages are permitted.

2. Measured at 2.5 V.

26 Electrical Data Chapter 7

AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms 25480D—June 2002

Preliminary Information

7.7 VCC_CORE Characteristics

The AMD Athlon MP processor model 6 is designed to provide

functional operation if the voltage and temperature parameters

are within the limits defined in Table 6, which also shows the

AC and DC characteristics for VCC_CORE. See Figure 7 on

page 27 for a graphical representation of the VCC_CORE

waveform.

Table 6. VCC_CORE AC and DC Characteristics

Symbol Parameter Limit in Working State Units

VCC_CORE_DC_MAX Maximum static voltage above VCC_CORE_NOM*50 mV

VCC_CORE_DC_MIN Maximum static voltage below VCC_CORE_NOM*–50 mV

VCC_CORE_AC_MAX Maximum excursion above VCC_CORE_NOM*150 mV

VCC_CORE_AC_MIN Maximum excursion below VCC_CORE_NOM*–100 mV

tMAX_AC Maximum excursion time for AC transients 10 µs

tMIN_AC Negative excursion time for AC transients 5 µs

Note:

*All voltage measurements are taken differentially at the COREFB/COREFB# pins.

Chapter 7 Electrical Data 27

25480D—June 2002 AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms

Preliminary Information

Figure 7 shows the processor core voltage (VCC_CORE)

waveform response to perturbation. The tMIN_AC (negative AC

transient excursion time) and tMAX_AC (positive AC transient

excursion time) represent the maximum allowable time below

or above the DC tolerance thresholds.

Figure 7. VCC_CORE Voltage Waveform

tmin_AC

VCC_CORE_MAX_AC

tmax_AC

VCC_CORE_MAX_DC

VCC_CORE_NOM

VCC_CORE_MIN_DC

VCC_CORE_MIN_AC

ICORE_MIN

ICORE_MAX

dI /dt

28 Electrical Data Chapter 7

AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms 25480D—June 2002

Preliminary Information

7.8 Absolute Ratings

The AMD Athlon MP processor model 6 should not be

subjected to conditions exceeding the absolute ratings, as such

conditions can adversely affect long-term reliability or result in

functional damage.

Table 7 lists the maximum absolute ratings of operation for the

AMD Athlon MP processor

Table 7. Absolute Ratings

Parameter Description Min Max

VCC_CORE AMD Athlon™ MP processor model 6 core supply –0.5 V VCC_CORE Max + 0.5 V

VCCA AMD Athlon MP processor model 6 PLL supply –0.5 V VCCA Max + 0.5 V

VPIN Voltage on any signal pin –0.5 V VCC_CORE Max + 0.5 V

TSTORAGE Storage temperature of processor –40ºC 100ºC

Chapter 7 Electrical Data 29

25480D—June 2002 AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms

Preliminary Information

7.9 VCC_CORE Voltage and Current

Table 8 shows the voltage and current for the AMD Athlon MP

processor model 6 during normal and reduced power states.

Table 8. VCC_CORE Voltage and Current

Model Number Frequency

(MHz)

Nominal

Voltage

Die

Temperature

ICC (Processor Current)

Maximum Typical

1500+ 1333

1.75 V 95°C

34.3 A 30.8 A

1600+ 1400 35.9 A 32.2 A

1800+ 1533

37.7 A 33.7 A

1900+ 1600

2000+ 1667

2100+ 1733

Stop Grant S1 or Sleep State1, 2, 3, 4, 5 1.30 V 50°C 2.69 A 0.61 A

Notes:

1. The cooling fan can be turned off during the Sleep state, but customers should test their systems in Sleep state to ensure that the

system, when using typical parts, has adequate cooling (without the fan during Sleep state) to meet the temperature specification

of the product.

2. See Figure 2, "AMD Athlon™ MP Processor Model 6 Power Management States" on page 9.

3. The maximum Stop Grant currents are absolute worst case currents for parts that may yield from the worst case corner of the

process and are not representative of the typical Stop Grant current that is currently about one-third of the maximum specified

current.

4. These currents occur when the AMD Athlon system bus is disconnected and a low power ratio of 1/64 is applied to the core clock

grid of the processor as dictated by a value of 6003_D22Fh programmed into the Clock Control (CLK_Ctl) MSR.

5. The Stop Grant current consumption is characterized and not tested.

30 Electrical Data Chapter 7

AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms 25480D—June 2002

Preliminary Information

7.10 SYSCLK and SYSCLK# AC and DC Characteristics

Table 9 shows the DC characteristics of the SYSCLK and

SYSCLK# differential clocks. The SYSCLK signal represents

CLKIN and RSTCLK tied together while the SYSCLK# signal

represents CLKIN# and RSTCLK# tied together.

Figure 8 shows the DC characteristics of the SYSCLK and

SYSCLK# signals.

Figure 8. SYSCLK and SYSCLK# Differential Clock Signals

Table 9. SYSCLK and SYSCLK# DC Characteristics

Symbol Description Min Max Units

VThreshold-DC Crossing before transition is detected (DC) 400 mV

VThreshold-AC Crossing before transition is detected (AC) 450 mV

ILEAK_P Leakage current through P-channel pullup to VCC_CORE –1 mA

ILEAK_N Leakage current through N-channel pulldown to VSS (Ground) 1 mA

VCROSS Differential signal crossover VCC_CORE/2±100 mV

CPIN Capacitance* 4 12* pF

Note:

* The following processor inputs have twice the listed capacitance because they connect to two input pads—SYSCLK and SYSCLK#.

SYSCLK connects to CLKIN/RSTCLK. SYSCLK# connects to CLKIN#/RSTCLK#.

VCROSS VThreshold-DC = 400mV VThreshold-AC = 450mV

Chapter 7 Electrical Data 31

25480D—June 2002 AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms

Preliminary Information

Table 10 shows the SYSCLK/SYSCLK# differential clock AC

characteristics of the AMD Athlon MP processor model 6.

Figure 9 on page 31 shows a sample waveform of the SYSCLK

signal.

Figure 9. SYSCLK Waveform

Table 10. SYSCLK and SYSCLK# AC Characteristics

Symbol Parameter Description Minimum Maximum Units Notes

Clock Frequency 50 133 MHz

Duty Cycle 30% 70%

t1Period 7.5 ns 1, 2

t2High Time 1.05 ns

t3Low Time 1.05 ns

t4Fall Time 2 ns

t5Rise Time 2 ns

Period Stability ± 300 ps

Notes:

1. Circuitry driving the AMD Athlon™ system bus clock inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the

PLL to track the jitter. The –20dB attenuation point, as measured into a 10- or 20-pF load must be less than 500 kHz.

2. Circuitry driving the AMD Athlon system bus clock inputs may purposely alter the AMD Athlon system bus clock frequency (spread

spectrum clock generators). In no cases can the AMD Athlon system bus period violate the minimum specification above.

AMD Athlon system bus clock inputs can vary from 100% of the specified frequency to 99% of the specified frequency at a

maximum rate of 100 kHz.

VCROSS

VThreshold-AC

32 Electrical Data Chapter 7

AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms 25480D—June 2002

Preliminary Information

7.11 AMD Athlon™ System Bus AC and DC Characteristics

Table 11 shows the DC characteristics of the AMD Athlon

system bus used by the AMD Athlon MP processor model 6. See

Table 8, “VCC_CORE Voltage and Current,” on page 29 for

information on TDIE and VCC_CORE. For information about

SYSCLK and SYSCLK#, see “SYSCLK and SYSCLK#” on page

71 and Table 19, “Pin Name Abbreviations,” on page 52.

Table 11. AMD Athlon™ System Bus DC Characteristics

Symbol Parameter Condition Min Max Units Notes

VREF DC Input Reference Voltage (0.5*VCC_CORE)

–50

(0.5*VCC_CORE)

+50 mV 1

IVREF_LEAK_P VREF Tristate Leakage Pullup VIN = VREF Nominal –100 µA

IVREF_LEAK_N VREF Tristate Leakage Pulldown VIN = VREF Nominal 100 µA

VIH Input High Voltage VREF + 200 VCC_CORE +

500 mV

VIL Input Low Voltage –500 VREF – 200 mV

VOH Output High Voltage IOUT = –200 µA0.85 VCC_CORE VCC_CORE+500 mV 2

VOL Output Low Voltage IOUT = 1 mA –500 400 mV 2

ILEAK_P Tristate Leakage Pullup VIN = VSS (Ground) –1 mA

ILEAK_N Tristate Leakage Pulldown VIN = VCC_CORE

Nominal 1mA

CIN Input Pin Capacitance 4 12 pF

Notes:

1. VREF is nominally set to 50% of VCC_CORE with actual values that are specific to motherboard design implementation. VREF must be

created with a sufficiently accurate DC source and a sufficiently quiet AC response to adhere to the ± 50 mV specification listed above.

2. Specified at the TDIE and VCC_CORE specifications in this document.

Chapter 7 Electrical Data 33

25480D—June 2002 AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms

Preliminary Information

The AC characteristics of the AMD Athlon system bus are

shown in Table 12 on page 33. The parameters are grouped

based on the source or destination of the signals involved.

Table 12. AMD Athlon™ System Bus AC Characteristics

Group Symbol Parameter Min Max Units Notes

All Signals TRISE Output Rise Slew Rate 1 3 V/ns 1

TFALL Output Fall Slew Rate 1 3 V/ns 1

Forward

Clocks

TSKEW-SAMEEDGE Output skew with respect to

the same clock edge –385ps2

TSKEW-DIFFEDGE Output skew with respect to a

different clock edge – 770 ps 2

TSU Input Data Setup Time 300 ps 3

THD Input Data Hold Time 300 ps 3

CIN Capacitance on input Clocks 4 12 pF

COUT Capacitance on output Clocks 4 12 pF

Sync

TVAL RSTCLK to Output Valid 250 2000 ps 4, 5

TSU Setup to RSTCLK 500 ps 4, 6

THD Hold from RSTCLK 1000 ps 4, 6

Notes:

1. Rise and fall time ranges are guidelines over which the I/O has been characterized.

2. TSKEW-SAMEEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal and its

forward clock, as measured at the package, with respect to the same clock edge.

TSKEW-DIFFEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal and its

forward clock, as measured at the package, with respect to different clock edges.

3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock.

4. The synchronous signals include PROCRDY, CONNECT, and CLKFWDRST.

5. TVAL is RSTCLK rising edge to output valid for PROCRDY. Test Load is 25 pF.

6. TSU is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. THD is hold of CONNECT/CLKFWDRST from rising edge of

RSTCLK.

34 Electrical Data Chapter 7

AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms 25480D—June 2002

Preliminary Information

7.12 General AC and DC Characteristics

Table 13 shows the AMD Athlon MP processor model 6 AC and

DC characteristics of the Southbridge, JTAG, test, and

miscellaneous pins.

Table 13. General AC and DC Characteristics

Symbol Parameter Description Condition Min Max Units Notes

VIH Input High Voltage (VCC_CORE/2) +

200 mV

VCC_CORE +

300 mV V1,2

VIL Input Low Voltage –300 350 mV 1, 2

VOH Output High Voltage VCC_CORE –

400

VCC_CORE +

300 mV

VOL Output Low Voltage –300 400 mV

ILEAK_P Tristate Leakage Pullup VIN = VSS

(Ground) –1 mA

ILEAK_N Tristate Leakage Pulldown VIN = VCC_CORE

Nominal 600 µA

IOH Output High Current –16 mA 3

IOL Output Low Current 16 mA 3

TSU Sync Input Setup Time 2.0 ns 4, 5

THD Sync Input Hold Time 0.0 ps 4, 5

TDELAY Output Delay with respect to RSTCLK 0.0 6.1 ns 5

Notes:

1. Characterized across DC supply voltage range.

2. Values specified at nominal VCC_CORE. Scale parameters between VCC_CORE minimum and VCC_CORE maximum.

3. IOL and IOH are measured at VOL max and VOH min, respectively.

4. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.

5. These are aggregate numbers.

6. Edge rates indicate the range over which inputs were characterized.

7. In asynchronous operation, the signal must persist for this time to enable capture.

8. This value assumes RSTCLK period is 10 ns ==> TBIT = 2*fRST.

9. The approximate value for standard case in normal mode operation.

10. This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency.

11. Reassertions of the signal within this time are not guaranteed to be seen by the core.

12. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.

13. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other

configurations.

14. Time to valid is for any open-drain pins. See requirements 7 and 8 in Chapter 8, “Power-Up Timing Requirements,“ for more

information.

Chapter 7 Electrical Data 35

25480D—June 2002 AMD Athlon™ MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms

Preliminary Information

TBIT Input Time to Acquire 20.0 ns 7, 8

TRPT Input Time to Reacquire 40.0 ns 9–13

TRISE Signal Rise Time 1.0 3.0 V/ns 6

TFALL Signal Fall Time 1.0 3.0 V/ns 6

CPIN Pin Capacitance 4 12 pF

TVALID Time to data valid 100 ns 14

Table 13. General AC and DC Characteristics (Continued)