FAN48630BUC31JX - ON SEMICONDUCTOR

October, 2019 − Rev. 2

1Publication Order Number:

FAN48630J/D

Synchronous Regulator

with Bypass Mode,

TINYBOOST®,

2.5 MHz, 1500 mA

FAN48630J

Description

The FAN48630J allows systems to take advantage of new battery

chemistries that can supply significant energy when the battery

voltage is lower than the required voltage for system power ICs. By

combining built−in power transistors, synchronous rectification, and

low supply current; this IC provides a compact solution for systems

using advanced Li−Ion battery chemistries.

The FAN48630J is a boost regulator designed to provide a minimum

output voltage (VOUT(MIN)) from a single−cell Li−Ion battery, even

when the battery voltage is below system minimum. Output voltage

regulation is guaranteed to a maximum load current of 1500 mA.

Quiescent current in Shutdown Mode is less than 3 mA, which

maximizes battery life. The regulator transitions smoothly between

Bypass and normal Boost Mode. The device can be forced into Bypass

Mode to reduce quiescent current.

The FAN48630J is available in a 16−bump, 0.4 mm pitch,

Wafer−Level Chip−Scale Package (WLCSP).

Features

•3 External Components: 0.47 mH Inductor and 0603 Case Size Input

and Output Capacitors

•Input Voltage Range: 2.35 V to 5.5 V

•Fixed Output Voltage Option: 3.15 V/3.6 V

•Up to 96% Efficient

•True Bypass Operation when VIN > Target VOUT

•Internal Synchronous Rectifier

•Soft−Start with True Load Disconnect

•Forced Bypass Mode

•VSEL Control to Optimize Target VOUT

•Short−Circuit Protection

•Low Operating Quiescent Current

•16−Bump, 0.4 mm Pitch WLCSP

Applications

•Boost for Low−Voltage Li−ion Batteries, Brownout Prevention,

Boosted Audio, USB OTG, and LTE / 3G RF Power

•Cell Phones, Smart Phones, Portable Instruments

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See detailed ordering and shipping information on page 2 of

this data sheet.

ORDERING INFORMATION

WLCSP16 1.78x1.78x0.586

CASE 567SY

MARKING DIAGRAM

Figure 1. Typical Application

VOUT

PGND

COUT

VIN

VSEL

BYP

CIN

Battery SYSTEM

LO AD

AGND

0.47 mH

0.47mF47 mF

FAN48630

12 = Alphanumeric Device Marking

KK = Lot Rune Code

X = Alphabetical Year Code

Y= 2−weeks Date Code

Z = Assembly Plant Code

Pin−1

Mark

2KK

XYZ

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Table 1. ORDERING INFORMATION

Part Number

Output Voltage

VSELO/VSEL1

Operating

Temperature Package Shipping

†

Device

Marking

FAN48630BUC31JX 3.15 V/3.60 V −40 to 85°C WLCSP Tape & Reel JH

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

TYPICAL APPLICATION

Figure 2. Typical Application Block Diagram

VIN

CIN

GND

Q1B Q1A

COUT

Q3B Q3A

VSEL

BYP

VOUT

Bypass

Control

Synchronous

Rectifier Control

Modulator Logic

and Control

Table 2. RECOMMENDED COMPONENTS

Component Description Vendor Parameter Typ. Unit

L1 0.47 mH, 30% Toko: DFE201612C

DFR201612C

Cyntec: PIFE20161B

L 0.47 mH

CIN 4.7 mF, 10%, 6.3 V, X5R, 0603 (1608) Murata: GRM188R60J475K

TDK: C1608X5R0J475K

C 4.7 mF

COUT 47 mF, 20%, 6.3 V, X5R, 0603 (1608) Samsung: CL10A476MQ8CZNE C 47

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PIN CONFIGURATION

Figure 3. Top Through View (Bumps Down) Figure 4. Bottom View

AGND

VIN

VSEL

AGND PGND

VOUT

B1 B2

A1 A2

D1 D2 D3

BYP

Table 3. PIN DEFINITIONS

Pin # Name Description

A1 EN Enable. When this pin is HIGH, the circuit is enabled (Note 1).

A2 PG Power Good. This is an open−drain output. PG is actively pulled LOW if output falls out of

regulation due to overload or if thermal protection threshold is exceeded.

A3–A4 VIN Input Voltage. Connect to Li−Ion battery input power source.

B1 VSEL Output Voltage Select. When boost is running, this pin can be used to select output voltage.

B2, C2, D1 AGND Analog Ground. This is the signal ground reference for the IC. All voltage levels are

measured with respect to this pin.

B3–B4 VOUT Output Voltage. Place COUT as close as possible to the device.

C1 BYP Bypass. This pin can be used to activate Forced Bypass Mode. When this pin is LOW,

the bypass switches (Q3 and Q1) are turned on and the IC is otherwise inactive.

C3–C4 SW Switching Node. Connect to inductor.

D2–D4 PGND Power Ground. This is the power return for the IC. The COUT bypass capacitor should be

returned with the shortest path possible to these pins.

1. Do not connect the EN pin to VIN. A logic voltage of 1.8 V should control the EN pin and enable/disable the device.

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Table 4. ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Min. Max. Unit

VIN VIN Input Voltage −0.3 6.5 V

VOUT VOUT Output Voltage 6.0 V

SW Node DC −0.3 8.0 V

Transient: 10 ns, 3 MHz −1.0 8.0 V

Other Pins −0.3 6.5

(Note 2)

ESD Electrostatic Discharge Protection Level Human Body Model per JESD22−A114 2.0 kV

Charged Device Model per JESD22−C101 1.5 kV

TJJunction Temperature −40 +150 °C

TSTG Storage Temperature −65 +150 °C

TLLead Soldering Temperature, 10 Seconds +260 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

2. Lesser of 6.5 V or VIN + 0.3 V.

Table 5. RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min. Max. Unit

VIN Supply Voltage 2.35 5.5 V

IOUT Output Current 0 1500 mA

TAAmbient Temperature −40 +85 °C

TJJunction Temperature −40 +125 °C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

Table 6. THERMAL PROPERTIES

Symbol Parameter Typ. Unit

θJA Junction−to−Ambient Thermal Resistance 80 °C/W

θJB Junction−to−Board Thermal Resistance 42

Junction−to−ambient thermal resistance is a function of application and board layout. This data is measured with four−layer Fairchild evaluation

boards (1 oz copper on all layers). Special attention must be paid not to exceed junction temperature TJ(max) at a given ambient temperate TA.

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Table 7. ELECTRICAL CHARACTERISTICS Recommended operating conditions, unless otherwise noted, circuit

per Figure 1, VIN = 2.35 V to 5.5 V, TA = −40°C to 85°C. Typical values are given at VIN = 3.0 V and TA = 25°C.

Symbol Parameter Condition Min. Typ. Max. Unit

IQVIN Quiescent Current Bypass Mode VOUT = 3.15 V,

VIN = 4.2 V

140 190 mA

Boost Mode VOUT = 3.15 V,

VIN = 2.5 V

150 250 mA

Shutdown: EN = 0, VIN = 3.0 V 1.5 5.0 mA

Forced Bypass Mode, VIN = 3.5 V 4 10 mA

ILK VOUT to VIN Reverse Leakage VOUT = 3.6 V, EN = 0 0.2 1.0 mA

ILK_OUT VOUT Leakage Current VOUT = 0, EN = 0, VIN = 4.2 V 0.1 1.0 mA

VUVLO Under−Voltage Lockout VIN Rising 2.20 2.35 V

VUVLO_HYS Under−Voltage Lockout Hystere-

sis

200 mV

VPG(OL) PG Low IPG = 5 mA 0.4 V

IPG_LK PG Leakage Current 1mA

VIH Logic Level High EN, VSEL, BYP 1.2 V

VIL Logic Level Low EN, VSEL, BYP 0.4 V

RLOW Logic Control Pin Pull Downs

(LOW Active) BYP, VSEL, EN 300 kΩ

IPD Weak Current Source Pull−Down BYP, VSEL, EN 100 nA

VREG Output Voltage Accuracy 2.35 V ≤ VIN ≤VOUT_TARGET −100 mV,

DC, 0 to 1500 mA

–2 4 %

fSW Switching Frequency VIN = 2.7 V, VOUT = 3.15 V,

Load = 1000 mA

2.0 2.5 3.0 MHz

IV_LIM Boost Valley Current Limit VIN = 2.6 V 2.6 2.9 3.1 A

VOVP Output Over−Voltage Protection

Threshold

6.0 6.3 V

VOVP_HYS Output Over−Voltage Protection

Hysteresis

300 mV

RDS(ON)N N−Channel Boost Switch RDS(ON) VIN = 3.5 V, VOUT = 3.5 V 85 120 mW

RDS(ON)P P−Channel Sync Rectifier

RDS(ON)

VIN = 3.5 V, VOUT = 3.5 V 65 85 mW

RDS(ON)P_BYP P−Channel Bypass Switch

RDS(ON)

VIN = 3.5 V, VOUT = 3.5 V 65 85 mW

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

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Table 8. SYSTEM CHARACTERISTICS

The following table is verified by design and verified while using the following external components: L = 0.47 mH, DFE201612C−R47M

(Toko), CIN = 4.7 mF, 0603 (1608 metric), C1608X5R0J475K (TDK), COUT = 47mF, 0603 (1608 metric), CL10A476MQ8CZNE

(Samsung). These parameters are not verified in production. Minimum and maximum values are at VIN = 2.5 V to 5.5 V, TA = −40°C

to +85°C; circuit per Figure 1, unless otherwise noted. Typical values are at TA = 25°C, VIN = 3.0 V, VOUT = 3.6 V, VEN = 1.8 V.

Symbol Parameter Condition Min. Typ. Max. Unit

ΔVOUT_LOAD Load Regulation IOUT = 0 A to 1 A, VIN = 3.0 V 80 mV/A

ΔVOUT_LINE Line Regulation 2.7 V ≤ VIN ≤ 3.0 V, IOUT = 1 A 7 mV/V

VOUT_RIPPLE Ripple Voltage VIN = 3.0 V, VOUT = 3.6 V,

IOUT = 800 mA, PWM Mode

10 mV

VIN = 3.0 V, VOUT = 3.6 V,

IOUT = 50 mA, PFM Mode

ηEfficiency VIN = 2.5 V, VOUT = 3.15 V,

IOUT = 20 mA, PFM

90 %

VIN = 3.0 V, VOUT = 3.15 V,

IOUT = 500 mA, PWM

VIN = 3.0 V, VOUT = 3.6 V,

IOUT = 600 mA, PWM

TSS Soft−Start EN High to 95% of Target_ VOUT.

RL = 50 W

550 ms

ΔVOUT_LOAD_TRX Load Transient VIN = 3.0 V, IOUT = 0.5 A ⇔1 A,

TR = TF = 1 ms"95 mV

ΔVOUT_LINE_TRX Line Transient VIN = 2.5 V ⇔ 3.0 V,

TR = TF = 10 ms, IOUT = 300 mA "15 mV

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TYPICAL CHARACTERISTICS

Unless otherwise specified; VIN = 3.0 V, VOUT = 3.6 V, and TA = 25°C; circuit and components according to Figure 1.

Figure 5. Efficiency vs. Load Current and Input

Voltage

Figure 6. Efficiency vs. Load Current and

Temperature

Figure 7. Efficiency vs. Load Current and Input Voltage,

VOUT = 3.15 V

Figure 8. Efficiency vs. Load Current and

Temperature, VOUT = 3.15 V

Figure 9. Output Regulation vs. Load Current and Input

Voltage

Figure 10. Output Regulation vs. Load Current

and Temperature

−2

−1

0 250 500 750 1000 1250 1500

Output Regulation (%)

Load Current (mA)

−40C

+25C

+85C

−2

−1

0 250 500 750 1000 1250 1500

Output Regulation (%)

Load Current (mA)

2.5 VIN

3.0 VIN

3.3 VIN

72%

76%

80%

84%

88%

92%

96%

100%

0 250 500 750 1000 1250 1500

Efficiency

Load Current (mA)

2.5 VIN

3.0 VIN

3.3 VIN

76%

80%

84%

88%

92%

96%

100%

0 250 500 750 1000 1250 1500

Efficiency

Load Current (mA)

−40C

+25C

+85C

76%

80%

84%

88%

92%

96%

100%

0 250 500 750 1000 1250 1500

2.5 VIN

3.0 VIN

3.3 VIN 80%

84%

88%

92%

96%

100%

0 250 500 750 1000 1250 1500

Efficiency

Load Current (mA)

−40C

+25C

+85C

Efficiency

Load Current (mA)

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TYPICAL CHARACTERISTICS (CONTINUED)

Unless otherwise specified; VIN = 3.0 V, VOUT = 3.6 V, and TA = 25°C; circuit and components according to Figure 1.

Figure 11. Quiescent Current vs. Input Voltage and

Temperature, VOUT = 3.15 V, Auto Mode

Figure 12. Quiescent Current vs. Input Voltage and

Temperature, VOUT = 3.15 V, Forced Bypass Mode

Figure 13. Output Ripple vs. Load Current and Input

Voltage

Figure 14. Frequency vs. Load Current and Input

Voltage

Figure 15. Startup, 50  Load Figure 16. Startup, 50  Load, VIN = 2.5 V, VOUT = 3.15 V

100

150

200

250

2.0 2.5 3.0 3.5 4.0 4.5

Input Voltage (V)

−40C Auto

+25C Auto

+85C Auto

2.0 2.5 3.0 3.5 4.0 4.5

Input Voltage (V)

−40C Bypass

+25C Bypass

+85C Bypass

0 250 500 750 1000 1250 1500

Output Ripple (mVpp)

Load Current (mA)

2.5 VIN

3.0 VIN

3.3 VIN

500

1,000

1,500

2,000

2,500

3,000

0 250 500 750 1000 1250 1500

Switching Frequency (KHz)

Load Current (mA)

2.5 VIN

3.0 VIN

3.3 VIN

IL (500mA/div)

VOUT (2V/div)

EN (2V/div)

PG (5V/div)

IL (500mA/div)

VOUT (1V/div)

EN (2V/div)

PG (5V/div)

Input Current (

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TYPICAL CHARACTERISTICS (CONTINUED)

Unless otherwise specified, VIN = 3.0 V; VOUT = 3.6 V, and TA = 25°C; circuit and components according to Figure 1.

Figure 17. Load Transient, IOUT = 500  1000 mA,

1 s Edge

Figure 18. Load Transient, IOUT = 100  500 mA,

1 s Edge, VOUT = 3.15 V

Figure 19. Line Transient, VIN = 3.0 V  3.6 V,

10 s Edge, IOUT = 500 mA, VOUT = 3.15 V

Figure 20. Line Transient, VIN = 2.5 V  3.0 V,

10 s Edge, IOUT = 300 mA

Figure 21. VSEL Step, VIN = 3 V, VOUT = 3.15  V3.6 V,

IOUT = 500 mA

IOUT (500mA/div)

VOUT (100mV/div)

IOUT (500mA/div)

VOUT (100mV/div)

VOUT (200mV/div)

VIN(200mV/div)

VOUT (50mV/div)

VIN(200mV/div)

VOUT (200mV/div)

VSEL (2V/div)

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CIRCUIT DESCRIPTION

FAN48630J is a synchronous boost regulator, typically

operating at 2.5 MHz in Continuous Conduction Mode

(CCM), which occurs at moderate to heavy load current and

low VIN voltages. The regulator includes a Bypass Mode

that activates when VIN is above the boost regulator’s

setpoint.

In anticipation of a heavy load transition, the setpoint can

be adjusted upward by fixed amounts with the VSEL pin to

reduce the required system headroom during lighter−load

operation to save power.

Table 9. Operating States

Mode Description Invoked When

LIN Linear Startup VIN > VOUT

SS Boost Soft−Start VOUT < VOUT(MIN)

BST Boost Operating Mode VOUT = VOUT(MIN)

BPS True Bypass Mode VIN > VOUT(MIN)

Boost Mode

The FAN48630J uses a current−mode modulator to

achieve excellent transient response and smooth transitions

between CCM and Discontinuous Conduction Mode

(DCM) operation. During CCM operation, the device

maintains a switching frequency of about 2.5 MHz.

In light−load operation (DCM), frequency is reduced to

maintain high efficiency.

Table 10. Boost Startup Sequence

Start

State Entry Exit End State

Timeout

(s)

LIN1 VIN >

UVLO,

EN = 1

VOUT >

VIN−300 mV

LIN2 512

LIN2 LIN1 Exit VOUT >

VIN−300 mV

TIMEOUT FAULT 1024

SS LIN1 or

LIN2 Exit

VOUT =

VOUT(MIN)

BST

OVERLOAD

TIMEOUT

FAULT 64

Shutdown and Startup

If EN is LOW, all bias circuits are off and the regulator is

in Shutdown Mode. During shutdown, current flow is

prevented from VIN to VOUT, as well as reverse flow from

VOUT to VIN. During startup, it is recommended to keep DC

current draw below 500 mA.

LIN State

When EN is HIGH and VIN > UVLO, the regulator

attempts to bring VOUT within 300 mV of VIN using the

internal fixed current source from VIN (Q3). The current is

limited to LIN1 set point.

If VOUT reaches VIN−300 mV during LIN1 Mode, the SS

state is initiated. Otherwise, LIN1 times out after 512 ms and

LIN2 Mode is entered.

In LIN2 Mode, the current source is incremented to 2 A.

If VOUT fails to reach VIN−300 mV after 1024 ms, a fault

condition is declared.

SS State

Upon the successful completion of the LIN state

(VOUT ≥VIN−300 mV), the regulator begins switching with

boost pulses current limited to 50% of nominal level.

During SS state, VOUT is ramped up by stepping the

internal reference. If VOUT fails to reach regulation during

the SS ramp sequence for more than 64 ms, a fault condition

is declared. If large COUT is used, the reference

is automatically stepped slower to avoid excessive input

current draw.

BST State

This is a normal operating state of the regulator.

BPS State

If VIN is above VREG when the SS Mode successfully

completes, the device transitions directly to BPS Mode.

FAULT State

The regulator enters the FAULT state under any of

the following conditions:

•VOUT fails to achieve the voltage required to advance

from LIN state to SS state.

•VOUT fails to achieve the voltage required to advance

from SS state to BST state.

•Boost current limit triggers for 2 ms during the BST

state.

•VDS protection threshold is exceeded during BPS state.

•VIN drops below UVLO threshold.

Once a FAULT is triggered, the regulator stops switching

and presents a high−impedance path between VIN to VOUT.

After waiting 20 ms, a restart is attempted.

Power Good

Power good is 0 FAULT, 1 POWER GOOD, open−drain

output.

The Power good pin is provided for signaling the system

when the regulator has successfully completed soft−start

and no faults have occurred. Power good also functions as

an early warning flag for high die temperature and overload

conditions.

•PG is released HIGH when the soft−start sequence is

successfully completed.

•PG is pulled LOW when PMOS current limit has

triggered for 64 ms OR the die the temperature exceeds

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120CC. PG is re−asserted when the device cools below

to 100CC.

•Any FAULT condition causes PG to be de−asserted.

Over−Temperature

The regulator shuts down when the die temperature

exceeds 150°C. Restart occurs when the IC has cooled by

approximately 20°C.

Bypass Operation

In normal operation, the device automatically transitions

from Boost Mode to Bypass Mode, if VIN goes above target

VOUT. In Bypass Mode, the device fully enhances both Q1

and Q3 to provide a very low impedance path from VIN to

VOUT. Entry to the Bypass Mode is triggered by condition

where VIN > VOUT and no switching has occurred during

past 5 ms. To soften the entry to Bypass Mode, Q3 is driven

as a linear current source for the first 5 ms. Bypass Mode exit

is triggered when VOUT reaches the target VOUT voltage.

During Automatic Bypass Mode, the device is short−circuit

protected by voltage comparator tracking the voltage drop

from VIN to VOUT; if the drop exceeds 200 mV, FAULT is

declared.

With sufficient load to enforce CCM operation, the

Bypass Mode to Boost Mode transition occurs at the target

VOUT. The corresponding input voltage at the transition

point is:

VIN vVOUT )ILOAD * (DCRL)RDS(ON)P)ŦRDS(ON)BYP (eq. 1)

The Bypass Mode entry threshold has 25 mV hysteresis

imposed at VOUT to prevent cycling between modes. The

transition from Boost Mode to Bypass Mode occurs at the

target VOUT+25 mV. The corresponding input voltage is:

VIN wVOUT )25mV )ILOAD * (DCRL)RDS(ON)P)(eq. 2)

Forced Bypass

Entry to Forced Bypass Mode initiates with a current limit

on Q3 and then proceeds to a true bypass state. To prevent

reverse current to the battery, the device waits until output

discharges below VIN before entering Forced Bypass Mode.

After the transition is complete, most of the internal

circuitry is disabled to minimize quiescent current draw.

Short−circuit, UVLO, output OVP and over−temperature

protections are inactive in Forced Bypass Mode.

In Forced Bypass Mode, VOUT can follow VIN below

VOUT(MIN).

VSEL

VSEL can be asserted in anticipation of a positive load

transient. Raising VSEL increases VOUT(MIN) by a fixed

amount and VOUT is stepped to the corresponding target

output voltage in 20 ms. The functionality can also be utilized

to mitigate undershoot during severe line transients, while

minimizing VOUT during more benign operating conditions

to save power.

Setting the EN pin voltage below 0.4 V disables the part.

Placing the voltage above 1.2 V enables the part. Do not

connect the EN pin to VIN. A logic voltage of 1.8 V should

control the EN pin and enable / disable the device. The EN

pin should be pulled HIGH after the VIN voltage has reached

a minimum voltage of 2.3 V.

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APPLICATION INFORMATION

Output Capacitance (COUT)

Stability

The effective capacitance (CEFF) of small, high−value,

ceramic capacitors decreases as bias voltage increases.

FAN48630J is guaranteed for stable operation with the

minimum value of CEFF (CEFF(MIN)) outlined in Table 11.

Table 11. Minimum CEFF Required for Stability

Operating Conditions

CEFF(MIN) (F

VOUT (V) ILOAD (mA)

3.15 0 to 1500 15

CEFF varies with manufacturer, material, and case size.

Inductor Selection

Recommended nominal inductance value is 0.47 mH.

FAN48630J employs valley−current limiting; peak

inductor current can reach 3.8 A for a short duration during

overload conditions. Saturation effects cause the inductor

current ripple to become higher under high loading as only

valley of the inductor current ripple is controlled.

A 0.33 mH inductor can be used for improved transient

performance.

Startup

Input current limiting is in effect during soft−start, which

limits the current available to charge COUT and any

additional capacitance on the VOUT line. If the output fails

to achieve regulation within the limits described in the

Startup section, a FAULT occurs, causing the circuit to shut

down then restart after 20 ms. If the total combined output

capacitance is very high, the circuit may not start on the first

attempt, but eventually achieves regulation if no load is

present. If a high−current load and high capacitance are both

present during soft−start, the circuit may fail to achieve

regulation and continually attempts soft−start, only to have

the output capacitance discharged by the load when in

a FAULT state.

Output Voltage Ripple

Output voltage ripple is inversely proportional to COUT.

During tON, when the boost switch is on, all load current is

supplied by COUT. Output ripple is calculated as:

VRIPPLE(P*P) +tON *ILOAD

COUT

(eq. 3)

and

tON +tSW *D+tSW *ǒ1*VIN

VOUTǓ(eq. 4)

therefore:

VRIPPLE(P*P) +tSW *ǒ1*VIN

VOUTǓ*ILOAD

COUT

(eq. 5)

and

tSW +1

fSW

(eq. 6)

Layout Recommendations

The layout recommendations below highlight various

top−copper pours using different colors.

To minimize spikes at VOUT, COUT must be placed as

close as possible to PGND and VOUT, as shown in

Figure 22.

For thermal reasons, it is suggested to maximize the pour

area for all planes other than SW. Especially the ground pour

should be set to fill all available PCB surface area and tied

to internal layers with a cluster of thermal vias.

ure 22. To

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Figure 23. Layer 2

Figure 24. Layer 3

Table 12. PRODUCT−SPECIFIC DIMENSIONS

Product D E X Y

FAN48630BUC31JX 1.780 ±0.030 1.780 ±0.030 0.290 0.290

TINYBOOST is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.

FAIRCHILD is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.

WLCSP16 1.78x1.78x0.586

CASE 567SY

ISSUE O

DATE 30 NOV 2016

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

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