ICE3B1565J - INFINEON TECHNOLOGIES AG

CoolSET®-F3R

(Jitter Version)

ICE3B0365J

ICE3B0565J

ICE3B1565J

ICE3B2065J

Off-Line SMPS Current Mode

Controller with integrated 650V

CoolMOS®and Startup cell

(frequency jitter Mode) in DIP-8

N e v e r s t o p t h i n k i n g .

Power Management & Supply

Datasheet, Version 2.7, 9 M ay 201 2

Edition 2012-5-09

Published by

Infineon Technologies AG,

81726 Munich, Germany,

Legal disclaimer

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characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any

information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties

and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights

of any third party.

Information

For further information on technology, delivery terms and conditions and prices, please contact your nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types in

question, please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may be used in life-support devices or systems only with the express written

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CoolMOS®, CoolSET®are trademarks of Infineon Technologies AG.

CoolSET®-F3R

ICE3Bxx65J

Revision History: 2012-5-09 Datasheet Version 2.7

Previous Version: 2.6

Page Subjects (major changes since last revision)

23 Revised typo in outline dimension

Type Package Marking VDS FOSC RDSon1)

1) typ @ T=25°C

230VAC ±15%2)

2) Calculated maximum input power rating at Ta=75°C, Tj=125°C and without copper area as heat sink

85-265 VAC2)

ICE3B0365J PG-DIP-8 ICE3B0365J 650V 67kHz 6.45W 22W 10W

ICE3B0565J PG-DIP-8 ICE3B0565J 650V 67kHz 4.70W 25W 12W

ICE3B1565J PG-DIP-8 ICE3B1565J 650V 67kHz 1.70W 42W 20W

ICE3BR2065J PG-DIP-8 ICE3B2065J 650V 67kHz 0.92W 57W 28W

Version 2.7 3 9 May 2012

CoolSET®-F3R

ICE3Bxx65J

Off-Line SMPS Current Mode Controller with

integrated 650V CoolMOS®and Startup cell

(frequency jitter Mode) in DIP-8

PG-DIP-8

Product Highlights

• Active Burst Mode to reach the lowest Standby Power

Requirements < 100mW

• Adjustable Blanking Window for High Load Jumps to

increase Reliability

• Frequency Jittering for Low EMI

• Pb-free lead plating, RoHS compilant

Features

• 650V Avalanche Rugged CoolMOS®with built in

switchable Startup Cell

• Active Burst Mode for lowest Standby Power

@ light load controlled by Feedback Signal

• Fast Load Jump Response in Active Burst Mode

• 67 kHz fixed Switching Frequency

• Auto Restart Mode for Over temperature

Detection

• Auto Restart Mode for Overvoltage Detection

• Auto Restart Mode for Overload and Open Loop

• Auto Restart Mode for VCC Undervoltage

• User defined Soft Start

• Minimum of external Components required

• Max Duty Cycle 75%

• Overall Tolerance of Current Limiting < ±5%

• Internal Leading Edge Blanking

• BiCMOS technology provides wide VCC Range

• Frequency Jittering for Low EMI

Description

The CoolSET®-F3(Jitter version) meets the requirements

for Off-Line Battery Adapters and low cost SMPS for the

lower power range. By use of a BiCMOS technology a wide

VCC range up to 26V is provided. This covers the changes

in the auxiliary supply voltage if a CV/CC regulation is

implemented on the secondary side. Furthermore an Active

Burst Mode is integrated to fullfillthe lowest Standby Power

Requirements <100mW at no load and Vin = 270VAC. As

during Active Burst Mode the controller is always active

there is an immediate response on load jumps possible

without any black out in the SMPS. In Active Burst Mode

the ripple of the output voltage can be reduced <1%.

Furthermore Auto Restart Mode is entered in case of

Overtemperature, VCC Overvoltage, Output Open loop or

Overload and VCC Undervoltage. By means of the internal

precise peak current limitation, the dimension of the

transformer and the secondary diode can be lowered which

leads to more cost efficiency.

CSoftS

CVCC

CBulk Converter

DC Output

Snubber

Power Management

PWM Controller

Current Mode

85 ... 270 VAC

Typical Application

RSense

SoftS

GND Active Burst Mode

Auto Restart Mode

Control

Unit

VCC

Startup Cell

Precise Low Tolerance Peak

Current Limitation

Drain

CoolSET™-F3

(Jitter Version)

Depl. CoolMOS™

CoolSET®-F3R

ICE3Bxx65J

Table of Contents Page

Version 2.7 4 9 May 2012

1 Pin Configuration and Functionality .............................5

1.1 Pin Configuration with PG-DIP-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

1.2 PinFunctionality ..............................................5

2 Representative Blockdiagram ..................................6

3 Functional Description ........................................7

3.1 Introduction ..................................................7

3.2 PowerManagement............................................7

3.3 StartupPhase ................................................8

3.4 PWMSection.................................................9

3.4.1 Oscillator ..................................................9

3.4.2 PWM-LatchFF1.............................................9

3.4.3 GateDriver ................................................9

3.5 CurrentLimiting ..............................................10

3.5.1 Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.5.2 Propagation Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.6 ControlUnit .................................................11

3.6.1 Adjustable Blanking Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.6.2 ActiveBurstMode ..........................................12

3.6.2.1 Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.6.2.2 Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.6.2.3 Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.6.3 ProtectionModes...........................................13

3.6.3.1 AutoRestartMode........................................14

4 Electrical Characteristics .....................................15

4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.2 OperatingRange .............................................16

4.3 Characteristics...............................................16

4.3.1 SupplySection.............................................16

4.3.2 Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.3.3 PWMSection..............................................17

4.3.4 ControlUnit ...............................................17

4.3.5 CurrentLimiting ............................................18

4.3.6 CoolMOS®Section .........................................18

5 Temperature derating curve ...................................20

6 Outline Dimension ...........................................23

7 Marking ....................................................24

8Schematic for recommended PCB layout ........................26

Version 2.7 5 9 May 2012

CoolSET®-F3R

ICE3Bxx65J

1 Pin Configuration and Functionality

1.1 Pin Configuration with PG-DIP-8

Figure 1 Pin Configuration PG-DIP-8(top view)

Note: Pin 4 and 5 are shorted within the DIP

package.

1.2 Pin Functionality

SoftS (Soft Start, Auto Restart & Frequency

Jittering Control)

The SoftS pin combines the function of Soft Start

during Start Up and error detection for Auto Restart

Mode. These functions are implemented and can be

adjusted by means of an external capacitor at SoftS to

ground. This capacitor also provides an adjustable

blanking window for high load jumps, before the IC

enters into Auto Restart Mode. Furthermore this pin is

also used to control the period of frequency jittering

during normal load.

FB (Feedback)

The information about the regulation is provided by the

FB Pin to the internal Protection Unit and to the internal

PWM-Comparator to control the duty cycle. The FB-

Signal controls in case of light load the Active Burst

Mode of the controller.

CS (Current Sense)

The Current Sense pin senses the voltage developed

on the series resistor inserted in the source of the

integrated CoolMOS®. If CS reaches the internal

threshold of the Current Limit Comparator, the Driver

output is immediately switched off. Furthermore the

current information is provided for the PWM-

Comparator to realize the Current Mode.

Drain (Drain of integrated CoolMOS®)

Pin Drain is the connection to the Drain of the internal

CoolMOSTM.

VCC (Power supply)

The VCC pin is the positive supply of the IC. The

operating range is between 10.3V and 26V.

GND (Ground)

The GND pin is the ground of the controller.

Pin Symbol Function

1 SoftS Soft-Start

2 FB Feedback

3 CS Current Sense/

650V1) CoolMOS®Source

4 Drain 650V1) CoolMOS®Drain

1) at Tj= 110°C

5 Drain 650V1) CoolMOS®Drain

6 N.C. Not Connected

7 VCC Controller Supply Voltage

8 GND Controller Ground

Package PG-DIP-8

GNDSoftS

VCC

N.C

Drain Drain

Version 2.7 6 9 May 2012

CoolSET®-F3R

ICE3Bxx65J

2 Representative Blockdiagram

Figure 2 Representative Blockdiagram

Version 2.7 7 9 May 2012

CoolSET®-F3R

ICE3Bxx65J

3 Functional Description

All values which are used in the functional description

are typical values. For calculating the worst cases the

min/max values which can be found in section 4

Electrical Characteristics have to be considered.

3.1 Introduction

CoolSET®-F3 Jitter version is the further development

of the CoolSET®-F2 to meet the requirements for the

lowest Standby Power at minimum load and no load

conditions. A new fully integrated Standby Power

concept is implemented into the IC in order to keep the

application design easy. Compared to CoolSET®-F2 no

further external parts are needed to achieve the lowest

Standby Power. An intelligent Active Burst Mode is

used for this Standby Mode. After entering this mode

there is still a full controlof the power conversion by the

secondary side via the same optocoupler that is used

for the normal PWM control. The response on load

jumps is optimized. The voltage ripple on Vout is

minimized. Vout is further on well controlled in this

mode.

The usually external connected RC-filter in the

feedback line after the optocoupler is integrated in the

IC to reduce the external part count.

Furthermore a high voltage Startup Cell is integrated

into the IC which is switched off once the Undervoltage

Lockout on-threshold of 18V is exceeded. This Startup

Cell is part of the integrated CoolMOS®. The external

startup resistor is no longer necessary as this Startup

Cell is connected to the Drain. Power losses are

therefore reduced. This increases the efficiency under

light load conditions drastically.

The Soft-Start capacitor is also used for providing an

adjustable blanking window for high load jumps. During

this time window the overload detection is disabled.

With this concept no further external components are

necessary to adjust the blanking window.

An Auto Restart Mode is implemented in the IC to

reduce the average power conversion in the event of

malfunction or unsafe operating condition in the SMPS

system. This feature increases the system’s

robustness and safety which would otherwise lead to a

destruction of the SMPS. Once the malfunction is

removed, normal operation is automatically initiated

after the next Start Up Phase.

The internal precise peak current limitation reduces the

costs for the transformer and the secondary diode. The

influence of the change in the input voltage on the

power limitation can be avoided together with the

integrated Propagation Delay Compensation.

Therefore the maximum power is nearly independent

on the input voltage which is required for wide range

SMPS. There is no need for an extra over-sizing of the

SMPS, e.g. the transformer or the secondary diode.

3.2 Power Management

Figure 3 Power Management

The Undervoltage Lockout monitors the external

supply voltage VVCC. When the SMPS is plugged to the

main line the internal Startup Cell is biased and starts

to charge the external capacitor CVCC which is

connected to the VCC pin. The VCC charge current

that is provided by the Startup Cell from the Drain pin is

1.05mA. When VVCC exceeds the on-threshold

VCCon=18V, bias circuit is switched on. Then the

Startup Cell is switched off by the Undervoltage

Lockout and therefore no power losses present due to

the connection of the Startup Cell to the Drain voltage.

To avoid uncontrolled ringing at switch-on a hysteresis

is implemented. The switch-off of the controller can

only take place after active mode was entered and

VVCC falls below 10.3V.

The maximum current consumption before the

controller is activated is about 300uA.

Internal Bias

Voltage

Reference

Power Management

VCC

Undervoltage Lockout

18V

10.3

Power-Down Reset

SoftS

Active Burst

Mode

Auto Restart

Mode

Startup Cell

Drain

CoolSET®-F3R

ICE3Bxx65J

Version 2.7 8 9 May 2012

When VVCC falls below the off-threshold VCCoff=10.3V

the bias circuit is switched off and the Power Down

reset let T1 discharging the soft-start capacitor CSoftS at

pin SoftS. Thus it is ensured that at every startup cycle

the voltage ramp at pin SoftS starts at zero.

The bias circuit is switched off if Auto Restart Mode is

entered. The current consumption is then reduced to

300uA.

Once the malfunction condition is removed, this block

will then turn back on. The recovery from Auto Restart

Mode does not require disconnecting the SMPS from

the AC line.

When Active Burst Mode is entered, some internal Bias

is switched off in order to reduce the current

consumption to about 500uA while keeping a

comparator (which trigger if VFB has exceeded 3.61V)

and the Soft Start capacitor clamped at 3.0 V as this is

necessary in this mode.

3.3 Startup Phase

Figure 4 Soft Start

At the beginning of the Startup Phase, the IC provides

a Soft Start duration whereby it controls the maximum

primary current by means of a duty cycle limitation. A

capacitor CSofts in combination with the internal pull up

resistor RSoftS determines the duty cycle until VSoftS

exceeds 3.1V.

When the Soft Start begins, CSoftS is immediately

charged up to approx. 0.8V by T2. Therefore the Soft

Start Phase takes place between 0.8V and 3.1V.

Above VSoftsS = 3.1V there is no longer duty cycle

limitation DCmax which is controlled by comparator C7

since comparator C2 blocks the gate G7 (see Figure

5).This maximum charge current in the very first stage

when VSoftS is below 0.8V, is limited to 0.9mA.

Figure 5 Startup Phase

By means of this extra charge stage, there is no delay

in the beginning of the Startup Phase when there is still

no switching. Furthermore Soft Start is finished at 3.1V

to have faster the maximum power capability. The duty

cycles DC1and DC2are depending on the mains and

the primary inductance of the transformer. The

limitation of the primary current by DC2is related to

VSoftS = 3.1V. But DC1is related to a maximum primary

current which is limited by the internal Current Limiting

with CS = 1V. Therefore the maximum Startup Phase

is divided into a Soft Start Phase until t1 and a phase

from t1 until t2 where maximum power is provided if

demanded by the FB signal.

Soft-Start

Comparator

Soft Start

CSoftS

RSoftS

3.25k5V

T3 0.8V

SoftS

Gate Driver

0.6V

x3.2

PWM OP

3.1V C2

Freq Jitter

Charging

current IFJ

Freq Jitter

Discharging

current IFJ Freq Jitter

Control

DCmax

DC1

DC2

VSoftS

max. Soft Start Phase

0.8V

3.1V

4.0V

max. Startup Phase

t1 t2

CoolSET®-F3R

ICE3Bxx65J

Version 2.7 9 9 May 2012

3.4 PWM Section

Figure 6 PWM Section

3.4.1 Oscillator and Jittering

The oscillator generates a fixed frequency with

frequency jittering of ±4% from the fixed frequency

(which is ±2.7kHz from 67kHz) at a jittering period TFJ.

The switching frequency is fswitch = 67kHz.

A resistor, a capacitor and a currentsource and current

sink which determine the frequency are integrated. The

charging and discharging current of the implemented

oscillator capacitor are internally trimmed, in order to

achieve a very accurate switching frequency. The ratio

of controlled charge to discharge current is adjusted to

reach a maximum duty cycle limitation of Dmax=0.75.

Once the Soft Start period is over and when the IC goes

into normal mode, the Soft Start capacitor will be

charged and discharged through internal current

source, IFJ to generate a triangular waveform with a

jittering period TFJ which is externally adjustable by the

Soft Start capacitor, CSoftS (See Figure 4).

TFJ = kFJ * CSoftS

where kFJ is a constant = 4 ms/uF

eg. TFJ = 4 ms if CSoftS = 1uF

3.4.2 PWM-Latch FF1

The oscillator clock output provides a set pulse to the

PWM-Latch when initiating the internal CoolMOS®

conduction. After setting the PWM-Latch can be reset

by the PWM comparator, the Soft Start comparator or

the Current-Limit comparator. In case of resetting the

driver is shut down immediately.

3.4.3 Gate Driver

The Gate Driver is a fast totem pole gate drive which is

designed to avoid cross conduction currents.

The Gate Driver is active low at voltages below the

undervoltage lockout threshold VVCCoff.

Figure 7 Gate Driver

Oscillator

Duty

Cycle

max

Gate Driver

0.75

Clock

PWM Section

FF1

Gate

Soft Start

Comparator

PWM

Comparator

Current

Limiting

Frequency

Jitter

SoftS

VCC

PWM-Latch

Depl. CoolMOS™

Gate Driver

Gate

CoolSET®-F3R

ICE3Bxx65J

Version 2.7 10 9 May 2012

3.5 Current Limiting

Figure 8 Current Limiting

There is a cycle by cycle Current Limiting realized by

the Current-Limit comparator C10 to provide an

overcurrent detection. The source current of the

integrated CoolMOS®is sensed via an external sense

resistor RSense . By means of RSense the source current

is transformed to a sense voltage VSense which is fed

into the pin CS. If the voltage VSense exceeds the

internal threshold voltage Vcsth the comparator C10

immediately turns off the gate drive by resetting the

PWM Latch FF1. A Propagation Delay Compensation

is added to support the immediate shut down without

delay of the integrated internal CoolMOS®in case of

Current Limiting. The influence of the AC input voltage

on the maximum output power can thereby be avoided.

To prevent the Current Limiting from distortions caused

by leading edge spikes a Leading Edge Blanking is

integrated in the current sense path for the

comparators C10, C12 and the PWM-OP.

The output of comparator C12 is activated by the Gate

G10 if Active Burst Mode is entered. Once activated the

current limiting is thereby reduced to 0.32V. This

voltage level determines the power level when the

Active Burst Mode is left if there is a higher power

demand.

3.5.1 Leading Edge Blanking

Figure 9 Leading Edge Blanking

Each time when the integrated internal CoolMOS®is

switched on a leading edge spike is generated due to

the primary-side capacitances and secondary-side

rectifier reverse recovery time. This spike can cause

the gate drive to switch off unintentionally. To avoid a

premature termination of the switching pulse, this spike

is blanked out with a time constant of tLEB = 220ns.

During this time, the gate drive will not be switched off.

3.5.2 Propagation Delay Compensation

In case of overcurrent detection, the switch-off of the

integrated internal CoolMOS®is delayed due to the

propagation delay of the circuit. This delay causes an

overshoot of the peak current Ipeak which depends on

the ratio of dI/dt of the peak current (see Figure 10).

Figure 10 Current Limiting

The overshoot of Signal2 is bigger than of Signal1 due

to the steeper rising waveform. This change in the

slope is depending on the AC input voltage.

Propagation Delay Compensation is integrated to limit

the overshoot dependency on dI/dt of the rising primary

current. That means the propagation delay time

between exceeding the current sense threshold Vcsth

and the switch off of the integrated inernal CoolMOS®

is compensated over temperature within a wide range.

Current Limiting

C10

C12

0.32V

G10

Propagation-Delay

Compensation

Vcsth

Active Burst

Mode

PWM Latch

FF1

10k

1pF

PWM-OP

Leading

Edge

Blanking

220ns

VSense

Vcsth tLEB =220ns

Sense

Limit

Propagation Delay

Overshoot1

peak1

Signal1Signal2

Overshoot2

peak2

CoolSET®-F3R

ICE3Bxx65J

Version 2.7 11 9 May 2012

Current Limiting is now possible in a very accurate way.

E.g. Ipeak = 0.5A with RSense = 2. Without Propagation

Delay Compensation the current sense threshold is set

to a static voltage level Vcsth=1V. A current ramp of

dI/dt = 0.4A/µs, that means dVSense/dt = 0.8V/µs, and a

propagation delay time of i.e. tPropagation Delay =180ns

leads then to an Ipeak overshoot of 14.4%. By means of

propagation delay compensation the overshoot is only

about 2% (see Figure 11).

Figure 11 Overcurrent Shutdown

The Propagation Delay Compensation is realized by

means of a dynamic threshold voltage Vcsth (see Figure

12). In case of a steeper slope the switch off of the

driver is earlier to compensate the delay.

Figure 12 Dynamic Voltage Threshold Vcsth

3.6 Control Unit

The Control Unit contains the functions for Active Burst

Mode and Auto Restart Mode. The Active Burst Mode

and the Auto Restart Mode are combined with an

Adjustable Blanking Window which is depending on the

external Soft Start capacitor. By means of this

Adjustable Blanking Window, the IC avoids entering

into these two modes accidentally. Furthermore it also

provides a certain time whereby the overload detection

is delayed. This delay is useful for applications which

normally works with a low current and occasionally

require a short duration of high current.

3.6.1 Adjustable Blanking Window

Figure 13 Adjustable Blanking Window

VSoftS swings between 3.2V and 3.6V after the SMPS is

settled and S2 is on while S3 is off, this is due to the

frequency jittering function that is making use of the

Soft Start pin. If overload occurs VFB is exceeding 4.5V.

Auto Restart Mode can’t be entered as the gate G5 is

still blocked by the comparator C3. But after VFB has

0,9

0,95

1,05

1,1

1,15

1,2

1,25

1,3

0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2

with compensation without compensation

dVSense s



Sense

csth

OSC

Signal1 Signal2

Sense

Propagation Delay

max. Duty Cycle

off time

4.0V

4.5V

1.35V

3.0V

Control Unit

Active

Burst

Mode

Auto

Restart

Mode

RSoftS

SoftS

Frequency

Jitter

CoolSET®-F3R

ICE3Bxx65J

Version 2.7 12 9 May 2012

exceeded 4.5V the switch S2 is opened and S3 is

closed. The external Soft Start capacitor can now be

charged further by the integrated pull up resistor RSoftS

via switch S3. The comparator C3 releases the gates

G5 and G6 once VSofts has exceeded 4.0V. Therefore

there is no entering of Auto Restart Mode possible

during this charging time of the external capacitor

CSoftS. The same procedure happens to the external

Soft Start capacitor if a low load condition is detected

by comparator C5 when VFB is falling below 1.35V.

Only after VSoftS has exceeded 4.0V and VFB is still

below 1.35V Active Burst Mode is entered.

3.6.2 Active Burst Mode

The controller provides Active Burst Mode for low load

conditions at VOUT. Active Burst Mode increases

significantly the efficiency at light load conditions while

supporting a low ripple on VOUT and fast response on

load jumps. During Active Burst Mode which is

controlled only by the FB signal the IC is always active

and can therefore immediately response on fast

changes at the FB signal. The Startup Cell is kept

switched off to avoid increased power losses for the

self supply.

Figure 14 Active Burst Mode

The Active Burst Mode is located in the Control Unit.

Figure 14 shows the related components.

3.6.2.1 Entering Active Burst Mode

The FB signal is always observed by the comparator

C5 if the voltage level fallsbelow 1.35V. In that case the

switch S1 and S2 is released which allows the

capacitor CSoftS to be charged via S3 starting from the

swinging voltage level between 3.2V and 3.6V in

normal operating mode. If VSoftS exceeds 4.0V the

comparator C3 releases the gate G6 to enter the Active

Burst Mode. The time window that is generated by

combining the FB and SoftS signals with gate G6

avoids a sudden entering of the Active Burst Mode due

to large load jumps. This time window can be adjusted

by the external capacitor CSoftS.

After entering Active Burst Mode a burst flag is set and

the internal bias is switched off in order to reduce the

current consumption of the IC down to approx. 500uA.

Also, switch S1 is closed to clamped the Soft Start

voltage to 3.0V. In this Off State Phase the IC is no

longer self supplied so that therefore CVCC has to

provide the VCC current (see Figure 15). Furthermore

gate G11 is then released to start the next burst cycle

once VFB has 3.0V exceeded.

It has to be ensured by the application that the VCC

remains above the Undervoltage Lockout Level of

10.3V to avoid that the Startup Cell is accidentally

switched on. Otherwise power losses are significantly

increased. The minimum VCC level during Active Burst

Mode is depending on the load conditions and the

application. The lowest VCC level is reached at no load

conditions at VOUT.

3.6.2.2 Working in Active Burst Mode

After entering the Active Burst Mode the FB voltage

rises as VOUT starts to decrease due to the inactive

PWM section. Comparator C6a observes the FB signal

if the voltage level 3.61V is exceeded. In that case the

internal circuit is again activated by the internal Bias to

start with switching. As now in Active Burst Mode the

gate G10 is released the current limit is only 0.32V to

reduce the conduction losses and to avoid audible

noise. If the load at VOUT is still below the starting level

for the Active Burst Mode the FB signal decreases

down to 3.0V. At this level C6b deactivates again the

internal circuit by switching off the internal Bias. The

gate G11 is released as after entering Active Burst

Mode the burst flag is set. If working in Active Burst

Mode the FB voltage is changing like a saw tooth

between 3.0V and 3.61V (see figure 15).

3.6.2.3 Leaving Active Burst Mode

The FB voltage immediately increases if there is a high

load jump. This is observed by comparator C4. As the

current limit is ca. 32% during Active Burst Mode a

certain load jump is needed that FB can exceed 4.5V.

Atthis time C4 resets the Active Burst Mode which also

4.0V

4.5V

C6a

3.61V

1.35V

Control Unit

Active

Burst

Mode

3.0V

S1 Internal Bias

RSoftS

SoftS

G10

Current

Limiting

C6b

3.0V

G11

Frequency

Jitter

CoolSET®-F3R

ICE3Bxx65J

Version 2.7 13 9 May 2012

blocks C12 by the gate G10. Maximum current can now

be provided to stabilize VOUT.

Figure 15 Signals in Active Burst Mode

3.6.3 Protection Modes

The IC provides several protection features that

increase the SMPS system’s robustness and safety.

The following table shows the possible system failures

and the corresponding protection modes.

3.6.3.1 Auto Restart Mode I

Figure 16 Auto Restart Mode I

The VCC voltage is observed by comparator C13 if

20.5V is exceeded. The output of C13 is combined with

both the output of C3 which checks for VSoftS < 4.0V and

the output of C4 which checks for VFB > 4.5V. Therefore

the overvoltage detection can only be active during Soft

Start Phase (VSoftS < 4.0V) and when FB signal is

outside the operating range > 4.5V. This means any

1.35V

3.61V

4.5V

VFB

3.0V

4.0V

VSoftS t

0.32V

1.0V

VCS

10.3V

VVCC t

500uA

IVCC

2mA

VOUT

Max. Ripple < 1%

Blanking Window

Current limit level

during Active Burst

Mode

3.0V

Entering

Active Burst

Mode

Leaving

Active Burst

Mode

3.6V~

3.2V

VCC Overvoltage Auto Restart Mode I

Over temperature Auto Restart Mode I

Overload Auto Restart Mode II

Open Loop Auto Restart Mode II

VCC Undervoltage Auto Restart Mode II

Short Optocoupler Auto Restart Mode II

Spike

Blanking

8.0us

Thermal Shutdown

Tj>140°C

Auto

Restart

Mode

Internal

Bias

Control Unit

C13

20.5V

VCC

4.5V

4.0V

SoftS

G12

G13

FF2

UVLO

CoolSET®-F3R

ICE3Bxx65J

Version 2.7 14 9 May 2012

small voltage overshoots of VVCC during normal

operating cannot trigger the Auto Restart Mode I.

In Order to ensure system reliability and prevent any

false activation, a blanking time is implemented before

the IC can enter into the Auto Restart Mode I. The

output of the VCC overvoltage detection is fed into a

spike blanking with a time constant of 8.0us.

The other fault detection which can result in the Auto

Restart Mode I and has this 8.0us blanking time is the

Overtemperature detection. This block checks for a

junction temperature of higher than 140°C for

malfunction operation.

Once Auto Restart Mode is entered, the internal bias is

switched off in order to reduce the currentconsumption

of the IC as much as possible. In this mode, the

average current consumption is only 300uA as the only

working blocks are the reference block and the

Undervoltage Lockout(UVLO) which controls the

Startup Cell by switching on/off at VVCCon/VVCCoff.

As there is no longer a self supply by the auxiliary

winding, VCC starts to drop. The UVLO switches on the

integrated Startup Cell when VCC falls below 10.3V. It

will continue to charge VCC up to 18V whereby it is

switched off again and the IC enters into the Start Up

Phase.

As long as all fault conditions have been removed, the

IC will automatically power up as usual with switching

cycle at the GATE output after Soft Start duration. Thus

the name Auto Restart Mode.

3.6.3.2 Auto Restart Mode II

Figure 17 Auto Restart Mode II

In case of Overload or Open Loop, FB exceeds 4.5V

which will be observed by C4. At this time, the external

Soft Start capacitor can now be charged further by the

integrated pull up resistor RSoftS via switch S3 (see

Figure 13). If VSoftS exceeds 4.0V which is observed by

C3, Auto Restart Mode II is entered as both inputs of

the gate G5 are high.

This charging of the Soft Start capacitor from

3.2V~3.6V to 4.0V defines a blanking window which

prevents the system from entering into Auto Restart

Mode II unintentionally during large load jumps. In this

event, FB will rise close to 5.0V for a short duration

before the loop regulates with FB less than 4.5V. This

is the same blanking time window as for the Active

Burst Mode and can therefore be adjusted by the

external CSoftS.

In case of VCC undervoltage, ie. VCC falls below

10.3V, the IC will be turned off with the Startup Cell

charging VCC as described earlier in this section. Once

VCC is charged above 18V, the IC will start a new

startup cycle. The same procedure applies when the

system is under Short Optocoupler fault condition, as it

will lead to VCC undervoltage.

4.0V

4.5V &

Control Unit

SoftS Internal

Bias

Auto

Restart

Mode

CoolSET®-F3R

ICE3Bxx65J

Version 2.7 15 9 May 2012

4 Electrical Characteristics

Note: All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are

not violated.

4.1 Absolute Maximum Ratings

Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction

of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7

(VCC) is discharged before assembling the application circuit.

Parameter Symbol Limit Values Unit Remarks

min. max.

Drain Source Voltage VDS - 650 V Tj= 110°C

Pulse drain current,

tplimited by max.

Tj=150°C

ICE3B0365J ID_Puls1 - 1.6 A

ICE3B0565J ID_Puls2 - 2.3 A

ICE3B1565J ID_Puls3 - 6.1 A

ICE3B2065J ID_Puls4 - 10.3 A

Avalanche energy,

repetitive tAR limited

by max. Tj=150°C1)

1) Repetetive avalanche causes additional power losses that can be calculated as PAV=EAR* f

ICE3B0365J EAR1 - 0.005 mJ

ICE3B0565J EAR2 - 0.01 mJ

ICE3B1565J EAR3 - 0.15 mJ

ICE3B2065J EAR4 - 0.4 mJ

Avalanche current,

repetitive tAR limited

by max. Tj=150°C1)

ICE3B0365J IAR1 - 0.3 A

ICE3B0565J IAR2 - 0.5 A

ICE3B1565J IAR3 - 1.5 A

ICE3B2065J IAR4 - 2.0 A

VCC Supply Voltage VVCC -0.3 27 V

FB Voltage VFB -0.3 5.0 V

SoftS Voltage VSoftS -0.3 5.0 V

CS Voltage VCS -0.3 5.0 V

Junction Temperature Tj-40 150 °C Controller & CoolMOS®

Storage Temperature TS-55 150 °C

Thermal Resistance

Junction-Ambient

RthJA - 90 K/W PG-DIP-8

ESD Capability VESD - 2 kV Human body model2)

2) According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kWseries resistor)

Version 2.7 16 9 May 2012

CoolSET®-F3R

ICE3Bxx65J

4.2 Operating Range

Note: Within the operating range the IC operates as described in the functional description.

4.3 Characteristics

4.3.1 Supply Section

Note: The electrical characteristics involve the spread of values guaranteed within the specified supply voltage

and junction temperature range TJfrom – 25 oC to 130 oC. Typical values represent the median values,

which are related to 25°C. If not otherwise stated, a supply voltage of VCC = 18 V is assumed.

Parameter Symbol Limit Values Unit Remarks

min. max.

VCC Supply Voltage VVCC VVCCoff 26 V

Junction Temperature of Controller TjCon -25 130 °C Max value limited due to

integrated thermal shut down

Junction Temperature of

CoolMOS®TJCoolMOS -25 150 °C

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Start Up Current IVCCstart - 300 450 mA VVCC = 17V

VCC Charge Current IVCCcharge1 - - 5.0 mA VVCC = 0V

IVCCcharge2 0.55 1.05 1.60 mA VVCC = 1V

IVCCcharge3 - 0.88 - mA VVCC = 17V

Leakage Current of

Start Up Cell & CoolMOS

IStartLeak - 0.2 50 mA VDrain= 450V

at Tj= 100°C

Supply

Current with

Inactive Gate

ICE3B0365J

ICE3B0565J

ICE3B1565J

IVCCsup_ng1 - 1.7 2.5 mA Soft Start pin is open

ICE3B2065J IVCCsup_ng2 - 3.3 4.2 mA

Supply Current with Active Gate IVCCsup_g - 2.5 3.6 mA VSoftS = 3.0V

IFB = 0

Supply Current in

Auto Restart Mode

with Inactive Gate

IVCCrestart - 300 - mA IFB = 0

ISofts = 0

Supply Current in

Active Burst Mode

with Inactive Gate

IVCCburst1 - 500 950 uA VFB = 2.5V

VSoftS = 3.0V

IVCCburst2 - 500 950 uA VVCC = 11.5V

VFB = 2.5V

VSoftS = 3.0V

VCC Turn-On Threshold

VCC Turn-Off Threshold

VCC Turn-On/Off Hysteresis

VVCCon

VVCCoff

VVCChys

17.0

9.6

18.0

10.3

7.7

19.0

11.0

CoolSET®-F3R

ICE3Bxx65J

Version 2.7 17 9 May 2012

4.3.2 Internal Voltage Reference

4.3.3 PWM Section

4.3.4 Control Unit

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Trimmed Reference Voltage VREF 4.90 5.00 5.10 V measured at pin FB

IFB = 0

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Fixed Oscillator Frequency fOSC3 58 67 76 kHz

fOSC4 62 67 74.5 kHz Tj= 25°C

Frequency Jittering Range fdelta -±2.7 - kHz Tj= 25°C

Max. Duty Cycle Dmax 0.70 0.75 0.80

Min. Duty Cycle Dmin 0 - - VFB < 0.3V

PWM-OP Gain AV3.0 3.2 3.4

Max. Level of Voltage Ramp VMax-Ramp - 0.6 - V

VFB Operating Range Min Level VFBmin - 0.5 - V

VFB Operating Range Max level VFBmax - - 4.3 V CS=1V limited by

Comparator C41)

1) This parameter is not subject to production test - verified by design/characterization

Feedback Pull-Up Resistor RFB 9 14 22 kW

Soft-Start Pull-Up Resistor RSoftS 30 45 62 kW

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Deactivation Level for SoftS

Comparator C7 by C2

VSoftSC2 2.98 3.10 3.22 V VFB = 5V

Clamped VSoftS Voltage during

Burst Mode

VSoftSclmp_bm 2.88 3.00 3.12 V

Activation Limit of

Comparator C3

VSoftSC3 3.85 4.00 4.15 V VFB = 5V

SoftS Startup Current ISoftSstart - 0.9 - mA VSoftS = 0V

Over Load & Open Loop

Detection Limit for

Comparator C4

VFBC4 4.33 4.50 4.67 V VSoftS = 4.5V

Active Burst Mode Level for

Comparator C5

VFBC5 1.23 1.35 1.43 V VSoftS = 4.5V

Active Burst Mode Level for

Comparator C6a

VFBC6a 3.48 3.61 3.76 V After Active Burst

Mode is entered

Version 2.7 18 9 May 2012

CoolSET®-F3R

ICE3Bxx65J

Note: The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP

4.3.5 Current Limiting

4.3.6 CoolMOS®Section

Active Burst Mode Level for

Comparator C6b

VFBC6b 2.88 3.00 3.12 V After Active Burst

Mode is entered

Overvoltage Detection Limit VVCCOVP 19.5 20.5 21.5 V VFB = 5V, VSoftS = 3V

Thermal Shutdown1) TjSD 130 140 150 °C

Spike Blanking tSpike - 8.0 - ms

1) The parameter is not subject to production test - verified by design/characterization

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Peak Current Limitation (incl.

Propagation Delay Time)

(see Figure 11)

Vcsth 1.01 1.06 1.11 V dVsense / dt = 0.6V/ms

Peak Current Limitation during

Active Burst Mode

VCS2 0.27 0.32 0.37 V

Leading Edge Blanking tLEB - 220 - ns VSoftS = 3.0V

CS Input Bias Current ICSbias -1.0 -0.2 0 µA VCS = 0V

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Drain Source Breakdown

Voltage

V(BR)DSS 600

650

Tj= 25°C

Tj= 110°C

Drain Source

On-Resistance

ICE3B0365J RDSon1 -

6.45

13.70

7.50

17.00

Tj= 25°C

Tj= 125°C1)

at ID= 0.3A

ICE3B0565J RDSon2 -

4.70

10.00

5.44

12.50

Tj= 25°C

Tj= 125°C1)

at ID= 0.5A

ICE3B1565J RDSon3 -

1.70

3.57

1.96

4.12

Tj= 25°C

Tj= 125°C1)

at ID= 1.5A

ICE3B2065J RDSon4 -

0.92

1.93

1.05

2.22

Tj= 25°C

Tj= 125°C1)

at ID= 2.0A

Effective output

capacitance,

energy related

ICE3B0365J Co(er)1 - 3.65 - pF VDS = 0V to 480V

ICE3B0565J Co(er)2 - 4.75 - pF

ICE3B1565J Co(er)3 - 11.63 - pF

ICE3B2065J Co(er)4 - 21 - pF

CoolSET®-F3R

ICE3Bxx65J

Version 2.7 19 9 May 2012

Rise Time trise - 302) - ns

Fall Time tfall - 302) - ns

1) The parameter is not subject to production test - verified by design/characterization

2) Measured in a Typical Flyback Converter Application

Version 2.7 20 9 May 2012

CoolSET®-F3R

ICE3Bxx65J

5 Temperature derating curve

Figure 18 Safe Operating area ( SOA ) curve for ICE3B0365J

Figure 19 Safe Operating area ( SOA ) curve for ICE3B0565J

CoolSET®-F3R

ICE3Bxx65J

Version 2.7 21 9 May 2012

Figure 20 Safe Operating area ( SOA ) curve for ICE3B1565J

Figure 21 Safe Operating area ( SOA ) curve for ICE3B2065J

Version 2.7 22 9 May 2012

CoolSET®-F3R

ICE3Bxx65J

Figure 22 SOA temperature derating coefficient curve

CoolSET®-F3R

ICE3Bxx65J

Version 2.7 23 9 May 2012

6 Outline Dimension

Figure 23 PG-DIP-8 ( Pb-free lead plating Platic Dual-in-Line Outline )

PG-DIP-8

(Plastic Dual In-Line Outline)

Version 2.7 24 9 May 2012

CoolSET®-F3R

ICE3Bxx65J

7 Marking

Figure 24 Marking for ICE3B0365J

Figure 25 Marking for ICE3B0565J

Marking

CoolSET®-F3R

ICE3Bxx65J

Version 2.7 25 9 May 2012

Figure 26 Marking for ICE3B1565J

Figure 27 Marking for ICE3B2065J

Marking

Version 2.7 26 9 May 2012

CoolSET®-F3R

ICE3Bxx65J

Schematic for recommended PCB layout

8 Schematic for recommended PCB layout

Figure 28 Schematic for recommended PCB layout

General guideline for PCB layout design using F3 CoolSET (refer to Figure 26):

1. “Star Ground “at bulk capacitor ground, C11:

“Star Ground “means all primary DC grounds should be connected to the ground of bulk capacitor C11

separately in one point. It can reduce the switching noise going into the sensitive pins of the CoolSET device

effectively. The primary DC grounds include the followings.

a. DC ground of the primary auxiliary winding in power transformer, TR1, and ground of C16 and Z11.

b. DC ground of the current sense resistor, R12

c. DC ground of the CoolSET device, GND pin of IC11; the signal grounds from C13, C14, C15 and collector of

IC12 should be connected to the GND pin of IC11 and then “star “connect to the bulk capacitor ground.

d. DC ground from bridge rectifier, BR1

e. DC ground from the bridging Y-capacitor, C4

2. High voltage traces clearance:

High voltage traces should keep enough spacing to the nearby traces. Otherwise, arcing would incur.

a. 400V traces (positive rail of bulk capacitor C11) to nearby trace: > 2.0mm

b. 600V traces (drain voltage of CoolSET IC11) to nearby trace: > 2.5mm

3. Filter capacitor close to the controller ground:

Filter capacitors, C13, C14 and C15 should be placed as close to the controller ground and the controller pin

as possible so as to reduce the switching noise coupled into the controller.

Guideline for PCB layout design when >3KV lightning surge test applied (refer to Figure 26):

1. Add spark gap

Spark gap is a pair of saw-tooth like copper plate facing each other which can discharge the accumulated

charge during surge test through the sharp point of the saw-tooth plate.

a. Spark Gap 3 and Spark Gap 4, input common mode choke, L1:

Gap separation is around 1.5mm (no safety concern)

CoolSET®-F3R

ICE3Bxx65J

Schematic for recommended PCB layout

Version 2.7 27 9 May 2012

b. Spark Gap 1 and Spark Gap 2, Live / Neutral to GROUND:

These 2 Spark Gaps can be used when the lightning surge requirement is >6KV.

230Vac input voltage application, the gap separation is around 5.5mm

115Vac input voltage application, the gap separation is around 3mm

2. Add Y-capacitor (C2 and C3) in the Live and Neutral to ground even though it is a 2-pin input

3. Add negative pulse clamping diode, D11 to the Current sense resistor, R12:

The negative pulse clamping diode can reduce the negative pulse going into the CS pin of the CoolSET and

reduce the abnormal behavior of the CoolSET. The diode can be a fast speed diode such as IN4148.

The principle behind is to drain the high surge voltage from Live/Neutral to Ground without passing through the

sensitive components such as the primary controller, IC11.

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