DAC8164
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SBAS410B –FEBRUARY 2008–REVISED MAY 2011
SERIAL INTERFACE be kept LOW or brought HIGH. In either case, the
minimum delay time from the 24th falling SCLK edge
The DAC8164 has a 3-wire serial interface (SYNC, to the next falling SYNC edge must be met in order to
SCLK, and DIN) compatible with SPI, QSPI, and properly begin the next cycle. To assure the lowest
Microwire interface standards, as well as most DSPs. power consumption of the device, care should be
See the Serial Write Operation timing diagram for an taken that the levels are as close to each rail as
example of a typical write sequence. possible. Refer to the Typical Characteristics section
for Figure 36,Figure 57, and Figure 79 (Supply
The DAC8164 input shift register is 24 bits wide, Current vs Logic Input Voltage).
consisting of eight control bits (DB23 to DB16) and 14
data bits (DB15 to DB2). Bits DB0 and DB1 are
ignored by the DAC and should be treated as don't IOVDD AND VOLTAGE TRANSLATORS
care bits. All 24 bits of data are loaded into the DAC The IOVDD pin powers the the digital input structures
under the control of the serial clock input, SCLK. of the DAC8164. For single-supply operation, it can
DB23 (MSB) is the first bit that is loaded into the DAC be tied to AVDD. For dual-supply operation, the IOVDD
shift register, and is followed by the rest of the 24-bit pin provides interface flexibility with various CMOS
word pattern, left-aligned. This configuration means logic families and should be connected to the logic
that the first 24 bits of data are latched into the shift supply of the system. Analog circuits and internal
register and any further clocking of data is ignored. logic of the DAC8164 use AVDD as the supply
The DAC8164 receives all 24 bits of data and voltage. The external logic high inputs translate to
decodes the first eight bits to determine the DAC AVDD by level shifters. These level shifters use the
operating/control mode. The 14 bits of data that IOVDD voltage as a reference to shift the incoming
follow are decoded by the DAC to determine the logic HIGH levels to AVDD. IOVDD is ensured to
equivalent analog output, while the last two bits (DB1 operate from 2.7V to 5.5V regardless of the AVDD
and DB0) are ignored. The data format is straight voltage, assuring compatibility with various logic
binary with all '0's corresponding to 0V output and all families. Although specified down to 2.7V, IOVDD
'1's corresponding to full-scale output (that is, VREF –operates at as low as 1.8V with degraded timing and
1 LSB). For all documentation purposes, the data temperature performance. For lowest power
format and representation here is a true 14-bit pattern consumption, logic VIH levels should be as close as
(that is, 3FFFh for full-scale), even if the usable 14 possible to IOVDD, and logic VIL levels should be as
bits of data are extracted from a left-justified 16-bit close as possible to GND voltages.
data format that the DAC8164 requires.
The write sequence begins by bringing the SYNC line INPUT SHIFT REGISTER
low. Data from the DIN line are clocked into the 24-bit The input shift register (SR) of the DAC8164 is 24
shift register on each falling edge of SCLK. The serial bits wide, as shown in Table 4, and consists of eight
clock frequency can be as high as 50MHz, making control bits (DB23 to DB16), 14 data bits (DB15 to
the DAC8164 compatible with high-speed DSPs. On DB2), and two don't care bits. The first two control
the 24th falling edge of the serial clock, the last data bits (DB23 and DB22) are the address match bits.
bit is clocked into the shift register and the shift The DAC8164 offers hardware-enabled addressing
register locks. Further clocking does not change the capability, allowing a single host to talk to up to four
shift register data. After 24 bits are locked into the DAC8164s through a single SPI bus without any glue
shift register, the eight MSBs are used as control bits logic, enabling up to 16-channel operation. The state
and the following 14 LSBs are used as data. After of DB23 should match the state of pin A1; similarly,
receiving the 24th falling clock edge, the DAC8164 the state of DB22 should match the state of pin A0. If
decodes the eight control bits and 14 data bits to there is no match, the control command and the data
perform the required function, without waiting for a (DB21...DB0) are ignored by the DAC8164. That is, if
SYNC rising edge. A new write sequence starts at the there is no match, the DAC8164 is not addressed.
next falling edge of SYNC. A rising edge of SYNC Address matching can be overridden by the
before the 24-bit sequence is complete resets the SPI broadcast update.
interface; no data transfer occurs. After the 24th
falling edge of SCLK is received, the SYNC line may
Table 4. Data Input Register Format
DB23 DB12
A1 A0 LD1 LD0 0 DAC Select 1 DAC Select 0 PD0 D13 D12 D11 D10
DB11 DB0
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X
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