DAC8164
24-BitShiftRegister
SYNC
SCLK
DIN
DataBufferA DACRegisterA
DataBufferB DACRegisterB
DataBufferC DACRegisterC
DataBufferD DACRegisterD
AVDD
VREF REF
H/V OUT
Buffer
Control
Register
Control
ControlLogic
2.5V
Reference
Power-Down
ControlLogic
14-BitDAC
14-BitDAC
14-BitDAC
14-BitDAC
V A
OUT
V B
OUT
V C
OUT
V D
OUT
GND LDAC ENABLEA1A0
DAC8164
IOVDD VREFL
DAC8164
www.ti.com
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
14-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output
DIGITAL-TO-ANALOG CONVERTER with 2.5V, 2ppm/°C Internal Reference
Check for Samples: DAC8164
1FEATURES DESCRIPTION
The DAC8164 is a low-power, voltage-output,
234•Relative Accuracy: 1LSB four-channel, 14-bit digital-to-analog converter (DAC).
•Glitch Energy: 0.15nV-s The device includes a 2.5V, 2ppm/°C internal
•Internal Reference: reference (enabled by default), giving a full-scale
output voltage range of 2.5V. The internal reference
–2.5V Reference Voltage (enabled by default) has an initial accuracy of 0.004% and can source up
–0.004% Initial Accuracy (typ) to 20mA at the VREFH/VREFOUT pin. The device is
–2ppm/°C Temperature Drift (typ) monotonic, provides very good linearity, and
minimizes undesired code-to-code transient voltages
–5ppm/°C Temperature Drift (max) (glitch). The DAC8164 uses a versatile 3-wire serial
–20mA Sink/Source Capability interface that operates at clock rates up to 50MHz.
•Power-On Reset to Zero-Scale The interface is compatible with standard SPI™,
QSPI™, Microwire™, and digital signal processor
•Ultra-Low Power Operation: 1mA at 5V (DSP) interfaces.
•Wide Power Supply Range: +2.7V to +5.5V The DAC8164 incorporates a power-on-reset circuit
•14-Bit Monotonic Over Temperature Range that ensures the DAC output powers up at zero-scale
•Settling Time: 10μsto±0.006% Full-Scale and remains there until a valid code is written to the
Range (FSR) device. The device contains a power-down feature,
•Low-Power Serial Interface with accessed over the serial interface, that reduces the
Schmitt-Triggered Inputs: Up to 50MHz current consumption of the device to 1.3μA at 5V.
Power consumption is 2.6mW at 3V, reducing to
•On-Chip Output Buffer Amplifier with 1.4μW in power-down mode. The low power
Rail-to-Rail Operation consumption, internal reference, and small footprint
•1.8V to 5.5V Logic Compatibility make this device ideal for portable, battery-operated
•Temperature Range: –40°C to +105°Cequipment.
The DAC8164 is drop-in and functionally compatible
APPLICATIONS with the DAC7564 and DAC8564, and functionally
compatible with the DAC7565,DAC8165 and
•Portable Instrumentation DAC8565. All these devices are available in a
•Closed-Loop Servo-Control TSSOP-16 package.
•Process Control, PLCs
•Data Acquisition Systems
•Programmable Attenuation
•PC Peripherals
RELATED
DEVICES 16-BIT 14-BIT 12-BIT
Pin and
Functionally DAC8564 DAC8164 DAC7564
Compatible
Functionally DAC8565 DAC8165 DAC7565
Compatible
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2SPI, QSPI are trademarks of Motorola, Inc.
3Microwire is a trademark of National Semiconductor.
4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright ©2008–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DAC8164
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
RELATIVE DIFFERENTIAL REFERENCE SPECIFIED
ACCURACY NONLINEARITY DRIFT PACKAGE- PACKAGE TEMPERATURE PACKAGE
PRODUCT (LSB) (LSB) (ppm/°C) LEAD DESIGNATOR RANGE MARKING
DAC8164A ±4±1 25 TSSOP-16 PW –40°C to +105°C DAC8164
DAC8164B ±2±1 25 TSSOP-16 PW –40°C to +105°C DAC8164B
DAC8164C ±4±1 5 TSSOP-16 PW –40°C to +105°C DAC8164
DAC8164D ±2±1 5 TSSOP-16 PW –40°C to +105°C DAC8164D
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted). DAC8164 UNIT
AVDD to GND –0.3 to +6 V
Digital input voltage to GND –0.3 to +VDD + 0.3 V
VOUT to GND –0.3 to +VDD + 0.3 V
VREF to GND –0.3 to +VDD + 0.3 V
Operating temperature range –40 to +125 °C
Storage temperature range –65 to +150 °C
Junction temperature range (TJmax) +150 °C
Power dissipation (TJmax –TA)/θJA W
Thermal impedance, θJA +118 °C/W
Thermal impedance, θJC +29 °C/W
Human body model (HBM) 4000 V
ESD rating Charged device model (CDM) 1500 V
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2Copyright ©2008–2011, Texas Instruments Incorporated
DAC8164
www.ti.com
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
ELECTRICAL CHARACTERISTICS
At AVDD = 2.7V to 5.5V and –40°C to +105°C range (unless otherwise noted). DAC8164
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE(1)
Resolution 14 Bits
Measured by the line DAC8164A, DAC8164C ±1±4 LSB
Relative accuracy passing through DAC8164B, DAC8164D ±1±2 LSB
codes 120 and 16200
Differential nonlinearity 14-bit monotonic ±0.3 ±1 LSB
Offset error ±5±8 mV
Offset error drift ±1μV/°C
Measured by the line passing through codes 120 and
16200.
Full-scale error ±0.2 ±0.5 % of FSR
Gain error ±0.05 ±0.2 % of FSR
AVDD = 5V ±1ppm of
Gain temperature coefficient FSR/°C
AVDD = 2.7V ±2
PSRR Power-supply rejection ratio Output unloaded 1 mV/V
OUTPUT CHARACTERISTICS(2)
Output voltage range 0 VREF V
To ±0.006% FSR, 0080h to 3F40h, RL= 2kΩ,8 10
0pF <CL<200pF
Output voltage settling time μs
RL= 2kΩ, CL= 500pF 12
Slew rate 2.2 V/μs
RL=∞470
Capacitive load stability pF
RL= 2kΩ1000
Code change glitch impulse 1LSB change around major carry 0.15 nV-s
Digital feedthrough SCLK toggling, SYNC high 0.15 nV-s
Channel-to-channel dc crosstalk Full-scale swing on adjacent channel 0.25 LSB
Channel-to-channel ac crosstalk 1kHz full-scale sine wave, outputs unloaded –100 dB
DC output impedance At mid-code input 1 Ω
Short-circuit current 50 mA
Coming out of power-down mode, AVDD = 5V 2.5
Power-up time μs
Coming out of power-down mode, AVDD = 3V 5
AC PERFORMANCE(2)
SNR 87 dB
THD –78 dB
TA= +25°C, BW = 20kHz, VDD = 5V, fOUT = 1kHz.
First 19 harmonics removed for SNR calculation.
SFDR 79 dB
SINAD 77 dB
DAC output noise density TA= +25°C, at mid-code input, fOUT = 1kHz 120 nV/√Hz
DAC output noise TA= +25°C, at mid-code input, 0.1Hz to 10Hz 6 μVPP
REFERENCE
AVDD = 5.5V 360 μA
Internal reference current consumption AVDD = 3.6V 348 μA
External VREF = 2.5V, if internal reference is disabled,
External reference current 80 μA
all four channels active
Reference input range VREFH voltage VREFL<VREFH, AVDD –(VREFH + VREFL) /2 >1.2V 0 AVDD V
Reference input range VREFL voltage VREFL<VREFH, AVDD –(VREFH + VREFL) /2 >1.2V 0 AVDD/2 V
Reference input impedance 31 kΩ
(1) Linearity calculated using a reduced code range of 120 to 16200; output unloaded.
(2) Ensured by design or characterization; not production tested.
Copyright ©2008–2011, Texas Instruments Incorporated 3
DAC8164
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
At AVDD = 2.7V to 5.5V and –40°C to +105°C range (unless otherwise noted). DAC8164
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REFERENCE OUTPUT
Output voltage TA= +25°C 2.4975 2.5 2.5025 V
Initial accuracy TA= +25°C–0.1 ±0.004 0.1 %
DAC8164A, DAC8164B(3) 5 25
Output voltage temperature drift ppm/°C
DAC8164C, DAC8164D(4) 2 5
Output voltage noise f = 0.1Hz to 10Hz 12 μVPP
TA= +25°C, f = 1MHz, CL= 0μF 50
Output voltage noise density TA= +25°C, f = 1MHz, CL= 1μF 20 nV/√Hz
(high-frequency noise) TA= +25°C, f = 1MHz, CL= 4μF 16
Load regulation, sourcing(5) TA= +25°C 30 μV/mA
Load regulation, sinking(5) TA= +25°C 15 μV/mA
Output current load capability(6) ±20 mA
Line regulation TA= +25°C 10 μV/V
Long-term stability/drift (aging)(5) TA= +25°C, time = 0 to 1900 hours 50 ppm
First cycle 100
Thermal hysteresis(5) ppm
Additional cycles 25
LOGIC INPUTS(6)
Input current ±1μA
2.7V ≤IOVDD ≤5.5V 0.3 ×IOVDD
VINL Logic input LOW voltage V
1.8V ≤IOVDD ≤2.7V 0.1 ×IOVDD
2.7V ≤IOVDD ≤5.5V 0.7 ×IOVDD
VINH Logic input HIGH voltage V
1.8V ≤IOVDD ≤2.7V 0.95 ×IOVDD
Pin capacitance 3 pF
POWER REQUIREMENTS
AVDD 2.7 5.5 V
IOVDD 1.8 5.5 V
IOIDD (6) 10 20 μA
AVDD = IOVDD = 3.6V to 5.5V 1 1.6
VINH = IOVDD and VINL = GND
Normal mode mA
AVDD = IOVDD = 2.7V to 3.6V 0.95 1.5
VINH = IOVDD and VINL = GND
IDD (7) AVDD = IOVDD = 3.6V to 5.5V 1.3 3.5
VINH = IOVDD and VINL = GND
All power-down modes μA
AVDD = IOVDD = 2.7V to 3.6V 0.5 2.5
VINH = IOVDD and VINL = GND
AVDD = IOVDD = 3.6V to 5.5V 3.6 8.8
VINH = IOVDD and VINL = GND
Normal mode mW
AVDD = IOVDD = 2.7V to 3.6V 2.6 5.4
VINH = IOVDD and VINL = GND
Power
Dissipation (7) AVDD = IOVDD = 3.6V to 5.5V 4.7 19
VINH = IOVDD and VINL = GND
All power-down modes μW
AVDD = IOVDD = 2.7V to 3.6V 1.4 9
VINH = IOVDD and VINL = GND
TEMPERATURE RANGE
Specified performance –40 +105 °C
(3) Reference is trimmed and tested at room temperature, and is characterized from –40°C to +120°C.
(4) Reference is trimmed and tested at two temperatures (+25°C and +105°C), and is characterized from –40°C to +120°C.
(5) Explained in more detail in the Application Information section of this data sheet.
(6) Ensured by design or characterization; not production tested.
(7) Input code = 8192, reference current included, no load.
4Copyright ©2008–2011, Texas Instruments Incorporated
V A
OUT LDAC
ENABLE
A1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DAC8164
V B
OUT
V H/V OUT
REF REF
AVDD
V L
REF
GND
V C
OUT
V D
OUT
A0
IOVDD
DIN
SCLK
SYNC
DAC8164
www.ti.com
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
PIN CONFIGURATIONS
PW PACKAGE
TSSOP-16
(Top View)
PIN DESCRIPTIONS
PIN NAME DESCRIPTION
1 VOUTA Analog output voltage from DAC A
2 VOUTB Analog output voltage from DAC B
VREFH/
3 Positive reference input / reference output 2.5V if internal reference used.
VREFOUT
4 AVDD Power-supply input, 2.7V to 5.5V
5 VREFL Negative reference input
6 GND Ground reference point for all circuitry on the part
7 VOUTC Analog output voltage from DAC C
8 VOUTD Analog output voltage from DAC D
Level-triggered control input (active low). This input is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register, and data are sampled on subsequent falling clock edges. The DAC output
9 SYNC updates following the 24th clock. If SYNC is taken high before the 24th clock edge, the rising edge of SYNC acts as
an interrupt, and the write sequence is ignored by the DAC8164. Schmitt-Trigger logic input.
10 SCLK Serial clock input. Data can be transferred at rates up to 50MHz. Schmitt-Trigger logic input.
Serial data input. Data are clocked into the 24-bit input shift register on each falling edge of the serial clock input.
11 DIN Schmitt-Trigger logic input.
12 IOVDD Digital input-output power supply
13 A0 Address 0—sets device address; see Table 5.
14 A1 Address 1—sets device address; see Table 5.
15 ENABLE The enable pin (active low) connects the SPI interface to the serial port
16 LDAC Load DACs; rising edge triggered, loads all DAC registers
Copyright ©2008–2011, Texas Instruments Incorporated 5
SCLK 1
24
SYNC
DIN DB23 DB0 DB23
t10
t6
t3
t2
t1
t7
t5
t4
t8
ENABLE
t9
t13
t12
t11
LDAC
t14
t15
DAC8164
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
www.ti.com
SERIAL WRITE OPERATION
6Copyright ©2008–2011, Texas Instruments Incorporated
DAC8164
www.ti.com
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
TIMING REQUIREMENTS(1) (2)
At AVDD = IOVDD= 2.7V to 5.5V and –40°C to +105°C range (unless otherwise noted). DAC8164
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOVDD = AVDD = 2.7V to 3.6V 40
t1(3) SCLK cycle time ns
IOVDD = AVDD = 3.6V to 5.5V 20
IOVDD = AVDD = 2.7V to 3.6V 20
t2SCLK HIGH time ns
IOVDD = AVDD = 3.6V to 5.5V 10
IOVDD = AVDD = 2.7V to 3.6V 20
t3SCLK LOW time ns
IOVDD = AVDD = 3.6V to 5.5V 10
IOVDD = AVDD = 2.7V to 3.6V 0
t4SYNC to SCLK rising edge setup time ns
IOVDD = AVDD = 3.6V to 5.5V 0
IOVDD = AVDD = 2.7V to 3.6V 5
t5Data setup time ns
IOVDD = AVDD = 3.6V to 5.5V 5
IOVDD = AVDD = 2.7V to 3.6V 4.5
t6Data hold time ns
IOVDD = AVDD = 3.6V to 5.5V 4.5
IOVDD = AVDD = 2.7V to 3.6V 0
t7SCLK falling edge to SYNC rising edge ns
IOVDD = AVDD = 3.6V to 5.5V 0
IOVDD = AVDD = 2.7V to 3.6V 40
t8Minimum SYNC HIGH time ns
IOVDD = AVDD = 3.6V to 5.5V 20
IOVDD = AVDD = 2.7V to 3.6V 130
t924th SCLK falling edge to SYNC falling edge ns
IOVDD = AVDD = 3.6V to 5.5V 130
IOVDD = AVDD = 2.7V to 3.6V 15
SYNC rising edge to 24th SCLK falling edge
t10 ns
(for successful SYNC interrupt) IOVDD = AVDD = 3.6V to 5.5V 15
IOVDD = AVDD = 2.7V to 3.6V 15
t11 ENABLE falling edge to SYNC falling edge ns
IOVDD = AVDD = 3.6V to 5.5V 15
IOVDD = AVDD = 2.7V to 3.6V 10
t12 24th SCLK falling edge to ENABLE rising edge ns
IOVDD = AVDD = 3.6V to 5.5V 10
IOVDD = AVDD = 2.7V to 3.6V 50
t13 24th SCLK falling edge to LDAC rising edge ns
IOVDD = AVDD = 3.6V to 5.5V 50
IOVDD = AVDD = 2.7V to 3.6V 10
t14 LDAC rising edge to ENABLE rising edge ns
IOVDD = AVDD = 3.6V to 5.5V 10
IOVDD = AVDD = 2.7V to 3.6V 10
t15 LDAC HIGH time ns
IOVDD = AVDD = 3.6V to 5.5V 10
(1) All input signals are specified with tR= tF= 3ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
(2) See the Serial Write Operation timing diagram.
(3) Maximum SCLK frequency is 50MHz at IOVDD = VDD = 3.6V to 5.5V and 25MHz at IOVDD = AVDD = 2.7V to 3.6V.
Copyright ©2008–2011, Texas Instruments Incorporated 7
2.503
2.502
2.501
2.500
2.499
2.498
2.497
1200 40 6020 100-40 -20
V (V)
REF
Temperature( C)°
10UnitsShown
80
2.503
2.502
2.501
2.500
2.499
2.498
2.497
1200 40 6020 80 100-40 -20
V (V)
REF
Temperature( C)°
13UnitsShown
40
30
20
10
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Population(%)
TemperatureDrift(ppm/°C)
Typ:2ppm/°C
Max:5ppm/ C°
30
20
10
0
13 5 7 9 11 13 15 17 19
Population(%)
TemperatureDrift(ppm/ C)°
Typ:5ppm/°C
Max:25ppm/ C°
200
150
100
50
0
-50
-100
-150
-200
1800
1900
300 600 900 1200 15000
Drift(ppm)
Time(Hours)
20UnitsShown
Average
40
30
20
10
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Typ:1.2ppm/°C
Max:3ppm/°C
Population(%)
TemperatureDrift(ppm/°C)
DAC8164
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS: Internal Reference
At TA= +25°C, unless otherwise noted.
INTERNAL REFERENCE VOLTAGE INTERNAL REFERENCE VOLTAGE
vs vs
TEMPERATURE (Grades C and D) TEMPERATURE (Grades A and B)
Figure 1. Figure 2.
REFERENCE OUTPUT TEMPERATURE DRIFT REFERENCE OUTPUT TEMPERATURE DRIFT
(–40°C to +120°C, Grades C and D) (–40°C to +120°, Grades A and B)
Figure 3. Figure 4.
REFERENCE OUTPUT TEMPERATURE DRIFT LONG-TERM
(0°C to +120°C, Grades C and D) STABILITY/DRIFT (1)
Figure 5. Figure 6.
(1) Explained in more detail in the Application Information section of this data sheet.
8Copyright ©2008–2011, Texas Instruments Incorporated
V (5 V/div)m
NOISE
Time(2s/div)
12 V(peak-to-peak)m
2.505
2.504
2.495
25-15 -5 15-25
V (V)
REF
I (mA)
LOAD
2.503
2.501
2.502
+25°C
+120 C°
-40°C
2.500
2.496
2.497
2.498
2.499
5-20 -10 0 10 20
2.505
2.504
2.495
25-15 -5 15-25
V (V)
REF
I (mA)
LOAD
2.503
2.501
2.502
2.500
2.496
2.497
2.498
2.499
5-20 -10 0 10 20
+25°C
-40°C
+120°C
2.503
2.502
2.501
2.498
5.53.0 3.5 4.02.5
V (V)
REF
AV (V)
DD
2.500
4.5 5.0
+120 C°
+25 C°
- °40 C
2.499
2.503
2.502
2.501
2.498
5.53.0 3.5 4.02.5
V (V)
REF
AV (V)
DD
2.500
4.5 5.0
+120 C°
+25 C°
- °40 C
2.499
DAC8164
www.ti.com
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
TYPICAL CHARACTERISTICS: Internal Reference (continued)
At TA= +25°C, unless otherwise noted.
INTERNAL REFERENCE NOISE DENSITY INTERNAL REFERENCE NOISE
vs
FREQUENCY 0.1Hz TO 10Hz
Figure 7. Figure 8.
INTERNAL REFERENCE VOLTAGE INTERNAL REFERENCE VOLTAGE
vs vs
LOAD CURRENT (Grades C and D) LOAD CURRENT (Grades A and B)
Figure 9. Figure 10.
INTERNAL REFERENCE VOLTAGE INTERNAL REFERENCE VOLTAGE
vs vs
SUPPLY VOLTAGE (Grades C and D) SUPPLY VOLTAGE (Grades A and B)
Figure 11. Figure 12.
Copyright ©2008–2011, Texas Instruments Incorporated 9
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelA,AV =5V, ternalV =4.99V
DD REF
Ex
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelB,AV =5V, ternalV =4.99V
DD REF
Ex
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelC,AV =5V, ternalV =4.99V
DD REF
Ex
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelD,AV =5V, ternalV =4.99V
DD REF
Ex
DAC8164
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS: DAC at AVDD = 5V
At TA= +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted.
LINEARITY ERROR AND LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C) vs DIGITAL INPUT CODE (–40°C)
Figure 13. Figure 14.
LINEARITY ERROR AND LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C) vs DIGITAL INPUT CODE (–40°C)
Figure 15. Figure 16.
10 Copyright ©2008–2011, Texas Instruments Incorporated
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelA,AV =5V, ternalV =4.99V
DD REF
Ex
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelB,AV =5V,ExternalV =4.99V
DD REF
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelC,AV =5V, ternalV =4.99V
DD REF
Ex
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelD,AV =5V, ternalV =4.99V
DD REF
Ex
DAC8164
www.ti.com
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued)
At TA= +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted. LINEARITY ERROR AND LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C) vs DIGITAL INPUT CODE (+25°C)
Figure 17. Figure 18.
LINEARITY ERROR AND LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C) vs DIGITAL INPUT CODE (+25°C)
Figure 19. Figure 20.
Copyright ©2008–2011, Texas Instruments Incorporated 11
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelA,AV =5V,ExternalV =4.99V
DD REF
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelB,AV =4.99V=5V, ternalV
DD REF
Ex
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelC,AV =4.99V=5V,ExternalV
DD REF
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelD,AV =5V,ExternalV =4.99V
DD REF
DAC8164
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued)
At TA= +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted. LINEARITY ERROR AND LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C) vs DIGITAL INPUT CODE (+105°C)
Figure 21. Figure 22.
LINEARITY ERROR AND LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C) vs DIGITAL INPUT CODE (+105°C)
Figure 23. Figure 24.
12 Copyright ©2008–2011, Texas Instruments Incorporated
Temperature( C)°
OffsetError(mV)
40-40 -20 0
4
3
2
1
0
-1
20 60 80 100 120
A =5VVDD
InternalV Enabled
REF ChC
ChB
ChA
ChD
Temperature( C)°
Full-ScaleError(mV)
40-40 -20 0
0.50
0.25
0
-0.25
-0.50
20 60
ChC
ChA ChB
ChD
80 100 120
AVDD =5V
InternalV Enabled
REF
5.5
4.5
3.5
2.5
-0.5
205 10 150
AnalogOutputVoltage(V)
I (mA)
SOURCE/SINK
AV =5V,ChA
DD
InternalReferenceDisabled
1.5
0.5
DACLoadedwith3FFFh
DACLoadedwith0000h
5.5
4.5
3.5
2.5
-0.5
205 10 150
AnalogOutputVoltage(V)
I (mA)
SOURCE/SINK
AV =5V,ChB
DD
InternalReferenceDIsabled
1.5
0.5
DACLoadedwith3FFFh
DACLoadedwith0000h
5.5
4.5
3.5
2.5
-0.5
205 10 150
AnalogOutputVoltage(V)
I (mA)
SOURCE/SINK
AV =5V,ChC
DD
InternalReferenceDisabled
1.5
0.5
DACLoadedwith3FFFh
DACLoadedwith0000h
5.5
4.5
3.5
2.5
-0.5
205 10 150
AnalogOutputVoltage(V)
I (mA)
SOURCE/SINK
AV =5V,ChD
DD
InternalReferenceDisabled
1.5
0.5
DACLoadedwith3FFFh
DACLoadedwith0000h
DAC8164
www.ti.com
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued)
At TA= +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted. OFFSET ERROR FULL-SCALE ERROR
vs TEMPERATURE vs TEMPERATURE
Figure 25. Figure 26.
SOURCE AND SINK SOURCE AND SINK
CURRENT CAPABILITY CURRENT CAPABILITY
Figure 27. Figure 28.
SOURCE AND SINK SOURCE AND SINK
CURRENT CAPABILITY CURRENT CAPABILITY
Figure 29. Figure 30.
Copyright ©2008–2011, Texas Instruments Incorporated 13
0 1638414336122881024081926144
2048 4096
DigitalInputCode
Power-SupplyCurrent( A)m
1300
1200
1100
1000
900
800
AV =5.5V
DD
InternalV Included
REF
Temperature( C)°
Power-SupplyCurrent(mA)
40-40 -20 0
1400
1300
1200
1100
1000
900
800
20 60 80 100 120
AV =5.5V
DD
InternalV Included
REF
DACLoadedwith2000h
1100
1090
1080
1050
5.53.1 3.5 3.92.7
Power-SupplyCurrent( A)m
AV (V)
DD
AV =2.7Vto5.5V
DD
InternalV Included
DACLoadedwith2000h
REF
1070
4.3 4.7 5.1
1060
1.2
1.0
0.2
5.53.1 3.5 3.9 4.32.7
Power-DownCurrent( A)m
AV (V)
DD
0.8
AV =2.7Vto5.5V
DD
REF
InternalV Included
0.6
4.7 5.1
0.4
Temperature( C)°
Power-DownCurrent( A)m
40-40 -20 0
3.0
2.5
2.0
1.5
1.0
0.5
0
20 60 80 100 120
AVDD =5.5V
V (V)
LOGIC
Power-SupplyCurrent(mA)
30 1 2
3200
2800
2400
2000
1600
1200
800
54 6
AV =IOV =5.5V
DD DD REF
,InternalV Included
SYNC Input(allotherdigitalinputs=GND)
Sweepfrom
0Vto5.5V
Sweepfrom
5.5Vto0V
DAC8164
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued)
At TA= +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted. POWER-SUPPLY CURRENT POWER-SUPPLY CURRENT
vs DIGITAL INPUT CODE vs TEMPERATURE
Figure 31. Figure 32.
POWER-SUPPLY CURRENT POWER-DOWN CURRENT
vs
POWER-SUPPLY VOLTAGE vs POWER-SUPPLY VOLTAGE
Figure 33. Figure 34.
POWER-DOWN CURRENT POWER-SUPPLY CURRENT
vs TEMPERATURE vs LOGIC INPUT VOLTAGE
Figure 35. Figure 36.
14 Copyright ©2008–2011, Texas Instruments Incorporated
0 54321
f (kHz)
OUT
THD(dB)
-40
-50
-60
-70
-80
-90
-100
THD
ChannelA,AVDD REF
=5V,ExternalV =4.99V
-1dBFSRDigitalInput,f =225kSPS
S
MeasurementBandwidth=20kHz
3rdHarmonic
2ndHarmonic
0 54321
f (kHz)
OUT
THD(dB)
-40
-50
-60
-70
-80
-90
-100
THD
ChannelB,AV =5V,ExternalV =4.99V
DD REF
-1dBFSRDigitalInput,f =225kSPS
S
MeasurementBandwidth=20kHz
3rdHarmonic
2ndHarmonic
0 54321
f (kHz)
OUT
THD(dB)
-40
-50
-60
-70
-80
-90
-100
THD
ChannelC,AV =5V,ExternalV =4.99V
DD REF
-1dBFSRDigitalInput,f =225kSPS
S
MeasurementBandwidth=20kHz
3rdHarmonic
2ndHarmonic
0 54321
f (kHz)
OUT
THD(dB)
-40
-50
-60
-70
-80
-90
-100
THD
3rdHarmonic
ChannelD,AV =5V,ExternalV =4.99V
DD REF
-1dBFSRDigitalInput,f =225kSPS
S
MeasurementBandwidth=20kHz
2ndHarmonic
60
40
20
0
Occurrence(%)
AV =5.5V
DD
InternalV Included
REF
50
30
10
950 1000 1050 1100 1150 1200
Power-SupplyCurrent( A)m
DAC8164
www.ti.com
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued)
At TA= +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted. TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION
vs OUTPUT FREQUENCY vs OUTPUT FREQUENCY
Figure 37. Figure 38.
TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION
vs OUTPUT FREQUENCY vs OUTPUT FREQUENCY
Figure 39. Figure 40.
POWER-SUPPLY CURRENT
HISTOGRAM
Figure 41.
Copyright ©2008–2011, Texas Instruments Incorporated 15
0 54321
f (kHz)
OUT
SNR(dB)
96
94
92
90
88
86
84
ChannelA
ChannelD
ChannelB
ChannelC
AllChannels,AV =5V,ExternalV =4.99V
DD REF
-1dBFSRDigitalInput,f =225kSPS
S
MeasurementBandwidth=20kHz
0 2015105
Frequency(Hz)
Gain(dB)
0
-20
-40
-60
-80
-100
-120
-140
AVDD REF
=5V,ExternalV =4.99V
fOUT S
=1kHz,f =225kSPS
MeasurementBandwidth=20kHz
Time(2 s/div)m
AV =5V
ExtV =4.096V
FromCode:0000h
ToCode:3FFFh
DD
REF
TriggerPulse5V/div
ZoomedRisingEdge
1mV/div
RisingEdge
1V/div
Time(2 s/div)m
AV =5V
ExtV =4.096V
FromCode:3FFFh
ToCode:0000h
DD
REF
TriggerPulse5V/div
ZoomedFallingEdge
1mV/div
Falling
Edge
1V/div
Time(2 s/div)m
AV =5V
ExtV =4.096V
FromCode:1000h
ToCode:3000h
DD
REF
TriggerPulse5V/div
ZoomedRisingEdge
1mV/div
Rising
Edge
1V/div
Time(2 s/div)m
AV =5V
ExtV =4.096V
FromCode:3000h
ToCode:1000h
DD
REF
TriggerPulse5V/div
ZoomedFallingEdge
1mV/div
Falling
Edge
1V/div
DAC8164
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued)
At TA= +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted. SIGNAL-TO-NOISE RATIO
vs OUTPUT FREQUENCY POWER SPECTRAL DENSITY
Figure 42. Figure 43.
FULL-SCALE SETTLING TIME: FULL-SCALE SETTLING TIME:
5V RISING EDGE 5V FALLING EDGE
Figure 44. Figure 45.
HALF-SCALE SETTLING TIME: HALF-SCALE SETTLING TIME:
5V RISING EDGE 5V FALLING EDGE
Figure 46. Figure 47.
16 Copyright ©2008–2011, Texas Instruments Incorporated
Time(2 s/div)m
AV =5V
FromCode:07FFh
ToCode:0800h
Glitch:0.09nV-s
DD
IntV =2.5V
REF
V (500 V/div)m
OUT
Time(2 s/div)m
AV =5V
IntV =2.5V
FromCode:0800h
ToCode:07FFh
Glitch:0.1nV-s
DD
REF
V (500 V/div)m
OUT
Time(5 s/div)m
AV =5V
FromCode:0800h
ToCode:0810h
Glitch:0.3nV-s
DD
IntV =2.5V
REF
V (1mV/div)
OUT
Time(5 s/div)m
AV =5V
FromCode:0810h
ToCode:0800h
Glitch:0.2nV-s
DD
IntV =2.5V
REF
V (1mV/div)
OUT
Time(2 s/div)m
AV =5V
FromCode:2000h
ToCode:2040h
Glitch:0.1nV-s
DD
IntV =2.5V
REF
V (2.5mV/div)
OUT
Time(2 s/div)m
AV =5V
FromCode:2040h
ToCode:2000h
Glitch:0.1nV-s
DD
IntV =2.5V
REF
V (2.5mV/div)
OUT
DAC8164
www.ti.com
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued)
At TA= +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted. GLITCH ENERGY: GLITCH ENERGY:
5V, 1LSB STEP, RISING EDGE 5V, 1LSB STEP, FALLING EDGE
Figure 48. Figure 49.
GLITCH ENERGY: GLITCH ENERGY:
5V, 16LSB STEP, RISING EDGE 5V, 16LSB STEP, FALLING EDGE
Figure 50. Figure 51.
GLITCH ENERGY: GLITCH ENERGY:
5V, 64LSB STEP, RISING EDGE 5V, 64LSB STEP, FALLING EDGE
Figure 52. Figure 53.
Copyright ©2008–2011, Texas Instruments Incorporated 17
1200
1000
800
600
0
1M100 1k 10k 100k10
Noise(nV/ )ÖHz
Frequency(Hz)
400
200
ZeroScale
Mid-Scale
FullScale
InternalReferenceEnabled
NoLoadatV H/V OUTPin
REF REF
400
350
300
250
0
1M100 1k 10k 100k10
Noise(nV/ )ÖHz
Frequency(Hz)
200
150
NoLoadonReference
4.8 FCapacitor
OnReference
m
50
100
DAC=Full-Scale
InternalReferenceEnabled
4.8 FversusNoLoadatV H/V OUTPinmREF REF
V (2 V/divm
NOISE )
Time(2s/div)
6 V(peak-to-peak)m
DAC=Mid-Scale
InternalReferenceEnabled
DAC8164
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued)
At TA= +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted. DAC OUTPUT NOISE DENSITY DAC OUTPUT NOISE DENSITY
vs vs
FREQUENCY(1) FREQUENCY (2)
Figure 54. Figure 55.
DAC OUTPUT NOISE
0.1Hz TO 10Hz
Figure 56.
(1) Explained in more detail in the Application Information section of this data sheet.
(2) See the Application Information section for more information.
18 Copyright ©2008–2011, Texas Instruments Incorporated
Temperature( C)°
Power-SupplyCurrent( A)m
40-40 -20 0
1400
1300
1200
1100
1000
900
800
20 60 80 100 120
AV =3.6V
DD
InternalV Included
REF
DACLoadedwith2000h
2400
2000
800
4.00.5 1.0 1.5 2.00
Power-SupplyCurrent( A)m
V (V)
LOGIC
Sweepfrom0Vto3.6V
1600
Sweepfrom
3.6Vto0V
AV =IOV =3.6V,InternalV Included
Input(allotherdigitalinputs=GND)
DD REFDD
SYNC
1200
2.5 3.53.0
80
60
40
0
Occurrence(%)
20
AV =3.6V
DD
InternalV Included
REF
900 950 1000 1050 1100 1150 1200
Power-SupplyCurrent( A)m
DAC8164
www.ti.com
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
TYPICAL CHARACTERISTICS: DAC at AVDD = 3.6V
At TA= +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted
POWER-SUPPLY CURRENT POWER-SUPPLY CURRENT
vs vs
LOGIC INPUT VOLTAGE TEMPERATURE
Figure 57. Figure 58.
POWER-SUPPLY CURRENT
HISTOGRAM
Figure 59.
Copyright ©2008–2011, Texas Instruments Incorporated 19
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelA,AV =2.7V,InternalV =2.5V
DD REF
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelB,AV =2.7V,InternalV =2.5V
DD REF
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelC,AV =2.7V,InternalV =2.5V
DD REF
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelD,AV =2.7V,InternalV =2.5V
DD REF
DAC8164
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V
At TA= +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted
LINEARITY ERROR AND LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C) vs DIGITAL INPUT CODE (–40°C)
Figure 60. Figure 61.
LINEARITY ERROR AND LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C) vs DIGITAL INPUT CODE (–40°C)
Figure 62. Figure 63.
20 Copyright ©2008–2011, Texas Instruments Incorporated
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelA,AV =2.7V,InternalV =2.5V
DD REF
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelB,AV =2.7V,InternalV =2.5V
DD REF
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelC,AV =2.7V,InternalV =2.5V
DD REF
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelD,AV =2.7V,InternalV =2.5V
DD REF
DAC8164
www.ti.com
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued)
At TA= +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted LINEARITY ERROR AND LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C) vs DIGITAL INPUT CODE (+25°C)
Figure 64. Figure 65.
LINEARITY ERROR AND LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C) vs DIGITAL INPUT CODE (+25°C)
Figure 66. Figure 67.
Copyright ©2008–2011, Texas Instruments Incorporated 21
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelA,AV =2.7V,InternalV =2.5V
DD REF
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelB,AV =2.7V,InternalV =2.5V
DD REF
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelC,AV =2.7V,InternalV =2.5V
DD REF
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelD,AV =2.7V,InternalV =2.5V
DD REF
DAC8164
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued)
At TA= +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted LINEARITY ERROR AND LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C) vs DIGITAL INPUT CODE (+105°C)
Figure 68. Figure 69.
LINEARITY ERROR AND LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C) vs DIGITAL INPUT CODE (+105°C)
Figure 70. Figure 71.
22 Copyright ©2008–2011, Texas Instruments Incorporated
Temperature( C)°
OffsetError(mV)
40-40 -20 0
4
3
2
1
0
-1
20 60 80 100 120
AV =2.7V
DD
InternalV Enabled
REF ChC
ChA
ChB
ChD
Temperature( C)°
Full-ScaleError(mV)
40-40 -20 0
0.50
0.25
0
-0.25
-0.50
20 60 80 100 120
AVDD =2.7V
InternalV Enabled
REF
ChC
ChA ChB
ChD
3.0
2.5
2.0
1.5
0
205 10 150
AnalogOutputVoltage (V)
I (mA)
SOURCE/SINK
AV =2.7V,ChA
DD
InternalReferenceEnabled
1.0
0.5
DACLoadedwith3FFFh
DACLoadedwith0000h
3.0
2.5
2.0
1.5
0
205 10 150
AnalogOutputVoltage(V)
I (mA)
SOURCE/SINK
AV =2.7V,ChB
DD
InternalReferenceEnabled
1.0
0.5
DACLoadedwith3FFFh
DACLoadedwith0000h
3.0
2.5
2.0
1.5
0
205 10 150
AnalogOutputVoltage(V)
I (mA)
SOURCE/SINK
AV =2.7V,ChC
DD
InternalReferenceEnabled
1.0
0.5
DACLoadedwith3FFFh
DACLoadedwith0000h
3.0
2.5
2.0
1.5
0
205 10 150
AnalogOutputVoltage(V)
I (mA)
SOURCE/SINK
AV =2.7V,ChD
DD
InternalReferenceEnabled
1.0
0.5
DACLoadedwith3FFFh
DACLoadedwith0000h
DAC8164
www.ti.com
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued)
At TA= +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted OFFSET ERROR FULL-SCALE ERROR
vs TEMPERATURE vs TEMPERATURE
Figure 72. Figure 73.
SOURCE AND SINK SOURCE AND SINK
CURRENT CAPABILITY CURRENT CAPABILITY
Figure 74. Figure 75.
SOURCE AND SINK SOURCE AND SINK
CURRENT CAPABILITY CURRENT CAPABILITY
Figure 76. Figure 77.
Copyright ©2008–2011, Texas Instruments Incorporated 23
0 1638414336122881024081926144
2048 4096
DigitalInputCode
Power-SupplyCurrent (mA)
1300
1200
1100
1000
900
800
AV =2.7V
DD
InternalV Included
REF
Time(2 s/div)m
AV =2.7V
IntV =2.5V
FromCode:0000h
ToCode:3FFFh
DD
REF
TriggerPulse2.7V/div
ZoomedRisingEdge
1mV/div
Rising
Edge
0.5V/div
Time(2 s/div)m
AV =2.7V
IntV =2.5V
FromCode:3FFFh
ToCode:0000h
DD
REF
TriggerPulse2.7V/div
ZoomedFallingEdge
1mV/div
Falling
Edge
0.5V/div
Time(2 s/div)m
AV =2.7V
IntV =2.5V
FromCode:1000h
ToCode:3000h
DD
REF
TriggerPulse2.7V/div
ZoomedRisingEdge
1mV/div
Rising
Edge
0.5V/div
Time(2 s/div)m
AV =2.7V
IntV =2.5V
FromCode:3000h
ToCode:1000h
DD
REF
TriggerPulse2.7V/div
ZoomedFallingEdge
1mV/div
Falling
Edge
0.5V/div
DAC8164
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued)
At TA= +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted POWER-SUPPLY CURRENT POWER-SUPPLY CURRENT
vs DIGITAL INPUT CODE vs LOGIC INPUT VOLTAGE
Figure 78. Figure 79.
FULL-SCALE SETTLING TIME: FULL-SCALE SETTLING TIME:
2.7V RISING EDGE 2.7V FALLING EDGE
Figure 80. Figure 81.
HALF-SCALE SETTLING TIME: HALF-SCALE SETTLING TIME:
2.7V RISING EDGE 2.7V FALLING EDGE
Figure 82. Figure 83.
24 Copyright ©2008–2011, Texas Instruments Incorporated
Time(2 s/div)m
AV =2.7V
IntV =2.5V
FromCode:07FFh
ToCode:0800h
Glitch:0.02nV-s
DD
REF
V (500 V/div)m
OUT
Time(2 s/div)m
AV =2.7V
IntV =2.5V
FromCode:0800h
ToCode:07FFh
Glitch:0.02nV-s
DD
REF
V (500 V/div)m
OUT
Time(5 s/div)m
AV =2.7V
IntV =2.5V
FromCode:0800h
ToCode:0810h
Glitch:0.01nV-s
DD
REF
V (1mV/div)
OUT
Time(5 s/div)m
AV =2.7V
IntV =2.5V
FromCode:0810h
ToCode:0800h
Glitch:0.01nV-s
DD
REF
V (1mV/div)
OUT
Time(2 s/div)m
AV =2.7V
IntV =2.5V
FromCode:2000h
ToCode:2040h
Glitch:0.1nV-s
DD
REF
V (2.5mV/div)
OUT
Time(2 s/div)m
AV =2.7V
IntV =2.5V
FromCode:2040h
ToCode:2000h
Glitch:0.1nV-s
DD
REF
V (2.5mV/div)
OUT
DAC8164
www.ti.com
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued)
At TA= +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted GLITCH ENERGY: GLITCH ENERGY:
2.7V, 1LSB STEP, RISING EDGE 2.7V, 1LSB STEP, FALLING EDGE
Figure 84. Figure 85.
GLITCH ENERGY: GLITCH ENERGY:
2.7V, 16LSB STEP, RISING EDGE 2.7V, 16LSB STEP, FALLING EDGE
Figure 86. Figure 87.
GLITCH ENERGY: GLITCH ENERGY:
2.7V, 64LSB STEP, RISING EDGE 2.7V, 64LSB STEP, FALLING EDGE
Figure 88. Figure 89.
Copyright ©2008–2011, Texas Instruments Incorporated 25
Temperature( C)°
Power-SupplyCurrent( A)m
40-40 -20 0
1400
1300
1200
1100
1000
900
800
20 60 80 100 120
AV =2.7V
DD
InternalV Included
REF
DACLoadedwith2000h
Temperature( C)°
Power-DownCurrent(mA)
40-40 -20 0
2.0
1.5
1.0
0.5
0
20 60 80 100 120
AVDD =2.7V
DAC8164
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued)
At TA= +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted POWER-SUPPLY CURRENT POWER-DOWN CURRENT
vs TEMPERATURE vs TEMPERATURE
Figure 90. Figure 91.
26 Copyright ©2008–2011, Texas Instruments Incorporated
DAC
Register
REF(+)
ResistorString
REF( )-
V L
REF
V H
REF
VOUTX
62kW
50kW50kW
V =
OUTXDIN
16384
2´ ´V V V
REF REF REF
L+( H L)-
VREF
R
R
R
R
VREF
2
RDIVIDER
ToOutputAmplifier
(2xGain)
DAC8164
www.ti.com
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER (DAC)
The DAC8164 architecture consists of a string DAC
followed by an output buffer amplifier. Figure 92
shows a block diagram of the DAC architecture.
Figure 92. DAC8164 Architecture
The input coding to the DAC8164 is straight binary,
so the ideal output voltage is given by Equation 1.
(1)
where DIN = decimal equivalent of the binary code
that is loaded to the DAC register; it can range from 0
to 16383. X represents channel A, B, C, or D.
RESISTOR STRING
The resistor string section is shown in Figure 93. It is
simply a string of resistors, each of value R. The
code loaded into the DAC register determines at
which node on the string the voltage is tapped off to Figure 93. Resistor String
be fed into the output amplifier by closing one of the
switches connecting the string to the amplifier. It is
monotonic because it is a string of resistors. OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating
rail-to-rail voltages on its output, giving an output
range of 0V to AVDD. It is capable of driving a load of
2kΩin parallel with 1000pF to GND. The source and
sink capabilities of the output amplifier can be seen in
the Typical Characteristics. The slew rate is 2.2V/μs,
with a full-scale settling time of 8μs with the output
unloaded.
Copyright ©2008–2011, Texas Instruments Incorporated 27
VREF
R1
1 Q2
NQ1
R2
Reference
Disable
DAC8164
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
www.ti.com
INTERNAL REFERENCE
The DAC8164 includes a 2.5V internal reference that
is enabled by default. The internal reference is
externally available at the VREFH/VREFOUT pin. A
minimum 100nF capacitor is recommended between
the reference output and GND for noise filtering.
The internal reference of the DAC8164 is a bipolar
transistor-based, precision bandgap voltage
reference. Figure 94 shows the basic bandgap
topology. Transistors Q1and Q2are biased such that
the current density of Q1is greater than that of Q2.
The difference of the two base-emitter voltages
(VBE1 –VBE2) has a positive temperature coefficient
and is forced across resistor R1. This voltage is
gained up and added to the base-emitter voltage of
Q2, which has a negative temperature coefficient. The
resulting output voltage is virtually independent of Figure 94. Simplified Schematic of the Bandgap
temperature. The short-circuit current is limited by Reference
design to approximately 100mA.
Enable/Disable Internal Reference To then enable the internal reference, either perform
a power-cycle to reset the device, or write the 24-bit
The internal reference in the DAC8164 is enabled by serial command shown in Table 2. These actions put
default and operates in automatic mode; however, the the internal reference back into the default mode. In
reference can be disabled for debugging, evaluation the default mode, the internal reference powers down
purposes, or when using an external reference. A automatically when all DACs power down in any of
serial command that requires a 24-bit write sequence the power-down modes (see the Power-Down Modes
(see the Serial Interface section) must be used to section); the internal reference powers up
disable the internal reference, as shown in Table 1.automatically when any DAC is powered up.
During the time that the internal reference is disabled,
the DAC functions normally using an external The DAC8164 also provides the option of keeping the
reference. At this point, the internal reference is internal reference powered on all the time, regardless
disconnected from the VREFH/VREFOUT pin (3-state of the DAC(s) state (powered up or down). To keep
output). Do not attempt to drive the VREFH/VREFOUT the internal reference powered on, regardless of the
pin externally and internally at the same time DAC(s) state, write the 24-bit serial command shown
indefinitely. in Table 3.
Table 1. Write Sequence for Disabling Internal Reference
(internal reference always powered down—012000h)
DB23 DB16 DB13 DB0
0000000100100000000000XX
|———————————————– Data Bits –——————————————|
Table 2. Write Sequence for Enabling Internal Reference
(internal reference powered up to default mode—010000h)
DB23 DB16 DB0
0000000100000000000000XX
|———————————————– Data Bits –——————————————|
Table 3. Write Sequence for Enabling Internal Reference
(internal reference always powered up—011000h)
DB23 DB16 DB12 DB0
0000000100010000000000XX
|———————————————– Data Bits –——————————————|
28 Copyright ©2008–2011, Texas Instruments Incorporated
DAC8164
www.ti.com
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
SERIAL INTERFACE be kept LOW or brought HIGH. In either case, the
minimum delay time from the 24th falling SCLK edge
The DAC8164 has a 3-wire serial interface (SYNC, to the next falling SYNC edge must be met in order to
SCLK, and DIN) compatible with SPI, QSPI, and properly begin the next cycle. To assure the lowest
Microwire interface standards, as well as most DSPs. power consumption of the device, care should be
See the Serial Write Operation timing diagram for an taken that the levels are as close to each rail as
example of a typical write sequence. possible. Refer to the Typical Characteristics section
for Figure 36,Figure 57, and Figure 79 (Supply
The DAC8164 input shift register is 24 bits wide, Current vs Logic Input Voltage).
consisting of eight control bits (DB23 to DB16) and 14
data bits (DB15 to DB2). Bits DB0 and DB1 are
ignored by the DAC and should be treated as don't IOVDD AND VOLTAGE TRANSLATORS
care bits. All 24 bits of data are loaded into the DAC The IOVDD pin powers the the digital input structures
under the control of the serial clock input, SCLK. of the DAC8164. For single-supply operation, it can
DB23 (MSB) is the first bit that is loaded into the DAC be tied to AVDD. For dual-supply operation, the IOVDD
shift register, and is followed by the rest of the 24-bit pin provides interface flexibility with various CMOS
word pattern, left-aligned. This configuration means logic families and should be connected to the logic
that the first 24 bits of data are latched into the shift supply of the system. Analog circuits and internal
register and any further clocking of data is ignored. logic of the DAC8164 use AVDD as the supply
The DAC8164 receives all 24 bits of data and voltage. The external logic high inputs translate to
decodes the first eight bits to determine the DAC AVDD by level shifters. These level shifters use the
operating/control mode. The 14 bits of data that IOVDD voltage as a reference to shift the incoming
follow are decoded by the DAC to determine the logic HIGH levels to AVDD. IOVDD is ensured to
equivalent analog output, while the last two bits (DB1 operate from 2.7V to 5.5V regardless of the AVDD
and DB0) are ignored. The data format is straight voltage, assuring compatibility with various logic
binary with all '0's corresponding to 0V output and all families. Although specified down to 2.7V, IOVDD
'1's corresponding to full-scale output (that is, VREF –operates at as low as 1.8V with degraded timing and
1 LSB). For all documentation purposes, the data temperature performance. For lowest power
format and representation here is a true 14-bit pattern consumption, logic VIH levels should be as close as
(that is, 3FFFh for full-scale), even if the usable 14 possible to IOVDD, and logic VIL levels should be as
bits of data are extracted from a left-justified 16-bit close as possible to GND voltages.
data format that the DAC8164 requires.
The write sequence begins by bringing the SYNC line INPUT SHIFT REGISTER
low. Data from the DIN line are clocked into the 24-bit The input shift register (SR) of the DAC8164 is 24
shift register on each falling edge of SCLK. The serial bits wide, as shown in Table 4, and consists of eight
clock frequency can be as high as 50MHz, making control bits (DB23 to DB16), 14 data bits (DB15 to
the DAC8164 compatible with high-speed DSPs. On DB2), and two don't care bits. The first two control
the 24th falling edge of the serial clock, the last data bits (DB23 and DB22) are the address match bits.
bit is clocked into the shift register and the shift The DAC8164 offers hardware-enabled addressing
register locks. Further clocking does not change the capability, allowing a single host to talk to up to four
shift register data. After 24 bits are locked into the DAC8164s through a single SPI bus without any glue
shift register, the eight MSBs are used as control bits logic, enabling up to 16-channel operation. The state
and the following 14 LSBs are used as data. After of DB23 should match the state of pin A1; similarly,
receiving the 24th falling clock edge, the DAC8164 the state of DB22 should match the state of pin A0. If
decodes the eight control bits and 14 data bits to there is no match, the control command and the data
perform the required function, without waiting for a (DB21...DB0) are ignored by the DAC8164. That is, if
SYNC rising edge. A new write sequence starts at the there is no match, the DAC8164 is not addressed.
next falling edge of SYNC. A rising edge of SYNC Address matching can be overridden by the
before the 24-bit sequence is complete resets the SPI broadcast update.
interface; no data transfer occurs. After the 24th
falling edge of SCLK is received, the SYNC line may
Table 4. Data Input Register Format
DB23 DB12
A1 A0 LD1 LD0 0 DAC Select 1 DAC Select 0 PD0 D13 D12 D11 D10
DB11 DB0
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X
Copyright ©2008–2011, Texas Instruments Incorporated 29
DAC8164
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
www.ti.com
LD1 (DB21) and LD0 (DB20) control the loading of DB21 = 0 and DB20 = 1: Single-channel update.
each analog output with the specified 14-bit data The data buffer and DAC register corresponding to a
value or power-down command. Bit DB19 must DAC selected by DB18 and DB17 update with the
always be '0'. The DAC channel select bits (DB18, contents of SR data (or power-down).
DB17) control the destination of the data (or DB21 = 1 and DB20 = 0: Simultaneous update. A
power-down command) from DAC A through DAC D. channel selected by DB18 and DB17 updates with
The final control bit, PD0 (DB16), selects the the SR data; simultaneously, all the other channels
power-down mode of the DAC8164 channels as well update with previously stored data (or power-down)
as the power-down mode of the internal reference. from data buffers.
The DAC8164 supports a number of different load DB21 = 1 and DB20 = 1: Broadcast update. All the
commands. The load commands include broadcast DAC8164s on the SPI bus respond, regardless of
commands to address all the DAC8164s on an SPI address matching. If DB18 = 0, SR data are ignored
bus. The load commands are summarized as follows: and any channels from all DAC8164s update with
previously stored data (or power-down). If DB18 = 1,
DB21 = 0 and DB20 = 0: Single-channel store. The SR data (or power-down) update any channels of all
data buffer corresponding to a DAC selected by DAC8164s in the system. This broadcast update
DB18 and DB17 updates with the contents of SR feature allows the simultaneous update of up to 16
data (or power-down). channels.
Refer to Table 5 for more information.
Table 5. Control Matrix for the DAC8164
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13-DB2 DB1-DB0
Don't
A1 A0 LD 1 LD 0 0 DAC Sel 1 DAC Sel 0 PD0 MSB MSB-1 MSB-2...LSB Care
(Address Select) DESCRIPTION
This address selects one of four possible
0/1 0/1 See Below devices on a single SPI data bus based on the
address pin(s) state of each device.
0 0 0 0 0 0 Data X Write to buffer A with data
0 0 0 0 1 0 Data X Write to buffer B with data
0 0 0 1 0 0 Data X Write to buffer C with data
0 0 0 1 1 0 Data X Write to buffer D with data
Write to buffer (selected by DB17 and DB18)
0 0 0 (00, 01, 10, or 11) 1 See Table 6 0 X with power-down command
A0 and A1 should Write to buffer with data and load DAC
correspond to the 0 1 0 (00, 01, 10, or 11) 0 Data X (selected by DB17 and DB18)
package address
set via pins 13 Write to buffer with power-down command and
0 1 0 (00, 01, 10, or 11) 1 See Table 6 0 X
and 14 load DAC (selected by DB17 and DB18)
Write to buffer with data (selected by DB17 and
1 0 0 (00, 01, 10, or 11) 0 Data X DB18) and then load all DACs simultaneously
from their corresponding buffers
Write to buffer with power-down command
(selected by DB17 and DB18) and then load all
1 0 0 (00, 01, 10, or 11) 1 See Table 6 0 X DACs simultaneously from their corresponding
buffers
Broadcast Modes
Simultaneously update all channels of all
X X 1 1 0 0 X X X X DAC8164 devices in the system with data
stored in each channels data buffer
Write to all devices and load all DACs with SR
X X 1 1 0 1 X 0 Data X data
Write to all devices and load all DACs with
X X 1 1 0 1 X 1 See Table 6 0 X power-down command in SR
30 Copyright ©2008–2011, Texas Instruments Incorporated
CLK
SYNC
DIN
ValidWriteSequence:
Output/ModeUpdates onthe24thFallingEdge
24thFallingEdge 24thFallingEdge
DB23 DB0 DB23 DB0
Invalid/InterruptedWriteSequence:
Output/ModeDoesNotUpdate onthe24thFallingEdge
DAC8164
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SBAS410B –FEBRUARY 2008–REVISED MAY 2011
SYNC INTERRUPT LDAC FUNCTIONALITY
In a normal write sequence, the SYNC line stays low The DAC8164 offers both a software and hardware
for at least 24 falling edges of SCLK and the simultaneous update function. The DAC
addressed DAC register updates on the 24th falling double-buffered architecture has been designed so
edge. However, if SYNC is brought high before the that new data can be entered for each DAC without
24th falling edge, it acts as an interrupt to the write disturbing the analog outputs.
sequence; the shift register resets and the write DAC8164 data updates are synchronized with the
sequence is discarded. Neither an update of the data falling edge of the 24th SCLK cycle, which follows a
buffer contents, DAC register contents, nor a change falling edge of SYNC. For such synchronous updates,
in the operating mode occurs (as shown in the LDAC pin is not required and it must be
Figure 95). connected to GND permanently. The LDAC pin is
used as a positive edge triggered timing signal for
POWER-ON RESET TO ZERO-SCALE asynchronous DAC updates. To do an LDAC
operation, single-channel store(s) should be done
The DAC8164 contains a power-on reset circuit that (loading DAC buffers) by setting LD0 and LD1 to '0'.
controls the output voltage during power-up. On Multiple single-channel updates can be done in order
power-up, the DAC registers are filled with zeros and to set different channel buffers to desired values and
the output voltages are set to zero-scale; they remain then make a rising edge on LDAC. Data buffers of all
that way until a valid write sequence and load channels must be loaded with desired data before an
command are made to the respective DAC channel. LDAC rising edge. After a low-to-high LDAC
The power-on reset is useful in applications where it transition, all DACs are simultaneously updated with
is important to know the state of the output of each the contents of the corresponding data buffers. If the
DAC while the device is in the process of powering contents of a data buffer are not changed by the
up. serial interface, the corresponding DAC output
No device pin should be brought high before power is remains unchanged after the LDAC trigger.
applied to the device. The internal reference is
powered on by default and remains that way until a ENABLE PIN
valid reference-change command is executed. For normal operation, the enable pin must be driven
to a logic low. If the enable pin is driven high, the
DAC8164 stops listening to the serial port. However,
SCLK, SYNC, and DIN must not be kept floating, but
must be at some logic level. This feature can be
useful for applications that share the same serial port.
Figure 95. SYNC Interrupt Facility
Copyright ©2008–2011, Texas Instruments Incorporated 31
V X
OUT
Amplifier
Resistor
String
DAC
Power-Down
Circuitry Resistor
Network
DAC8164
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
www.ti.com
POWER-DOWN MODES DACs. However, for the three power-down modes,
the supply current falls to 1.3μA at 5.5V (0.5μA at
The DAC8164 has two separate sets of power-down 3.6V). Not only does the supply current fall, but the
commands. One set is for the DAC channels and the output stage also switches internally from the output
other set is for the internal reference. For more of the amplifier to a resistor network of known values.
information on powering down the reference, see the
Enable/Disable Internal Reference section. The advantage of this switching is that the output
impedance of the device is known while it is in
DAC Power-Down Commands power-down mode. As described in Table 6, there are
three different power-down options. VOUT can be
The DAC8164 uses four modes of operation. These connected internally to GND through a 1kΩresistor, a
modes are accessed by setting three bits (PD2, PD1, 100kΩresistor, or open circuited (High-Z). The output
and PD0) in the shift register. Table 6 shows how to stage is shown in Figure 96. In other words, DB16,
control the operating mode with data bits PD0 DB15, and DB14 = '111' represent a power-down
(DB16), PD1 (DB15), and PD2 (DB14). condition with Hi-Z output impedance for a selected
channel. '101' represents a power-down condition
Table 6. DAC Operating Modes with 1kΩoutput impedance, and '110' represents a
PD0 PD1 PD2 power-down condition with 100kΩoutput impedance.
(DB16) (DB15) (DB14) DAC OPERATING MODES
0 X X Normal operation
1 0 1 Output typically 1kΩto GND
1 1 0 Output typically 100kΩto GND
1 1 1 Output high-impedance
The DAC8164 treats the power-down condition as
data; all the operational modes are still valid for
power-down. It is possible to broadcast a power-down
condition to all the DAC8164s in a system; it is also
possible to simultaneously power-down a channel
while updating data on other channels. Figure 96. Output Stage During Power-Down
When the PD0 bit is set to '0', the device works
normally with its typical current consumption of 1mA All analog channel circuitries are shut down when the
at 5.5V with an input code = 8192. The reference power-down mode is exercised. However, the
current is included with the operation of all four contents of the DAC register are unaffected when in
power down. The time required to exit power-down is
typically 2.5μs for VDD = 5V, and 5μs for VDD = 3V.
See the Typical Characteristics for more information.
32 Copyright ©2008–2011, Texas Instruments Incorporated
DAC8164
www.ti.com
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
OPERATING EXAMPLES: DAC8164
For the following examples, ensure that DAC pins A0 and A1 are both connected to ground. Pins A0 and A1
must always match data bits DB22 and DB23 within the SPI write sequence/protocol. X = don't care; value can
be either '0' or '1'.
Example 1: Write to Data Buffer A Through Buffer D; Load DAC A Through DAC D Simultaneously
•1st: Write to data buffer A:
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12-DB2 DB1-DB0
(A1) (A0) (LD1) (LD0) (DAC Sel 1) (DAC Sel 0) (PD0)
0 0 0 0 0 0 0 0 D13 D12 D11 D10-D0 X
•2nd: Write to data buffer B:
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12-DB2 DB1-DB0
(A1) (A0) (LD1) (LD0) (DAC Sel 1) (DAC Sel 0) (PD0)
0 0 0 0 0 0 1 0 D13 D12 D11 D10-D0 X
•3rd: Write to data buffer C:
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12-DB2 DB1-DB0
(A1) (A0) (LD1) (LD0) (DAC Sel 1) (DAC Sel 0) (PD0)
0 0 0 0 0 1 0 0 D13 D12 D11 D10-D0 X
•4th: Write to data buffer D and simultaneously update all DACs:
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12-DB2 DB1-DB0
(A1) (A0) (LD1) (LD0) (DAC Sel 1) (DAC Sel 0) (PD0)
0 0 1 0 0 1 1 0 D13 D12 D11 D10-D0 X
The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously settle to the specified values upon
completion of the 4th write sequence. (The DAC voltages update simultaneously after the 24th SCLK falling edge
of the fourth write cycle).
Example 2: Load New Data to DAC A Through DAC D Sequentially
•1st: Write to data buffer A and load DAC A: DAC A output settles to specified value upon completion:
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12-DB2 DB1-DB0
(A1) (A0) (LD1) (LD0) (DAC Sel 1) (DAC Sel 0) (PD0)
0 0 0 1 0 0 0 0 D13 D12 D11 D10-D0 X
•2nd: Write to data buffer B and load DAC B: DAC B output settles to specified value upon completion:
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12-DB2 DB1-DB0
(A1) (A0) (LD1) (LD0) (DAC Sel 1) (DAC Sel 0) (PD0)
0 0 0 1 0 0 1 0 D13 D12 D11 D10-D0 X
•3rd: Write to data buffer C and load DAC C: DAC C output settles to specified value upon completion:
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12-DB2 DB1-DB0
(A1) (A0) (LD1) (LD0) (DAC Sel 1) (DAC Sel 0) (PD0)
0 0 0 1 0 1 0 0 D13 D12 D11 D10-D0 X
•4th: Write to data buffer D and load DAC D: DAC D output settles to specified value upon completion:
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12-DB2 DB1-DB0
(A1) (A0) (LD1) (LD0) (DAC Sel 1) (DAC Sel 0) (PD0)
0 0 0 1 0 1 1 0 D13 D12 D11 D10-D0 X
After completion of each write cycle, DAC analog output settles to the voltage specified.
Copyright ©2008–2011, Texas Instruments Incorporated 33
DAC8164
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
www.ti.com
Example 3: Power-Down DAC A and DAC B to 1kΩand Power-Down DAC C and DAC D to 100kΩ
Simultaneously
•1st: Write power-down command to data buffer A: DAC A to 1kΩ.
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12-DB2 DB1-DB0
(A1) (A0) (LD1) (LD0) (DAC Sel 1) (DAC Sel 0) (PD0)
0 0 0 0 0 0 0 1 0 1 X X X
•2nd: Write power-down command to data buffer B: DAC B to 1kΩ.
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12-DB2 DB1-DB0
(A1) (A0) (LD1) (LD0) (DAC Sel 1) (DAC Sel 0) (PD0)
0 0 0 0 0 0 1 1 0 1 X X X
•3rd: Write power-down command to data buffer C: DAC C to 100kΩ.
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12-DB2 DB1-DB0
(A1) (A0) (LD1) (LD0) (DAC Sel 1) (DAC Sel 0) (PD0)
0 0 0 0 0 1 0 1 1 0 X X X
•4th: Write power-down command to data buffer D: DAC D to 100kΩand simultaneously update all DACs.
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12-DB2 DB1-DB0
(A1) (A0) (LD1) (LD0) (DAC Sel 1) (DAC Sel 0) (PD0)
0 0 1 0 0 1 1 1 1 0 X X X
The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously power-down to each respective specified
mode upon completion of the fourth write sequence.
Example 4: Power-Down DAC A Through DAC D to High-Impedance Sequentially
•1st: Write power-down command to data buffer A and load DAC A: DAC A output = Hi-Z:
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12-DB2 DB1-DB0
(A1) (A0) (LD1) (LD0) (DAC Sel 1) (DAC Sel 0) (PD0)
0 0 0 1 0 0 0 1 1 1 X X X
•2nd: Write power-down command to data buffer B and load DAC B: DAC B output = Hi-Z:
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12-DB2 DB1-DB0
(A1) (A0) (LD1) (LD0) (DAC Sel 1) (DAC Sel 0) (PD0)
0 0 0 1 0 0 1 1 1 1 X X X
•3rd: Write power-down command to data buffer C and load DAC C: DAC C output = Hi-Z:
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12-DB2 DB1-DB0
(A1) (A0) (LD1) (LD0) (DAC Sel 1) (DAC Sel 0) (PD0)
0 0 0 1 0 1 0 1 1 1 X X X
•4th: Write power-down command to data buffer D and load DAC D: DAC D output = Hi-Z:
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12-DB2 DB1-DB0
(A1) (A0) (LD1) (LD0) (DAC Sel 1) (DAC Sel 0) (PD0)
0 0 0 1 0 1 1 1 1 1 X X X
The DAC A, DAC B, DAC C, and DAC D analog outputs sequentially power-down to high-impedance upon
completion of the first, second, third, and fourth write sequences, respectively.
34 Copyright ©2008–2011, Texas Instruments Incorporated
DAC8164
www.ti.com
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
Example 5: Power-Down All Channels Simultaneously while Reference is Always Powered Up
•1st: Write sequence for enabling the DAC8164 internal reference all the time:
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11-DB2 DB1-DB0
(A1) (A0) (LD1) (LD0) (DAC Sel 1) (DAC Sel 0) (PD0)
0 0 0 0 0 0 0 1 0 0 0 1 X X
•2nd: Write sequence to power-down all DACs to high-impedance:
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11-DB2 DB1-DB0
(A1) (A0) (LD1) (LD0) (DAC Sel 1) (DAC Sel 0) (PD0)
0 0 1 1 0 1 0 1 1 1 X X X X
The DAC A, DAC B, DAC C, and DAC D analog outputs sequentially power-down to high-impedance upon
completion of the first and second write sequences, respectively.
Example 6: Write a Specific Value to All DACs while Reference is Always Powered Down
•1st: Write sequence for disabling the DAC8164 internal reference all the time (after this sequence, the
DAC8164 requires an external reference source to function):
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11-DB2 DB1-DB0
(A1) (A0) (LD1) (LD0) (DAC Sel 1) (DAC Sel 0) (PD0)
0 0 0 0 0 0 0 1 0 0 1 0 X X
•2nd: Write sequence to write specified data to all DACs:
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11-DB2 DB1-DB0
(A1) (A0) (LD1) (LD0) (DAC Sel 1) (DAC Sel 0) (PD0)
0 0 1 1 0 1 0 0 D13 D12 D11 D10 D9–D0 X
The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously settle to the specified values upon
completion of the fourth write sequence. (The DAC voltages update simultaneously after the 24th SCLK falling
edge of the fourth write cycle). Reference is always powered-down.
Example 7: Write a Specific Value to DAC A, while Reference is Placed in Default Mode and All Other
DACs are Powered Down to High-Impedance
•1st: Write sequence for placing the DAC8164 internal reference into default mode. Alternately, this step can
be replaced by performing a power-on reset (see the Power-On Reset section):
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11-DB2 DB1-DB0
(A1) (A0) (LD1) (LD0) (DAC Sel 1) (DAC Sel 0) (PD0)
0 0 0 0 0 0 0 1 0 0 0 0 X X
•2nd: Write sequence to power-down all DACs to high-impedance (after this sequence, the DAC8164 internal
reference powers down automatically):
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11-DB2 DB1-DB0
(A1) (A0) (LD1) (LD0) (DAC Sel 1) (DAC Sel 0) (PD0)
0 0 1 1 0 1 0 1 1 1 X X X X
•3rd: Write sequence to power-up DAC A to a specified value (after this sequence, the DAC8164 internal
reference powers up automatically):
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11-DB2 DB1-DB0
(A1) (A0) (LD1) (LD0) (DAC Sel 1) (DAC Sel 0) (PD0)
0 0 0 1 0 0 0 0 D13 D12 D11 D10 D9–D0 X
The DAC B, DAC C, and DAC D analog outputs simultaneously power-down to high-impedance, and DAC A
settles to the specified value upon completion.
Copyright ©2008–2011, Texas Instruments Incorporated 35
DriftError= ´10 (ppm/ C)°
6
V V-
REF_MAX REF_MIN
V T´
REF RANGE
5
6
7
8
12
11
10
9
IOVDD
DIN
SCLK
SYNC
V L
REF
GND
V C
OUT
V D
OUT
AVDD
DAC8164
1
2
3
4
16
15
14
13
LDAC
ENABLE
A1
A0
V A
OUT
V B
OUT
V H/V OUT
REF REF
AVDD
0.1 Fm
150nF
DAC8164
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
www.ti.com
APPLICATION INFORMATION
INTERNAL REFERENCE Temperature Drift
The internal reference of the DAC8164 does not The internal reference is designed to exhibit minimal
require an external load capacitor for stability drift error, defined as the change in reference output
because it is stable with any capacitive load. voltage over varying temperature. The drift is
However, for improved noise performance, an calculated using the box method described by
external load capacitor of 150nF or larger connected Equation 2:
to the VREFH/VREFOUT output is recommended.
Figure 97 shows the typical connections required for
operation of the DAC8164 internal reference. A
supply bypass capacitor at the AVDD input is also (2)
recommended. Where:
VREF_MAX = maximum reference voltage observed
within temperature range TRANGE.
VREF_MIN = minimum reference voltage observed
within temperature range TRANGE.
VREF = 2.5V, target value for reference output
voltage.
The internal reference (grades C and D) features an
exceptional typical drift coefficient of 2ppm/°C
from –40°C to +120°C. Characterizing a large number
of units, a maximum drift coefficient of 5ppm/°C
(grades C and D) is observed. Temperature drift
results are summarized in the Typical Characteristics.
Noise Performance
Figure 97. Typical Connections for Operating the Typical 0.1Hz to 10Hz voltage noise can be seen in
DAC8164 Internal Reference Figure 8,Internal Reference Noise. Additional filtering
can be used to improve output noise levels, although
Supply Voltage care should be taken to ensure the output impedance
does not degrade the ac performance. The output
The internal reference features an extremely low noise spectrum at VREFH/VREFOUT without any
dropout voltage. It can be operated with a supply of external components is depicted in Figure 7,Internal
only 5mV above the reference output voltage in an Reference Noise Density vs Frequency. Another
unloaded condition. For loaded conditions, refer to noise density spectrum is also shown in Figure 7.
the Load Regulation section. The stability of the This spectrum was obtained using a 4.8μF load
internal reference with variations in supply voltage capacitor at VREFH/VREFOUT for noise filtering.
(line regulation, dc PSRR) is also exceptional. Within Internal reference noise impacts the DAC output
the specified supply voltage range of 2.7V to 5.5V, noise; see the DAC Noise Performance section for
the variation at VREFH/VREFOUT is less than 10μV/V; more details.
see the Typical Characteristics.
36 Copyright ©2008–2011, Texas Instruments Incorporated
V =
HYST ´10 (ppm/ C)°
6
|V V |-
REF_PRE REF_POST
VREF_NOM
OutputPin
Meter Load
ForceLine
SenseLine
Contactand
TraceResistance
IL
VOUT
DAC8164
www.ti.com
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
Load Regulation Thermal Hysteresis
Load regulation is defined as the change in reference Thermal hysteresis for a reference is defined as the
output voltage as a result of changes in load current. change in output voltage after operating the device at
The load regulation of the internal reference is +25°C, cycling the device through the operating
measured using force and sense contacts as shown temperature range, and returning to +25°C.
in Figure 98. The force and sense lines reduce the Hysteresis is expressed by Equation 3:
impact of contact and trace resistance, resulting in
accurate measurement of the load regulation
contributed solely by the internal reference.
Measurement results are summarized in the Typical (3)
Characteristics. Force and sense lines should be Where:
used for applications that require improved load VHYST = thermal hysteresis.
regulation. VREF_PRE = output voltage measured at +25°C
pre-temperature cycling.
VREF_POST = output voltage measured after the
device cycles through the temperature range
of –40°C to +120°C, and returns to +25°C.
DAC NOISE PERFORMANCE
Typical noise performance for the DAC8164 with the
internal reference enabled is shown in Figure 54 to
Figure 56. Output noise spectral density at the VOUT
pin versus frequency is depicted in Figure 54 for
full-scale, midscale, and zero-scale input codes. The
Figure 98. Accurate Load Regulation of the typical noise density for midscale code is 120nV/√Hz
DAC8164 Internal Reference at 1kHz and 100nV/√Hz at 1MHz. High-frequency
noise can be improved by filtering the reference noise
as shown in Figure 55, where a 4.8μF load capacitor
Long-Term Stability is connected to the VREFH/VREFOUT pin and
Long-term stability/aging refers to the change of the compared to the no-load condition. Integrated output
output voltage of a reference over a period of months noise between 0.1Hz and 10Hz is close to 6μVPP
or years. This effect lessens as time progresses (see (midscale), as shown in Figure 56.
Figure 6, the typical long-term stability curve). The
typical drift value for the internal reference is 50ppm
from 0 hours to 1900 hours. This parameter is
characterized by powering-up and measuring 20 units
at regular intervals for a period of 1900 hours.
Copyright ©2008–2011, Texas Instruments Incorporated 37
VREFH
V
REF
H
+6V
±5V
-6V
OPA703
DAC8164
10 Fm0.1 Fm
R1
10kW
R2
10kW
3-Wire
SerialInterface
VOUT
GND
AVDD
AV
DD
V L
REF
V =
O- ´VREF
D
16384
VREF ´ ´
R +R
1 2
R1
R2
R1
V =
O-5V
10 D´
16384
+6V
±2.5V
-6V
OPA703
DAC8164
150nF
R1
10kW
R2
10kW
3-Wire
SerialInterface
VOUT
GND
AVDD
AV
DD
VREFH
V L
REF
DAC8164
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
www.ti.com
BIPOLAR OPERATION USING THE DAC8164
The DAC8164 is designed for single-supply
operation, but a bipolar output range is also possible
using the circuit in either Figure 99 or Figure 100.
The circuit shown gives an output voltage range of
±VREF. Rail-to-rail operation at the amplifier output is
achievable using an OPA703 as the output amplifier.
The output voltage for any input code can be
calculated with Equation 4:
Figure 99. Bipolar Output Range Using External
Reference at 5V
(4)
where Drepresents the input code in decimal
(0–16383).
With VREFH = 5V, R1= R2= 10kΩ.
(5)
This result has an output voltage range of ±5V with
0000h corresponding to a –5V output and 3FFFh
corresponding to a +5V output, as shown in
Figure 99. Similarly, using the internal reference, a
±2.5V output voltage range can be achieved, as
Figure 100 shows.
Figure 100. Bipolar Output Range Using Internal
Reference
38 Copyright ©2008–2011, Texas Instruments Incorporated
SYNC
SCLK
DIN
Microwireä
CS
SK
SO
DAC8164(1)
NOTE:(1)Additionalpinsomittedforclarity.
PC7
SCK
MOSI
SYNC
DAC8164(1)
SCLK
DIN
NOTE:(1)Additionalpinsomittedforclarity.
68HC11(1)
P3.3
TXD
RXD
SYNC
DAC8164(1)
SCLK
DIN
NOTE:(1)Additionalpinsomittedforclarity.
80C51/80L51(1)
DAC8164
www.ti.com
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
DAC8164 to Microwire Interface
MICROPROCESSOR INTERFACING Figure 102 shows an interface between the DAC8164
DAC SPI Interfacing and any Microwire-compatible device. Serial data are
shifted out on the falling edge of the serial clock and
Care must be taken with the digital control signals are clocked into the DAC8164 on the rising edge of
that are applied directly to the DAC, especially with the SK signal.
the SYNC pin. The SYNC pin must not be toggled
without having a full SCLK pulse in between. If this
condition is violated, the SPI interface locks up in an
erroneous state, causing the DAC to behave
incorrectly and have errors. The DAC can be
recovered from this faulty state by writing a valid SPI
command or using the SYNC pin correctly;
communication will then be restored. Avoid glitches
and transients on the SYNC line to ensure proper
operation. Figure 102. DAC8164 to Microwire Interface
DAC8164 to an 8051 Interface
Figure 101 shows a serial interface between the DAC8164 to 68HC11 Interface
DAC8164 and a typical 8051-type microcontroller. Figure 103 shows a serial interface between the
The setup for the interface is as follows: TXD of the DAC8164 and the 68HC11 microcontroller. SCK of
8051 drives SCLK of the DAC8164, while RXD drives the 68HC11 drives the SCLK of the DAC8164, while
the serial data line of the device. The SYNC signal is the MOSI output drives the serial data line of the
derived from a bit-programmable pin on the port of DAC. The SYNC signal derives from a port line
the 8051; in this case, port line P3.3 is used. When (PC7), similar to the 8051 diagram.
data are to be transmitted to the DAC8164, P3.3 is
taken low. The 8051 transmits data in 8-bit bytes;
thus, only eight falling clock edges occur in the
transmit cycle. To load data to the DAC, P3.3 is left
low after the first eight bits are transmitted; then, a
second write cycle is initiated to transmit the second
byte of data. P3.3 is taken high following the
completion of the third write cycle. The 8051 outputs
the serial data in a format that has the LSB first. The
DAC8164 requires its data with the MSB as the first
bit received. The 8051 transmit routine must therefore Figure 103. DAC8164 to 68HC11 Interface
take this requirement into account, and mirror the
data as needed. The 68HC11 should be configured so that its CPOL
bit is '0' and its CPHA bit is '1'. This configuration
causes data appearing on the MOSI output to be
valid on the falling edge of SCK. When data are
being transmitted to the DAC, the SYNC line is held
low (PC7). Serial data from the 68HC11 are
transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. (Data are
transmitted MSB first.) In order to load data to the
DAC8164, PC7 is left low after the first eight bits are
Figure 101. DAC8164 to 80C51/80L51 Interface transferred; then, a second and third serial write
operation are performed to the DAC. PC7 is taken
high at the end of this procedure.
Copyright ©2008–2011, Texas Instruments Incorporated 39
DAC8164
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
www.ti.com
LAYOUT
A precision analog component requires careful layout, The power applied to VDD should be well-regulated
adequate bypassing, and clean, well-regulated power and low noise. Switching power supplies and dc/dc
supplies. converters often have high-frequency glitches or
spikes riding on the output voltage. In addition, digital
The DAC8164 offers single-supply operation, and is components can create similar high-frequency spikes
often used in close proximity with digital logic, as their internal logic switches states. This noise can
microcontrollers, microprocessors, and digital signal easily couple into the DAC output voltage through
processors. The more digital logic present in the various paths between the power connections and
design and the higher the switching speed, the more analog output.
difficult it is to keep digital noise from appearing at
the output. As with the GND connection, VDD should be
connected to a power-supply plane or trace that is
As a result of the single ground pin of the DAC8164, separate from the connection for digital logic until
all return currents (including digital and analog return they are connected at the power-entry point. In
currents for the DAC) must flow through a single addition, a 1μF to 10μF capacitor and 0.1μF bypass
point. Ideally, GND would be connected directly to an capacitor are strongly recommended. In some
analog ground plane. This plane would be separate situations, additional bypassing may be required,
from the ground connection for the digital such as a 100μF electrolytic capacitor or even a Pi
components until they were connected at the filter made up of inductors and capacitors—all
power-entry point of the system. designed to essentially low-pass filter the supply and
remove the high-frequency noise.
40 Copyright ©2008–2011, Texas Instruments Incorporated
DAC8164
www.ti.com
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
PARAMETER DEFINITIONS
With the increased complexity of many different Full-Scale Error
specifications listed in product data sheets, this Full-scale error is defined as the deviation of the real
section summarizes selected specifications related to full-scale output voltage from the ideal output voltage
digital-to-analog converters. while the DAC register is loaded with the full-scale
code. Ideally, the output should be VDD –1 LSB. The
STATIC PERFORMANCE full-scale error is expressed in percent of full-scale
Static performance parameters are specifications range (%FSR).
such as differential nonlinearity (DNL) or integral
nonlinearity (INL). These are dc specifications and Offset Error
provide information on the accuracy of the DAC. They The offset error is defined as the difference between
are most important in applications where the signal actual output voltage and the ideal output voltage in
changes slowly and accuracy is required. the linear region of the transfer function. This
difference is calculated by using a straight line
Resolution defined by two codes. Since the offset error is defined
Generally, the DAC resolution can be expressed in by a straight line, it can have a negative or positve
different forms. Specifications such as IEC 60748-4 value. Offset error is measured in mV.
recognize the numerical, analog, and relative
resolution. The numerical resolution is defined as the Zero-Code Error
number of digits in the chosen numbering system The zero-code error is defined as the DAC output
necessary to express the total number of steps of the voltage, when all '0's are loaded into the DAC
transfer characteristic, where a step represents both register. Zero-scale error is a measure of the
a digital input code and the corresponding discrete difference between actual output voltage and ideal
analogue output value. The most commonly-used output voltage (0V). It is expressed in mV. It is
definition of resolution provided in data sheets is the primarily caused by offsets in the output amplifier.
numerical resolution expressed in bits.
Gain Error
Least Significant Bit (LSB) Gain error is defined as the deviation in the slope of
The least significant bit (LSB) is defined as the the real DAC transfer characteristic from the ideal
smallest value in a binary coded system. The value of transfer function. Gain error is expressed as a
the LSB can be calculated by dividing the full-scale percentage of full-scale range (%FSR).
output voltage by 2n, where nis the resolution of the
converter. Full-Scale Error Drift
Most Significant Bit (MSB) Full-scale error drift is defined as the change in
full-scale error with a change in temperature.
The most significant bit (MSB) is defined as the Full-scale error drift is expressed in units
largest value in a binary coded system. The value of of %FSR/°C.
the MSB can be calculated by dividing the full-scale
output voltage by 2. Its value is one-half of full-scale. Offset Error Drift
Relative Accuracy or Integral Nonlinearity (INL) Offset error drift is defined as the change in offset
error with a change in temperature. Offset error drift
Relative accuracy or integral nonlinearity (INL) is is expressed in μV/°C.
defined as the maximum deviation between the real
transfer function and a straight line passing through Zero-Code Error Drift
the endpoints of the ideal DAC transfer function. DNL
is measured in LSBs. Zero-code error drift is defined as the change in
zero-code error with a change in temperature.
Differential Nonlinearity (DNL) Zero-code error drift is expressed in μV/°C.
Differential nonlinearity (DNL) is defined as the Gain Temperature Coefficient
maximum deviation of the real LSB step from the
ideal 1LSB step. Ideally, any two adjacent digital The gain temperature coefficient is defined as the
codes correspond to output analog voltages that are change in gain error with changes in temperature.
exactly one LSB apart. If the DNL is less than 1LSB, The gain temperature coefficient is expressed in ppm
the DAC is said to be monotonic. of FSR/°C.
Copyright ©2008–2011, Texas Instruments Incorporated 41
SR=max
DV(t)
OUT
Dt
DAC8164
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
www.ti.com
Power-Supply Rejection Ratio (PSRR) Channel-to-Channel DC Crosstalk
Power-supply rejection ratio (PSRR) is defined as the Channel-to-channel dc crosstalk is defined as the dc
ratio of change in output voltage to a change in change in the output level of one DAC channel in
supply voltage for a full-scale output of the DAC. The response to a change in the output of another DAC
PSRR of a device indicates how the output of the channel. It is measured with a full-scale output
DAC is affected by changes in the supply voltage. change on one DAC channel while monitoring
PSRR is measured in decibels (dB). another DAC channel remains at midscale; it is
expressed in LSB.
Monotonicity Channel-to-Channel AC Crosstalk
Monotonicity is defined as a slope whose sign does
not change. If a DAC is monotonic, the output AC crosstalk in a multi-channel DAC is defined as the
changes in the same direction or remains at least amount of ac interference experienced on the output
constant for each step increase (or decrease) in the of a channel at a frequency (f) (and its harmonics),
input code. when the output of an adjacent channel changes its
value at the rate of frequency (f). It is measured with
one channel output oscillating with a sine wave
DYNAMIC PERFORMANCE frequency of 1kHz, while monitoring the amplitude of
Dynamic performance parameters are specifications 1kHz harmonics on an adjacent DAC channel output
such as settling time or slew rate, which are important (kept at zero scale); it is expressed in dB.
in applications where the signal rapidly changes
and/or high frequency signals are present. Signal-to-Noise Ratio (SNR)
Signal-to-noise ratio (SNR) is defined as the ratio of
Slew Rate the root mean-squared (RMS) value of the output
The output slew rate (SR) of an amplifier or other signal divided by the RMS values of the sum of all
electronic circuit is defined as the maximum rate of other spectral components below one-half the output
change of the output voltage for all possible input frequency, not including harmonics or dc. SNR is
signals. measured in dB.
Total Harmonic Distortion (THD)
Total harmonic distortion + noise is defined as the
Where ΔVOUT(t) is the output produced by the ratio of the RMS values of the harmonics and noise
amplifier as a function of time t.to the value of the fundamental frequency. It is
expressed in a percentage of the fundamental
Output Voltage Settling Time frequency amplitude at sampling rate fS.
Settling time is the total time (including slew time) for Spurious-Free Dynamic Range (SFDR)
the DAC output to settle within an error band around
its final value after a change in input. Settling times Spurious-free dynamic range (SFDR) is the usable
are specified to within ±0.003% (or whatever value is dynamic range of a DAC before spurious noise
specified) of full-scale range (FSR). interferes or distorts the fundamental signal. SFDR is
the measure of the difference in amplitude between
Code Change/Digital-to-Analog Glitch Energy the fundamental and the largest harmonically or
non-harmonically related spur from dc to the full
Digital-to-analog glitch impulse is the impulse injected Nyquist bandwidth (half the DAC sampling rate, or
into the analog output when the input code in the fS/2). A spur is any frequency bin on a spectrum
DAC register changes state. It is normally specified analyzer, or from a Fourier transform, of the analog
as the area of the glitch in nanovolts-second (nV-s), output of the DAC. SFDR is specified in decibels
and is measured when the digital input code changes relative to the carrier (dBc).
by 1LSB at the major carry transition.
Signal-to-Noise plus Distortion (SINAD)
Digital Feedthrough SINAD includes all the harmonic and outstanding
Digital feedthrough is defined as impulse seen at the spurious components in the definition of output noise
output of the DAC from the digital inputs of the DAC. power in addition to quantizing any internal random
It is measured when the DAC output is not updated. It noise power. SINAD is expressed in dB at a specified
is specified in nV-s, and measured with a full-scale input frequency and sampling rate, fS.
code change on the data bus; that is, from all '0's to
all '1's and vice versa.
42 Copyright ©2008–2011, Texas Instruments Incorporated
DAC8164
www.ti.com
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
DAC Output Noise Density Full-Scale Range (FSR)
Output noise density is defined as Full-scale range (FSR) is the difference between the
internally-generated random noise. Random noise is maximum and minimum analog output values that the
characterized as a spectral density (nV/√Hz). It is DAC is specified to provide; typically, the maximum
measured by loading the DAC to midscale and and minimum values are also specified. For an n-bit
measuring noise at the output. DAC, these values are usually given as the values
matching with code 0 and 2n.
DAC Output Noise
DAC output noise is defined as any voltage deviation
of DAC output from the desired value (within a
particular frequency band). It is measured with a DAC
channel kept at midscale while filtering the output
voltage within a band of 0.1Hz to 10Hz and
measuring its amplitude peaks. It is expressed in
terms of peak-to-peak voltage (Vpp).
Copyright ©2008–2011, Texas Instruments Incorporated 43
DAC8164
SBAS410B –FEBRUARY 2008–REVISED MAY 2011
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (February 2008) to Revision B Page
•Changed Output Voltage parameter min/max values from 2.4995 and 2.5005 to 2.4975 and 2.5025, respectively ........... 4
•Changed Initial Accuracy parameter min/max values from –0.02 and 0.02 to –0.1 and 0.1, respectively ........................... 4
•Changed values for SCLK High TIme parameter from 20 and 10 to 10 and 20. ................................................................. 7
•Added DAC SPI Interfacing subsection to Microprocessor Interfacing section .................................................................. 39
44 Copyright ©2008–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 6-May-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
DAC8164IAPW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC8164IAPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC8164IAPWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC8164IAPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC8164IBPW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC8164IBPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC8164IBPWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC8164IBPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC8164ICPW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC8164ICPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC8164ICPWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC8164ICPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC8164IDPW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC8164IDPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC8164IDPWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC8164IDPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
PACKAGE OPTION ADDENDUM
www.ti.com 6-May-2011
Addendum-Page 2
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DAC8164IAPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
DAC8164IBPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
DAC8164ICPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
DAC8164IDPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC8164IAPWR TSSOP PW 16 2000 367.0 367.0 35.0
DAC8164IBPWR TSSOP PW 16 2000 367.0 367.0 35.0
DAC8164ICPWR TSSOP PW 16 2000 367.0 367.0 35.0
DAC8164IDPWR TSSOP PW 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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