Isolated Sigma-Delta Modulator
Data Sheet AD7400
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006–2012 Analog Devices, Inc. All rights reserved.
FEATURES
10 MHz clock rate
Second-order modulator
16 bits no missing codes
±2 LSB INL typical at 16 bits
3.5 μV/°C maximum offset drift
On-board digital isolator
On-board reference
Low power operation: 18 mA maximum at 5.25 V
−40°C to +105°C operating range
16-lead SOIC package
Safety and regulatory approvals
UL recognition
5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 891 V peak
APPLICATIONS
AC motor controls
Data acquisition systems
A/D + opto-isolator replacements
GENERAL DESCRIPTION
The AD74001 is a second-order, sigma-delta (Σ-Δ) modulator
that converts an analog input signal to a high speed, 1-bit data
stream with on-chip digital isolation based on Analog Devices,
Inc. iCoupler® technology. The AD7400 operates from a 5 V
power supply and accepts a differential input signal of ±200 mV
(±320 mV full scale). The analog input is continuously sampled
by the analog modulator, eliminating the need for external
sample-and-hold circuitry. The input information is contained
in the output stream as a density of ones with a data rate of
10 MHz. The original information can be reconstructed with an
appropriate digital filter. The serial I/O can use a 5 V or a 3 V
supply (VDD2).
The serial interface is digitally isolated. High speed CMOS,
combined with monolithic air core transformer technology,
means the on-chip isolation provides outstanding performance
characteristics superior to alternatives such as optocoupler
devices. The part contains an on-chip reference. The AD7400 is
offered in a 16-lead SOIC and has an operating temperature
range of −40°C to +105°C.
An external clock version, AD7401, is also available.
1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329.
FUNCTIONAL BLOCK DIAGRAM
04718-001
V
IN
+
V
DD1
V
DD2
V
IN
–Σ-∆ ADC
CONTROL LOGIC
AD7400
BUF
T/H
REF
UPDATE
GND
1
GND
2
MDAT
MCLKOUT
ENCODE
ENCODE DECODE
DECODE
WATCHDOG
WATCHDOG
UPDATE
Figure 1.
AD7400 Data Sheet
Rev. F | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 4
Insulation and Safety-Related Specifications ............................ 5
Regulatory Information ............................................................... 5
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics .............................................................................. 6
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ..............................................9
Terminology .................................................................................... 12
Theory of Operation ...................................................................... 13
Circuit Information .................................................................... 13
Analog Input ............................................................................... 13
Differential Inputs ...................................................................... 14
Digital Filter ................................................................................ 15
Applications Information .............................................................. 17
Grounding and Layout .............................................................. 17
Evaluating the AD7400 Performance ...................................... 17
Insulation Lifetime ..................................................................... 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
3/12—Rev. E to Rev. F
Changed IDD1 Parameter from 12 mA to 13 mA, Table 1 ............ 3
7/11—Rev. D to Rev. E
Changes to Minimum External Air Gap (Clearance) Parameter,
Table 3 and Minimum External Tracking (Creepage) Parameter,
Table 3 ................................................................................................ 5
Changes to Figure 5; Pin 1 Description, Table 8; and Pin 7
Description, Table 8 .......................................................................... 8
4/11—Rev. C to Rev. D
Changes to Dynamic Input Current Parameter, Table 1 ............. 3
1/11—Rev. B to Rev. C
Changes to Features Section............................................................ 1
Changes to Input-to-Output Momentary Withstand Voltage
Parameter, Table 3, UL Column, Table 4, and Note 1, Table 4 .......... 5
Changes to Ordering Guide ..................................................................... 18
9/07—Rev. A to Rev. B
Updated VDE Certification Throughout ...................................... 1
Changes to Table 6 ............................................................................. 7
12/06—Rev. 0 to Rev. A
Changes to Features .......................................................................... 1
Changes to Table 6 ............................................................................. 7
Changes to Analog Input Section ................................................. 13
Changes to Figure 26 ...................................................................... 15
1/06—Revision 0: Initial Version
Data Sheet AD7400
Rev. F | Page 3 of 20
SPECIFICATIONS
VDD1 = 4.5 V to 5.25 V, VDD2 = 3 V to 5.5 V, VIN+ = −200 mV to +200 mV, and VIN− = 0 V (single-ended); TA = TMIN to TMAX,
fMCLK = 10 MHz, tested with Sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted.1
Table 1.
Parameter Y Version1, 2 Unit Test Conditions/Comments
STATIC PERFORMANCE
Resolution 16 Bits min Filter output truncated to 16 bits
Integral Nonlinearity3 ±15 LSB max −40°C to +85°C; ±2 LSB typical
±25 LSB max >85°C to 105°C
Differential Nonlinearity3 ±0.9 LSB max Guaranteed no missing codes to 16 bits
Offset Error
3
±0.5
mV max
±50 µV typ TA = 25°C
Offset Drift vs. Temperature 3.5 µV/°C max −40°C to +105°C
1 µV/°C typ
Offset Drift vs. VDD1 120 µV/V typ
Gain Error3 ±1 mV max
Gain Error Drift vs. Temperature 23 µV/°C typ −40°C to +105°C
Gain Error Drift vs. VDD1 110 µV/V typ
ANALOG INPUT
Input Voltage Range
±200
mV min/mV max
For specified performance; full range ±320 mV
Dynamic Input Current ±8 µA max VIN+ = 400 mV, VIN− = 0 V
±0.5 µA typ VIN+ = VIN− = 0 V
Input Capacitance 10 pF typ
DYNAMIC SPECIFICATIONS VIN+ = 35 Hz, 400 mV p-p sine
Signal-to-(Noise + Distortion) Ratio (SINAD)3 70 dB min −40°C to +85°C
65 dB min >85°C to 105°C
79 dB typ
Signal-to-Noise Ratio (SNR) 71 dB min −40°C to +105°C
Total Harmonic Distortion (THD)3 −88 dB typ
Peak Harmonic or Spurious Noise (SFDR)3 −88 dB typ
Effective Number of Bits (ENOB)3 11.5 Bits
Isolation Transient Immunity3 25 kV/µs min
30 kV/µs typ
LOGIC OUTPUTS
Output High Voltage, VOH VDD2 − 0.1 V min IO = −200 µA
Output Low Voltage, VOL 0.4 V max IO = +200 µA
POWER REQUIREMENTS
VDD1 4.5/5.25 V min/V max
VDD2 3/5.5 V min/V max
IDD1 4 13 mA max VDD1 = 5.25 V
IDD2 5 6 mA max VDD2 = 5.5 V
4 mA max VDD2 = 3.3 V
1 Temperature range is −40°C to +85°C.
2 All voltages are relative to their respective ground.
3 See the Terminology section.
4 See Figure 14.
5 See Figure 15.
AD7400 Data Sheet
Rev. F | Page 4 of 20
TIMING SPECIFICATIONS
VDD1 = 4.5 V to 5.25 V, VDD2 = 3 V to 5.5 V, TA = TMAX to TMIN, unless otherwise noted.1
Table 2.
Parameter Limit at TMIN, TMAX Unit Description
fMCLKOUT2 10 MHz typ Master clock output frequency
9/11 MHz min/MHz max Master clock output frequency
t13 40 ns max Data access time after MCLK rising edge
t23 10 ns min Data hold time after MCLK rising edge
t3 0.4 × tMCLKOUT ns min Master clock low time
t4 0.4 × tMCLKOUT ns min Master clock high time
1 Sample tested during initial release to ensure compliance.
2 Mark space ratio for clock output is 40/60 to 60/40.
3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
04718-002
200µA IOL
200µA IOH
+1.6V
TO O UTPUT
PIN CL
25pF
Figure 2. Load Circuit for Digital Output Timing Specifications
04718-003
MCLKOUT
MDAT
t
1
t
2
t
4
t
3
Figure 3. Data Timing
Data Sheet AD7400
Rev. F | Page 5 of 20
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 3.
Parameter Symbol Value Unit Conditions
Input-to-Output Momentary Withstand Voltage
V
ISO
V rms
1-minute duration
Minimum External Air Gap (Clearance) L(I01) 8.1 min mm Measured from input terminals to output
terminals, shortest distance through air
Minimum External Tracking (Creepage) L(I02) 7.46 min mm Measured from input terminals to output
terminals, shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.017
min
mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material group (DIN VDE 0110, 1/89, Table 1)
REGULATORY INFORMATION
Table 4.
UL1 CSA VDE2
Recognized Under 1577
Component Recognition Program1
Approved under CSA Component
Acceptance Notice #5A
Certified according to DIN V VDE V 0884-10 (VDE V 0884-
10):2006-122
5000 V rms Isolation Voltage Reinforced insulation per CSA
60950-1-03 and IEC 60950-1, 630 V
rms maximum working voltage
Reinforced insulation per DIN V VDE V 0884-10 (VDE V 0884-
10):2006-12, 891V peak
File E214100 File 205078 File 2471900-4880-0001
1 In accordance with UL 1577, each AD7400 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 15 µA).
2 In accordance with DIN V VDE V 0884-10, each AD7400 is proof tested by applying an insulation test voltage ≥ 1671 V peak for 1 second (partial discharge detection
limit = 5 pC).
AD7400 Data Sheet
Rev. F | Page 6 of 20
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
means of protective circuits.
Table 5.
Description Symbol Characteristic Unit
INSTALLATION CLASSIFICATION PER DIN VDE 0110
For Rated Mains Voltage ≤ 300 V rms I–IV
For Rated Mains Voltage ≤ 450 V rms I–II
For Rated Mains Voltage ≤ 600 V rms I–II
CLIMATIC CLASSIFICATION 40/105/21
POLLUTION DEGREE (DIN VDE 0110, Table 1) 2
MAXIMUM WORKING INSULATION VOLTAGE VIORM 891 V peak
INPUT-TO-OUTPUT TEST VOLTAGE, METHOD B1
VIORM × 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC VPR 1671 V peak
INPUT-TO-OUTPUT TEST VOLTAGE, METHOD A VPR
After Environmental Test Subgroup 1 1426 V peak
VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC
After Input and/or Safety Test Subgroup 2/3 1069 V peak
VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC
HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, tTR = 10 sec) VTR 6000 V peak
SAFETY-LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE, ALSO SEE Figure 4)
Case Temperature TS 150 °C
Side 1 Current
I
S1
265
mA
Side 2 Current
I
S2
335
mA
INSULATION RESISTANCE AT TS, VIO = 500 V RS >109 Ω
CASE TEMPERATURE (°C)
SAFETY-LIMITING CURRENT (mA)
0
0
350
300
250
200
150
100
50
50 100 150 200
SIDE #1
SIDE #2
04718-026
Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per DIN V VDE V 0884-10
Data Sheet AD7400
Rev. F | Page 7 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. All voltages are relative to
their respective ground.
Table 6.
Parameter Rating
VDD1 to GND1 −0.3 V to +6.5 V
VDD2 to GND2 −0.3 V to +6.5 V
Analog Input Voltage to GND1 −0.3 V to VDD1 + 0.3 V
Output Voltage to GND2 −0.3 V to VDD2 + 0.3 V
Input Current to Any Pin Except Supplies1 ±10 mA
Operating Temperature Range −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
SOIC Package
θJA Thermal Impedance 89.2°C/W
θJC Thermal Impedance 55.6°C/W
Resistance (Input-to-Output), RI-O 1012 Ω
Capacitance (Input-to-Output), CI-O2 1.7 pF typ
Pb-Free Temperature, Soldering
Reflow 260 (+0)°C
ESD
1.5 kV
1 Transient currents of up to 100 mA do not cause SCR to latch-up.
2 f = 1 MHz.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 7. Maximum Continuous Working Voltage1
Parameter Max Unit Constraint
AC Voltage,
Bipolar Waveform
565 VPK 50-year minimum lifetime
AC Voltage,
Unipolar Waveform
891 VPK Maximum CSA/VDE
approved working voltage
DC Voltage 891 V Maximum CSA/VDE
approved working voltage
1 Refers to continuous voltage magnitude imposed across the isolation
barrier. See the Insulation Lifetime section for more details.
ESD CAUTION
AD7400 Data Sheet
Rev. F | Page 8 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04718-004
NC = NO CO NNECT
AD7400
TOP VIEW
(Not to Scale)
V
DD1
V
DD2
V
IN
+
V
IN
–
GND
2
GND
2
V
DD1
/NC
GND
1
1
2
3
NC
4
NC
5
NC
MCLKOUT
NC
16
15
14
NC
6
7
8
MDAT
NC
11
10
9
13
12
Figure 5. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1 Supply Voltage. 4.5 V to 5.25 V. This is the supply voltage for the isolated side of the AD7400 and is relative to
GND1.
2 VIN+ Positive Analog Input. Specified range of ±200 mV.
3 VIN− Negative Analog Input. Normally connected to GND1.
4 to 6, 10, 12, 15 NC No Connect.
7 VDD1/NC Supply Voltage. 4.5 V to 5.25 V. This is the supply voltage for the isolated side of the AD7400 and is relative
to GND1.
No Connect (NC). If desired, Pin 7 may be allowed to float. It should not be tied to ground. The AD7400
will operate normally provided that the supply voltage is applied to Pin 1.
8 GND1 Ground 1. This is the ground reference point for all circuitry on the isolated side.
9, 16 GND2 Ground 2. This is the ground reference point for all circuitry on the nonisolated side.
11 MDAT
Serial Data Output. The single bit modulator output is supplied to this pin as a serial data stream.
The bits are clocked out on the rising edge of the MCLKOUT output and valid on the following
MCLKOUT rising edge.
13 MCLKOUT
Master Clock Logic Output. 10 MHz typical. The bit stream from the modulator is valid on the rising edge
of MCLKOUT.
14 VDD2 Supply Voltage. 3 V to 5.5 V. This is the supply voltage for the nonisolated side and is relative to GND2.
Data Sheet AD7400
Rev. F | Page 9 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, using a 20 kHz brick wall filter, unless otherwise noted.
100
0
20
10
30
40
50
60
70
80
90
1000 200 300 400 500 600 700 800 900 1000
04718-005
SUPPLY RIPPLE FREQUENCY (kHz)
PSRR (dB)
200mV p-p SINEWAVE ON V
DD1
NO DECOUPLING
V
DD1
= V
DD2
= 4.5V TO 5.25V
Figure 6. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
(1 MHz Filter Used)
0
–90
–80
–70
–60
–50
–40
–30
–20
–10
04000350030002500200015001000500
04718-006
INP UT FRE QUENC Y (Hz)
SI NAD ( dB)
V
DD1
= V
DD2
= 4.5V
V
DD1
= V
DD2
= 5.25V V
DD1
= V
DD2
= 5V
Figure 7. SINAD vs. Analog Input Frequency for Various Supply Voltages
FREQUENCY (kHz)
(dB)
0
–20
–180
–160
–140
–120
–100
–80
–60
–40
02018161412108642
04718-007
8192 PO INT FF T
fIN = 35Hz
SI NAD = 79.6991d B
THD = –92.6722d B
DECIMATION BY 256
Figure 8. Typical FFT, ±200 mV Range
(Using Sinc3 Filter, 256 Decimation Rate)
0
–90
–80
–70
–60
–50
–40
–30
–20
–10
0.195 0.3150.215 0.235 0.255 0.275 0.295
04718-008
± INPUT AMPLITUDE (V)
SI NAD ( dB)
V
DD1
= V
DD2
= 5V
Figure 9. SINAD vs. VIN
CODE
DNL ERRO R ( LSB)
0.5
–0.4
–0.3
–0.2
0
–0.1
0.1
0.2
0.3
0.4
04718-009
0600005000040000300002000010000
V
IN
+ = –200mV TO +200mV
V
IN
– = 0V
Figure 10. Typical DNL, ±200 mV Range
(Using Sinc3 Filter, 256 Decimation Rate)
CODE
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6 0600005000040000300002000010000
04718-010
VIN+ = –200mV TO + 200mV
VIN–= 0V
INL ERROR (L S B)
Figure 11. Typical INL, ±200 mV Range
(Using Sinc3 Filter, 256 Decimation Rate)
AD7400 Data Sheet
Rev. F | Page 10 of 20
–200
100
50
–50
0
–100
–150
–45–35–25–15 –5 5 15 25 35 45 55 65 75 85 95 105
04718-011
TEMPERATURE (°C)
OFF SET (µV)
V
DD1
= V
DD2
= 4.5V
V
DD1
= V
DD2
= 5.25V
V
DD1
= V
DD2
= 5V
Figure 12. Offset Drift vs. Temperature for Various Supply Voltages
V
DD1
= V
DD2
= 4.5V
–0.20
0.20
0.15
–0.05
0
0.05
0.10
–0.10
–0.15
–45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 95 105
04718-012
TEMPERATURE (°C)
GAIN (%)
V
DD1
= V
DD2
= 5V
V
DD1
= V
DD2
= 5.25V
Figure 13. Gain Error Drift vs. Temperature for Various Supply Voltages
0.0089
0.0090
0.0091
0.0092
0.0093
0.0094
0.0095
0.0096
0.0097
0.0098
0.0099
–0.34
–0.30
–0.26
–0.22
–0.18
–0.14
–0.10
–0.06
–0.02
0.02
0.30
0.06
0.10
0.14
0.18
0.22
0.26
0.34
04718-013
V
IN
DC INPUT VOLTAGE (V)
I
DD1
(A)
V
DD1
= V
DD2
= 5V
T
A
= +85°C T
A
= +25°C
T
A
= –40°C
Figure 14. IDD1 vs. VIN at Various Temperatures
0.0030
0.0031
0.0032
0.0033
0.0034
0.0035
0.0036
–0.34
–0.30
–0.26
–0.22
–0.18
–0.14
–0.10
–0.06
–0.02
0.02
0.30
0.06
0.10
0.14
0.18
0.22
0.26
0.34
04718-014
VIN DC INPUT VOLTAGE (V)
IDD2 (A)
VDD1 = VDD2 = 5V
IDD2 @ +85
°C
I
DD2
@ –40°C
I
DD2
@ +25°C
Figure 15. IDD2 vs. VIN at Various Temperatures
VIN+DC INPUT (V)
IIN (µA)
VDD1=VDD2=4.5V TO 5.25V
9
6
3
0
–3
–6
–9
–0.05
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
–0.30
–0.25
–0.20
–0.15
–0.10
–0.35
04718-015
Figure 16. IIN vs. VIN+ DC Input
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
110 100 1000 100000.1
04718-016
RIPPLE FREQUENCY (kHz)
CMRR (dB)
Figure 17. CMRR vs. Common-Mode Ripple Frequency
Data Sheet AD7400
Rev. F | Page 11 of 20
1.0
0.8
0.6
0.4
0.2
0
–0.30
–0.20
–0.25
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0.25
0.30 04718-017
V
IN
DC INP UT (V)
NOISE (mV)
BANDWIDTH = 100kHz
Figure 18. RMS Noise Voltage vs. VIN DC Input
11.0
10.8
10.6
10.4
10.2
10.0
9.8
9.6
9.4
9.2
9.0
–45
–35
–25
–15
–5
5
15
25
35
45
55
65
75
85
95
105
04718-024
TEMPERATURE (°C)
MCL KOUT ( M Hz )
VDD1= VDD2= 4.5V
VDD1= VDD2= 5V
VDD1= VDD2= 5.25V
Figure 19. MCLKOUT vs. Temperature for Various Supplies
AD7400 Data Sheet
Rev. F | Page 12 of 20
TERMINOLOGY
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
and the ideal 1 LSB change between any two adjacent codes in
the ADC.
Integral Nonlinearity
Integral nonlinearity is the maximum deviation from a straight
line passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are specified negative
full scale, −200 mV (VIN+ − VIN−), Code 12,288 for the 16-bit
level, and specified positive full scale, +200 mV (VIN+ − VIN−),
Code 53,248 for the 16-bit level.
Offset Error
Offset error is the deviation of the midscale code (Code 32,768
for the 16-bit level) from the ideal VIN+ − VIN− (that is, 0 V).
Gain Error
Gain error includes both positive full-scale gain error and
negative full-scale gain error. Positive full-scale gain error is the
deviation of the specified positive full-scale code (53,248 for the
16-bit level) from the ideal VIN+ − VIN− (+200 mV) after the
offset error is adjusted out. Negative full-scale gain error is the
deviation of the specified negative full-scale code (12,288 for
the 16-bit level) from the ideal VIN+ − VIN− (−200 mV) after the
offset error is adjusted out. Gain error includes reference error.
Signal-to-(Noise + Distortion) Ratio (SINAD)
This ratio is the measured ratio of signal-to-(noise + distortion)
at the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantization levels in the digitization
process; the more levels, the smaller the quantization noise. The
theoretical signal-to-(noise + distortion) ratio for an ideal N-bit
converter with a sine wave input is given by
Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB
Therefore, for a 12-bit converter, this is 74 dB.
Effective Number of Bits (ENOB)
The ENOB is defined by
ENOB = (SINAD − 1.76)/6.02
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7400, it is defined as
1
6
54
3
2
V
VVVVV
THD
22222
log20)dB(
++++
=
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2, excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
Common-Mode Rejection Ratio (CMRR)
CMRR is defined as the ratio of the power in the ADC output at
±200 mV frequency, f, to the power of a 200 mV p-p sine wave
applied to the common-mode voltage of VIN+ and VIN− of
frequency fS, expressed as
CMRR (dB) = 10log(Pf/PfS)
where:
Pf is the power at frequency f in the ADC output.
PfS is the power at frequency fS in the ADC output.
Power Supply Rejection Ratio (PSRR)
Variations in power supply affect the full-scale transition but
not converter linearity. PSRR is the maximum change in the
specified full-scale (±200 mV) transition point due to a change
in power supply voltage from the nominal value (see Figure 6).
Isolation Transient Immunity
The isolation transient immunity specifies the rate of rise/fall of
a transient pulse applied across the isolation boundary beyond
which clock or data is corrupted. (It was tested using a transient
pulse frequency of 100 kHz.)
Data Sheet AD7400
Rev. F | Page 13 of 20
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7400 isolated Σ-Δ modulator converts an analog input
signal into a high speed (10 MHz typical), single-bit data
stream; the time average of the modulator’s single-bit data is
directly proportional to the input signal. Figure 22 shows a
typical application circuit where the AD7400 is used to provide
isolation between the analog input, a current sensing resistor,
and the digital output, which is then processed by a digital filter
to provide an N-bit word.
ANALOG INPUT
The differential analog input of the AD7400 is implemented
with a switched capacitor circuit. This circuit implements a
second-order modulator stage that digitizes the input signal
into a 1-bit output stream. The sample clock (MCLKOUT)
provides the clock signal for the conversion process as well as
the output data-framing clock. This clock source is internal on
the AD7400. The analog input signal is continuously sampled
by the modulator and compared to an internal voltage reference.
A digital stream that accurately represents the analog input over
time appears at the output of the converter (see Figure 20).
04718-019
MODULATOR OUTPUT
+FS ANALOG INPUT
–FS ANALOG INPUT
ANALOG INPUT
Figure 20. Analog Input vs. Modulator Output
A differential signal of 0 V results (ideally) in a stream of 1s and
0s at the MDAT output pin. This output is high 50% of the time
and low 50% of the time. A differential input of 200 mV pro-
duces a stream of 1s and 0s that are high 81.25% of the time. A
differential input of −200 mV produces a stream of 1s and 0s
that are high 18.75% of the time.
A differential input of 320 mV results in a stream of, ideally, all
1s. This is the absolute full-scale range of the AD7400, while
200 mV is the specified full-scale range, as shown in Table 9.
Table 9. Analog Input Range
Analog Input Voltage Input
Full-Scale Range +640 mV
Positive Full Scale +320 mV
Positive Specified Input Range +200 mV
Zero 0 mV
Negative Specified Input Range −200 mV
Negative Full Scale −320 mV
To reconstruct the original information, this output needs to be
digitally filtered and decimated. A Sinc3 filter is recommended
because this is one order higher than that of the AD7400
modulator. If a 256 decimation rate is used, the resulting
16-bit word rate is 39 kHz, assuming a 10 MHz internal clock
frequency. Figure 21 shows the transfer function of the AD7400
relative to the 16-bit output.
04718-020
65535
53248
SPECIFIED RANGE
ANALOG INPUT
ADC CODE
12288
–320mV –200mV +200mV +320mV
0
Figure 21. Filtered and Decimated 16-Bit Transfer Characteristic
04718-018
Σ-∆
MOD/
ENCODER
INPUT
CURRENT
NONISOLATED
5V/3V
ISOLATED
5V
V
DD1
R
SHUNT
V
IN
+
V
IN
–
GND
1
V
DD
GND
V
DD2
MD AT MD AT
SINC
3
FILTER
AD7400
MCLKOUT
SDAT
CS
SCL
K
MCLK
GND
2
DECODER
DECODER
+
ENCODER
Figure 22. Typical Application Circuit
AD7400 Data Sheet
Rev. F | Page 14 of 20
DIFFERENTIAL INPUTS
The analog input to the modulator is a switched capacitor
design. The analog signal is converted into charge by highly
linear sampling capacitors. A simplified equivalent circuit
diagram of the analog input is shown in Figure 23. A signal
source driving the analog input must be able to provide the
charge onto the sampling capacitors every half MCLKOUT cycle
and settle to the required accuracy within the next half cycle.
φA
φB
1kΩ
V
IN
–
φA
φB
φB φB
1kΩ
V
IN
+2pF
2pF
φA φA
MCLKOUT
04718-027
Figure 23. Analog Input Equivalent Circuit
Because the AD7400 samples the differential voltage across its
analog inputs, low noise performance is attained with an input
circuit that provides low common-mode noise at each input.
The amplifiers used to drive the analog inputs play a critical role in
attaining the high performance available from the AD7400.
When a capacitive load is switched onto the output of an op
amp, the amplitude momentarily drops. The op amp tries to
correct the situation and, in the process, hits its slew rate limit.
This nonlinear response, which can cause excessive ringing, can
lead to distortion. To remedy the situation, a low-pass RC filter
can be connected between the amplifier and the input to the
AD7400. The external capacitor at each input aids in supplying
the current spikes created during the sampling process, and the
resistor isolates the op amp from the transient nature of the load.
The recommended circuit configuration for driving the differential
inputs to achieve best performance is shown in Figure 24. A
capacitor between the two input pins sources or sinks charge
to allow most of the charge that is needed by one input to be
effectively supplied by the other input. The series resistor again
isolates any op amp from the current spikes created during the
sampling process. Recommended values for the resistors and
capacitor are 22 Ω and 47 pF, respectively.
R
VIN–
R
VIN+
C
AD7400
04718-028
Figure 24. Differential Input RC Network
Data Sheet AD7400
Rev. F | Page 15 of 20
DIGITAL FILTER
A Sinc3 filter is recommended for use with the AD7400. This
filter can be implemented on an FPGA or a DSP. The following
Verilog code provides an example of a Sinc3 filter implementation
on a Xilinx® Spartan-II 2.5 V FPGA. This code can possibly be
compiled for another FPGA, such as an Altera® device. Note
that the data is read on the negative clock edge in this case,
although it can be read on the positive edge if preferred. Figure 28
shows the effect of using different decimation rates with various
filter types.
/*`Data is read on negative clk edge*/
module DEC256SINC24B(mdata1, mclk1, reset,
DATA);
input mclk1; /*used to clk filter*/
input reset; /*used to reset filter*/
input mdata1; /*ip data to be
filtered*/
output [15:0] DATA; /*filtered op*/
integer location;
integer info_file;
reg [23:0] ip_data1;
reg [23:0] acc1;
reg [23:0] acc2;
reg [23:0] acc3;
reg [23:0] acc3_d1;
reg [23:0] acc3_d2;
reg [23:0] diff1;
reg [23:0] diff2;
reg [23:0] diff3;
reg [23:0] diff1_d;
reg [23:0] diff2_d;
reg [15:0] DATA;
reg [7:0] word_count;
reg word_clk;
reg init;
/*Perform the Sinc ACTION*/
always @ (mdata1)
if(mdata1==0)
ip_data1 <= 0; /* change from a 0
to a -1 for 2's comp */
else
ip_data1 <= 1;
/*ACCUMULATOR (INTEGRATOR)
Perform the accumulation (IIR) at the speed
of the modulator.
04718-021
MCLKOUT
IP_DATA1
ACC1+ ACC2+ ACC3
+Z
+Z
+Z
Figure 25. Accumulator
Z = one sample delay
MCLKOUT = modulators conversion bit rate
*/
always @ (negedge mclk1 or posedge reset)
if (reset)
begin
/*initialize acc registers on reset*/
acc1 <= 0;
acc2 <= 0;
acc3 <= 0;
end
else
begin
/*perform accumulation process*/
acc1 <= acc1 + ip_data1;
acc2 <= acc2 + acc1;
acc3 <= acc3 + acc2;
end
/*DECIMATION STAGE (MCLKOUT/ WORD_CLK)
*/
always @ (posedge mclk1 or posedge reset)
if (reset)
word_count <= 0;
else
word_count <= word_count + 1;
always @ (word_count)
word_clk <= word_count[7];
/*DIFFERENTIATOR (including decimation stage)
Perform the differentiation stage (FIR) at a
lower speed.
WORD_CLK
ACC3 DIFF1 DIFF3
+
–
+
–
DIFF2
Z
–1
–
+
–
Z
–1
Z
–1
04718-022
Figure 26. Differentiator
Z = one sample delay
WORD_CLK = output word rate
*/
AD7400 Data Sheet
Rev. F | Page 16 of 20
always @ (posedge word_clk or posedge reset)
if(reset)
begin
acc3_d2 <= 0;
diff1_d <= 0;
diff2_d <= 0;
diff1 <= 0;
diff2 <= 0;
diff3 <= 0;
end
else
begin
diff1 <= acc3 - acc3_d2;
diff2 <= diff1 - diff1_d;
diff3 <= diff2 - diff2_d;
acc3_d2 <= acc3;
diff1_d <= diff1;
diff2_d <= diff2;
end
/* Clock the Sinc output into an output
register
04718-023
WORD_CLK
DATADIFF3
Figure 27. Clocking Sinc Output into an Output Register
WORD_CLK = output word rate
*/
always @ (posedge word_clk)
begin
DATA[15] <= diff3[23];
DATA[14] <= diff3[22];
DATA[13] <= diff3[21];
DATA[12] <= diff3[20];
DATA[11] <= diff3[19];
DATA[10] <= diff3[18];
DATA[9] <= diff3[17];
DATA[8] <= diff3[16];
DATA[7] <= diff3[15];
DATA[6] <= diff3[14];
DATA[5] <= diff3[13];
DATA[4] <= diff3[12];
DATA[3] <= diff3[11];
DATA[2] <= diff3[10];
DATA[1] <= diff3[9];
DATA[0] <= diff3[8];
end
endmodule
80
70
60
50
40
30
20
10
0
90
10 100 1k1
04718-025
DECIMATION RATE
SNR (dB)
SINC3
SINC2
SINC1
Figure 28. SNR vs. Decimation Rate for Different Filter Types
Data Sheet AD7400
Rev. F | Page 17 of 20
APPLICATIONS INFORMATION
GROUNDING AND LAYOUT
Supply decoupling with a value of 100 nF is strongly recom-
mended on both VDD1 and VDD2. Decoupling on one or both
VDD1 pins does not significantly affect performance. In
applications involving high common-mode transients, care
should be taken to ensure that board coupling across the
isolation barrier is minimized. Furthermore, the board layout
should be designed so that any coupling that occurs equally
affects all pins on a given component side. Failure to ensure this
may cause voltage differentials between pins to exceed the
absolute maximum ratings of the device, thereby leading to
latch-up or permanent damage. Any decoupling used should be
placed as close to the supply pins as possible.
Series resistance in the analog inputs should be minimized to
avoid any distortion effects, especially at high temperatures. If
possible, equalize the source impedance on each analog input to
minimize offset. Beware of mismatch and thermocouple effects
on the analog input PCB tracks to reduce offset drift.
EVALUATING THE AD7400 PERFORMANCE
A simple standalone AD7400 evaluation board is available with
split ground planes and a board split beneath the AD7400
package to ensure isolation. This board allows access to each
pin on the device for evaluation purposes. External supplies and
all other circuitry (such as a digital filter) must be provided by
the user.
INSULATION LIFETIME
All insulation structures, subjected to sufficient time and/or
voltage, are vulnerable to breakdown. In addition to the testing
performed by the regulatory agencies, Analog Devices has
carried out an extensive set of evaluations to determine the
lifetime of the insulation structure within the AD7400.
These tests subjected populations of devices to continuous
cross-isolation voltages. To accelerate the occurrence of failures,
the selected test voltages were values exceeding those of normal
use. The time-to-failure values of these units were recorded and
used to calculate acceleration factors. These factors were then
used to calculate the time to failure under normal operating
conditions. The values shown in Table 7 are the lesser of the
following two values:
• The value that ensures at least a 50-year lifetime of
continuous use
• The maximum CSA/VDE approved working voltage
It should also be noted that the lifetime of the AD7400 varies
according to the waveform type imposed across the isolation
barrier. The iCoupler insulation structure is stressed differently
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 29, Figure 30, and Figure 31 illustrate the different
isolation voltage waveforms.
0V
RATED PEAK VOLTAGE
04718-029
Figure 29. Bipolar AC Waveform
0V
RATED PEAK VOLTAGE
04718-030
Figure 30. Unipolar AC Waveform
0V
RATED PEAK VOLTAGE
04718-031
Figure 31. DC Waveform
AD7400 Data Sheet
Rev. F | Page 18 of 20
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AA
10.50 (0.4134)
10.10 (0.3976)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75(0.0295)
0.25(0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
C
OPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
16 9
8
1
1.27 (0.0500)
BSC
03-27-2007-B
Figure 32. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD7400YRWZ −40°C to +105°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
AD7400YRWZ-REEL −40°C to +105°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
AD7400YRWZ-REEL7 −40°C to +105°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
EVAL-AD7400EDZ Evaluation Board
EVAL-CED1Z Development Board
1 Z = RoHS Compliant Part.
Data Sheet AD7400
Rev. F | Page 19 of 20
NOTES
AD7400 Data Sheet
Rev. F | Page 20 of 20
NOTES
©2006–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04718-0-3/12(F)