19-5004; Rev 1; 6/10 TION KIT EVALUA BLE AVAILA Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier Features The MAX97000 audio subsystem combines a mono speaker amplifier with a stereo headphone amplifier and an analog DPST switch. The headphone and speaker amplifiers have independent volume control and on/off control. The four inputs are configurable as two differential inputs or four single-ended inputs. S 1.6V to 2.0V Headphone Supply Voltage The entire subsystem is designed for maximum efficiency. The high-efficiency 725mW Class D speaker amplifier operates directly from the battery and consumes no more than 1FA in shutdown mode. The Class H headphone amplifier utilizes a dual-mode charge pump to maximize efficiency while outputting a ground-referenced signal that does not require output coupling capacitors. S 40mW/Channel Headphone Output (RHP = 16I) S 2.7V to 5.5V Speaker Supply Voltage S Internal LDO Allows Single-Supply Operation S 725mW Speaker Output (VPVDD = 3.7V, ZSPK = 8I + 68H) S Low-Emission Class D Amplifier S Efficient Class H Headphone Amplifier S Ground-Referenced Headphone Outputs S Two Stereo Single-Ended/Mono Differential Inputs S Integrated Distortion Limiter (Speaker Outputs) The speaker amplifier incorporates a distortion limiter to automatically reduce the volume level when excessive clipping occurs. This allows high gain for low-level signals without compromising the quality of large signals. S Integrated DPST Analog Switch S No Clicks and Pops S TDMA Noise Free All control is performed using the 2-wire, I2C interface. The MAX97000 operates in the extended -40NC to +85NC temperature range, and is available in the 2mm x 2mm, 25-bump WLP package (0.4mm pitch). S 2mm x 2mm, 25-Bump 0.4mm Pitch WLP Package Ordering Information Applications Cell Phones PART TEMP RANGE PIN-PACKAGE MAX97000EWA+ -40NC to +85NC 25 WLP +Denotes a lead(Pb)-free/RoHS-compliant package. Portable Multimedia Players Simplified Block Diagram 1.8V BATTERY 2.7V TO 5.5V I2C CONTROL POWER SUPPLY MAX97000 STEREO/ MONO INPUT STEREO/ MONO INPUT VOLUME LIMITER VOLUME CLASS D AMPLIFIER CLASS H AMPLIFIER CHARGE PUMP SWITCH ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. MAX97000 General Description MAX97000 Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier TABLE OF CONTENTS General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional Diagram/Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Digital I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I2C Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Class D Speaker Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Ultra-Low EMI Filterless Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Distortion Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Headphone Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DirectDrive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Class H Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2 I2 C Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 I2 C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Distortion Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Charge-Pump Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Early STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Write Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Read Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Filterless Class D Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 RF Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Optional Ferrite Bead Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Input Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Charge-Pump Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Charge-Pump Flying Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Charge-Pump Holding Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Supply Bypassing, Layout, and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 WLP Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3 MAX97000 TABLE OF CONTENTS (CONTINUED) Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier MAX97000 Functional Diagram/Typical Application Circuit OPTIONAL 1.6V TO 2.0V 10F 2.5V TO 5.5V 1F 2.7V TO 5.5V 1F 1F VDD LDOIN B1 B2 10F PVDD C1 LDO INA1 E4 BIAS MUX PGAINA -6dB TO +18dB 0.47F INADIFF OPTIONAL 1F HPVDD LPMODE HPLVOL: -64dB TO +6dB 0.47F INA2 E5 + HPVDD HPRVOL: -64dB TO +6dB INB1 D4 PVDD SPKVOL: -30dB TO +20dB INB2 D5 E1 OUTP CLASS D +12dB MIX PGAINB -6dB TO +18dB A5 HPR HPVSS HPRMIX INBDIFF OPTIONAL 0.47F CLASS H 0/3dB HPREN MIX PGAINB -6dB TO +18dB B5 HPL HPVSS HPLMIX OPTIONAL 0.47F CLASS H 0/3dB HPLEN MIX PGAINA -6dB TO +18dB C5 BIAS D1 OUTN SPKEN SPKMIX PGND + THD LIMITER OPTIONAL THDCLP ANALOG SWITCHES COM1 D2 E2 NC1 COM2 D3 E3 NC2 VDD SWEN SDA B3 SCL B4 SHDN C4 VDD I2C INTERFACE/ SHUTDOWN MAX97000 C3 GND CHARGE PUMP C2 PGND A1 C1P A2 A3 A4 C1N HPVDD HPVSS 1F 1F 4 1F Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier Continuous Current In/Out of COM1, COM2, NC1, NC2....................................................... Q150mA Continuous Input Current (all other pins)......................... Q20mA Duration of OUT_ Short Circuit to GND or PVDD..................................................................Continuous Duration of Short Circuit Between OUTP and OUTN..............................................................Continuous Duration of HP_ Short Circuit to GND or VDD...........Continuous Continuous Power Dissipation (TA = +70NC) Multilayer Board 25 WLP (derate 19.2mW/NC above +70NC).................850mW Junction Temperature......................................................+150NC Operating Temperature Range........................... -40NC to +85NC Storage Temperature Range............................. -65NC to +150NC Soldering Temperature (reflows)......................................+260NC Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VLDOIN = VPVDD = V SHDN = 3.7V, VGND = VPGND = 0V. Input signal applied at INA configured single-ended, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB, speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1FF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER Speaker Amplifier SupplyVoltage Range Headphone Amplifier Supply Voltage Range LDO Input Supply-Voltage Range SYMBOL CONDITIONS MAX UNITS Guaranteed by PSRR test 2.7 5.5 V VDD Guaranteed by PSRR test 1.6 2 V VLDOIN Guaranteed by PSRR test 5.5 V ISHDN Low-power mode, TA = +25NC, LPMODE = 0x01 IPVDD 0.4 HP mode, TA = +25NC, stereo SE input on INA, INB disabled ILDOIN 1.45 2 IPVDD 0.79 1.2 ILDOIN SPK mode, TA = +25NC mono differential input on INB, INA disabled IPVDD 0.42 0.75 1.38 2.2 SPK + HP mode, TA = +25NC stereo ILDOIN SE input on INA, INB disabled IPVDD 1.45 2 1.8 2.7 IPVDD 90 175 1.45 2 0.7 ILDOIN 60 110 TA = +25NC, internal gain, IPVDD + ILDOIN, hardware Turn-On Time tON Time from power-on to full operation including soft-start Input Resistance RIN TA = +25NC, internal gain RF 2.5 ILDOIN TA = +25NC, internal gain, software Feedback Resistance TYP VPVDD Quiescent Supply Current Shutdown Current MIN FA 1 8 Gain = -6dB, -3dB ms 41.2 Gain = 0dB to +9dB 16 20.6 27 Gain = +18dB 5.5 7.2 9.5 19 20 21 TA = +25NC, external gain mA kI kI 5 MAX97000 ABSOLUTE MAXIMUM RATINGS (Voltages with respect to GND.) VDD, HPVDD.........................................................-0.3V to +2.2V PVDD, LDOIN........................................................-0.3V to +6.0V PGND....................................................................-0.1V to +0.1V HPVSS..................................................................-2.2V to + 0.3V C1N...................................... (HPVSS - 0.3V) to (HPVDD + 0.3V) C1P...........................................................- 0.3V to (VDD + 0.3V) HPL, HPR.............................. (HPVSS - 0.3V) to (HPVDD +0.3V) INA1, INA2, INB1, INB2, BIAS..............................-0.3V to +6.0V SDA, SCL, SHDN..................................................-0.3V to +6.0V COM1, COM2, NC1, NC2, OUTP, OUTN.......................................-0.3V to (PVDD + 0.3V) Continuous Current In/Out of PVDD, PGND, OUT_....... Q800mA Continuous Current In/Out of HPR, HPL, VDD, LDOIN............................................................... Q140mA MAX97000 Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier ELECTRICAL CHARACTERISTICS (continued) (VLDOIN = VPVDD = V SHDN = 3.7V, VGND = VPGND = 0V. Input signal applied at INA configured single-ended, preamp gain = 0dB, HPLVOL = HPRVOL= SPKVOL = 0dB, speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1FF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL Maximum Input Signal Swing CONDITIONS MIN 2.3 Preamp = +18dB 0.29 Preamp = external gain Common-Mode Rejection Ratio CMRR Input DC Voltage Bias Voltage TYP Preamp = 0dB f = 1kHz (differential input mode) MAX UNITS VP-P 2.3 x RIN,EX/RF Gain = 0dB 55 Gain = +18dB 32 IN__ inputs dB 1.125 1.2 1.275 V 1.13 1.2 1.27 V TA = +25NC, SPKM = 1 Q0.5 Q4 TA = +25NC, SPKVOL = 0dB, SPKMIX = 0x01, IN_DIFF = 0V Q1.5 VBIAS SPEAKER AMPLIFIER Output Offset Voltage Click-and-Pop Level VOS KCP Peak voltage, TA = +25NC, A-weighted, 32 samples per second, volume at mute (Note 2) Into shutdown PSRR THD+N P 1%, f = 1kHz, ZSPK = 8I + 68FH (Note 3) Output Power Total Harmonic Distortion + Noise TA = +25NC (Note 2) THD+N Signal-to-Noise Ratio SNR Oscillator Frequency fOSC -70 dBV Out of shutdown VPVDD = 2.7V to 5.5V Power-Supply Rejection Ratio -70 50 65 f = 1kHz, VRIPPLR = 200mVP-P 65 f = 20kHz, VRIPPLR = 200mVP-P 59 VPVDD = 4.2V 930 VPVDD = 3.7V 725 VPVDD = 3.3V 562 f = 1kHz, POUT = 360mW, TA = +25NC, ZSPK = 8I + 68FH 0.05 A-weighted, SPKMIX IN_DIFF = 0 = 0x03, referenced to (single-ended) 725mW IN_DIFF = 1 (differential) mW 0.6 93 93 11.5 E % dB kHz kHz Q20 Current Limit 6 dB 250 Gain Output Noise 75 f = 217Hz, VRIPPLR = 200mVP-P Spread-Spectrum Bandwidth Efficiency mV 12 12.5 dB 1.5 A POUT = 725mW, f = 1kHz, ZSPK = 8I + 68FH 87 % A-weighted, (SPKMIX = 0x01), IN_DIFF = 1, SPKVOL = 0dB 50 FVRMS Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier (VLDOIN = VPVDD = V SHDN = 3.7V, VGND = VPGND = 0V. Input signal applied at INA configured single-ended, preamp gain = 0dB, HPLVOL = HPRVOL= SPKVOL = 0dB, speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1FF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 80 83 85 UNITS CHARGE PUMP VHPL = VHPR = 0V Charge-Pump Frequency Positive Output Voltage VHPVDD Negative Output Voltage VHPVSS Headphone Output Voltage Threshold VHPL = VHPR = 0.2V 665 VHPL = VHPR = 0.5V 500 VHPL, VHPR > VTH 1.8 VHPL, VHPR < VTH 0.9 VHPL, VHPR > VTH -1.8 VHPL, VHPR < VTH -0.9 kHz V V VTH1 Output voltage at which the charge pump switches between fast and slow clock 0.1 0.16 0.21 VTH2 Output voltage at which the charge pump switches modes, VOUT rising or falling 0.40 0.46 0.52 Mode Transition Timeouts V Time it takes for the charge pump to transition from invert to split mode 32 ms Time it takes for the charge pump to transition from split to invert mode 20 Fs HEADPHONE AMPLIFIERS Output Offset Voltage Click-and-Pop Level VOS KCP TA = +25NC volume at mute Q0.15 TA = +25NC, HP_VOL = 0dB, HP_MIX = 0x1, IN_DIFF = 0 Q0.5 Peak voltage, TA = +25NC, A-weighted, 32 Into shutdown samples per second, volume at mute Out of shutdown (Note 2) VLDOIN = 2.5V to 5.5V Power-Supply Rejection Ratio Output Power Channel-to-Channel Gain Tracking PSRR POUT TA = +25NC (Note 2) THD+N = 1%, f = 1kHz mV -74 dBV -74 70 85 f = 217Hz, VRIPPLE = 200mVP-P 84 f = 1kHz, VRIPPLE = 200mVP-P 80 f = 20kHz, VRIPPLE = 200mVP-P 62 RHP = 16I 40 RHP = 32I RHP = 32I, LPMODE = 1, LP gain = 3dB 23 TA = +25NC, HPL to HPR, volume at maximum, HPLMIX = 0x01, HPRMIX = 0x02, IN_DIFF = 0 Q0.6 dB mW 34 Q0.3 Q2.5 % 7 MAX97000 ELECTRICAL CHARACTERISTICS (continued) MAX97000 Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier ELECTRICAL CHARACTERISTICS (continued) (VLDOIN = VPVDD = V SHDN = 3.7V, VGND = VPGND = 0V. Input signal applied at INA configured single-ended, preamp gain = 0dB, HPLVOL = HPRVOL= SPKVOL = 0dB, speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1FF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER Total Harmonic Distortion + Noise Signal-to-Noise Ratio SYMBOL THD+N SNR CONDITIONS POUT = 10mW, f = 1kHz MIN TYP RHP = 32I 0.02 RHP = 16I 0.03 A-weighted, RHP = 16I, HPLMIX = 0x01, HPRMIX = 0x02, IN_DIFF = 0 MAX 0.1 UNITS % 100 dB Slew Rate SR 0.35 V/Fs Capacitive Drive CL 200 pF 65 dB Crosstalk HPL to HPR, HPR to HPL, f = 20Hz to 20kHz ANALOG SWITCH INC_ = 20mA, VCOM_ = 0V and PVDD, SWEN = 1 TA = +25NC Total Harmonic Distortion + Noise VDIFCOM_ = 2VP-P, VCMCOM_= PVDD/2, f = 1kHz, SWEN = 1, ZSPK = 8I + 68FH 10I in series with each switch 0.05 No series resistors 0.3 Off-Isolation SWEN = 0, COM1 and COM2 to GND = 50I, f = 10kHz, referred to signal applied to NC1 and NC2 On-Resistance RON 1.6 4 I TA = TMIN to TMAX 5.2 % 105 dB PREAMPLIFIER Gain PGAIN_ = 000 -6.5 -6 -5.5 PGAIN_ = 001 -3.5 -3 -2.5 PGAIN_ = 010 -0.5 0 0.5 PGAIN_ = 011 2.5 3 3.5 PGAIN_ = 100 5.5 6 6.5 PGAIN_ = 101 8.5 9 9.5 PGAIN_ = 110 17.5 18 18.5 dB VOLUME CONTROL Volume Level Mute Attenuation HP_VOL = 0x1F 5.5 6 6.5 HP_VOL = 0x00 -68 -64 -60 SPKVOL = 0x3F 19 20 21 SPKVOL = 0x00 -31 -30 -29 f = 1kHz Zero-Crossing Detection Timeout Speaker 109 Headphone 101 dB dB 100 ms 1 ms LIMITER Attack Time Release Time Constant 8 THDT1 = 0 1.4 THDT1 = 1 2.8 s Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier (VLDOIN = VPVDD = V SHDN = 3.7V, VGND = VPGND = 0V. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS DIGITAL INPUTS (SDA, SCL, SHDN) Input Voltage High VIH Input Voltage Low Input Hysteresis Input Capacitance Input Leakage Current MIN TYP 1.3 0.5 200 CIN UNITS V VIL VHYS IIN MAX V mV 10 pF TA = +25NC Q1.0 VLDOIN = 0, TA = +25NC Q1.0 FA DIGITAL OUTPUTS (SDA Open Drain) Output Low Voltage VOL ISINK = 3mA 0.4 V I2C TIMING CHARACTERISTICS (VLDOIN = VPVDD = V SHDN = 3.7V, VGND = VPGND = 0V. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 400 kHz Serial-Clock Frequency fSCL 0 Bus Free Time Between STOP and START Conditions tBUF 1.3 Fs Hold Time (Repeated) START Condition tHD,STA 0.6 Fs SCL Pulse-Width Low tLOW 1.3 Fs SCL Pulse-Width High tHIGH 0.6 Fs Setup Time for a Repeated START Condition tSU,STA 0.6 Fs Data Hold Time tHD,DAT 0 Data Setup Time 900 ns tSU,DAT 100 SDA and SCL Receiving Rise Time tR (Note 4) 20 + 0.1CB 300 ns SDA and SCL Receiving Fall Time tF (Note 4) 20 + 0.1CB 300 ns SDA Transmitting Fall Time tF (Note 4) 20 + 0.1CB 300 ns 400 pF 50 ns Setup Time for STOP Condition tSU,STO Bus Capacitance CB Pulse Width of Suppressed Spike tSP Note Note Note Note 1: 2: 3: 4: ns 0.6 0 Fs 100% production tested at TA = +25NC. Specifications overtemperature limits are guaranteed by design. Amplifier inputs are AC-coupled to GND. Class D amplifier testing performed with a resistive load in series with an inductor to simulate an actual speaker load. CB is in pF. 9 MAX97000 DIGITAL I/O CHARACTERISTICS MAX97000 Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier SDA tBUF tSU,STA tSU,DAT tLOW tHD,STA tSP tHD,DAT tSU,STO tHIGH SCL tHD,STA tR tF START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 1. I2C Interface Timing Diagram Typical Operating Characteristics (VLDOIN = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = , RHP = . CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1F. TA = +25C, unless otherwise noted.) GENERAL 2.0 1.5 1.0 0.5 INPUTS AC-COUPLED TO GND 4.0 SOFTWARE 3.5 3.0 2.5 2.0 1.5 HARDWARE 1.0 0.5 0 0 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 10 4.5 SHUTDOWN CURRENT (A) SPEAKER ONLY INPUTS AC-COUPLED TO GND INA CONNECTED TO OUTPUT 2.5 SUPPLY CURRENT (mA) MAX97000 toc01 3.0 MAX97000 toc02 SHUTDOWN CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. SUPPLY VOLTAGE 5.0 5.5 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier SPEAKER AMPLIFIER THD+N vs. FREQUENCY 1 1 POUT = 1000mW 0.1 POUT = 200mW 0.01 VPVDD = 3.7V ZSPRK = 8I + 68F THD+N (%) POUT = 500mW 0.1 VPVDD = 3.7V ZSPRK = 4I + 33F THD+N (%) THD+N (%) 1 10 MAX97000 toc04 MAX97000 toc03 VPVDD = 3.7V ZSPRK = 8I + 68F THD+N vs. FREQUENCY 10 MAX97000 toc05 THD+N vs. FREQUENCY 10 0.1 SSM POUT = 200mW 0.01 0.01 FFM 0.001 1 10 0.01 100 0.1 THD+N vs. OUTPUT POWER VPVDD = 5.0V ZSPRK = 8I + 68F 0.01 0.1 fIN = 1kHz 0.1 fIN = 100Hz 10 100 THD+N vs. OUTPUT POWER fIN = 6kHz 1 1 FREQUENCY (kHz) VPVDD = 5.0V ZSPRK = 4I + 33F 10 THD+N (%) THD+N (%) fIN = 1kHz 0.01 0.001 THD+N vs. OUTPUT POWER fIN = 6kHz 0.1 100 100 MAX97000 toc06 100 1 10 FREQUENCY (kHz) FREQUENCY (kHz) 10 1 100 VPVDD = 4.2V ZSPRK = 8I + 68F 10 fIN = 6kHz 1 THD+N (%) 0.1 MAX97000 toc07 0.01 fIN = 1kHz 0.1 0.01 MAX97000 toc08 0.001 fIN = 100Hz 0.01 fIN = 100Hz 0.001 0.5 1.0 1.5 2.0 2.5 0.001 0 0.5 1.0 1.5 POUT (mW) THD+N vs. OUTPUT POWER 3.5 4.0 0 0.2 0.4 VPVDD = 3.7V ZSPRK = 8I + 68F 10 0.01 fIN = 1kHz fIN = 100Hz 0.01 VPVDD = 3.7V ZSPRK = 4I + 33F 10 0.5 1.0 1.5 POUT (mW) 2.0 2.5 3.0 1.6 fIN = 1kHz 0.1 0.01 0.001 0 1.4 1 fIN = 100Hz fIN = 100Hz 0.001 1.2 fIN = 6kHz 1 0.1 1.0 THD+N vs. OUTPUT POWER THD+N (%) THD+N (%) fIN = 1kHz 0.8 100 fIN = 6kHz 1 0.6 POUT (mW) THD+N vs. OUTPUT POWER fIN = 6kHz THD+N (%) 3.0 100 MAX97000 toc09 VPVDD = 4.2V ZSPRK = 4I + 33F 0.1 2.5 POUT (mW) 100 10 2.0 MAX97000 toc10 0 MAX97000 toc11 0.001 0.001 0 0.2 0.4 0.6 0.8 POUT (mW) 1.0 1.2 1.4 0 0.5 1.0 1.5 2.0 2.5 POUT (mW) 11 MAX97000 Typical Operating Characteristics (continued) (VLDOIN = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = , RHP = . CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1F. TA = +25C, unless otherwise noted.) Typical Operating Characteristics (continued) (VLDOIN = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = , RHP = . CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1F. TA = +25C, unless otherwise noted.) 80 60 50 40 50 40 30 20 20 VPVDD = 5.0V fIN = 1kHz 0.5 1.0 1.5 2.0 2.5 2.0 1.5 THD+N = 1% 0.2 0.4 0.6 0.8 1.0 1.2 1.4 2.5 1.6 3.0 3.5 4.0 4.5 5.0 POUT (W) POUT (W) SUPPLY VOLTAGE (V) OUTPUT POWER vs. SUPPLY VOLTAGE OUTPUT POWER vs. LOAD RESISTANCE POWER-SUPPLY REJECTION RATIO vs. FREQUENCY 1.0 THD+N = 1% 0.6 1.4 THD+N = 10% 1.2 1.0 0.8 0.4 0.2 0.2 THD+N = 1% 3.5 4.0 4.5 5.0 10 POWER-SUPPLY REJECTION RATIO vs. SUPPLY VOLTAGE -80 SSM fIN = 1kHz -40 -60 -80 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 100 FFM fIN = 1kHz -20 -40 -60 -80 -100 -120 -120 3.5 10 IN-BAND OUTPUT SPECTRUM -100 -100 1 0 AMPLITUDE (dBV) -20 AMPLITUDE (dBV) -60 3.0 0.1 FREQUENCY (kHz) IN-BAND OUTPUT SPECTRUM -40 2.5 0.01 1000 0 MAX97000 toc18 VRIPPLE = 200mVP-P fIN = 1kHz INPUTS AC-COUPLED GND -20 100 LOAD RESISTANCE (I) SUPPLY VOLTAGE (V) 0 MAX97000 toc17 -100 1 5.5 MAX97000 toc19 3.0 -60 -80 0 2.5 -40 0.6 0.4 0 VPVDD = 3.7V VRIPPLE = 200mVP-P INPUTS AC-COUPLED GND -20 5.5 MAX97000 toc20 THD+N = 10% 1.2 0.8 1.6 PSRR (dB) 1.4 0 MAX97000 toc16 1.6 VPVDD = 3.7V fIN = 1kHz ZSPRK = LOAD + 68F 1.8 OUTPUT POWER (W) fIN = 1kHz ZSPRK = 8I + 68F 1.8 2.0 MAX97000 toc15 2.0 12 THD+N = 10% 0 0 3.0 2.5 0.5 0 0 3.0 1.0 VPVDD = 3.7V fIN = 1kHz 10 0 OUTPUT POWER (W) 60 30 10 ZSPRK = 4I + 33F 70 fIN = 1kHz ZSPRK = 4I + 33F 3.5 OUTPUT POWER (W) ZSPRK = 4I + 33F 70 EFFICIENCY (%) EFFICIENCY (%) 80 ZSPRK = 8I + 68F 90 4.0 MAX97000 toc14 MAX97000 toc12 ZSPRK = 8I + 68F 90 OUTPUT POWER vs. SUPPLY VOLTAGE EFFICIENCY vs. OUTPUT POWER 100 MAX97000 toc13 EFFICIENCY vs. OUTPUT POWER 100 PSRR (dB) MAX97000 Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier 0 5 10 FREQUENCY (kHz) 15 20 0 5 10 FREQUENCY (kHz) 15 20 Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier -40 -60 -80 -20 -30 -40 -50 -60 -70 -80 -100 -90 -100 -120 1 0.1 10 100 1000 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) SPEAKER VOLUME GAIN vs. SPKVOL CODE HARDWARE SHUTDOWN RESPONSE 1000 MAX97000 toc24 MAX97000 toc23 30 20 SPEAKER VOLUME GAIN (dB) RBW = 100Hz SSM -10 OUTPUT AMPLITUDE (dBV) OUTPUT AMPLITUDE (dBV) MAX97000 toc21 RBW = 100Hz FFM -20 0 MAX97000 toc22 WIDEBAND OUTPUT SPECTRUM WIDEBAND OUTPUT SPECTRUM 0 SHDN 2V/div 10 0 -10 SPKR OUTPUT 500mV/div -20 -30 -40 0 10 20 30 40 50 60 1ms/div 70 SPKVOL CODE (NUMERIC) SOFTWARE SHUTDOWN RESPONSE SOFTWARE TURN-ON RESPONSE MAX97000 toc25 400s/div MAX97000 toc26 SDA 2V/div SDA 2V/div SPKR OUTPUT 1V/div SPKR OUTPUT 1V/div 4ms/div 13 MAX97000 Typical Operating Characteristics (continued) (VLDOIN = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = , RHP = . CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1F. TA = +25C, unless otherwise noted.) Typical Operating Characteristics (continued) (VLDOIN = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = , RHP = . CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1F. TA = +25C, unless otherwise noted.) HEADPHONE AMPLIFIER POUT = 30mW 0.1 0.01 10 1 10 POWER DISSIPATION vs. OUTPUT POWER fIN = 6kHz 0.1 0.01 POWER DISSIPATION (mW) fIN = 1kHz fIN = 100Hz 140 120 RLOAD = 16I 100 80 RLOAD = 32I 60 10 20 30 40 50 60 70 30 40 50 60 70 80 OUTPUT POWER (mW) OUTPUT POWER (mW) OUTPUT POWER vs. LOAD RESISTANCE POWER-SUPPLY REJECTION RATIO vs. FREQUENCY CCHARGE_PUMP = 1F 40 30 -20 VRIPPLE = 200mVP-P INPUTS AC-COUPLED GND CCHARGE_PUMP = 0.47F 10 1 100 1000 LOAD RESISTANCE (I) OUTPUT SPECTRUM -40 -60 20 10 THD+N = 1% 0 90 0 RLOAD = 32I fIN = 1kHz -20 -40 AMPLITUDE (dBV) CCHARGE_PUMP = 2.2F 50 PSRR (dB) fIN = 1kHz THD+N = 1% 60 0 MAX97000 toc33 70 THD+N = 10% 30 10 20 60 40 20 10 50 50 20 0 40 fIN = 1kHz 60 40 80 30 70 MAX97000 toc34 0 20 80 0 0.001 10 OUTPUT POWER vs. LOAD RESISTANCE fIN = 1kHz POUT = PHPL + PHPR 160 0 MAX97000 toc31 THD+N vs. OUTPUT POWER 180 100 OUTPUT POWER (mW) FREQUENCY (kHz) 1 THD+N (%) 0.1 FREQUENCY (kHz) RLOAD = 16I fIN = 100Hz 0.001 0.01 100 fIN = 6kHz MAX97000 toc32 1 MAX97000 toc30 10 0.1 OUTPUT POWER (mW) 0.01 fIN = 1kHz 0.1 0.01 0.001 0.001 -60 -80 -100 -120 -80 -140 -100 0 1 10 100 LOAD RESISTANCE (I) 14 1 POUT = 10mW POUT = 5mW RLOAD = 32I MAX97000 toc35 0.01 MAX97000 toc29 1 THD+N (%) POUT = 25mW 10 MAX97000 toc28 RLOAD = 16I THD+N (%) 1 THD+N (%) 10 MAX97000 toc27 RLOAD = 32I 0.1 THD+N vs. OUTPUT POWER THD+N vs. FREQUENCY THD+N vs. FREQUENCY 10 OUTPUT POWER (mW) MAX97000 Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier 1000 -160 0.01 0.1 1 10 FREQUENCY (kHz) 100 0 4 8 12 16 FREQUENCY (kHz) 20 24 Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier -20 -100 RLOAD = 16I -10 -40 -20 CMRR (dB) -80 -60 PREGAIN = +9dB -30 -80 HPL TO HPR -40 -100 HPR TO HPL -50 PREGAIN = +18dB -120 -140 MAX97000 toc38 RLOAD = 32I CROSSTALK (dB) -60 0 MAX97000 toc37 RLOAD = 16I fIN = 1kHz -40 PREGAIN = 0dB -120 -160 4 8 12 16 20 0.1 0.01 24 1 10 100 -60 0.01 FREQUENCY (kHz) FREQUENCY (kHz) HEADPHONE VOLUME GAIN vs. HP_VOL CODE 0.1 1 10 100 FREQUENCY (kHz) HARDWARE SHUTDOWN RESPONSE MAX97000 toc40 10 MAX97000 toc39 0 HEADPHONE VOLUME GAIN (dB) AMPLITUDE (dBV) 0 MAX97000 toc36 0 -20 COMMON-MODE REJECTION RATIO vs. FREQUENCY CROSSTALK vs. FREQUENCY OUTPUT SPECTRUM RIGHT AND LEFT 0 -10 SHDN 2V/div -20 -30 -40 HPL/HPR 500mV/div -50 -60 -70 0 5 10 15 20 25 HP_VOL CODE (NUMERIC) 30 35 1ms/div SOFTWARE TURN-ON RESPONSE SOFTWARE SHUTDOWN RESPONSE MAX97000 toc42 MAX97000 toc41 1ms/div SDA 2V/div SDA 2V/div HPL/HPR 500mV/div HPL/HPR 500mV/div 4ms/div 15 MAX97000 Typical Operating Characteristics (continued) (VLDOIN = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = , RHP = . CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1F. TA = +25C, unless otherwise noted.) Typical Operating Characteristics (continued (VLDOIN = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = , RHP = . CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1F. TA = +25C, unless otherwise noted.) ANALOG SWITCH TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER CLASS H OPERATION MAX97000 toc43 HPVDD 0V RLOAD = 32I EXTERNAL CLASS AB CONNECTED DIRECTLY TO COM1 AND COMR THD+N (%) 1 HPL/HPR 200mV/div HPVSS 0V MAX97000 toc44 10 HPVDD 1V/div 0.1 f = 6kHz f = 100kHz 0.01 HPVSS 1V/div f = 100kHz 0.001 0 10ms/div 5 10 15 20 25 30 OUTPUT POWER (mW) BYPASS SWITCH OFF-ISOLATION ON-RESISTANCE vs. VCOM 2.0 VPVDD = 3.7V VPVDD = 5.0V 1.5 1.0 VPVDD = 3.0V 0.5 -20 -40 -60 -80 -100 -120 0 -140 0 1 2 3 VCOM (V) 16 MAX97000 toc46 VPVDD = 2.7V 2.5 OFF ISOLATION (dB) INC = 20mA 0 MAX97000 toc45 3.0 RON (I) MAX97000 Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier 4 5 6 0.01 0.1 1 FREQUENCY (kHz) 10 100 Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier TOP VIEW (BUMP SIDE DOWN) 1 2 3 4 5 + MAX97000 A C1P C1N HPVDD HPVSS HPR B VDD LDOIN SDA SCL HPL C PVDD PGND GND SHDN BIAS D OUTN COM1 COM2 INB1 INB2 E OUTP NC1 NC2 INA1 INA2 2.0mm x 2.0mm Pin Description BUMP NAME FUNCTION A1 C1P Charge-Pump Flying Capacitor Positive Terminal. Connect a 1FF capacitor between C1P and C1N. A2 C1N Charge-Pump Flying Capacitor Negative Terminal. Connect a 1FF capacitor between C1P and C1N. A3 HPVDD Headphone Amplifier Positive Power Supply. Bypass with a 1FF capacitor to PGND. A4 HPVSS Headphone Amplifier Negative Power Supply. Bypass with a 1FF capacitor to PGND. A5 HPR Headphone Amplifier Right Output B1 VDD LDO Output and Headphone Amplifier Supply. Bypass with a 1FF and a 10FF capacitor to GND. Power VDD or LDOIN. When powering VDD, leave LDOIN unconnected. B2 LDOIN B3 SDA Serial Data Input/Output. Connect a pullup resistor from SDA to the I2C bus supply. B4 SCL Serial-Clock Input. Connect a pullup resistor from SCL to the I2C bus supply. Headphone Amplifier Left Output LDO Input. Generates VDD if no 1.8V power supply is available. Leave unconnected to disable. Do not power VDD when powering LDOIN. B5 HPL C1 PVDD Class D Power Supply. Bypass with a 1FF and a 10FF capacitor to PGND. C2 PGND Class D Power Ground and Charge Pump Ground C3 GND Analog Ground. C4 SHDN BIAS Active-Low Shutdown C5 Common-Mode Bias. Bypass to GND with a 1FF capacitor. 17 MAX97000 Pin Configuration Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier MAX97000 Pin Description (continued) BUMP NAME D1 OUTN Negative Speaker Output FUNCTION D2 COM1 Analog Switch 1 Input D3 COM2 Analog Switch 2 Input D4 INB1 Input B1. Left or negative input. D5 INB2 Input B2. Right or positive input. E1 OUTP Positive Speaker Output E2 NC1 Analog Switch 1 Output E3 NC2 Analog Switch 2 Output E4 INA1 Input A1. Left or negative input. E5 INA2 Input A2. Right or positive input. Detailed Description Internal Linear Regulator The MAX97000 includes an internal regulator (LDOIN) to generate VDD in cases where no 1.8V supply is available. Using the regulator allows single-supply operation directly from a Li+ battery. To enable the internal regulator apply a power supply to LDOIN and do not connect power to VDD. When not using the internal regulator, leave LDOIN unconnected and power VDD from a 1.8V supply. The MAX97000 audio subsystem combines a mono speaker amplifier with a stereo headphone amplifier and an analog DPST switch. The high-efficiency 725mW Class D speaker amplifier operates directly from the battery and consumes no more than 1FA when in shutdown mode. The headphone amplifier utilizes a dual-mode charge pump and a Class H output stage to maximize efficiency while outputting a ground-referenced signal that does not require output coupling capacitors. The headphone and speaker amplifiers have independent volume control and on/off control. The four inputs are configurable as two differential inputs or four singleended inputs. All control is performed using the 2-wire, I2C interface. Signal Path The MAX97000 signal path consists of flexible inputs, signal mixing, volume control, and output amplifiers (Figure 2). The inputs can be configured for singleended or differential signals (Figure 3). The internal preamplifiers feature programmable gain settings using internal resistors and an external gain setting using a trimmed internal feedback resistor. The external option allows any desired gain to be selected. Following preamplification, the input signals are mixed, volume adjusted, and routed to the headphone and speaker amplifiers based on the desired configuration. The speaker amplifier incorporates a distortion limiter to automatically reduce the volume level when excessive clipping occurs. This allows high gain for low-level signals without compromising the quality of large signals. INA2 INA1 INPUT A -6dB TO +18dB MIXER AND MUX INB2 INB1 Figure 2. Signal Path 18 -64dB TO +6dB 0/3dB -64dB TO +6dB 0/3dB -30dB TO +20dB +12dB INPUT B -6dB TO +18dB Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier MAX97000 STEREO SINGLE-ENDED IN_2 (R) R TO MIXER IN_1 (L) L DIFFERENTIAL IN_2 (+) IN_1 (-) TO MIXER Figure 3. Differential and Stereo Single-Ended Input Configurations Mixers The MAX97000 features independent mixers for the left headphone, right headphone, and speaker paths. Each output can select any combination of any inputs. This allows for mixing two audio signals together and routing independent signals to the headphone and speaker amplifiers. If one of the inputs is not selected by either mixer, it is automatically powered down to save power. Class D Speaker Amplifier The MAX97000 Class D speaker amplifier utilizes active emissions limiting and spread-spectrum modulation to minimize the EMI radiated by the amplifier. 19 Ultra-Low EMI Filterless Output Stage Traditional Class D amplifiers require the use of external LC filters or shielding to meet EN55022B electromagnetic-interference (EMI) regulation standards. Maxim's active emissions limiting edge-rate control circuitry and spread-spectrum modulation reduces EMI emissions, while maintaining up to 87% efficiency. Maxim's spreadspectrum modulation mode flattens wideband spectral components, while proprietary techniques ensure that the cycle-to-cycle variation of the switching period does not degrade audio reproduction or efficiency. The MAX97000's spread-spectrum modulator randomly varies the switching frequency by Q20kHz around the center frequency (250kHz). Above 10MHz, the wideband spectrum looks like noise for EMI purposes (see Figure 4). 40 AMPLITUDE (dBV/m) 30 20 10 0 -10 30 60 80 100 120 140 160 180 200 220 240 260 280 300 850 900 950 1000 FREQUENCY (MHz) 40 30 AMPLITUDE (dBV/m) MAX97000 Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier 20 10 0 -10 300 350 400 450 500 550 600 650 700 FREQUENCY (MHz) Figure 4. EMI with 15cm of Speaker Cable 20 750 800 Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier Figure 5 shows the typical output vs. input curves with and without the distortion limiter. The dotted line shows the maximum gain for a given distortion limit without the distortion limiter. The solid line shows how, with the distortion limiter enabled, the gain can be increased without exceeding the set distortion limit. When the limiter is enabled, selecting a high gain level results in peak signals being attenuated while low signals are left unchanged. This increases the perceived loudness without the harshness of a clipped waveform. Headphone Amplifier DirectDrive Traditional single-supply headphone amplifiers have outputs biased at a nominal DC voltage (typically half the supply). Large coupling capacitors are needed to block this DC bias from the headphone. Without these capacitors, a significant amount of DC current flows to the headphone, resulting in unnecessary power dissipation and possible damage to both headphone and headphone amplifier. Maxim's DirectDrive(R) architecture uses a charge pump to create an internal negative supply voltage. This allows the headphone outputs of the MAX97000 to be biased at GND while operating from a single supply (Figure 6). Without a DC component, there is no need for the large DC-blocking capacitors. Instead of two large (220FF, typ) capacitors, the MAX97000 charge pump requires three small ceramic capacitors, Analog Switch The MAX97000 integrates a DPST analog audio switch. This switch can be used to disconnect an independent audio signal, or drive the 8I speaker by connecting NC1 and NC2 to OUTN and OUTP, respectively. Unlike discrete solutions, the switch design reduces coupling of Class D switching noise to the COM_ inputs. This eliminates the need for a costly T-switch. Drive COM1 and COM2 with a low-impedance source to minimize noise on the pins. In applications that do not require the analog switch, leave COM1, COM2, NC1, and NC2 unconnected. VDD VDD / 2 GND CONVENTIONAL AMPLIFIER BIASING SCHEME +VDD VOUT MAXIMUM THD+N LEVEL SGND -VDD VIN DirectDrive AMPLIFIER BIASING SCHEME Figure 5. Limiter Gain Curve Figure 6. Traditional Amplifier Output vs. MAX97000 DirectDrive Output DirectDrive is a registered trademark of Maxim Integrated Products, Inc. 21 MAX97000 Distortion Limiter The MAX97000 speaker amplifiers integrate a limiter to provide speaker protection and audio compression. When enabled, the limiter monitors the audio signal at the output of the Class D speaker amplifier and decreases the gain if the distortion exceeds the predefined threshold. The limiter automatically tracks the battery voltage to reduce the gain as the battery voltage drops. MAX97000 Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier conserving board space, reducing cost, and improving the frequency response of the headphone amplifier. See the Output Power vs. Load Resistance graph in the Typical Operating Characteristics for details of the possible capacitor sizes. There is a low DC voltage on the amplifier outputs due to amplifier offset. However, the offset of the MAX97000 is typically Q0.15mV, which, when combined with a 32I load, results in less than 5FA of DC current flow to the headphones. In addition to the cost and size disadvantages of the DC-blocking capacitors required by conventional headphone amplifiers, these capacitors limit the amplifier's low-frequency response and can distort the audio signal. Previous attempts at eliminating the output-coupling capacitors involved biasing the headphone return (sleeve) to the DC bias voltage of the headphone amplifiers. This method raises some issues: * * * The sleeve is typically grounded to the chassis. Using the midrail biasing approach, the sleeve must be isolated from system ground, complicating product design. During an ESD strike, the amplifier's ESD structures are the only path to system ground. Thus, the amplifier must be able to withstand the full energy from an ESD strike. When using the headphone jack as a line out to other equipment, the bias voltage on the sleeve may conflict with the ground potential from other equipment, resulting in possible damage to the amplifiers. Charge Pump The MAX97000's dual-mode charge pump generates both the positive and negative power supply for the headphone amplifier. To maximize efficiency, both the charge pump's switching frequency and output voltage change based on signal level. When the input signal level is less than 10% of VDD, the switching frequency is reduced to a low rate. This minimizes switching losses in the charge pump. When the input signal exceeds 10% of VDD, the switching frequency increases to support the load current. For input signals below 25% of VDD, the charge pump generates Q(VDD/2) to minimize the voltage drop across the amplifier's power stage and thus improve efficiency. Input signals that exceed 25% of VDD cause the charge pump to output QVDD. The higher output voltage allows for full output power from the headphone amplifier. To prevent audible gliches when transitioning from the Q(VDD/2) output mode to the QVDD output mode, the charge pump transitions very quickly. This quick change draws significant current from VDD for the duration of the transition. The bypass capacitor on VDD supplies the required current and prevents droop on VDD. The charge pump's dynamic switching mode can be turned off through the I2C interface. The charge pump can then be forced to output either Q(VDD/2) or QVDD regardless of input signal level. Class H Operation A Class H amplifier uses a Class AB output stage with power supplies that are modulated by the output signal. In the case of the MAX97000, two nominal power-supply differentials of 1.8V (+0.9V to -0.9V) and 3.6V (+1.8V to -1.8V) are available from the charge pump. Figure 7 shows the operation of the output-voltage-dependent power supply. Low-Power Mode To minimize power consumption when using the headphone amplifier, enable the low-power mode. In this mode, the headphone mixers and volume control are bypassed and shut down. I2C Slave Address The MAX97000 uses a slave address of 0x9A or 1001101RW. The address is defined as the 7 most significant bits (MSBs) followed by the read/write bit. Set the read/write bit to 1 to configure the MAX97000 to read mode. Set the read/write bit to 0 to configure the MAX97000 to write mode. The address is the first byte of information sent to the MAX97000 after the START (S) condition. 1.8V 0.9V HPVDD VTH_H OUTPUT VOLTAGE VTH_L -0.9V HPVSS -1.8V Figure 7. Class H Operation 22 32ms 32ms Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier Write zeros to all unused bits in the register table when updating the register, unless otherwise noted. Tables 2 through 7 describe each bit. Table 1. Register Map REGISTER B7 B6 INADIFF INBDIFF B5 B4 B3 B2 B1 B0 ADDRESS DEFAULT R/W 0x00 0x00 R/W HPRMIX 0x01 0x00 R/W SPKMIX 0x02 0x00 R/W STATUS Input Gain Headphone Mixers PGAINA PGAINB HPLMIX Speaker Mixer 0 0 0 Headphone Left ZCD SLEW HPLM HPLVOL 0x03 0x00 R/W Headphone Right LPGAIN 0 HPRM HPRVOL 0x04 0x00 R/W Speaker FFM SPKM Reserved 0 0 Limiter 0 0x05 0x00 R/W 0 SPKVOL 0 0 0 0x06 0x00 R/W 0 0 0 THDT1 0x07 0x00 R/W SPKEN 0 HPLEN HPREN SWEN 0x08 0x01 R/W 0 0 0 CPSEL FIXED 0x09 0x00 R/W 0xFF 0x00 R 0 0 THDCLP Power Management SHDN Charge Pump 0 LPMODE 0 0 REVISION ID Rev ID REV Table 2. Input Register REGISTER BIT 7 6 0x00 NAME INADIFF INBDIFF Input B Differential Mode. Configures the input B channel as either a mono differential signal (INB = INB2 - INB1) or as a stereo signal (INB1 = left, INB2 = right). 0 = Stereo single-ended 1 = Differential Input A Preamp Gain. Set the input gain to maximize output signal level for a given input signal range to improve the SNR of the system. PGAINA = 111 switches to a trimmed 20kI feedback resistor for external gain setting. 5 4 3 DESCRIPTION Input A Differential Mode. Configures the input A channel as either a mono differential signal (INA = INA2 - INA1) or as a stereo signal (INA1 = left, INA2 = right). 0 = Stereo single-ended 1 = Differential PGAINA VALUE 000 001 010 011 100 101 110 111 LEVEL (dB) -6 -3 0 3 6 9 18 External 23 MAX97000 I2C Registers Nine internal registers program the MAX97000. Table 1 lists all the registers, their addresses, and power-onreset states. Register 0xFF indicates the device revision. MAX97000 Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier Table 2. Input Register (continued) REGISTER BIT NAME 2 1 DESCRIPTION Input B Preamp Gain. Set the input gain to maximize output signal level for a given input signal range to improve the SNR of the system. PGAINB = 111 switches to a trimmed 20kI feedback resistor for external gain setting. PGAINB 0 VALUE LEVEL (dB) 000 -6 001 -3 010 0 011 3 100 6 101 9 110 18 111 External Mixers Table 3. Mixer Registers REGISTER BIT NAME 7 Left Headphone Mixer. Selects which of the four inputs is routed to the left headphone output. 6 HPLMIX 5 4 0x01 3 HPRMIX 1 0 3 SPKMIX 0 24 INPUT No input INA1 (Disabled when INADIFF = 1) INA2 (Select when INADIFF = 1) INB1 (Disabled when INBDIFF = 1) INB2 (Select when INBDIFF = 1) VALUE 0000 xxx1 xx1x x1xx 1xxx INPUT No input INA1 (Disabled when INADIFF = 1) INA2 (Select when INADIFF = 1) INB1 (Disabled when INBDIFF = 1) INB2 (Select when INBDIFF = 1) Speaker Mixer. Selects which of the four inputs is routed to the speaker output. 2 1 VALUE 0000 xxx1 xx1x x1xx 1xxx Right Headphone Mixer. Selects which of the four inputs is routed to the right headphone output. 2 0x02 DESCRIPTION VALUE 0000 xxx1 xx1x x1xx 1xxx INPUT No input INA1 (Disabled when INADIFF = 1) INA2 (Select when INADIFF = 1) INB1 (Disabled when INBDIFF = 1) INB2 (Select when INBDIFF = 1) Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier Table 4. Volume Control Registers REGISTER 0x03 BIT NAME 7 ZCD 6 SLEW 5 HPLM 4 2 HPLVOL 0 Left Headphone Mute 0 = Unmuted 1 = Muted Left Headphone Volume 3 1 DESCRIPTION Zero-Crossing Detection. Determines whether zero-crossing detection is used on all volume control changes to reduce clicks and pops. Disabling zero-crossing detection allows volume changes to occur immediately. 0 = Enabled 1 = Disabled Volume Slewing. Determines whether volume slewing is used on all volume control changes to reduce clicks and pops. When enabled, volume changes cause the MAX97000 to ramp through intermediate volume settings whenever a change to the volume is made. If ZCD = 1, slewing occurs at a rate of 0.2ms per step. If ZCD = 0, slew time depends on the input signal. Write a 1 to this bit to disable slewing and implement volume changes immediately. This bit also activates soft-start at power-on and soft-stop and power-off. 0 = Enabled 1 = Disabled VALUE 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F LEVEL (dB) -64 -60 -56 -52 -48 -44 -40 -37 -34 -31 -28 -25 -22 -19 -16 -14 VALUE 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F LEVEL (dB) -12 -10 -8 -6 -4 -2 -1 0 1 2 3 4 4.5 5 5.5 6 25 MAX97000 Volume Control MAX97000 Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier Table 4. Volume Control Registers (continued) REGISTER BIT NAME 7 LPGAIN 5 HPRM 4 0x04 2 HPRVOL 1 0 7 FFM 6 SPKM 4 0x05 3 SPKVOL 0 26 VALUE LEVEL (dB) VALUE LEVEL (dB) 0x00 -64 0x10 -12 0x01 -60 0x11 -10 0x02 -56 0x12 -8 0x03 -52 0x13 -6 0x04 -48 0x14 -4 0x05 -44 0x15 -2 0x06 -40 0x16 -1 0x07 -37 0x17 0 0x08 -34 0x18 1 0x09 -31 0x19 2 0x0A -28 0x1A 3 0x0B -25 0x1B 4 0x0C -22 0x1C 4.5 0x0D -19 0x1D 5 0x0E -16 0x1E 5.5 0x0F -14 0x1F 6 Fixed-Frequency Oscillation. Removes spread spectrum from the class D oscillator. 0 = Spread-spectrum mode 1 = Fixed-frequency mode Speaker Mute 0 = Unmuted 1 = Mute Speaker Volume 5 1 Right Headphone Mute 0 = Unmuted 1 = Muted Right Headphone Volume 3 2 DESCRIPTION Low-Power Mode Gain. Controls the headphone amplifier gain when LPMODE 0. 0 = 0dB 1 = 3dB VALUE 0x00-0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 LEVEL (dB) -30 -26 -22 -18 -14 -12 -10 -8 -6 -4 -2 0 1 2 VALUE 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 LEVEL (dB) 3 4 5 6 7 8 9 10 11 12 12.5 13 13.5 14 VALUE 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F LEVEL (dB) 14.5 15 15.5 16 16.5 17 17.5 18 18.5 19 19.5 20 Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier Table 5. Distortion Limiter Register REGISTER BIT NAME 7 Distortion Limit 6 THDCLP 0x07 5 4 0 DESCRIPTION THDT1 VALUE 0000 0001-1001 1010 1011 1100 1101 1110 1111 THD LIMIT (%) Disabled P4 P5 P6 P8 P 11 P 12 P 15 Distortion Release Time Constant 0 = 1.4s 1 = 2.8s Power Management Table 6. Power Management Register REGISTER BIT NAME 7 SHDN DESCRIPTION Software Shutdown 0 = Device disabled 1 = Device enabled Low-Power Headphone Mode. Enables low-power headphone mode. When activated this mode directly connects the selected channel to the headphone amplifiers, bypassing the mixers and the volume control. Additionally, low-power mode disables the speaker path. 6 LPMODE 5 0x08 VALUE 00 01 10 11 INPUT Disabled INA (SE) Connected to the headphone output INB (SE) Connected to the headphone output INA (Diff) to HPL and INB (Diff) to HPR 4 SPKEN Speaker Amplifier Enable 0 = Disabled 1 = Enabled 2 HPLEN Left Headphone Amplifier Enable 0 = Disabled 1 = Enabled 1 HPREN Right Headphone Amplifier Enable 0 = Disabled 1 = Enabled 0 SWEN Analog Switch 0 = Open 1 = Closed 27 MAX97000 Distortion Limiter MAX97000 Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier Charge-Pump Control Table 7. Charge-Pump Control Register REGISTER BIT 1 NAME CPSEL Charge-Pump Output Select. Works with the FIXED to set Q1.8V or Q0.9V outputs on HPVDD and HPVSS. Ignored when FIXED = 0. 0 = Q1.8V on HPVDD/HPVSS 1 = Q0.9V on HPVDD/HPVSS FIXED Class H Mode. When enabled, this bit forces the charge pump to generate static power rails for HPVDD and HPVSS, instead of dynamically adjusting them based on output signal level. 0 = Class H mode 1 = Fixed-supply mode 0x09 0 DESCRIPTION I2C Serial Interface The MAX97000 features an I2C/SMBusK-compatible, 2-wire serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the MAX97000 and the master at clock rates up to 400kHz. Figure 1 shows the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. The master device writes data to the MAX97000 by transmitting the proper slave address followed by the register address and then the data word. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted to the MAX97000 is 8 bits long and is followed by an acknowledge clock pulse. A master reading data from the MAX97000 transmits the proper slave address followed by a series of nine SCL pulses. The MAX97000 transmits data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence is framed by a START or REPEATED START condition, a not acknowledge, and a STOP condition. SDA operates as both an input and an open-drain output. A pullup resistor, typically greater than 500I, is required on SDA. SCL operates only as an input. A pullup resistor, typically greater than 500I, is required on SCL if there are multiple masters on the bus, or if the single master has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the MAX97000 from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). S Sr SCL SDA Figure 8. START, STOP, and REPEATED START Conditions START and STOP Conditions SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 8). A START condition from the master signals the beginning of a transmission to the MAX97000. The master terminates transmission and frees the bus by issuing a STOP condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition. Early STOP Conditions The MAX97000 recognizes a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition. Slave Address The slave address is defined as the seven most significant bits (MSBs) followed by the read/write bit. For the MAX97000 the seven most significant bits are 1001101. Setting the read/write bit to 1 (slave address = 0x9B) configures the MAX97000 for read mode. Setting the read/write bit to 0 (slave address = 0x9A) configures the MAX97000 for write mode. The address is the first byte of information sent to the MAX97000 after the START condition. SMBus is a trademark of Intel Corp. 28 P Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier acknowledge is sent by the master after each read byte to allow data transfer to continue. A not-acknowledge is sent when the master reads the final byte of data from the MAX97000, followed by a STOP condition. Write Data Format A write to the MAX97000 includes transmission of a START condition, the slave address with the R//W bit set to 0, 1 byte of data to configure the internal register address pointer, 1 or more bytes of data, and a STOP condition. Figure 10 illustrates the proper frame format for writing 1 byte of data to the MAX97000. Figure 11 illustrates the frame format for writing n-bytes of data to the MAX97000. CLOCK PULSE FOR ACKNOWLEDGMENT START CONDITION SCL 28 1 9 NOT ACKNOWLEDGE SDA ACKNOWLEDGE Figure 9. Acknowledge ACKNOWLEDGE FROM MAX97000 B7 ACKNOWLEDGE FROM MAX97000 SLAVE ADDRESS S 0 B6 B5 B4 B3 B2 B1 B0 ACKNOWLEDGE FROM MAX97000 A REGISTER ADDRESS A A DATA BYTE R/W P 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 10. Writing 1 Byte of Data to the MAX97000 ACKNOWLEDGE FROM MAX97000 ACKNOWLEDGE FROM MAX97000 S SLAVE ADDRESS ACKNOWLEDGE FROM MAX97000 0 A REGISTER ADDRESS R/W ACKNOWLEDGE FROM MAX97000 B7 B6 B5 B4 B3 B2 B1 B0 A DATA BYTE 1 B7 B6 B5 B4 B3 B2 B1 B0 A 1 BYTE DATA BYTE n A P 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 11. Writing n-Bytes of Data to the MAX97000 29 MAX97000 Acknowledge The acknowledge bit (ACK) is a clocked 9th bit that the MAX97000 uses to handshake receipt each byte of data when in write mode (Figure 9). The MAX97000 pulls down SDA during the entire master-generated 9th clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master will retry communication. The master pulls down SDA during the 9th clock cycle to acknowledge receipt of data when the MAX97000 is in read mode. An MAX97000 Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier The slave address with the R/W bit set to 0 indicates that the master intends to write data to the MAX97000. The MAX97000 acknowledges receipt of the address byte during the master-generated 9th SCL pulse. The first byte transmitted from the MAX97000 are the contents of register 0x00. Transmitted data is valid on the rising edge of SCL. The address pointer autoincrements after each read data byte. This autoincrement feature allows all registers to be read sequentially within one continuous frame. A STOP condition can be issued after any number of read data bytes. If a STOP condition is issued followed by another read operation, the first data byte to be read is from register 0x00. The second byte transmitted from the master configures the MAX97000's internal register address pointer. The pointer tells the MAX97000 where to write the next byte of data. An acknowledge pulse is sent by the MAX97000 upon receipt of the address pointer data. The address pointer can be preset to a specific register before a read command is issued. The master presets the address pointer by first sending the MAX97000's slave address with the R/W bit set to 0 followed by the register address. A REPEATED START condition is then sent followed by the slave address with the R/W bit set to 1. The MAX97000 then transmits the contents of the specified register. The address pointer autoincrements after transmitting the first byte. The third byte sent to the MAX97000 contains the data that is written to the chosen register. An acknowledge pulse from the MAX97000 signals receipt of the data byte. The address pointer autoincrements to the next register address after each received data byte. This autoincrement feature allows a master to write to sequential registers within one continuous frame. The master signals the end of transmission by issuing a STOP condition. Register addresses greater than 0x09 are reserved. Do not write to these addresses. The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all correctly received bytes except the last byte. The final byte must be followed by a not acknowledge from the master and then a STOP condition. Figure 12 illustrates the frame format for reading 1 byte from the MAX97000. Figure 13 illustrates the frame format for reading multiple bytes from the MAX97000. Read Data Format Send the slave address with the R/W bit set to 1 to initiate a read operation. The MAX97000 acknowledges receipt of its slave address by pulling SDA low during the 9th SCL clock pulse. A START command followed by a read command resets the address pointer to register 0x00. S ACKNOWLEDGE FROM MAX97000 ACKNOWLEDGE FROM MAX97000 SLAVE ADDRESS REGISTER ADDRESS 0 R/W NOT ACKNOWLEDGE FROM MASTER ACKNOWLEDGE FROM MAX97000 A Sr SLAVE ADDRESS REPEATED START 1 R/W A DATA BYTE A P 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 12. Reading 1 Byte of Data from the MAX97000 ACKNOWLEDGE FROM MAX97000 S SLAVE ADDRESS 0 R/W ACKNOWLEDGE FROM MAX97000 REGISTER ADDRESS ACKNOWLEDGE FROM MAX97000 A REPEATED START Sr SLAVE ADDRESS 1 R/W A DATA BYTE A P 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 13. Reading n-Bytes of Data from the MAX97000 30 Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier Filterless Class D Operation Traditional Class D amplifiers require an output filter to recover the audio signal from the amplifier's output. The filters add cost, increase the solution size of the amplifier, and can decrease efficiency and THD+N performance. The traditional PWM scheme uses large differential output swings (2 x VDD peak-to-peak) and causes large ripple currents. Any parasitic resistance in the filter components results in a loss of power, lowering the efficiency. The MAX97000 does not require an output filter. The device relies on the inherent inductance of the speaker coil and the natural filtering of both the speaker and the human ear to recover the audio component of the square-wave output. Eliminating the output filter results in a smaller, less costly, more efficient solution. Because the frequency of the MAX97000 output is well beyond the bandwidth of most speakers, voice coil movement due to the square-wave frequency is very small. Although this movement is small, a speaker not designed to handle the additional power can be damaged. For optimum results, use a speaker with a series inductance > 10FH. Typical 8I speakers exhibit series inductances in the 20FH to 100FH range. RF Susceptibility GSM radios transmit using time-division multiple access (TDMA) with 217Hz intervals. The result is an RF signal with strong amplitude modulation at 217Hz and its harmonics that is easily demodulated by audio amplifiers. The MAX97000 is designed specifically to reject RF signals; however, PCB layout has a large impact on the susceptibility of the end product. In RF applications, improvements to both layout and component selection decrease the MAX97000's susceptibility to RF noise and prevent RF signals from being demodulated into audible noise. Trace lengths should be kept below 1/4 of the wavelength of the RF frequency of interest. Minimizing the trace lengths prevents them from functioning as antennas and coupling RF signals into the MAX97000. The wavelength (l) in meters is given by: l = c/f where c = 3 x 108 m/s, and f = the RF frequency of interest. Route audio signals on middle layers of the PCB to allow ground planes above and below shield them from RF interference. Ideally the top and bottom layers of the PCB should primarily be ground planes to create effective shielding. Additional RF immunity can also be obtained from relying on the self-resonant frequency of capacitors as it exhibits the frequency response similar to a notch filter. Depending on the manufacturer, 10pF to 20pF capacitors typically exhibit self-resonance at RF frequencies. These capacitors when placed at the input pins can effectively shunt the RF noise at the inputs of the MAX97000. For these capacitors to be effective, they must have a low-impedance, low-inductance path to the ground plane. Do not use microvias to connect to the ground plane as these vias do not conduct well at RF frequencies. Component Selection Optional Ferrite Bead Filter Additional EMI suppression can be achieved using a filter constructed from a ferrite bead and a capacitor to ground (Figure 14). Use a ferrite bead with low DC resistance, high-frequency (> 600MHz) impedance between 100I and 600I, and rated for at least 1A. The capacitor value varies based on the ferrite bead chosen and the actual speaker lead length. Select a capacitor less than 1nF based on EMI performance. Input Capacitor An input capacitor, CIN, in conjunction with the input impedance of the MAX97000 line inputs forms a highpass filter that removes the DC bias from an incoming analog signal. The AC-coupling capacitor allows the amplifier to automatically bias the signal to an optimum DC level. Assuming zero-source impedance, the -3dB point of the highpass filter is given by: f-3dB = 1 2RINCIN Choose CIN such that f-3dB is well below the lowest frequency of interest. For best audio quality, use capacitors whose dielectrics have low-voltage coefficients, such as tantalum or aluminum electrolytic. Capacitors with highvoltage coefficients, such as ceramics, may result in increased distortion at low frequencies. OUTP MAX97000 OUTN Figure 14. Optional Class D Ferrite Bead Filter 31 MAX97000 Applications Information MAX97000 Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier Charge-Pump Capacitor Selection Use capacitors with an ESR less than 100mI for optimum performance. Low-ESR ceramic capacitors minimize the output resistance of the charge pump. Most surfacemount ceramic capacitors satisfy the ESR requirement. For best performance over the extended temperature range, select capacitors with an X7R dielectric. Charge-Pump Flying Capacitor The value of the flying capacitor (connected between C1N and C1P) affects the output resistance of the charge pump. A value that is too small degrades the device's ability to provide sufficient current drive, which leads to a loss of output voltage. Increasing the value of the flying capacitor reduces the charge-pump output resistance to an extent. Above 1FF, the on-resistance of the internal switches and the ESR of external chargepump capacitors dominate. Charge-Pump Holding Capacitor The holding capacitor (bypassing HPVDD and HPVSS) value and ESR directly affect the ripple on the supply. Increasing the capacitor's value reduces output ripple. Likewise, decreasing the ESR reduces both ripple and output resistance. Lower capacitance values can be used in systems with low maximum output power levels. See the Output Power vs. Load Resistance graph in the Typical Operating Characteristics section for more information. Supply Bypassing, Layout, and Grounding Proper layout and grounding are essential for optimum performance. Use a large continuous ground plane on a dedicated layer of the PCB to minimize loop areas. Connect GND and PGND directly to the ground plane using the shortest trace length possible. Proper grounding improves audio performance, minimizes crosstalk between channels, and prevents any digital noise from coupling into the analog audio signals. Place the capacitor between C1P and C1N as close as possible to the MAX97000 to minimize trace length from C1P to C1N. Inductance and resistance added between C1P and C1N reduce the output power of the headphone amplifier. Bypass HPVDD and HPVSS with capacitors located close to the pins with a short trace length to PGND. Close decoupling of HPVDD and HPVSS minimizes supply ripple and maximizes output power from the headphone amplifier. 32 Bypass PVDD to PGND with as little trace length as possible. Connect OUTP and OUTN to the speaker using the shortest and widest traces possible. Reducing trace length minimizes radiated EMI. Route OUTP/OUTN as a differential pair on the PCB to minimize the loop area and thereby the inductance of the circuit. If filter components are used on the speaker outputs, be sure to locate them as close to the MAX97000 as possible to ensure maximum effectiveness. Minimize the trace length from any ground tied passive components to PGND to further minimize radiated EMI. An evaluation kit (EV kit) is available to provide an example layout for the MAX97000. The EV kit allows quick setup of the MAX97000 and includes easy-to-use software allowing all internal registers to be controlled. WLP Applications Information For the latest application details on WLP construction, dimensions, tape carrier information, PCB techniques, bump-pad layout, and recommended reflow temperature profile, as well as the latest information on reliability testing results, refer to the Application Note: UCSP - A Wafer-Level Chip-Scale Package on Maxim's website at www.maxim-ic.com/ucsp. See Figure 15 for the recommended PCB footprint for the MAX97000. 0.24mm 0.21mm Figure 15. Recommended PCB Footprint Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 25 WLP W252F2+1 21-0453 33 MAX97000 Package Information Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier MAX97000 Revision History REVISION NUMBER REVISION_ DATE 0 11/09 Initial release 1 6/10 Updated to show the device allows VDD to be externally supplied DESCRIPTION PAGES_ CHANGED -- 1, 4, 5, 18 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 34 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.