1. General description
The PCA9574 is a CMOS device that provides 8 bits of General Purpose parallel
Input/Output (GPIO) expansion in low voltage processor and handheld battery powered
mobile applications and was developed to enhance the NXP family of I2C-bus I/O
expanders. The improvements include lower supply current, lower operating voltage of
1.1 V to 3.6 V, dual and separate supply rails to allow voltage level translation anywhere
between 1.1 V and 3.6 V, 400 kHz clock frequency, and smaller packaging. Any of the
eight I/O ports can be configured as an input or output independent of each other and
default on star t-up to input s. I/O exp ander s provide a simple solution when additional I/Os
are needed while keep ing interconne ctions to a minimum; for example in batte ry powered
mobile applications and clamshell devices for interfacing to sensors, push buttons,
keypad, etc. In addition to providing a flexible set of GPIOs, it simplifies interconnection of
a processor running at one voltage level to I/O devices operating at a different (usually
higher) volt age level. PCA9574 h as built-in level shif ting feat ure that makes these de vices
extremely flexible in mixed signal environments where communication between
incompatible I/Os is required. The core of PCA9574 can operate at a voltage as low as
1.1 V while the I/O bank ca n op er a te in th e ra ng e 1.1 V to 3.6 V. Bus-hold with
programmable on-chip pull-up or pull-down feature for I/Os is also provided.
The system master can enable the I/Os as either inputs or outputs by writing to the I/O
configuration register bits. The data for each input or output is kept in the corresponding
Input or Output register. The polarity of the read register can be inverted with the Polarity
inversion regis te r (ac tive H IGH or active LOW oper a tion ) . Eithe r a bus- ho ld fu nction or
pull-up/pull-down feature can be selected by programming corresponding registers. The
bus-hold provides a valid logic level when the I/O bus is not actively driven. When
bus-hold feature is not selected, the I/O ports can be configured to have pull-up or
pull-down by programming the pull-up/pull-down configuration register.
An open-drain interrupt output pin (INT) allows monitoring of the input pins and is asserted
each time a change occurs on an input port unless that port is masked
(default = masked). A ‘GPIO All Call’ command allows programming multiple PCA9574s
at the same time even if they have different individual I2C-bus addresses. This allows
optimal code programming when more than one device needs to be programm ed with the
same instruction or if all output s need to be turned on or of f at the same time. The internal
Power-On Reset (POR) or hardware reset pin (RESET) initializes the eight I/Os as inputs,
sets the registers to their default values and initializes the device state machine. The I/O
bank is held in its default state when the logic supply (VDD) is off.
One address select pin allows up to two PCA9574 devices to be connected with two
different addresses on the same I2C-bus.
PCA9574
8-bit I2C-bus and SMBus, level translating, low voltage GPIO
with reset and interrupt
Rev. 4 — 25 April 2012 Product data sheet
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Product data sheet Rev. 4 — 25 April 2012 2 of 33
NXP Semiconductors PCA9574
8-bit I2C-bus and SMBus, level translating, low volage GPIO
The PCA9574 is available in TSSOP16, HVQFN16 and XQFN16 packages and is
specified over the 40 °C to +85 °C industrial temperature range.
2. Features and benefits
400 kHz I2C-bus serial interface
Compliant with I2C-bus Standard-mode (100 kHz)
Separate supply rails for core logic and I/O bank provides voltage level shifting
1.1 V to 3.6 V operation with level shifting feature
Very low standby current: < 1 μA
8 configurable I/O pins that default to inputs at power-up
Outputs:
Totem pole: 1 mA source and 3 mA sink
Independently programmable 100 kΩ pull-up or pull-down for each I/O pin
Open-drain active LOW interrupt (INT) output pin allows moni toring of logic level
change of pins programmed as inputs
Inputs:
Programmable bus hold provides valid logic level when inputs are not actively
driven
Programmable Interrupt M ask Control fo r inpu t pins that do not require an interrupt
when their states change or to prevent spurious interrupts default to mask at
power-up
Polarity inversion register allows inversion of the polarity of the I/O pins when read
Active LOW reset (RESET) input pin resets device to power-up default state
GPIO All Call address allows programming of more than one device at the same time
with the same parameters
2 programmable slave addresses using 1 address pin
40 °C to +85 °C operation
ESD protection exceeds 7000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: TSSOP16, HVQFN16 and XQFN16
3. Applications
Cell phones
Media players
Multi voltage environments
Battery operated mobile gadgets
Motherboards
Servers
RAID systems
Industrial control
Medical equipment
PLCs
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Product data sheet Rev. 4 — 25 April 2012 3 of 33
NXP Semiconductors PCA9574
8-bit I2C-bus and SMBus, level translating, low volage GPIO
Gaming machines
Instrumentation and test measurement
4. Ordering information
4.1 Ordering options
5. Block diagram
Table 1. Ordering information
Type number Package
Name Description Version
PCA9574PW TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
PCA9574BS HVQFN16 plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 3 ×3×0.85 mm SOT758-1
PCA9574HK XQFN16 plastic, extremely thin quad flat package; no leads;
16 terminals; body 1.80 ×2.60 ×0.50 mm SOT1161-1
Table 2. Ordering options
Type number Topside mark Temperature range
PCA9574PW PCA9574 Tamb = 40 °C to +85 °C
PCA9574BS P74 Tamb = 40 °C to +85 °C
PCA9574HK 74 Tamb = 40 °C to +85 °C
Remark: All I/Os are set to inputs at power-up and RESET.
Fig 1. Block diagram of PCA9574
PCA9574
POWER-ON
RESET
002aad054
I
2
C-BUS/SMBus
CONTROL
INPUT
FILTER
SCL
SDA
V
DD
INPUT/
OUTPUT
PORTS
P0
V
SS
8-bit
write pulse
read pulse
P2
P4
P6
P1
P3
P5
P7
LP
FILTER
V
DD
INT
A0
RESET
V
DD(IO)
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Product data sheet Rev. 4 — 25 April 2012 4 of 33
NXP Semiconductors PCA9574
8-bit I2C-bus and SMBus, level translating, low volage GPIO
Fig 2. Simplified schematic of the I/Os (P0 to P7)
INTERRUPT
MASK
VDD(IO)
P0 to P7
output port
register data
configuration
register
DQ
CK Q
data from
shift register
write
configuration
pulse
output port
register
DQ
CK
write pulse
polarity
inversion
register
DQ
CK
data from
shift register
write polarity
pulse
input port
register
DQ
CK
read pulse
input port
register data
polarity
inversion
register data
002aad066
FF
data from
shift register
FF
FF
FF
Q1
Q2
VSS
to INT
BUS-HOLD
AND
PULL-UP/PULL-DOWN
CONTROL
ESD
protection
diode
100 kΩ
VDD(IO)
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Product data sheet Rev. 4 — 25 April 2012 5 of 33
NXP Semiconductors PCA9574
8-bit I2C-bus and SMBus, level translating, low volage GPIO
6. Pinning information
6.1 Pinning
Fig 3. Pin configuration for TSSOP16 Fig 4. Pin configuration for HVQ FN1 6
Fig 5. Pin configuration for XQFN16
PCA9574PW
002aad052
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
INT V
DD
A0 SDA
RESET SCL
P0 P7
P1 P6
P2 P5
P3 P4
V
SS
V
DD(IO)
002aad053
PCA9574BS
Transparent top view
P2 P5
P1 P6
P0 P7
RESET SCL
P3
VSS
VDD(IO)
P4
A0
INT
VDD
SDA
4 9
3 10
2 11
1 12
5
6
7
8
16
15
14
13
terminal 1
index area
PCA9574HK
terminal 1
index area
002aag669
Transparent top view
8P4
7VDD(IO)
6VSS
5P3
SD
A
13
VDD
14
INT15
A016
SCL12
P711
P610
P59
1RESET
2P0
3P1
4P2
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Product data sheet Rev. 4 — 25 April 2012 6 of 33
NXP Semiconductors PCA9574
8-bit I2C-bus and SMBus, level translating, low volage GPIO
6.2 Pin description
[1] HVQFN16 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
7. Functional description
7.1 Device address
Following a START condition the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). The address of the
PCA9574 is shown in Figure 6. Slave address pi n A0 chooses 1 of 2 slave addres ses:
40h or 42h.
The last bit of the first byte defines the operation to be performed. When set to logic 1 a
read is selected, while logic 0 selects a write operation.
Table 3. Pin description
Symbol Pin Type Description
TSSOP16 HVQFN16 XQFN16
INT 1 15 15 O active LOW interrupt output;
active LOW SMBus alert output
A0 2 16 16 I address input
RESET 311I activeLOW reset input
P0422I/O input/output 0
P1533I/O input/output 1
P2644I/O input/output 2
P3755I/O input/output 3
VSS 86
[1] 6 ground supply ground
VDD(IO) 9 7 7 power supply I/O bank supply vo ltage
P4 10 8 8 I/O input/output 4
P5 11 9 9 I/O input/output 5
P6 12 10 10 I/O input/output 6
P7 13 11 11 I/O input/output 7
SCL 14 12 12 I serial clock line
SDA 15 13 13 I/O serial data line
VDD 16 14 14 power su pply supply voltage
Fig 6. PCA9574 device address
002aad055
0 1 0 0 0 0 A0 R/W
fixed
slave address
hardware selectable
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Product data sheet Rev. 4 — 25 April 2012 7 of 33
NXP Semiconductors PCA9574
8-bit I2C-bus and SMBus, level translating, low volage GPIO
7.2 Command register
Following the successful acknowledgement of the slave address + R/W bit, the bus
master will send a byte to the PCA9574, which will be stored in the Command register.
The lowest three bits are used as a pointer to determine which register will be accessed.
Only a command register code with the three least significant bits equal to the eight
allowable values as defined in Table 4 “Register summary will be acknowledged.
Reserved or undefined command codes will not be acknowledged. At power-up, this
register defaults to 00h, with the AI bit set to ‘0’, and the lowest 3 bits set to ‘0’.
If the Auto-Increment flag is set (AI = 1), the three least significant bits of the Command
register are au to ma tic ally incre m en te d after a read or write. This allows the user to
program and/or read the eight command registers (listed in Table 4) sequentially. It will
then roll over to register 00h after the last register is accessed and the selected registers
will be overwritten or re-read.
If the Auto-Increment flag is cleared (AI = 0), the three least significant bits are not
incremented after data is read or written, only one register will be repeatedly read or
written.
7.3 Register definitions
7.4 Writing to port registers
Data is transmitted to the PCA9574 by sending the device address and setting the least
significant bit to logic 0 (see Figure 6 for device address). The comma nd byte is sent af ter
the address and determines which register will receive the data following the command
byte. Each 8-bit register may be updated independently of the other registers.
Reset state = 00h
Remark: The Command register does not apply to Software Reset I2C-bus address.
Fig 7. Command registe r
002aad056
AI X X X X D2 D1 D0
register address
Auto-Increment flag
Table 4. Register summary
Register
number D2 D1 D0 Name Type Function
00h 000IN read onlyInput port register
01h 001INVRTread/writePolarity inversion register
02h 0 1 0 BKEN read/write Bus-hold enable register
03h 011PUPDread/writePull-up/pull-down selector register
04h 100CFG read/writePort configuration register
05h 101OUT read/writeOutput port register
06h 110MSK read/writeInterrupt mask register
07h 111INTSread onlyInterrupt status register
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Product data sheet Rev. 4 — 25 April 2012 8 of 33
NXP Semiconductors PCA9574
8-bit I2C-bus and SMBus, level translating, low volage GPIO
7.5 Reading the port registers
In order to read data from the PCA9574, the bus master must first send the PCA9574
address with the least significan t bit set to a logic 0 (see Figure 6 for device address). The
command byte is sent after the address and determines which register will be accessed.
After a restart, the device address is sent again but this time, the least significant bit is set
to logic 1. Data from the register defined by the command byte will then be sent by the
PCA9574. Data is clocked into the register on the falling edge of the acknowledge clock
pulse. After the first byte is read, additional bytes may be read using the auto-increment
feature.
7.5.1 Register 0 - Input port register
This register is read-only. It reflects the incoming logic levels of the pins, regardless of
whether the pin is defined as an input or an output by the Configuration register. Writes to
this register will be acknowledged but will have no effect.
The default ‘X’ is determined by the externally applied logic level.
7.5.2 Register 1 - Polarity inversion register
This register allows the user to invert the polarity of the Input port register data. If a bit in
this register is set (written with ‘1’), the corresponding Input port data is inverted. If a bit in
this register is cleared (written with a ‘0’) , the I nput port data polarity is retained.
Table 5. Register 0 - Input port register (address 00h) bit description
Bit Symbol Access Value Description
7 I0.7 read only X determined by externally applied logic level
6 I0.6 read only X
5 I0.5 read only X
4 I0.4 read only X
3 I0.3 read only X
2 I0.2 read only X
1 I0.1 read only X
0 I0.0 read only X
Table 6. Register 1 - Polarity inversion register (address 01h) bit description
Legend: * default value.
Bit Symbol Access Value Description
7 N0.7 R/W 0* inverts polarity of Input port register data
0 = Input port register data retained (default value)
1 = Input port register data inverted
6N0.6 R/W 0*
5N0.5 R/W 0*
4N0.4 R/W 0*
3N0.3 R/W 0*
2N0.2 R/W 0*
1N0.1 R/W 0*
0N0.0 R/W 0*
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Product data sheet Rev. 4 — 25 April 2012 9 of 33
NXP Semiconductors PCA9574
8-bit I2C-bus and SMBus, level translating, low volage GPIO
7.5.3 Register 2 - Bus-hold/pull-up/pull-down enable register
Bit 0 of this register allows the user to enable/di sable the bus-hold feature fo r the I/O pins.
Setting the bit 0 to logic 1 enables bus-hold feature for the I/O bank. In this mode, the
pull-up/pull-downs will be disabled. Setting the bit 0 to logic 0 disables bus-hold feature.
Bit 1 of this register allows the user to enable/disable pull-up/pull-downs on the I/O pins.
Setting the bit 1 to logic 1 enables selection of pull-up/pull- do wn usin g Reg ister 3. Setting
the bit 1 to logic 0 disables pull-up/pull-downs on the I/O pins and contents of Register 3
will have no effect on the I/O.
Table 7. Register 2 - Bus-hold/pull-up/pull-down enable register (address 02h) bit
description
Legend: * default value.
Bit Symbol Access Value Description
7 E0.7 R/W X not used
6E0.6 R/W X
5E0.5 R/W X
4E0.4 R/W X
3E0.3 R/W X
2E0.2 R/W X
1 E0.1 R/W 0* allows the user to enable/disable pull-up/pull-downs on the
I/O pins
0 = disables pull-up/pull-downs on the I/O pins and
contents of Register 3 will have no effect on the I/O
(default value)
1 = enables selection of pull-up/pull-down using
Register 3
0 E0.0 R/W 0* allows user to enable/disable the bus-hold feature for the I/O
pins
0 = disables bus-hold feature (default value)
1 = enables bus-hold feature
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Product data sheet Rev. 4 — 25 April 2012 10 of 33
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8-bit I2C-bus and SMBus, level translating, low volage GPIO
7.5.4 Register 3 - Pull-up/pull-down selector register
When bus-hold feature is not selected and bit 1 of Register 2 is set to logic 1, the I/O port
can be configured to have pull-up or pull-down by programming the pull-up/pull-down
register. Setting a bit to logic 1 will select a 100 kΩ pull-up resistor for that I/O pin. Setting
a bit to logic 0 will select a 100 kΩ pull-d ow n re sist or for th at I/O pin. If the bus-hold
feature is enabled, writing to this register will have no effect on pull-up/pull-down
selection.
7.5.5 Register 4 - Configuration register
This register configures the direction of the I/O pins. If a bit in this register is set (written
with logic 1), the corresponding port pin is enabled as an input with hi gh-impedance
output driver. If a bit in this register is cle ared (written with logic 0), the corresponding port
pin is enabled as an output. At reset, the device’s ports are inputs.
Table 8. Register 3 - Pull-up/pull-down selecto r register (address 03h) bit description
Legend: * default value.
Bit Symbol Access Value Description
7 P0.7 R/W 1* configures I/O port pin to have pull-up or pull-down when
bus-hold feature not selected and bit 1 of Register 2 is
logic 1
0 = selects a 100 kΩ pull-down resistor for that I/O pin
1 = selects a 100 kΩ pull-up resistor for that I/O pin
(default value)
6P0.6R/W1*
5P0.5R/W1*
4P0.4R/W1*
3P0.3R/W1*
2P0.2R/W1*
1P0.1R/W1*
0P0.0R/W1*
Table 9. Register 4 - Configuration register (addre ss 04h) bit description
Legend: * default value.
Bit Symbol Access Value Description
7 C0.7 R/W 1* configures the direction of the I/O pins
0 = corresponding port pin enabled as an output
1 = corresponding port pin configured as input
(default value)
6 C0.6 R/W 1*
5 C0.5 R/W 1*
4 C0.4 R/W 1*
3 C0.3 R/W 1*
2 C0.2 R/W 1*
1 C0.1 R/W 1*
0 C0.0 R/W 1*
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Product data sheet Rev. 4 — 25 April 2012 11 of 33
NXP Semiconductors PCA9574
8-bit I2C-bus and SMBus, level translating, low volage GPIO
7.5.6 Register 5 - Output port register
This register is an output-only port. It reflects the outgoing logic levels of the pins defined
as outputs by Register 4. Bit values in this register have no effect on pins defined as
inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the
output selection, not the actual pin value.
7.5.7 Register 6 - Interrupt mask register
All the bits of Interrupt mask register are set to logic 1 upon power-on or software reset,
thus disabling interrupts. Interrupts may be enabled by setting corresponding mask bits to
logic 0.
Table 10. Reg ister 5 - Output port register (address 05h) bit description
Legend: * default value.
Bit Symbol Access Value Description
7 O0.7 R/W 0* reflects outgoing logic levels of pins defined as
outputs by Register 4
6O0.6 R/W 0*
5O0.5 R/W 0*
4O0.4 R/W 0*
3O0.3 R/W 0*
2O0.2 R/W 0*
1O0.1 R/W 0*
0O0.0 R/W 0*
Table 11. Register 6 - Interrupt mask register (add ress 06h) bit description
Legend: * default value.
Bit Symbol Access Value Description
7 M0.7 R/W 1* enable or disable interrupts
0 = enable interru pt
1 = disable interrupt (default value)
6M0.6 R/W 1*
5M0.5 R/W 1*
4M0.4 R/W 1*
3M0.3 R/W 1*
2M0.2 R/W 1*
1M0.1 R/W 1*
0M0.0 R/W 1*
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Product data sheet Rev. 4 — 25 April 2012 12 of 33
NXP Semiconductors PCA9574
8-bit I2C-bus and SMBus, level translating, low volage GPIO
7.5.8 Register 7 - Interrupt status register
This register is read-only. It is used to identify the source of interrupt.
Remark: If the interrupts are masked, this register will return all zeros.
7.6 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9574 in
a reset condition until VDD has reached VPOR. At that point, the reset condition is released
and the PCA9574 registers and state machine will initialize to their default states. The
power-on reset typically completes the reset and enables the part by the time the power
supply is above VPOR. However , when it is required to reset the part by lowe ring the power
supply, it is necessary to lower it below 0.2 V.
7.7 RESET input
A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The
PCA9574 registers and I2C-bus state machine will be held in their default state until the
RESET input is once again HIGH.
7.8 Software reset
The Software Reset Call allows all the devices in the I2C-bus to be reset t o th e po we r- up
state value through a specific formatted I2C-bus command. To be performed correctly, it
implies that the I2C-bus is functional and that there is no device hanging the bus.
The Software Reset sequence is defined as following:
1. A START command is sent by the I2C-bus master.
2. The reserved General Call I2C-bus address ‘0000 000’ with the R/W bit set to 0 (w rite)
is sent by the I2C-bus master.
3. The PCA9574 device(s) acknowledge(s) after seeing the General Call address
‘0000 0000’ (00h) only. If the R/W bit is set to logic 1 (read), no acknowledge is
returned to the I2C-bus master.
4. Once the General Call address has been sent and acknowledged, the master sends
1 byte. The value of the byte must be equal to 06h.The PCA9574 acknowledges this
value only. If the byte is not equal to 06h, the PCA9574 does not acknowledge it. If
more than 1 byte of data is sent, the PCA9574 does not acknowledge anymore.
Table 12. Regis t er 7 - Interrupt status register (address 07h) bit description
Legend: * default value.
Bit Symbol Access Value Description
7 S0.7 read only 0* identifies source of interrupt
6 S0.6 read only 0*
5 S0.5 read only 0*
4 S0.4 read only 0*
3 S0.3 read only 0*
2 S0.2 read only 0*
1 S0.1 read only 0*
0 S0.0 read only 0*
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Product data sheet Rev. 4 — 25 April 2012 13 of 33
NXP Semiconductors PCA9574
8-bit I2C-bus and SMBus, level translating, low volage GPIO
5. Once the right byte has been sent and correctly acknowledged, the master sends a
STOP command to end the Software Reset sequence: the PCA9574 then resets to
the default valu e (p ow er -u p va lue ) an d is ready to be addressed again within the
specified bus free time. If the master sends a Repeated START instead, no reset is
performed. The I2C- bus master mu st interpret a non- acknowledge from the PCA9574
(at any time) as a ‘Software Reset Abort’. The PCA9574 does not initiate a software
reset.
7.9 Interrupt output (INT)
The open-drain a ctive LOW interrupt is activated when one o f the port p ins chan ges st ate
and the port pin is configured as an input and the interrupt on it is not masked. The
interrupt is deactivated when the port pin input returns to its previous state or the Input
Port register is read. It is hi ghly recomme nded to pro gram the M SK regi ster, and the CFG
registers during the initialization sequence after power-up, since any change to them
during Normal mode operation may cause undesirable interrupt events to happen.
Remark: Changing an I/O from an output to an input may cause a false interrupt to occur
if the state of th e pin does n ot match the contents of the Input port register . Only a read of
the Input port register that contains the bit(s) image of the input(s) that generated the
interrupt clears the interrupt condition.
7.10 Standby
The PCA9574 goes into st andby when the I2C-bus is idle. Standby supply current is lower
than 1.0 μA (typical).
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Product data sheet Rev. 4 — 25 April 2012 14 of 33
NXP Semiconductors PCA9574
8-bit I2C-bus and SMBus, level translating, low volage GPIO
8. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line commu nication between dif ferent ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bi t is transferred durin g each clock pulse . The data o n the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 8).
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HI GH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 9).
8.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 10).
Fig 8. Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 9. Definition of START and STOP conditions
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Product data sheet Rev. 4 — 25 April 2012 15 of 33
NXP Semiconductors PCA9574
8-bit I2C-bus and SMBus, level translating, low volage GPIO
8.3 Acknowledge
The number of data bytes transferred between the START and th e STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addresse d must gener ate an acknowledg e af ter the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocke d ou t of th e sla ve tr an smitter. The device that acknowledges has to
pull down the SDA line during the acknowledge cl ock pulse , so that the SDA line is st able
LOW during the HIGH period of the acknowledge related clock pulse; set-up time a nd hold
time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter mus t leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 10. System configuratio n
002aaa966
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
I2C-BUS
MULTIPLEXER
SLAVE
Fig 11. Acknowledgement on the I2C-bus
002aaa987
S
START
condition
9821
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from master
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Product data sheet Rev. 4 — 25 April 2012 16 of 33
NXP Semiconductors PCA9574
8-bit I2C-bus and SMBus, level translating, low volage GPIO
9. Bus transactions
Data is transmitted to the PCA9574 registers using ‘Write Byte’ transfers (see Figure 12
and Figure 13).
Data is read from the PCA9574 registers using ‘Read Byte’ transfers (see Figure 14 and
Figure 15).
Fig 12. Write to Output port register
0 AS
slave address
START condition R/W acknowledge
from slave
002aad057
00001010
command byte
A
acknowledge
from slave
12345678SCL 9
SDA DATA 1 A
write to port
data out from port
tv(Q)
acknowledge
from slave
DATA 1 VALID
data to port
10000A00P
STOP
condition
Fig 13. Write to Polarity inversion, Bus-hold enable, Pul l-up/pull-down selector, Confi guration, Interrupt mask
and Interrupt status registers
0 AS
slave address
START condition R/W acknowledge
from slave
002aad058
0000XXX0
command byte
A
acknowledge
from slave
12345678SCL 9
SDA DATA A
data to register
acknowledge
from slave
data to register
10000A00P
STOP
condition
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Product data sheet Rev. 4 — 25 April 2012 17 of 33
NXP Semiconductors PCA9574
8-bit I2C-bus and SMBus, level translating, low volage GPIO
Fig 14. Read from register
10000A00AS0
START condition R/W
acknowledge
from slave
002aad059
A
acknowledge
from slave
SDA
A P
command byte
acknowledge
from master
data from register
DATA (first byte)
slave address
STOP
condition
S
(repeated)
START condition
(cont.)
(cont.) 10000A01A0
R/W
acknowledge
from slave
slave address
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
NA
no acknowledge
from master
data from register
DATA (last byte)
This figure assumes the command byte has previously been programmed with 00h.
Transfer of data can be stopped at any moment by a STOP condition.
Fig 15. Read Input port register
10000A01AS0
slave address
START condition R/W acknowledge
from slave
002aad060
data from port
A
acknowledge
from master
SDA 1
no acknowledge
from master
read from
port
data into
port
data from port
DATA 1
DATA 4
INT
DATA 4
DATA 2
DATA 3
P
STOP
condition
tv(INT) trst(INT)
th(D) tsu(D)
2345678
SCL 91
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Product data sheet Rev. 4 — 25 April 2012 18 of 33
NXP Semiconductors PCA9574
8-bit I2C-bus and SMBus, level translating, low volage GPIO
10. Application design-in information
11. Limiting values
Device address configured as 0100 0000b for this example.
P0, P2, P3 configured as outputs.
P1, P4, P5 configured as inputs.
P6, P7 are not used and must be configured as outputs.
Fig 16. Typical application
PCA9574
P0
P1
SCL
SDA
VDD
SCL
SDA P2
P3
VDD
VSS
MASTER
CONTROLLER
VSS
VDD = 1.1 V to 3.6 V
SUBSYSTEM 1
(e.g., temp. sensor)
INT
SUBSYSTEM 2
(e.g., counter)
RESET
controlled switch
(e.g., CBT device)
A
B
enable
INT
VDD(IO)
INT
1.1 kΩ2 kΩ
SUBSYSTEM 3
(e.g., alarm system)
ALARM
P4
P5
VDD(IO)
A0
P6
P7
1.6 kΩ1.6 kΩ
RESETRESET
VDD(IO) = 3.6 V
002aad061
SUBSYSTEM 4
(e.g., RF module)
CTRL
Table 13. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +4.0 V
VDD(IO) input/outpu t sup ply voltage VSS 0.5 VDD +0.5 V
II/O input/output current - ±5mA
IIinput current - ±20 mA
IDD supply current - 90 mA
ISS ground supply curren t - 90 mA
Ptot total power dissipation - 75 mW
Tstg storage temperature 65 +150 °C
Tamb ambient temperature 40 +85 °C
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Product data sheet Rev. 4 — 25 April 2012 19 of 33
NXP Semiconductors PCA9574
8-bit I2C-bus and SMBus, level translating, low volage GPIO
12. Static characteristics
Table 14. Static characteristics
VDD = 1.1 V to 3.6 V; VDD(IO) = 1.1 V to 3.6 V; VSS =0V; T
amb =
40
°
C to +85
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
VDD supply voltage 1.1 - 3.6 V
VDD(IO) input/output supply voltage 1.1 - VDD +0.5 V
IDD supply current operating mode; VDD =3.6V;
no load; fSCL = 100 kHz; I/O = inputs - 135 200 μA
IstbL LOW-level standby current Standby mode; VDD = 3.6 V; no load;
VI=V
SS; fSCL = 0 kHz; I/O = inputs -0.251 μA
IstbH HIGH-level standby current Standby mode; VDD = 3.6 V; no load;
VI=V
DD; fSCL = 0 kHz; I/O = inputs -0.251 μA
VPOR power-on reset voltage no load; VI=V
DD or VSS (rising VDD)- 0.81.0 V
Input SCL; input/outpu t S DA
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD -3.6 V
IOL LOW-level output current VOL =0.2V; V
DD =1.1V 1 - - mA
VOL =0.4V; V
DD =2.3V 3 - - mA
ILleakage current VI=V
DD or VSS 1-+1 μA
Ciinput capacitance VI=V
SS -610pF
I/Os
VIL LOW-level input voltage 0.5 - +0.3VDD(IO) V
VIH HIGH-level input voltage 0.7VDD(IO) -3.6 V
IOH HIGH-level output current VOH =0.9V; V
DD(IO) =1.1V 1 - - mA
IOL LOW-level output current VOL =0.2V; V
DD(IO) =1.1V 1 - - mA
VOL =0.5V; V
DD(IO) =3.6V 2 3 - mA
VOH HIGH-level output voltage IOH =1mA; V
DD(IO) = 1.1 V 0.8 - - V
ILIH HIGH-level input leakage
current VDD(IO) =3.6V; V
I=V
DD(IO) --1 μA
ILIL LOW-level input leakage
current VDD(IO) =3.6V; V
I=V
SS --1μA
Ciinput capacitance - 3.7 5 pF
Cooutput capacitance - 3.7 5 pF
Interrupt INT
IOL LOW-level output current VOL =0.4V; V
DD =1.1V 3 - - mA
Select input A0; RESET
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD -3.6 V
ILI input leakage current VI=V
DD or VSS 1-+1 μA
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Product data sheet Rev. 4 — 25 April 2012 20 of 33
NXP Semiconductors PCA9574
8-bit I2C-bus and SMBus, level translating, low volage GPIO
Fig 17. VOH at VDD =3.3V, V
DD(IO) =1.2V, I
OH =1 mA Fig 18. VOH at VDD =3.3V, V
DD(IO) =3.3V, I
OH =1mA
1.0
2.0
3.0
VOH
(V)
0
Tamb (°C)
40 10020
002aae765
0 20 40 60 80
4.0
VOH
(V)
0
Tamb (°C)
40 10020
002aae766
0 20 40 60 80
1.0
2.0
3.0
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Product data sheet Rev. 4 — 25 April 2012 21 of 33
NXP Semiconductors PCA9574
8-bit I2C-bus and SMBus, level translating, low volage GPIO
13. Dynamic characteristics
[1] tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[3] Cb = total capacitance of one bus line in pF.
Table 15. Dynamic characteristics
VDD = 1.1 V to 3.6 V; VDD(IO) = 1.1 V to 3.6 V; VSS =0V; T
amb =
40
°
C to +85
°
C; unless otherwise specified.
Symbol Parameter Conditions Standard-mode
I2C-bus Fast-mode I2C-bus Unit
Min Max Min Max
fSCL SCL clock frequency 0 100 0 400 kHz
tBUF bus free time between a STOP and
START condition 4.7 - 1.3 - μs
tHD;STA hold time (repeated) START condition 4.0 - 0.6 - μs
tSU;STA set-up time for a repeated START
condition 4.7 - 0.6 - μs
tSU;STO set-up time for ST OP condition 4.0 - 0.6 - μs
tVD;ACK data valid acknowledge time [1] 0.3 3.45 0.1 0.9 μs
tHD;DAT data hold time 0 - 0 - ns
tVD;DAT data valid time [2] 300 - 50 - ns
tSU;DAT data set-up time 250 - 100 - ns
tLOW LOW period of the SCL clock 4.7 - 1.3 - μs
tHIGH HIGH period of the SCL clock 4.0 - 0.6 - μs
tffall time of both SDA and SCL signals - 300 20 + 0.1Cb[3] 300 ns
trrise time of both SDA and SCL signals - 1000 20 + 0.1Cb[3] 300 ns
tSP pulse width of spikes that must be
suppressed by the input filter -50 - 50ns
Port timing
tv(Q) data output valid time - 200 - 200 ns
tsu(D) data input set-up time 150 - 150 - ns
th(D) data input hold time 1 - 1 - μs
Interrupt timing
tv(INT) valid time on pin INT -4 - 4μs
trst(INT) reset time on pin INT -4 - 4μs
Reset
tw(rst) reset pulse width 6 - 6 - ns
trec(rst) reset recovery time 0 - 0 - ns
trst(SDA) SDA reset time Figure 20 - 450 - 450 ns
trst(GPIO) GPIO reset time Figure 20 - 450 - 450 ns
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Product data sheet Rev. 4 — 25 April 2012 22 of 33
NXP Semiconductors PCA9574
8-bit I2C-bus and SMBus, level translating, low volage GPIO
Fig 19. Definition of timing
t
SP
t
BUF
t
HD;STA
PP S
t
LOW
t
r
t
HD;DAT
t
f
t
HIGH
t
SU;DAT
t
SU;STA
Sr
t
HD;STA
t
SU;STO
SDA
SCL
002aaa986
0.7 × V
DD
0.3 × V
DD
0.7 × V
DD
0.3 × V
DD
Fig 20. Reset timing
SDA
SCL
002aad062
trst
50 %
30 %
50 % 50 %
50 %
trec(rst) tw(rst)
RESET
P0 to P7 output off
START
trst
ACK or read cycle
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Product data sheet Rev. 4 — 25 April 2012 23 of 33
NXP Semiconductors PCA9574
8-bit I2C-bus and SMBus, level translating, low volage GPIO
14. Test information
RL = load resistance.
CL = load capacitance includes jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generators.
(1) F or SDA, no 500 Ω pull-down.
Fig 21. Test circuitry for switching times
PULSE
GENERATOR
V
O
CL
50 pF
RL
500 Ω
002aad582
RT
V
I
V
DD
DUT
2V
DD
open
V
SS
500 Ω(1)