PLR135/T7 - Everlight - Datasheet.Directory

Everlight Electronics Co., Ltd. http://www.everlight.com Rev 2 Page: 1 of 8

Device NO.: DPL-135-001 Prepared date: 07-25-2005 Prepared By: Chin-Chia Hsu

Technical Data Sheet

Photo link Light Receiver Unit

PLR135

Features

1. High PD sensitivity optimized for red light

2. Data : NRZ signal

3. Low power consumption for extended battery

life

4. Built-in threshold control for improved noise

Margin

5. Good ESD protection: up to 8KV

6. Pb Free

7. Receiver sensitivity: up to –27dBm (Min. for 16Mbps)

up to –21dBm (Min. for 25Mbps

8. The product itself will remain within RoHS compliant

version.

Descriptions

The optical receiver is packaged with custom

optic data link interface, integrated on a proprietary

CMOS PDIC process.

The unit functions by converting optical signals

into electric ones.

The unit is operated at 2.4 ~ 5.5 V and the signal

output interface is TTL compatible with high

performance at low power consumption.

Applications

1. Digital Optical Data-Link

2. Dolby AC-3 Digital Audio Interface

Everlight Electronics Co., Ltd. http://www.everlight.com Rev 2 Page: 2 of 8

Device NO.: DPL-135-001 Prepared date: 07-25-2005 Prepared By: Chin-Chia Hsu

PLR135

Package Dimensions

321

Pin Function

1 :Vout

2:GND

3:Vcc

Notes: 1.All dimensions are in mm.

2.General Tolerance: Pin length tolerance is ±0.25 mm

others are ±0.10 mm

Everlight Electronics Co., Ltd. http://www.everlight.com Rev 2 Page: 3 of 8

Device NO.: DPL-135-001 Prepared date: 07-25-2005 Prepared By: Chin-Chia Hsu

PLR135

Absolute Maximum Ratings( Ta = 25 ºC)

Parameter Symbol Rating Unit

Supply Voltage Vcc -0.5 ~ +5.5 V

Output Voltage Vout Vcc +0.3 V

Storage Temperature Tstg -40 to 85 ºC

Operating Temperature Topr -20 to 70 ºC

Soldering Temperature Tsol 260* ºC

* Soldering time ≤ 10 s.

Electro-Optical Characteristics(Ta=-20~70℃,Vcc=3V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Power supply voltage Vcc - 2.40 3.00 5.50 V

Peak sensitivity wavelength λp - - 650 - nm

Maximum receiver power Pc,max Refer to Fig.1 - - -14

dBm

Minimum receiver power Pc,min Refer to Fig.1 -27 - -

dBm

Dissipation current Icc Refer to Fig.2 - 4 12

mA

High level output voltage VOH Refer to Fig.3 2.1 2.5 - V

Low level output voltage VOL Refer to Fig.3 - 0.2 0.4

V

Rise time tr Refer to Fig.3 10 20

ns

Fall time tf Refer to Fig.3 10 20

ns

Propagation delay Low to High tPLH Refer to Fig.3 - - 120 ns

Propagation delay High to Low tPHL Refer to Fig.3 - - 120 ns

Pulse Width Distortion ∆tw Refer to Fig.3 -25 - +25 ns

Refer to Fig.3, Pc=-14dBm - 1 15 ns

Jitter ∆tj Refer to Fig.3, Pc=-27dBm - 5 20 ns

Transfer rate T NRZ signal

0.1 - 16

Mb/s

Everlight Electronics Co., Ltd. http://www.everlight.com Rev 2 Page: 4 of 8

Device NO.: DPL-135-001 Prepared date: 07-25-2005 Prepared By: Chin-Chia Hsu

PLR135

Measuring Method

*Fig.1 Measuring Method of Maximum and Minimum Input Power that Receiver Unit Need

Transmitter

Standard plastic optic fiber cable

PLR135 Receiver Unit

Control Circuit

Optical Power Meter

*Fig.2 Measuring Method of Dissipation Current

Vin

Standard Transmitter Unit

Signal

Input

47uH

16 Mbps NRZ "0101" su ccessive signal input

Vcc GND

Standard plastic optic fiber cable

PLR135 Receiver Unit

3V

A

GND

0.1uF

Vcc Vout

Everlight Electronics Co., Ltd. http://www.everlight.com Rev 2 Page: 5 of 8

Device NO.: DPL-135-001 Prepared date: 07-25-2005 Prepared By: Chin-Chia Hsu

L2:47uH

C1:0.1uF

Vout

5V

L2

Vcc GND

C1

Receiver Unit

C2

C2:30pF (Suggestion)

PLR135

*Fig.3 Measuring Method of Output Voltage, Pulse and Jitter

Output

Vin

16 Mbps NRZ "0101" successive signal input

Standard Transmitter Unit

Input

Signal

Input

tw = TPHL-TPLH

tj2tj1

50%

50% CH2

47uH

T

TPLH PHL

Vcc GND

CH1

Standard pl astic optic fiber cable

PLR135 Receiver Unit

3V

A

GND

0.1uF

Vcc Vout

Application Circuit

(1) General application circuit for Vcc=3V (2) General application circuit for Vcc=5V

L2:47uH

C1:0.1uF

Vout

3V

L2

Vcc GND

C1

Receiver Unit

Note: For having good coupling, the C1,C2 capacitor must be placed within 7mm

Everlight Electronics Co., Ltd. http://www.everlight.com Rev 2 Page: 6 of 8

Device NO.: DPL-135-001 Prepared date: 07-25-2005 Prepared By: Chin-Chia Hsu

PLR135

Typical Electro-Optical Characteristics Curves

*Fig.4 Power supply voltage vs. Minimum

receiver power *Fig.5 Transfer rate vs. Minimum receiver

power

2.02.53.03.54.04.55.05.56.0

-20

-22

-24

-26

-28

-30

Operating Transfer Rate

16Mbps

25Mbps

Optical Input Sensitivity (dBm)

Operating Voltage (V)

0 5 10 15 20 25

-18

-20

-22

-24

-26

-28

-30

-32 Operating Voltage Vcc=3.3V

Optical Input Sensitivity (dBm)

Transfer Rate (Mbps)

Note: Before using the PLR135 device, please confirm the minimum sensitivity at different

operating voltage and transmission rate.

Everlight Electronics Co., Ltd. http://www.everlight.com Rev 2 Page: 7 of 8

Device NO.: DPL-135-001 Prepared date: 07-25-2005 Prepared By: Chin-Chia Hsu

PLR135

RELIABILITY TEST ITEMS

Test Sample Size Number (n)

No. Item Test Condition

Hour/Cycle (Piece) Failure (c)

1 Soldering Heat 260ºC±5ºC 10 seconds 22 n=22, c=0

2 High Temp. Storage Ta=100ºC 1000hrs 22 n=22, c=0

3 Low Temp. Storage Ta=-55ºC 1000hrs 22 n=22, c=0

High Temp. &

4 Humid. Test Ta=85ºC, RH=85% 1000hrs 22 n=22, c=0

-55ºC ~~~~ 85ºC

5 Temperature Cycle (30min) (5min) (30min) 300cycle 22 n=22, c=0

-10ºC ~~~~ 100ºC

6 Thermal Shock (5min) (10sec) (5min) 300cycle 22 n=22, c=0

7 DC Operating Life Vcc=3V, Ta=25ºC 1000hrs 22 n=22, c=0

Everlight Electronics Co., Ltd. http://www.everlight.com Rev 2 Page: 8 of 8

Device NO.: DPL-135-001 Prepared date: 07-25-2005 Prepared By: Chin-Chia Hsu

PLR135

Application Notes: PLR135 Series PCB layout for motherboard integration

To achieve better jitter and low input optical power performances, several PCB layout

guidelines must be followed. These guidelines ensure the most reliable PLR135 POF performance

for the motherboard integration. Failed to implement these PCB guidelines may affect the PLR135

jitter and low input power performances.

1. Careful decoupling of the power supplies is very important. Place a 0.1uf surface mount (size

805 or smaller) capacitor as close as (less than 2cm) to the POF Vdd and Gnd leads. The 0.1uf

act as a low impedance path to ground for any stray high frequency transient noises.

2. To reduce the digital noises form the digital IC on the motherboard, the planar capacitance

formed by an isolated Vcc and Gnd planes is critical. The POF device must be mounted directly

on these two planes to reduce the lead parasitic inductance.

3. The isolated Vdd and Gnd planes must be connected to the main Vcc and Gnd (digital) planes at

a single point using ferrite beads. The beads are used to block the high frequency noises from

the digital planes while still allowing the DC connections between the planes

EVERLIGHT ELECTRONICS CO., LTD. Tel: 886-2-2267-2000, 2267-9936

Office: No 25, Lane 76, Sec 3, Chung Yang Rd, Fax: 886-2267-6244, 2267-6189, 2267-6306

Tucheng, Taipei 236, Taiwan, R.O.C http://www.everlight.com