5-68
FAST AND LS TTL DATA
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54LS/74LS73A offers individual J, K, clear , and clock inputs. These
dual flip-flops are designed so that when the clock goes HIGH, the inputs are
enabled and data will be accepted. The logic level of the J and K inputs may
be allowed to change when the clock pulse is HIGH and the bistable will per-
form according to the truth table as long as minimum set-up times are ob-
served. Input data is transferred to the outputs on the negative-going edge of
the clock pulse.
LOGIC DIAGRAM (Each Flip-Flop)
Q
K
13 (8)
3 (10)
Q
12 (9)
CLEAR
2 (6)
J
14 (7)
1 (15)
CLOCK (CP)
MODE SELECT — TRUTH TABLE
OPERATING MODE
INPUTS OUTPUTS
OPERATING MODE
CDJ K Q Q
Reset (Clear)
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
L
H
H
H
H
X
h
l
h
l
X
h
h
l
l
L
q
L
H
q
H
q
H
L
q
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time
l, h (q) = prior to the HIGH to LOW clock transition.
SN54/74LS73A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 632-08
N SUFFIX
PLASTIC
CASE 646-06
14 1
14
1
ORDERING INFORMATION
SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC
14 1
D SUFFIX
SOIC
CASE 751A-02
LOGIC SYMBOL
14
1
3
12
13
J Q
CP
K Q
CD
2VCC = PIN 4
GND = PIN 11
7
5
10
9
8
J Q
CP
K Q
CD
6
5-69
FAST AND LS TTL DATA
SN54/74LS73A
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54
74 4.5
4.75 5.0
5.0 5.5
5.25 V
TAOperating Ambient Temperature Range 54
74 –55
025
25 125
70 °C
IOH Output Current — High 54, 74 –0.4 mA
IOL Output Current — Low 54
74 4.0
8.0 mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min Typ Max
Unit
Test Conditions
VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54 0.7
V
Guaranteed Input LOW Voltage for
All Inputs
VIL
Input LOW Voltage
74 0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH
Output HIGH Voltage
54 2.5 3.5 V
V
CC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOH
Output HIGH Voltage
74 2.7 3.5 V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL
Output LOW Voltage
54, 74 0.25 0.4 V IOL = 4.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VOL
Output LOW Voltage
74 0.35 0.5 V IOL = 8.0 mA
VIN = VIL or VIH
per Truth Table
IIH
Input HIGH Current
J, K
Clear
Clock
20
60
80 µA VCC = MAX, VIN = 2.7 V
IIH
Input HIGH Current
J, K
Clear
Clock
0.1
0.3
0.4 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current J, K
Clear, Clock –0.4
–0.8 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
ICC Power Supply Current 6.0 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min Typ Max
Unit
Test Conditions
fMAX Maximum Clock Frequency 30 45 MHz Figure 1
VCC = 5.0 V
CL = 15 pF
t
PLH
tPHL
Propagation Delay,
Clock to Output
15 20 ns
Figure 1
VCC = 5.0 V
CL = 15 pF
tPLH
tPHL
Propagation Delay,
Clock to Output
15 20 ns
Figure 1
CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min Typ Max
Unit
Test Conditions
tWClock Pulse Width High 20 ns Figure 1
VCC = 5.0 V
tWClear Pulse Width 25 ns Figure 2
VCC = 5.0 V
tsSetup Time 20 ns
Figure 1
VCC = 5.0 V
thHold Time 0 ns
Figure 1
5-70
FAST AND LS TTL DATA
SN54/74LS73A
tPHL
tPHL tPLH
Figure 1. Clock to Output Delays, Data
Set-Up and Hold Times, Clock Pulse Width
Figure 2. Set and Clear to Output Delays,
Set and Clear Pulse Widths
AC WAVEFORMS
tW
1.3 V 1.3 V
tW
1.3 V 1.3 V
1.3 V
1.3 V1.3 V
1.3 V
tPLH tPHL
tPLH
tPHL
SET
CLEAR
Q
Q
*The shaded areas indicate when the input is permitted to change for predictable output performance.
J or K *
CP
Q
Q
1.3 V
1.3 V 1.3 V
1.3 V
1.3 V 1.3 V
1.3 V
1.3 V
ts(L) th(L) = 0
tW(L) ts(H) th(H) = 0
tW(H)
tPLH
1
fMAX