A3966SLBTR-T - Allegro Microsystems

Description

The A3966 is designed to drive both windings of a two-phase

bipolar stepper motor. The device includes two full-bridges

capable of continuous output currents of ±650 mA and operating

voltages to 30 V. Motor winding current can be controlled by

the internal fixed-frequency, pulse-width modulated (PWM),

current-control circuitry. The peak load current limit is set

by user selection of a reference voltage and current-sensing

resistors.

The fixed-frequency pulse duration is set by a user-selected

external RC timing network. The capacitor in the RC timing

network also determines a user-selectable blanking window that

prevents false triggering of the PWM current-control circuitry

during switching transitions.

To reduce on-chip power dissipation, the full-bridge power

outputs have been optimized for low saturation voltages. The

sink drivers feature the Allegro® patented Satlington® output

structure. The Satlington outputs combine the low voltage drop

of a saturated transistor and the high peak current capability

of a Darlington.

For each bridge, a PHASE input controls load-current polarity

by selecting the appropriate source and sink driver pair. For

29319.25K

Features and Benefits

▪ ±650 mA continuous output current

▪ 30 V output voltage rating

▪ Internal fixed-frequency PWM current control

▪ Satlington® sink drivers

▪ User-selectable blanking window

▪ Internal ground-clamp and flyback diodes

▪ Internal thermal-shutdown circuitry

▪ Crossover-current protection and UVLO protection

Dual Full-Bridge PWM Motor Driver

Continued on the next page…

Package: 16 pin SOICW (suffix LB)

Typical Application

Not to scale

A3966

Dwg. EP-047-4A

PHASE

ENABLE

47 μF

+24 V

56 kΩ

680 pF

PHASE

ENABLE

+5 V

39 kΩ

10 kΩ

0.5 Ω

+5 V

0.5 Ω

LOGICLOGIC

314

017

98 RC

REF

Dual Full-Bridge PWM Motor Driver

A3966

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

each bridge, an ENABLE input, when held high, disables the output

drivers. Special power-up sequencing is not required. Internal circuit

protection includes thermal shutdown with hysteresis, ground-clamp

and flyback diodes, and crossover-current protection.

The A3966 is supplied in a 16-lead plastic wide SOIC with two pins

internally fused to the die pad for enhanced thermal dissipation. These

pins are at ground potential and need no electrical isolation. The

device is lead (Pb) free, with 100% matte tin leadframe plating.

Description (continued)

Pin-out Diagram

Selection Guide

Part Number Packing Ambient Temperature Range

(°C)

A3966SLBTR–T 1000 pieces / reel –20 to 85

Absolute Maximum Ratings

Characteristic Symbol Notes Rating Units

Load Supply Voltage VBB 30 V

Logic Supply Voltage VCC 7.0 V

Input Voltage VIN –0.3 to VCC + 0.3 V

Sense Voltage VS1.0 V

Output Current* IOUT

Peak Output current rating may be limited by duty

cycle, ambient temperature, and heat sinking.

Under any set of conditions, do not exceed the

specified current rating or TJ(max)

±750 mA

Continuous ±650 mA

Package Power Dissipation PD

TA = 25°C; per SEMI G42-88 Specification, Thermal Test

Board Standardization for Measuring Junction-to-Ambient

Thermal Resistance of Semiconductor Packages. 1.87 W

Operating Ambient Temperature T ARange S –20 to 85 ºC

Maximum Junction Temperature TJ(max) 150 ºC

Storage Temperature Tstg –55 to 150 ºC

OUT1B

GROUND GROUND

OUT1A

PHASE1

OUT2A

SENSE1

ENABLE1

LOAD

SUPPLY

REFERENCE

PHASE2

ENABLE 2

SENSE2

OUT2B

LOGIC

SUPPLY

LOGICLOGIC

314

017

98 RC

VREF

VBB

VCC

VBB

Dual Full-Bridge PWM Motor Driver

A3966

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

FUNCTIONAL BLOCK DIAGRAM

TRUTH TABLE

PHASE ENABLE OUTA OUTB

X H Off Off

H L H L

L L L H

X = Irrelevant

R2S

R1S

REFERENCE

÷4

VCC

LOGIC

SUPPLY

PHASE 1

LOAD

SUPPLY

OUT 1A

OUT1B

VBB

RTCT

Dwg. FP-036-6

SENSE

UVLO

& TSD

BLANKING

GATE

PWM LATCH +

–

CURRENT-SENSE

COMPARATOR

ENABLE1

OSC

PHASE2

GROUND

SENSE

UVLO

& TSD

BLANKING

GATE

PWM LATCH

–

CURRENT-SENSE

COMPARATOR

ENABLE2

CONTROL LOGIC

SOURCE

ENABLE

OUT2A

OUT2B

1222

111

CONTROL LOGIC 1

SOURCE

ENABLE 1

Typical output saturation voltages showing

Satlington sink-driver operation.

200

Dwg. GP-064-1A

007004

300

OUTPUT CURRENT IN MILLIAMPERES

2.0

OUTPUT SATURATION VOLTAGE IN VOLTS

1.0

0.5

1.5

2.5

500 600

= +25°C

SOURCE DRIVER

SINK DRIVER

Dual Full-Bridge PWM Motor Driver

A3966

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Load Supply Voltage Range VBB Operating, IOUT =p650 mA, L = 3 mH VCC —30 V

Output Leakage Current ICEX VOUT 050.1<—V03= MA

VOUT 05-0.1-<—V0= MA

Output Saturation Voltage VCE(SAT) Source Driver, IOUT = -400 mA — 1.7 2.0 V

Source Driver, IOUT = -650 mA — 1.8 2.1 V

Sink Driver, IOUT = +400 mA, VS = 0.5 V — 0.3 0.5 V

Sink Driver, IOUT = +650 mA, VS = 0.5 V — 0.7 1.3 V

Clamp Diode Forward Voltage VFIFV4.11.1—Am004=

IFV6.14.1—Am056=

Motor Supply Current IBB(ON) VENABLE1 = VENABLE2 = 0.8 V — 3.0 5.0 mA

(No Load) IBB(OFF) VENABLE1 = VENABLE2 = 2.4 V — <1.0 200 MA

ELECTRICAL CHARACTERISTICS at TA= +25oC, VBB = 30 V, VCC = 4.75 V to 5.5 V, VREF = 2 V,

VS = 0 V, 56 k & 680 pF RC to Ground (unless noted otherwise)

Limits

stinU.xaM.pyT.niMsnoitidnoCtseTlobmyScitsiretcarahC

Output Drivers

Logic Supply Voltage Range VCC V05.5—57.4gnitarepO

Logic Input Voltage VIN(1) 2.4 — — V

VIN(0) — — 0.8 V

Logic Input Current IIN(1) VIN 020.1<—V4.2= MA

IIN(0) VIN 002-02-<—V8.0= MA

Reference Input Volt. Range VREF V0.2–1.0gnitarepO

Reference Input Current IREF -2.5 0 1.0 MA

Reference Divider Ratio VREF/VTRIP 3.8 4.0 4.2 —

Current-Sense Comparator VIO VREF Vm0.600.6-V0=

Input Offset Voltage

Current-Sense Comparator VSV0.1—3.0-gnitarepO

Input Voltage Range

Sense-Current Offset ISO IS–I

OUT, 50 mA bIOUT b 650 mA 12 18 24 mA

Control Logic

NOTES:1. Typical Data is for design information only.

2. Negative current is defined as coming out of (sourcing) the specified device terminal.

Dual Full-Bridge PWM Motor Driver

A3966

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

PWM RC Frequency fosc CT= 680 pF, RT = 56 k722.9 25.4 27.9 kHz

PWM Propagation Delay Time tPWM Comparator Trip to Source OFF — 1.0 1.4 Ms

Cycle Reset to Source ON — 0.8 1.2 Ms

Cross-Over Dead Time tcodt 1k0.38.12.0V52otdaoL Ms

Propagation Delay Times tpd IOUT = p650 mA, 50% to 90%:

ENABLE ON to Source ON — 100 — ns

ENABLE OFF to Source OFF — 500 — ns

ENABLE ON to Sink ON — 200 — ns

ENABLE OFF to Sink OFF — 200 — ns

PHASE Change to Sink ON — 2200 — ns

PHASE Change to Sink OFF — 200 — ns

PHASE Change to Source ON — 2200 — ns

PHASE Change to Source OFF — 200 — ns

Thermal Shutdown Temp. TJ—165— oC

Thermal Shutdown Hysteresis $TJ—15—oC

UVLO Enable Threshold VT(UVLO)+ Increasing VCC — 4.1 4.6 V

UVLO Hysteresis VT(UVLO)hys 0.1 0.6 — V

Logic Supply Current ICC(ON) VENABLE 1 = VENABLE 2 = 0.8 V — — 50 mA

ICC(OFF) VENABLE 1 = VENABLE 2 = 2.4 V — — 9.0 mA

Limits

stinU.xaM.pyT.niMsnoitidnoCtseTlobmyScitsiretcarahC

ELECTRICAL CHARACTERISTICS at TA= +25oC, VBB = 30 V, VCC = 4.75 V to 5.5 V, VREF = 2 V,

VS = 0 V, 56 k & 680 pF RC to Ground (unless noted otherwise) (cont.)

Control Logic (continued)

NOTES:1. Typical Data is for design information only.

2. Negative current is defined as coming out of (sourcing) the specified device terminal.

Dual Full-Bridge PWM Motor Driver

A3966

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Internal PWM Current Control. The A3966 dual full-

bridges are designed to drive both windings of a bipolar

stepper motor. Load current can be controlled in each motor

winding by an internal ﬁ xed-frequency PWM control cir-

cuit. The current-control circuitry works as follows: when

the outputs of the full-bridge are turned on, current increas-

es in the motor winding. The load current is sensed by the

current-control comparator via an external sense resistor

(RS). Load current continues to increase until it reaches

the predetermined value, set by the selection of external

current-sensing resistors and reference input voltage (VREF)

according to the equation:

ITRIP = IOUT + ISO = VREF/(4 RS)

where ISO is the sense-current error (typically 18 mA) due

to the base-drive current of the sink driver transistor.

At the trip point, the comparator resets the source-en-

able latch, turning off the source driver of that full-bridge.

The source turn-off of one full-bridge is independent of

the other full-bridge. Load inductance causes the current to

recirculate through the sink driver and ground-clamp diode.

The current decreases until the internal clock oscillator sets

the source-enable latches of both Full-bridges, turning on

the source drivers of both bridges. Load current increases

again, and the cycle is repeated.

The frequency of the internal clock oscillator is set by

the external timing components RTCT. The frequency can

be approximately calculated as:

fosc = 1/(RT CT + tblank)

where tblank is deﬁ ned below.

The range of recommended values for RT and CT are

20 to 100 k and 470 to 1000 pF respectively. Nominal

values of 56 k and 680 pF result in a clock frequency of

25 kHz.

Current-Sense Comparator Blanking. When the

source driver is turned on, a current spike occurs due to the

reverse-recovery currents of the clamp diodes and switch-

ing transients related to distributed capacitance in the load.

To prevent this current spike from erroneously resetting the

source enable latch, the current-control comparator output

is blanked for a short period of time when the source driver

is turned on. The blanking time is set by the timing compo-

nent CT according to the equation:

tblank = 1900 CT (μs).

A nominal CT value of 680 pF will give a blanking time

of 1.3 μs.

The current-control comparator is also blanked when

the Full-bridge outputs are switched by the PHASE or

ENABLE inputs. This internally generated blank time is

approximately 1 μs.

FUNCTIONAL DESCRIPTION

–

Dwg. WM-003-2

PHASE

OUT

TRIP

blank

INTERNAL

OSCILLATOR

BRIDGE

ON SOURCE

OFF

BRIDGE

R C

ALL

OFF

Enlargement A

See Enlargement A

Dwg. EP-006-16

BRIDGE ON

SOURCE OFF

ALL OFF

Dual Full-Bridge PWM Motor Driver

A3966

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Load Current Regulation. Due to internal logic and

switching delays, td , the actual load current peak will be

slightly higher than the ITRIP value. These delays, plus the

blanking time, limit the minimum value the current control

circuitry can regulate. To produce zero current in a wind-

ing, the ENABLE terminal should be held high, turning off

all output drivers for that full-bridge.

Logic Inputs. A logic high on the PHASE input results

in current ﬂ owing from OUTA to OUTB of that full-bridge.

A logic low on the PHASE input results in current ﬂ owing

from OUTB to OUTA. An internally generated dead time,

tcodt , of approximately 1 μs prevents crossover-current

spikes that can occur when switching the PHASE input.

A logic high on the ENABLE input turns off all four

output drivers of that full-bridge. This results in a fast cur-

rent decay through the internal ground clamp and ﬂ yback

diodes. A logic low on the ENABLE input turns on the

selected source and sink driver of that full-bridge.

The ENABLE inputs can be pulse-width modulated

for applications that require a fast current-decay PWM. If

external current-sensing circuitry is used, the internal cur-

rent-control logic can be disabled by connecting the RTCT

terminal to ground.

The REFERENCE input voltage is typically set with a

resistor divider from VCC. This reference voltage is inter-

nally divided down by 4 to set up the current-comparator

trip-voltage threshold. The reference input voltage range is

0 to 2 V.

Output Drivers. To minimize on-chip power dissipa-

tion, the sink drivers incorporate a Satlington structure.

The Satlington output combines the low VCE(sat) features

of a saturated transistor and the high peak-current capabil-

ity of a Darlington (connected) transistor. A graph showing

typical output saturation voltages as a function of output

current is on page 5.

Miscellaneous Information. Thermal protection

circuitry turns off all output drivers should the junction

temperature reach 165 °C typical. This is intended only to

protect the device from failures due to excessive junction

temperatures and should not imply that output short circuits

are permitted. Normal operation is resumed when the junc-

tion temperature has decreased about 15°C.

The A3966 current control employs a ﬁ xed-frequency,

variable duty cycle PWM technique. As a result, the cur-

rent-control regulation may become unstable if the duty

cycle exceeds 50%.

To minimize current-sensing inaccuracies caused by

ground trace IR drops, each current-sensing resistor should

have a separate return to the ground terminal of the device.

For low-value sense resistors, the I x R drops in the printed-

wiring board can be signiﬁ cant and should be taken into ac-

count. The use of sockets should be avoided as their contact

resistance can cause variations in the effective value of RS.

The LOAD SUPPLY terminal, VBB, should be decou-

pled with an electrolytic capacitor (47 μF recommended)

placed as close to the device as physically practical. To

minimize the effect of system ground I x R drops on the

logic and reference input signals, the system ground should

have a low-resistance return to the load supply voltage.

The frequency of the clock oscillator will determine the

amount of ripple current. A lower frequency will result in

higher current ripple, but reduced heating in the motor and

driver IC due to a corresponding decrease in hysteretic core

losses and switching losses respectively. A higher frequen-

cy will reduce ripple current, but will increase switching

losses and EMI.

FUNCTIONAL DESCRIPTION (continued)

Dual Full-Bridge PWM Motor Driver

A3966

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Package LB, 16-pin SOICW

Satlington® is a registered trademark of Allegro MicroSystems, Inc. (Allegro), and Satlington devices are manufactured under U. S. Patent

No. 5,684,427.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-

mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;

nor for any in fringe ment of patents or other rights of third parties which may result from its use.

For the latest version of this document, visit our website:

www.allegromicro.com

9.50

0.65

2.25

1.27

SEATING

PLANE

C0.10

16X

1.27

0.25

0.20 ±0.10

0.41 ±0.10 2.65 MAX

10.30±0.33

7.50±0.10

4° ±4

0.27 +0.07

–0.06

0.84 +0.44

–0.43

10.30±0.20

GAUGE PLANE

SEATING PLANE

For Reference Only

Pins 4 and 13 fused internally

Dimensions in millimeters

(reference JEDEC MS-013 AA)

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

ATerminal #1 mark area

BReference pad layout (reference IPC SOIC127P1030X265-16M)

All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary

to meet application process requirements and PCB layout tolerances

BPCB Layout Reference View