(1) PERICOM PI74FCT16373T PI74FCT162373T PI74FCT162H373T Product Features: Common Features: PI74FCT16373T, PI74FCT162373T, and PI74FCT 162H373T are high-speed, low power devices with high current drive. * Vee =5V 410% Hysteresis on all inputs Packages available: 48-pin 240 mil wide plastic TSSOP (A48) ~ 48-pin 300 mil wide plastic SSOP (V48) PI74FCT16373T Features: * High output drive: lon = -32 mA; Jot = 64 mA Power off disable outputs permit live insertion * Typical Votp (Output Ground Bounce) < |.0V at Vcc = 5V, Ta = 25C PI74FCT162373T Features: Balanced output drivers: +24 mA * Reduced system switching noise Typical Voip (Output Ground Bounce) < 0.6V at Vcc = 5V, Ta = 25C PI74FCT162H373T Features: * Bus Hold retains last active bus state during 3-state * Eliminates the need for external pull-up resistors Fast CMOS 16-Bit Transparent Latches Product Description: Pericom Semiconductors PI74FCT series of logic circuits are pro- duced in the Companys advanced 0.6 micron CMOS technology, achieving industry leading speed grades. The PI74FCT 16373T, PI74FCT162373T, and PI74FCT 162H373T are |6-bit transparent latches designed with 3-state outputs and are intended for bus oriented applications. The Output Enable and Latch Enable controls are organized to operate as two 8-bit latches or one |6-bitlatch. When Latch Enable (LE) is HIGH, the flip-flops appear transparent to the data. The data that meets the set-up time when LE is LOW is latched. When OE is HIGH, the bus output is in the high impedance state. The PI74FCT16373T output buffers are designed with a Power- Off disable allowing live insertion of boards when used as backplane drivers. The PI74FCT162373T has 24 mA balanced output drivers. It is designed with current limiting resistors at its outputs to control the output edge rate resulting in lower ground bounce and undershoot. This eliminates the need for external terminating resistors for most interface applications. The PI74FCT162H373T has Bus Hold which retains the inputs last state whenever the input goes to high-impedance preventing floating inputs and eliminating the need for pull-up/down resistors. Logic Block Diagram 10E _> 20E .]> iLE 2LE q q 1Do D 2Do D O- 100 O 200 Cc c v Y __ ne TO 7 OTHER CHANNELS TO 7 OTHER CHANNELS 187 PS2033A 03/11/96(1) PERICOM PI74FCT16373/162373/162H373T 16-BIT TRANSPARENT LATCHES Product Pin Description Truth Table Pin Name Description Inputs Outputs xOE Output Enable Inputs (Active LOW) xDx xOE xLE xOx xLE Latch Enable Inputs (Active HIGH) H L H H xDx Inputs L L H L xOx 3-State Outputs Xx H X Z GND Ground Note: 1. H=High Voltage Level, X = Dont Care, L = Low Voc Power Voltage Level, Z = High Impedance Note: |. For the PI74FCT162H373T, these pins have Bus Hold. All other pins are standard, outputs, or I/Os. Product Pin Configuration 10 (110 100 (7 101 GND (] 102 [7] 103 (J vec (J 104 [7] 105 ([] GND] 10 48.PIN 106 (1 v48 107] 12 A48 200 [FJ 13 201 [[] 14 GND [[] 15 202] 16 203 (FJ 17 vec [-] 18 204 [FJ 19 205 [[] 20 GND [_] 21 206 (| 22 207 [J 23 20E [[] 24 oon N DO RB wD HY = 48 47 46 45 44 43 42 4 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 [_] 1L [_] 1Do [_] 101 [_] GND [J 1D2 [_] 103 [_] Vcc [_] 1D4 [_] 1Ds [_] GND [_] 106 [_] 107 [__] 2Do [_] 201 [_] GND [_] 2b2 [_] 2D3 [_] vec [_] 2D4 [_] 2D5 [_] GND [__] 2D6 [_] 207 [_] 2LE 188 PS2033A 03/11/96(1) PERICOM Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) PI74FCT16373/162373/162H373T 16-BIT TRANSPARENT LATCHES 0, Note: Storage Temperature .......... ccc cseeseeseeresscesseseeesseeseesaeeseneasaes 65C to +150C Stresses greater than those listed under Ambient Temperature with Power Applied 0.0... eeeeecneenerens 40Cto+85C | MAXIMUM RATINGS may cause permanent . . . damage to the device. This is a stress ratin Supply Voltage to Ground Potential (Inputs & Vcc Only) ............ -0.5V to+7.0V only avd functional operation of the devic at Supply Voltage to Ground Potential (Outputs & D/O Only)........... O0.5Vto+7.0V | these or any other conditions above those DC Input Voltage .......ceccssccssescssescnsscsceceneccaeessecsseceuvesueessscenenesnseenes -0.5Vto+7.0V | indicated in the operational sections of this specification is not implied. Exposure to DC Output Current 120mA | absolute maximum rating conditions for Power Dissipation .........ccccscssessscsesceeseecenseseeessseecansceceseesvseaeseesacsesvseaeseseaeseaees 1.0W | extended periods may affect reliability. DC Electrical Characteristics (Over the Operating Range, TA = 40C to +85C, Vcc = 5.0V + 10%) Parameters | Description Test Conditions Min. | Typ | Max | Units Vin Input HIGH Voltage Guaranteed Logic HIGH Level 20 Vv Vit Input LOW Voltage Guaranteed Logic LOW Level 08 v TH Input HIGH Current Standard Input, Vcc = Max. Vin= Vcc 1 HA GH Input HIGH Current Standard I/O, Vcc = Max. Vin= Vcc 1 HA lin Input HIGH Current Bus Hold Input, Vcc = Max. Vin=Vec +100 HA hn Input HIGH Current Bus Hold /O, Vcc = Max. | Vin= Vee +100 | pA | Ii Input LOW Current Standard Input, Vcc = Min. Vin=GND -l pA hit Input LOW Current Standard I/O, Vcc= Min. Vin=GND -l BA fit Input LOW Current Bus Hold Input", Vcc = Min. Vin=GND +100 pA Tit Input LOW Current Bus Hold /O, Vcc = Min. Vin=GND +100 HA TsHH Bus Hold Bus Hold Input, Vcc = Min. Vin=2.0V 50 HA TBHL Sustain Current Vin=0.8V +50 IozH" High Impedance Vcc= Max. VouT=2.7V 1 pA loz Output Current Vec=Max. Vout=0.5V -l HA ViK Clamp Diode Voltage Vec=Min., In=-I18mA -0.7 1.2 Vv los Short Circuit Current Vec=Max., VouT=GND -80 -140 | -200 mA Io Output Drive Current Vec= Max. VouT=2.5V ~50 -180 mA Vu , Input Hysteresis 100 mV Notes: . Typical values are at Vcc = 5.0V, +25C ambient and maximum loading. . Pins with Bus Hold are identified in the pin description. Mb wD . This specification does not apply to bi-directional functionalities with Bus Hold. . For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. . Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 189 PS2033A 03/11/96(1) PERICOM PI74FCT16373/162373/162H373T 16-BIT TRANSPARENT LATCHES PI74FCT16373T Output Drive Characteristics (Over the Operating Range) Parameters | Description Test Conditions Min. | Typ | Max ~~ Units Vou Output HIGH Voltage =| Vcc=Min., VIN= Vinor Vit lon =-3.0 mA 25 3.5 v | Ion=-15.0mA 24 35 a a Tou =32.0 mA 2.0 3.0 - Vou ___| Output LOW Voltage |_| Vcc = Min., Vin = Vin or Vi | Tou = 64 mA 02 | 058 VV | lorF Power Down Disable Vcc=0V, Vinor VouTS4.5V _ +100 pA PI74FCT 162373T/162H373T Output Drive Characteristics (Over the Operating Range) Parameters | Description Test Conditions' Min. | Typ? | Max. | Units Vou Output HIGH Voltage | Vec=Min., ViIN= Vinor VIL lou =-24.0mA 24 33 Vv VoL Output LOW Voltage | Vcc=Min., Vin= Vidor Vit loL=24mA _ 03 O55 | Vo | lop. Output LOW Current | Vec=5V, Vin= Vinor Vit, VouT= sve _ | | 15 150 mA lopx OutputHIGHCurrent =| Vec=5V, Vin= Vinor VIL, Vout= |.5V" -60 -115 | -150 mA Capacitance (Ta = 25C, f = | MHz) Parameters Description Test Conditions Typ Max. Units Cin Input Capacitance _ __ Vin=0V 45 6 pF Cour Output Capacitance Vout = 0V 5.5 8 pF Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is determined by device characterization but is not production tested. 190 PS2033A 03/11/96() PER ICOM PI74FCT16373/162373/162H373T 16-BIT TRANSPARENT LATCHES Power Supply Characteristics Parameters| Description Test Conditions"! Min. | Typ| Max. | Units Icc Quiescent Power Vcc = Max. Vin = GND or Vec 0.1 500 pA Supply Current Alcc Supply Current per Vcc = Max. Vin = 3.4V?) 0.5 L5 mA Input @ TTL HIGH Iccp . Supply Current per Vcc = Max., VIN = Vcc 60 100 pA/ Input per MHz'*? Outputs Open Vin = GND MHz xOE = GND, xLE = Vec One Bit Toggling 50% Duty Cycle Ic Total Power Supply Vcc = Max., Vin = Vcc 0.6 15 | mA Current Outputs Open Vin = GND fi = 10 MHz 50% Duty Cycle xOE = GND, xLE = Vcc One Bit Toggling Vine34V00 0.9 | 23 | Vin = GND Vcc = Max., Vin = Vee 24 | 45% Outputs Open Vin = GND ft = 2.5 MHz 50% Duty Cycle xOE = GND, xLE = Vec 16 Bits Toggling Vin = 3.4V 6.4 16.5 Vin = GND Notes: |. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device. 2. Typical values are at Vec = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested. 6. Ic =IQuiesceNT + [inputs + IDYNAMIC Ic = Icc + Alcc DHNt + Iccp (fce/2 + fiNi) Icc = Quiescent Current Alcc = Power Supply Current for a TTL High Input (Vin = 3.4V) Du = Duty Cycle for TTL Inputs High Nr = Number of TTL Inputs at Du Iccb = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fcr = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz. 191 PS2033A 03/11/96PI74FCT16373/162373/162H373T () P ER / COM 16-BIT TRANSPARENT LATCHES PI74FCT16373T Switching Characteristics over Operating Range 16373T 16373AT 16373CT 16373DT 16373ET Com. Com. Com. Com. Com. Parameters Description Conditions" Min | Max | Min | Max | Min | Max | Min | Max | Min | Max | Unit tPLH Propagation Delay CL=50pF IS | 80 |} 15 | 52 ] 15 | 42 | IS | 38 | 15 | 34 | os CPHL xDx toxOx Ri=500Q tPLH Propagation Delay 2.0 | 13.0] 2.0) 85 | 20] 55 | 15 | 40 | 15 | 3.7 |] as (PHL xLE to xOx (P7H Output Enable Time LS |] 120) 15 | 65 15 ] 5.5 15 | 48 1S | 44 ns {PZ xOE to xOx (Paz OutputDisableTime is | 75 | 18 | 55] 15] 50] 15 | 40 | 15 | 40 | os {PLZ xOEtoxOx tsu Setup Time HIGH 20 | | 20} | 20] ~ |] 15] LO} ns or LOW, xDx to xLE tu Hold Time HIGH 1s] ] 15} ] ts} |] 10] | 10} | os or LOW, xDx to xLE tw xLE Pulse Width 60 |] | 50); | 50] | 30) | 30] ns HIGH" tsk(o) Output Skew |o05)/]05)/] 05] ] 05 | ] 05 | ns PI74FCT162373T Switching Characteristics over Operating Range 162373T 162373AT | 162373CT | 162373DT | 162373ET Com. Com, Com. Com. Com. Parameters Description Conditions" Min | Max | Min | Max | Min | Max | Min | Max | Min | Max | Unit tPLH Propagation Delay Ci =50pF 15 | 80] IS | 52 15 | 42 | 15 | 38 (5 | 34 | ns {PHL xDxtoxOx RL=500Q tPLH Propagation Delay 2.0 | 130] 20 | 85 | 20) 55 |] 15 | 40 |] 15 ) 3.7 |] os tPHL xLE to xOx tre Output Enable Time 15] 120) 15 | 65 | 15 | 55 |] 15 |] 48 7] 1S | 44 | ns tei xOE to xOx tPH7. Output Disable Time' 15S | 75 5] 55 IS | 50 1S | 40 [5 | 40 | ns tPLz xOEtoxOx tsu Setup Time HIGH 20] | 20) | 20} ] 15] | LO] ns or LOW, xDx to xLE tH Hold Time HIGH 15} |] ls] ] 15} ] 107; | lO] ns or LOW, xDx to xLE tw xLE Pulse Width 60} | 50) | 50} | 30) | 30] ns HIGH tsk(o) Output Skew |05;}/ ]05} |] 05] ] 05) ] 05 | ns Notes: 1. See test circuit and wave forms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not production tested. 4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design. 192 PS2033A 03/11/96(1) PERICOM PI74FCT16373/162373/162H373T 16-BIT TRANSPARENT LATCHES PI74FCT162H373T Switching Characteristics over Operating Range 162H373T | 162H373AT | 162H373CT | 162H373DT | 162H373ET Com. Com. Com. Com. Com. Parameters Description Conditions | Min | Max | Min | Max | Min | Max | Min | Max | Min | Max | Unit tPLH Propagation Delay Cu = 50 pF 15 | 80) 15 | 52] 15] 42 ] 15 | 38! 15 { 34 ] os tPHL xDx to xOx Ri =5002 tPLH Propagation Delay 2.0 | 13.0] 20] 85 | 20) 55 ] 15 | 40] 15] 3.7 | ns tPHL xLE to xOx tz Output Enable Time 15] 120) 15 | 65 | 15] 55 ] 15 | 487 15 | 44 |] ns trz. xOE to xOx tpHz Output Disable Time 15] 75 ] 15 | 55 | 15 | 50] 15 |] 404 15] 40] os tPLz xOE to xOx tsu Setup Time HIGH 20] |} 20) } 207) 7] 1s) |] lo) ns or LOW, xDx to xLE tH Hold Time HIGH 5S} ] 15} }] 15) |] 10} J 10] 7] os or LOW, xDx to xLE tw xLE Pulse Width 60} | 50) | 50] | 30] | 30] | ns HIGH (sK{o) Output Skew? |05/] | 05S | 05 | 05; 1] 05 ns Notes: 1. See test circuit and wave forms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not production tested. 4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design. Pericom Semiconductor Corporation 2380 Bering Drive + San Jose, CA 95131 1-800-435-2336 * Fax (408) 435-1100 http:/Awww.pericom.com 193 PS2033A 03/11/96