GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
72Mb Pipelined and Flow Through
Synchronous NBT SRAM
300 MHz–167 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
119- & 209-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.03a 2/2009 1/35 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119- or 209-bump BGA package
• RoHS-compliant 119- and 209-bump BGA packages
available
Functional Description
The GS8642Z18/36/72 is a 72Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8642Z18/36/72 may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8642Z18/36/72 is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump, 165-bump or 209-bump BGA package.
Parameter Synopsis
-300 -250 -200 -167 Unit
Pipeline
3-1-1-1
tKQ(x18/x36)
tKQ(x72)
tCycle
2.3
3.0
3.3
2.5
3.0
4.0
3.0
3.0
5.0
3.4
3.4
6.0
ns
ns
ns
Curr (x18)
Curr (x36)
Curr (x72)
400
480
590
340
410
520
290
350
435
260
305
380
mA
mA
mA
Flow Through
2-1-1-1
tKQ
tCycle
5.5
5.5
6.5
6.5
7.5
7.5
8.0
8.0
ns
ns
Curr (x18)
Curr (x36)
Curr (x72)
285
330
425
245
280
370
220
250
315
210
240
300
mA
mA
mA
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 2/35 © 2004, GSI Technology
GS8642Z72C Pad Out–209-Bump BGA—Top View (Package C)
12345678910 11
ADQGDQGAE2 AADV AE3 ADQBDQBA
BDQGDQGBC BG NC W A BB BF DQBDQBB
CDQGDQGBH BD NC E1 NC BE BA DQBDQBC
DDQGDQGVSS NC NC GNC NC VSS DQBDQBD
EDQPGDQPCVDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPFDQPBE
FDQCDQCVSS VSS VSS ZQ VSS VSS VSS DQFDQFF
GDQCDQCVDDQ VDDQ VDD MCH VDD VDDQ VDDQ DQFDQFG
HDQCDQCVSS VSS VSS MCL VSS VSS VSS DQFDQFH
JDQCDQCVDDQ VDDQ VDD MCH VDD VDDQ VDDQ DQFDQFJ
KNC NC CK NC VSS CKE VSS NC NC NC NC K
LDQHDQHVDDQ VDDQ VDD FT VDD VDDQ VDDQ DQADQAL
MDQHDQHVSS VSS VSS MCL VSS VSS VSS DQADQAM
NDQHDQHVDDQ VDDQ VDD MCH VDD VDDQ VDDQ DQADQAN
PDQHDQHVSS VSS VSS ZZ VSS VSS VSS DQADQAP
RDQPDDQPHVDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPADQPER
TDQDDQDVSS NC NC LBO NC NC VSS DQEDQET
UDQDDQDNC AAAAANC DQEDQEU
VDQDDQDAAAA1 A A A DQEDQEV
WDQDDQDTMS TDI AA0 ATDO TCK DQEDQEW
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 3/35 © 2004, GSI Technology
GS8642Z72 209-Bump BGA Pin Description
Symbol Type Description
A0, A1IAddress field LSBs and Address Counter Preset Inputs
An IAddress Inputs
DQA
DQB
DQC
DQD
DQE
DQF
DQG
DQH
I/O Data Input and Output pins
BA, BBIByte Write Enable for DQA, DQB I/Os; active low
BC,BDIByte Write Enable for DQC, DQD I/Os; active low
BE, BF, BG,BHIByte Write Enable for DQE, DQF, DQG, DQH I/Os; active low
NC —No Connect
CK IClock Input Signal; active high
E1IChip Enable; active low
E3IChip Enable; active low
E2IChip Enable; active high
GIOutput Enable; active low
ADV IBurst address counter advance enable
ZZ ISleep Mode control; active high
FT IFlow Through or Pipeline mode; active low
LBO ILinear Burst Order mode; active low
MCH IMust Connect High
MCH IMust Connect High
MCL Must Connect Low
WIWrite Enable; active low
ZQ I
FLXDrive Output Impedance Control
Low = Low Impedance [High Drive],
High = High Impedance [Low Drive]
CKE IClock Enable; active low
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 4/35 © 2004, GSI Technology
TMS IScan Test Mode Select
TDI IScan Test Data In
TDO OScan Test Data Out
TCK IScan Test Clock
VDD ICore power supply
VSS II/O and Core Ground
VDDQ IOutput driver power supply
GS8642Z72 209-Bump BGA Pin Description
Symbol Type Description
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 5/35 © 2004, GSI Technology
GS8642Z36B Pad Out–119-Bump BGA—Top View
1234567
A VDDQ A A A A A VDDQ A
BNC E2 AADV AE3 NC B
CNC A A VDD A A NC C
DDQC DQPC VSS ZQ VSS DQPB DQB D
EDQC DQC VSS E1 VSS DQB DQB E
F VDDQ DQC VSS G VSS DQB VDDQ F
GDQC DQC BC ABB DQB DQB G
HDQC DQC VSS W VSS DQB DQB H
J VDDQ VDD NC VDD NC VDD VDDQ J
KDQD DQD VSS CK VSS DQA DQA K
LDQD DQD BD NC BA DQA DQA L
M VDDQ DQD VSS CKE VSS DQA VDDQ M
NDQD DQD VSS A1 VSS DQA DQA N
PDQD DQPD VSS A0 VSS DQPA DQA P
RNC ALBO VDD FT ANC R
TNC AAAAAZZ T
U VDDQ TMS TDI TCK TDO NC VDDQ U
7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 6/35 © 2004, GSI Technology
GS8642Z18B Pad Out–119-Bump BGA—Top View
1234567
A VDDQ A A A A A VDDQ A
BNC E2 AADV AE3 NC B
CNC A A VDD A A NC C
DDQB NC VSS ZQ VSS DQPA NC D
ENC DQB VSS E1 VSS NC DQA E
F VDDQ NC VSS G VSS DQA VDDQ F
GNC DQB BB ANC NC DQA G
HDQB NC VSS W VSS DQA NC H
J VDDQ VDD NC VDD NC VDD VDDQ J
KNC DQB VSS CK VSS NC DQA K
LDQB NC NC NC BA DQA NC L
M VDDQ DQB VSS CKE VSS NC VDDQ M
NDQB NC VSS A1 VSS DQA NC N
PNC DQPB VSS A0 VSS NC DQA P
RNC ALBO VDD FT ANC R
TAAAAAAZZ T
U VDDQ TMS TDI TCK TDO NC VDDQ U
7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 7/35 © 2004, GSI Technology
BPR1999.05.18
GS8642Z18/36 119-Bump BGA Pin Description
Symbol Type Description
A0, A1IAddress field LSBs and Address Counter Preset Inputs
An IAddress Inputs
DQA
DQB
DQC
DQD
I/O Data Input and Output pins
BA, BB, BC, BDIByte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
NC —No Connect
CK IClock Input Signal; active high
CKE IClock Enable; active low
W I Write Enable; active low
E1IChip Enable; active low
E3IChip Enable; active low
E2IChip Enable; active high
G I Output Enable; active low
ADV IBurst address counter advance enable
ZZ ISleep mode control; active high
FT IFlow Through or Pipeline mode; active low
LBO ILinear Burst Order mode; active low
ZQ IFLXDrive Output Impedance Control
Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
TMS IScan Test Mode Select
TDI IScan Test Data In
TDO OScan Test Data Out
TCK IScan Test Clock
VDD ICore power supply
VSS II/O and Core Ground
VDDQ IOutput driver power supply
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 8/35 © 2004, GSI Technology
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write
cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Function W BABBBCBD
Read H X X X X
Write Byte “a” L L H H H
Write Byte “b” L H L H H
Write Byte “c” L H H L H
Write Byte “d” L H H H L
Write all Bytes L L L L L
Write Abort/NOP L H H H H
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 9/35 © 2004, GSI Technology
Synchronous Truth Table
Operation Type Address CK CKE ADV WBx E1E2E3GZZ DQ Notes
Read Cycle, Begin Burst RExternal L-H L L H X L H L L L Q
Read Cycle, Continue Burst BNext L-H L H X X X X X L L Q 1,10
NOP/Read, Begin Burst RExternal L-H L L H X L H L H L High-Z 2
Dummy Read, Continue Burst BNext L-H L H X X X X X H L High-Z 1,2,10
Write Cycle, Begin Burst WExternal L-H L L L L L H L X L D 3
Write Abort, Begin Burst DNone L-H L L L H L H L X L High-Z 1
Write Cycle, Continue Burst BNext L-H L H X L X X X X L D 1,3,10
Write Abort, Continue Burst BNext L-H L H X H X X X X L High-Z 1,2,3,10
Deselect Cycle, Power Down DNone L-H L L X X H X X X L High-Z
Deselect Cycle, Power Down DNone L-H L L X X X X H X L High-Z
Deselect Cycle, Power Down DNone L-H L L X X X L X X L High-Z
Deselect Cycle, Continue DNone L-H L H X X X X X X L High-Z 1
Sleep Mode None X X X X X X X X X H High-Z
Clock Edge Ignore, Stall Current L-H H X X X X X X X L - 4
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-
lect cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 10/35 © 2004, GSI Technology
Pipelined and Flow Through Read Write Control State Diagram
Deselect
New Read New Write
Burst Read Burst Write
W
R
B
R
B
W
DD
B
B
W
R
DB
W
R
DD
Current State (n) Next State (n+1)
Transition
ƒ
Input Command Code
Key Notes
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Synchronous Truth Table.
Clock (CK)
Command
Current State Next State
ƒ
n n+1 n+2 n+3
ƒƒƒ
Current State and Next State Definition for Pipelined and Flow through Read/Write Control State Diagram
WR
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 11/35 © 2004, GSI Technology
Pipeline Mode Data I/O State Diagram
Intermediate Intermediate
Intermediate
Intermediate Intermediate
Intermediate
High Z
(Data In)
Data Out
(Q Valid)
High Z
BWB
R
B
D
R
W
R
W
DD
Current State (n) Next State (n+2)
Transition
ƒ
Input Command Code
Key
Transition
Intermediate State (N+1)
Notes
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Clock (CK)
Command
Current State Intermediate
ƒ
n n+1 n+2 n+3
ƒƒƒ
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Next State
State
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 12/35 © 2004, GSI Technology
Flow Through Mode Data I/O State Diagram
High Z
(Data In)
Data Out
(Q Valid)
High Z
BWB
R
B
D
R
W
R
W
DD
Current State (n) Next State (n+1)
Transition
ƒ
Input Command Code
Key Notes
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Clock (CK)
Command
Current State Next State
ƒ
n n+1 n+2 n+3
ƒƒƒ
Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 13/35 © 2004, GSI Technology
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
FLXDrive™
The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive
strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.
Note:
There are pull-up deviceson the ZQ and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip
will operate in the default states as specified in the above tables.
Mode Pin Functions
Mode Name Pin Name State Function
Burst Order Control LBO LLinear Burst
HInterleaved Burst
Output Register Control FT LFlow Through
H or NC Pipeline
Power Down Control ZZ L or NC Active
H Standby, IDD = ISB
FLXDrive Output Impedance Control ZQ LHigh Drive (Low Impedance)
H or NC Low Drive (High Impedance)
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 14/35 © 2004, GSI Technology
Burst Counter Sequences
BPR 1999.05.18
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal. Not
all vendors offer this option, however most mark the pin VDD or VDDQ on pipelined parts and VSS on flow through parts. GSI NBT
SRAMs are fully compatible with these sockets. Other vendors mark the pin as a No Connect (NC). GSI RAMs have an internal
pull-up device on the FT pin so a floating FT pin will result in pipelined operation. If the part being replaced is a pipelined mode
part, the GSI RAM is fully compatible with these sockets. In the unlikely event the part being replaced is a Flow Through device,
the pin will need to be pulled low for correct operation.
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 10 11 00
3rd address 10 11 00 01
4th address 11 00 01 10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01
4th address 11 10 01 00
tZZR
tZZHtZZS
tKLtKL
tKHtKH
tKCtKC
CK
ZZ
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 15/35 © 2004, GSI Technology
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol Description Value Unit
VDD Voltage on VDD Pins –0.5 to 4.6 V
VDDQ Voltage in VDDQ Pins –0.5 to 4.6 V
VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 ( 4.6 V max.) V
VIN Voltage on Other Input Pins –0.5 to VDD +0.5 ( 4.6 V max.) V
IIN Input Current on Any Pin +/–20 mA
IOUT Output Current on Any I/O Pin +/–20 mA
PDPackage Power Dissipation 1.5 W
TSTG Storage Temperature –55 to 125 oC
TBIAS Temperature Under Bias –55 to 125 oC
Power Supply Voltage Ranges
Parameter Symbol Min. Typ. Max. Unit Notes
3.3 V Supply Voltage VDD3 3.0 3.3 3.6 V
2.5 V Supply Voltage VDD2 2.3 2.5 2.7 V
3.3 V VDDQ I/O Supply Voltage VDDQ3 3.0 3.3 3.6 V
2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 2.7 V
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 16/35 © 2004, GSI Technology
VDDQ3 Range Logic Levels
Parameter Symbol Min. Typ. Max. Unit Notes
VDD Input High Voltage VIH 2.0 —VDD + 0.3 V 1
VDD Input Low Voltage VIL –0.3 —0.8 V 1
VDDQ I/O Input High Voltage VIHQ 2.0 —VDDQ + 0.3 V1,3
VDDQ I/O Input Low Voltage VILQ –0.3 —0.8 V1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
VDDQ2 Range Logic Levels
Parameter Symbol Min. Typ. Max. Unit Notes
VDD Input High Voltage VIH 0.6*VDD —VDD + 0.3 V 1
VDD Input Low Voltage VIL –0.3 —0.3*VDD V 1
VDDQ I/O Input High Voltage VIHQ 0.6*VDD —VDDQ + 0.3 V1,3
VDDQ I/O Input Low Voltage VILQ –0.3 —0.3*VDD V1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Recommended Operating Temperatures
Parameter Symbol Min. Typ. Max. Unit Notes
Ambient Temperature (Commercial Range Versions) TA025 70 C 2
Ambient Temperature (Industrial Range Versions) TA–40 25 85 C 2
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 17/35 © 2004, GSI Technology
Note:
These parameters are sample tested.
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
Parameter Symbol Test conditions Typ. Max. Unit
Input Capacitance CIN VIN = 0 V 4 5 pF
Input/Output Capacitance CI/O VOUT = 0 V 6 7 pF
AC Test Conditions
Parameter Conditions
Input high level VDD – 0.2 V
Input low level 0.2 V
Input slew rate 1 V/ns
Input reference level VDDQ/2
Output reference level VDDQ/2
Output load Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
20% tKC
VSS – 2.0 V
50%
VSS
VIH
Undershoot Measurement and Timing Overshoot Measurement and Timing
20% tKC
VDD + 2.0 V
50%
VDD
VIL
DQ
VDDQ/2
5030pF*
Output Load 1
* Distributed Test Jig Capacitance
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 18/35 © 2004, GSI Technology
DC Electrical Characteristics
Parameter Symbol Test Conditions Min Max
Input Leakage Current
(except mode pins) IIL VIN = 0 to VDD –2 uA 2 uA
ZZInput Current IIN1
VDD VIN VIH
0 V VIN VIH
–1 uA
–1 uA
1 uA
100 uA
Output Leakage Current (x36/x72) IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA
Output Leakage Current (x18) IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA
Output High Voltage VOH2 IOH = –8 mA, VDDQ = 2.375 V 1.7 V —
Output High Voltage VOH3 IOH = –8 mA, VDDQ = 3.135 V 2.4 V —
Output Low Voltage VOL IOL = 8 mA —0.4 V
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 19/35 © 2004, GSI Technology
Notes:
1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation.
2. All parameters listed are worst case scenario.
Operating Currents
Parameter Test Conditions Mode Symbol
-300 -250 -200 -167
Unit
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
Operating
Current
Device Selected;
All other inputs
VIH or VIL
Output open
(x72)
Pipeline IDD
IDDQ
520
70
540
70
460
60
480
60
385
50
405
50
340
40
360
40 mA
Flow
Through
IDD
IDDQ
375
50
385
50
330
40
340
40
285
30
295
30
270
30
280
30 mA
(x32/
x36)
Pipeline IDD
IDDQ
420
60
440
60
360
50
380
50
310
40
330
40
270
35
290
35 mA
Flow
Through
IDD
IDDQ
300
30
320
30
255
25
275
25
230
20
250
20
220
20
240
20 mA
(x18)
Pipeline IDD
IDDQ
370
30
390
30
315
25
335
25
270
20
290
20
240
20
260
20 mA
Flow
Through
IDD
IDDQ
270
15
290
15
230
15
250
15
205
15
225
15
195
15
215
15 mA
Standby
Current ZZ VDD – 0.2 V —
Pipeline ISB 100 120 100 120 100 120 100 120 mA
Flow
Through ISB 100 120 100 120 100 120 100 120 mA
Deselect
Current
Device Deselected;
All other inputs
VIH or VIL
—
Pipeline IDD 150 165 140 155 130 146 125 140 mA
Flow
Through IDD 135 150 125 140 120 135 120 135 mA
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 20/35 © 2004, GSI Technology
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
AC Electrical Characteristics
Parameter Symbol -300 -250 -200 -167 Unit
Min Max Min Max Min Max Min Max
Pipeline
Clock Cycle Time tKC 3.3 —4.0 —5.0 —6.0 —ns
Clock to Output Valid
(x18/x36) tKQ —2.3 —2.5 —3.0 —3.4 ns
Clock to Output Valid
(x72) tKQ —3.0 —3.0 —3.0 —3.4 ns
Clock to Output Invalid tKQX 1.5 —1.5 —1.5 —1.5 —ns
Clock to Output in Low-Z tLZ11.5 —1.5 —1.5 —1.5 —ns
Setup time tS 1.1 —1.2 —1.4 —1.5 —ns
Hold time tH 0.1 —0.2 —0.4 —0.5 —ns
Flow
Through
Clock Cycle Time tKC 5.5 —6.5 —7.5 —8.0 —ns
Clock to Output Valid tKQ —5.5 —6.5 —7.5 —8.0 ns
Clock to Output Invalid tKQX 3.0 —3.0 —3.0 —3.0 —ns
Clock to Output in Low-Z tLZ13.0 —3.0 —3.0 —3.0 —ns
Setup time tS 1.5 —1.5 —1.5 —1.5 —ns
Hold time tH 0.5 —0.5 —0.5 —0.5 —ns
Clock HIGH Time tKH 1.0 —1.3 —1.3 —1.3 —ns
Clock LOW Time tKL 1.2 —1.5 —1.5 —1.5 —ns
Clock to Output in
High-Z (x18/x36) tHZ11.5 2.3 1.5 2.5 1.5 3.0 1.5 3.0 ns
Clock to Output in
High-Z (x72) tHZ11.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 ns
G to Output Valid
(x18/x36) tOE —2.3 —2.5 —3.0 —3.5 ns
G to Output Valid
(x72) tOE —3.0 —3.0 —3.0 —3.5 ns
G to output in Low-Z tOLZ10—0—0—0—ns
G to output in High-Z
(x18/36) tOHZ1—2.3 —2.5 —3.0 —3.0 ns
G to output in High-Z
(x72) tOHZ1—3.0 —3.0 —3.0 —3.0 ns
ZZ setup time tZZS25—5—5—5—ns
ZZ hold time tZZH21—1—1—1—ns
ZZ recovery tZZR 20 —20 —20 —20 —ns
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 21/35 © 2004, GSI Technology
Pipeline Mode Timing (NBT)
Write A Read B Suspend Read C Write D Write No-op Read E Deselect
tHZ
tKQXtKQ
tLZtH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tKCtKC
tKLtKL
tKHtKH
AB CD E
D(A) D(D) Q(E)Q(B) Q(C)
CK
A
CKE
E*
ADV
W
Bn
DQ
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 22/35 © 2004, GSI Technology
Flow Through Mode Timing (NBT)
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output
drivers are powered by VDDQ.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
Write A Write B Write B+1 Read C Cont Read D Write E Read F Write G
D(A) D(B) D(B+1) Q(C) Q(D) D(E) Q(F) D(G)
tOLZ
tOE
tOHZ
tKQX
tKQ
tLZtHZ
tKQXtKQ
tLZ
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tKCtKC
tKLtKL
tKHtKH
AB C DEFG
*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1
CK
CKE
E
ADV
W
Bn
A0–An
DQ
G
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 23/35 © 2004, GSI Technology
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG Pin Descriptions
Pin Pin Name I/O Description
TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TMS Test Mode Select In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
TDI Test Data In In
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
TDO Test Data Out Out
Output that is active depending on the state of the TAP state machine. Output changes in
response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 24/35 © 2004, GSI Technology
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Instruction Register
ID Code Register
Boundary Scan Register
012
0
····
31 30 29 12
0
Bypass Register
TDI TDO
TMS
TCK Test Access Port (TAP) Controller
108
·
10
·
·· ······
Control Signals
·
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 25/35 © 2004, GSI Technology
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
ID Register Contents
Die
Revision
Code
Not Used I/O
Configuration
GSI Technology
JEDEC Vendor
ID Code
Presence Register
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
x72 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1
x36 X X X X 0 0 0 X 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1
x32 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 1 1 0 0 1 1
x18 X X X X 0 0 0 X 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1
x16 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 0 1 1
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 26/35 © 2004, GSI Technology
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
Test Logic Reset
Run Test Idle
0
0
1
0
1
1
0
0
1
1
1
0
0
1
1
0
00
0
1
1
0 0
110
0
0
1
111
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 27/35 © 2004, GSI Technology
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
ated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary
Instruction Code Description Notes
EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1
IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2
SAMPLE-Z 010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
1
RFU 011 Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1
SAMPLE/
PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO. 1
GSI 101 GSI private instruction. 1
RFU 110 Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1
BYPASS 111 Places Bypass Register between TDI and TDO. 1
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 28/35 © 2004, GSI Technology
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter Symbol Min. Max. Unit Notes
3.3 V Test Port Input High Voltage VIHJ3 2.0 VDD3 +0.3 V 1
3.3 V Test Port Input Low Voltage VILJ3 –0.3 0.8 V 1
2.5 V Test Port Input High Voltage VIHJ2 0.6 * VDD2 VDD2 +0.3 V 1
2.5 V Test Port Input Low Voltage VILJ2 –0.3 0.3 * VDD2 V 1
TMS, TCK and TDI Input Leakage Current IINHJ –300 1uA 2
TMS, TCK and TDI Input Leakage Current IINLJ –1100 uA 3
TDO Output Leakage Current IOLJ –1 1 uA 4
Test Port Output High Voltage VOHJ 1.7 —V5, 6
Test Port Output Low Voltage VOLJ —0.4 V5, 7
Test Port Output CMOS High VOHJC VDDQ – 100 mV —V5, 8
Test Port Output CMOS Low VOLJC —100 mV V5, 9
Notes:
1. Input Under/overshoot voltage must be –2 V < Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
2. VILJ VIN VDDn
3. 0 V VIN VILJn
4. Output Disable, VOUT = 0 to VDDn
5. The TDO output driver is served by the VDDQ supply.
6. IOHJ = –4 mA
7. IOLJ = + 4 mA
8. IOHJC = –100 uA
9. IOLJC = +100 uA
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
JTAG Port AC Test Conditions
Parameter Conditions
Input high level VDD – 0.2 V
Input low level 0.2 V
Input slew rate 1 V/ns
Input reference level VDDQ/2
Output reference level VDDQ/2
DQ
VDDQ/2
5030pF*
JTAG Port AC Test Load
* Distributed Test Jig Capacitance
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 29/35 © 2004, GSI Technology
JTAG Port Timing Diagram
Boundary Scan (BSDL Files)
For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: apps@gsitechnology.com.
JTAG Port AC Electrical Characteristics
Parameter Symbol Min Max Unit
TCK Cycle Time tTKC 50 —ns
TCK Low to TDO Valid tTKQ —20 ns
TCK High Pulse Width tTKH 20 —ns
TCK Low Pulse Width tTKL 20 —ns
TDI & TMS Set Up Time tTS 10 —ns
TDI & TMS Hold Time tTH 10 —ns
tTH
tTS
tTKQ
tTH
tTS
tTH
tTS
tTKLtTKLtTKHtTKHtTKCtTKC
TCK
TDI
TMS
TDO
Parallel SRAM input
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 30/35 © 2004, GSI Technology
209 BGA Package Drawing (Package C)
14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array
Symbol Min Typ Max Units
A1.70 mm
A1 0.40 0.50 0.60 mm
b0.50 0.60 0.70 mm
c0.31 0.36 0.38 mm
D21.9 22.0 22.1 mm
D1 18.0 (BSC) mm
E13.9 14.0 14.1 mm
E1 10.0 (BSC) mm
e1.00 (BSC) mm
aaa 0.15 mm
Rev 1.0
A
A1
C
be
e
E
E1
D1
D
aaa
Bottom View
Side View
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 31/35 © 2004, GSI Technology
Package Dimensions—119-Bump FPBGA (Package B, Variation 2)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1 2 3 4 5 6 7 7 6 5 4 3 2 1
A1 TOP VIEW A1
BOTTOM VIEW
1.27
7.62
1.27
20.32
14±0.10
22±0.10
B
A
0.20(4x)
Ø0.10
Ø0.30
C
C A B
S
SØ0.60~0.90 (119x)
C
SEATING PLANE
0.15 C
0.50~0.70
1.86.±0.13
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
SS
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 32/35 © 2004, GSI Technology
Package Dimensions—209-Bump BGA (Package C)
14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array
C
11 10 9 8 7 6 5 4 3 2 1
BOTTOM VIEW
Ø0.10
Ø0.30
C
C A B
M
M
Ø0.50~0.70 (209x)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
1.0
1.0
18.0
22.0
B
14.0
A
0.20(4x)
1.0 1.0
10.0
1 2 3 4 5 6 7 8 9 10 11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
A1 CORNER TOP VIEW
SEATING PLANE
0.15 C
0.40~0.60
1.70 MAX.
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 33/35 © 2004, GSI Technology
Ordering Information for GSI Synchronous Burst RAMs
Org Part Number1Type Package Speed2
(MHz/ns) TA3
4M x 18 GS8642Z18B-300 NBT PL/FT 119 BGA (var.2) 300/5.5 C
4M x 18 GS8642Z18B-250 NBT PL/FT 119 BGA (var.2) 250/6.5 C
4M x 18 GS8642Z18B-200 NBT PL/FT 119 BGA (var.2) 200/7.5 C
4M x 18 GS8642Z18B-167 NBT PL/FT 119 BGA (var.2) 167/8 C
2M x 36 GS8642Z36B-300 NBT PL/FT 119 BGA (var.2) 300/5.5 C
2M x 36 GS8642Z36B-250 NBT PL/FT 119 BGA (var.2) 250/6.5 C
2M x 36 GS8642Z36B-200 NBT PL/FT 119 BGA (var.2) 200/7.5 C
2M x 36 GS8642Z36B-167 NBT PL/FT 119 BGA (var.2) 167/8 C
1M x 72 GS8642Z72C-300 NBT PL/FT 209 BGA 300/5.5 C
1M x 72 GS8642Z72C-250 NBT PL/FT 209 BGA 250/6.5 C
1M x 72 GS8642Z72C-200 NBT PL/FT 209 BGA 200/7.5 C
1M x 72 GS8642Z72C-167 NBT PL/FT 209 BGA 167/8 C
4M x 18 GS8642Z18B-300I NBT PL/FT 119 BGA (var.2) 300/5.5 I
4M x 18 GS8642Z18B-250I NBT PL/FT 119 BGA (var.2) 250/6.5 I
4M x 18 GS8642Z18B-200I NBT PL/FT 119 BGA (var.2) 200/7.5 I
4M x 18 GS8642Z18B-167I NBT PL/FT 119 BGA (var.2) 167/8 I
2M x 36 GS8642Z36B-300I NBT PL/FT 119 BGA (var.2) 300/5.5 I
2M x 36 GS8642Z36B-250I NBT PL/FT 119 BGA (var.2) 250/6.5 I
2M x 36 GS8642Z36B-200I NBT PL/FT 119 BGA (var.2) 200/7.5 I
2M x 36 GS8642Z36B-167I NBT PL/FT 119 BGA (var.2) 167/8 I
1M x 72 GS8642Z72C-300I NBT PL/FT 209 BGA 300/5.5 I
1M x 72 GS8642Z72C-250I NBT PL/FT 209 BGA 250/6.5 I
1M x 72 GS8642Z72C-200I NBT PL/FT 209 BGA 200/7.5 I
1M x 72 GS8642Z72C-167I NBT PL/FT 209 BGA 167/8 I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8642Z18B-167IB.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 34/35 © 2004, GSI Technology
4M x 18 GS8642Z18GB-300 NBT PL/FT RoHS-compliant 119 BGA (var.2) 300/5.5 C
4M x 18 GS8642Z18GB-250 NBT PL/FT RoHS-compliant 119 BGA (var.2) 250/6.5 C
4M x 18 GS8642Z18GB-200 NBT PL/FT RoHS-compliant 119 BGA (var.2) 200/7.5 C
4M x 18 GS8642Z18GB-167 NBT PL/FT RoHS-compliant 119 BGA (var.2) 167/8 C
2M x 36 GS8642Z36GB-300 NBT PL/FT RoHS-compliant 119 BGA (var.2) 300/5.5 C
2M x 36 GS8642Z36GB-250 NBT PL/FT RoHS-compliant 119 BGA (var.2) 250/6.5 C
2M x 36 GS8642Z36GB-200 NBT PL/FT RoHS-compliant 119 BGA (var.2) 200/7.5 C
2M x 36 GS8642Z36GB-167 NBT PL/FT RoHS-compliant 119 BGA (var.2) 167/8 C
1M x 72 GS8642Z72GC-300 NBT PL/FT RoHS-compliant 209 BGA 300/5.5 C
1M x 72 GS8642Z72GC-250 NBT PL/FT RoHS-compliant 209 BGA 250/6.5 C
1M x 72 GS8642Z72GC-200 NBT PL/FT RoHS-compliant 209 BGA 200/7.5 C
1M x 72 GS8642Z72GC-167 NBT PL/FT RoHS-compliant 209 BGA 167/8 C
4M x 18 GS8642Z18GB-300I NBT PL/FT RoHS-compliant 119 BGA (var.2) 300/5.5 I
4M x 18 GS8642Z18GB-250I NBT PL/FT RoHS-compliant 119 BGA (var.2) 250/6.5 I
4M x 18 GS8642Z18GB-200I NBT PL/FT RoHS-compliant 119 BGA (var.2) 200/7.5 I
4M x 18 GS8642Z18GB-167I NBT PL/FT RoHS-compliant 119 BGA (var.2) 167/8 I
2M x 36 GS8642Z36GB-300I NBT PL/FT RoHS-compliant 119 BGA (var.2) 300/5.5 I
2M x 36 GS8642Z36GB-250I NBT PL/FT RoHS-compliant 119 BGA (var.2) 250/6.5 I
2M x 36 GS8642Z36GB-200I NBT PL/FT RoHS-compliant 119 BGA (var.2) 200/7.5 I
2M x 36 GS8642Z36GB-167I NBT PL/FT RoHS-compliant 119 BGA (var.2) 167/8 I
1M x 72 GS8642Z72GC-300I NBT PL/FT RoHS-compliant 209 BGA 300/5.5 I
1M x 72 GS8642Z72GC-250I NBT PL/FT RoHS-compliant 209 BGA 250/6.5 I
1M x 72 GS8642Z72GC-200I NBT PL/FT RoHS-compliant 209 BGA 200/7.5 I
1M x 72 GS8642Z72GC-167I NBT PL/FT RoHS-compliant 209 BGA 167/8 I
Ordering Information for GSI Synchronous Burst RAMs (Cont.)
Org Part Number1Type Package Speed2
(MHz/ns) TA3
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8642Z18B-167IB.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2009 35/35 © 2004, GSI Technology
72Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content Page;Revisions;Reason
8642Zxx_r1 • Creation of new datasheet
8642Zxx_r1; 8642Zxx_r1_01 Content • Changed “E” package to “F”
• Added Pb-Free information
8642Zxx_r1_01;
8642Zxx_r1_02 Content • Removed F package entirely
8642Zxx_r1_02;
8642Zxx_r1_03 Content
• Changed Pb-free to RoHS-compliant (entire document)
• Changed 167 MHz tKQ to 3.4 ns (pg. 1, 20)
• Added status to ordering information table (pg. 32, 33)
• Rev1.03a: updated coplanarity for 119, 209 BGA mechanical,
removed Status from Ordering Information column, Updated
Synchronous Truth Table, removed “Preliminary” banner due
to MP status.
