MF10-N www.ti.com SNOS547C - JUNE 1999 - REVISED APRIL 2013 MF10-N Universal Monolithic Dual Switched Capacitor Filter Check for Samples: MF10-N FEATURES DESCRIPTION * * The MF10-N consists of 2 independent and extremely easy to use, general purpose CMOS active filter building blocks. Each block, together with an external clock and 3 to 4 resistors, can produce various 2nd order functions. Each building block has 3 output pins. One of the outputs can be configured to perform either an allpass, highpass or a notch function; the remaining 2 output pins perform lowpass and bandpass functions. The center frequency of the lowpass and bandpass 2nd order functions can be either directly dependent on the clock frequency, or they can depend on both clock frequency and external resistor ratios. The center frequency of the notch and allpass functions is directly dependent on the clock frequency, while the highpass center frequency depends on both resistor ratio and clock. Up to 4th order functions can be performed by cascading the two 2nd order building blocks of the MF10-N; higher than 4th order functions can be obtained by cascading MF10-N packages. Any of the classical filter configurations (such as Butterworth, Bessel, Cauer and Chebyshev) can be formed. 1 * * * * * * * Easy to Use Clock to Center Frequency Ratio Accuracy 0.6% Filter Cutoff Frequency Stability Directly Dependent on External Clock Quality Low Sensitivity to External Component Variation Separate Highpass (or Notch or Allpass), Bandpass, Lowpass Outputs fO x Q Range up to 200 kHz Operation up to 30 kHz 20-pin 0.3 Wide PDIP Package 20-pin Surface Mount (SOIC) Wide-Body Package For pin-compatible device with improved performance refer to LMF100 datasheet. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1999-2013, Texas Instruments Incorporated MF10-N SNOS547C - JUNE 1999 - REVISED APRIL 2013 www.ti.com System Block Diagram Package in 20 pin molded wide body SOIC and 20 pin PDIP. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Supply Voltage (V+ - V-) 14V + V + 0.3V Voltage at Any Pin V- - 0.3V Input Current at Any Pin Package Input Current (3) 5 mA (3) 20 mA Power Dissipation (4) 500 mW Storage Temperature 150C ESD Susceptability (5) 2000V Soldering Information SO Package (1) (2) (3) (4) (5) 2 N Package: 10 sec 260C Vapor Phase (60 Sec.) 215C Infrared (15 Sec.) 220C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V- or VIN > V+) the absolute value of current at that pin should be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, JA, and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX - TA)/JA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJMAX = 125C, and the typical junction-to-ambient thermal resistance of the MF10ACN/CCN when board mounted is 55C/W. For the MF10AJ/CCJ, this number increases to 95C/W and for the MF10ACWM/CCWM this number is 66C/W. Human body model, 100 pF discharged through a 1.5 k resistor. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N MF10-N www.ti.com SNOS547C - JUNE 1999 - REVISED APRIL 2013 Operating Ratings (1) Temperature Range (TMIN TA TMAX) (1) 0C TA 70C MF10ACN, MF10CCN, MF10CCWM Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Electrical Characteristics V+ = +5.00V and V- = -5.00V unless otherwise specified. Boldface limits apply for TMIN to TMAX; all other limits TA = TJ = 25C. Symbol Parameter Conditions MF10ACN, MF10CCN, MF10CCWM Typical (1) V+ - V- IS Supply Voltage Center Frequency Range fCLK Clock Frequency Range fCLK/fO fCLK/fO 50:1 Clock to Center Frequency Ratio Deviation 100:1 Clock to Center Frequency Ratio Deviation 9 Max 14 Clock Applied to Pins 10 & 11 No Input Signal Min fO x Q < 200 kHz Hz 20 kHz Min 5.0 10 Hz 1.0 MHz Max 1.5 MF10A MF10C MF10A MF10C Min DC Offset Voltage (5) Max Min Max VOS3 0.2 0.6 0.6 Q = 10, Mode 1 Vpin12 = 5V fCLK = 250 KHz 0.2 1.5 1.5 Q = 10, Mode 1 Vpin12 = 0V fCLK = 500 kHz 0.2 0.6 0.6 0.2 1.5 1.5 DC Offset Voltage (5) Min Max VOS2 DC Offset Voltage 10 (5) 2 6 6 Vpin12 = 0V fCLK = 500 kHz 2 6 6 % 0 0.2 0.2 dB 5.0 20 20 mV -150 -185 -185 -85 -85 Vpin12 = +5V (fCLK/fO = 50) SA/B = V+ Vpin12 = +5V (fCLK/fO = 50) SA/B = V- Vpin12 = +5V (fCLK/fO = 50) All Modes Vpin12 = 0V (fCLK/fO = 100) SA/B = V+ -300 mV Vpin12 = 0V (fCLK/fO = 100) SA/B = V- -140 mV Vpin12 = 0V (fCLK/fO = 100) All Modes -140 mV -70 -70 -100 -100 -20 -20 DC Offset Voltage (5) VOUT Minimum Output BP, LP Pins RL = 5k 4.25 3.8 3.8 Voltage Swing N/AP/HP Pin RL = 3.5k 4.25 3.8 3.8 Op Amp Gain BW Product SR Op Amp Slew Rate (1) (2) (3) (4) (5) mV mV VOS3 GBW % mV Vpin12 = 5V fCLK = 250 kHz Mode 1 R1 = R2 = 10k VOS2 mA 0.2 Q = 10, Mode 1 DC Offset Voltage (5) 12 30 Q Error (MAX) (4) DC Lowpass Gain 12 V 0.1 Q = 10, Mode 1 VOS1 8 Units Max Clock Feedthrough HOLP Design Limit (3) Min Maximum Supply Current fO Tested Limit (2) mV V V 2.5 MHz 7 V/s Typicals are at 25C and represent most likely parametric norm. Tested limits are ensured to AOQL (Average Outgoing Quality Level). Design limits are specified but not 100% tested. These limits are not used to calculate outgoing quality levels. The accuracy of the Q value is a function of the center frequency (fO). This is illustrated in the curves under the heading "Typical Performance Characteristics". VOS1, VOS2, and VOS3 refer to the internal offsets as discussed in OFFSET VOLTAGE. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N 3 MF10-N SNOS547C - JUNE 1999 - REVISED APRIL 2013 www.ti.com Electrical Characteristics (continued) V+ = +5.00V and V- = -5.00V unless otherwise specified. Boldface limits apply for TMIN to TMAX; all other limits TA = TJ = 25C. Symbol Parameter MF10ACN, MF10CCN, MF10CCWM Conditions Typical (1) (6) (7) Maximum Output Short Circuit Current (7) Design Limit (3) Units Vpin12 = +5V, (fCLK/fO = 50) 83 dB Vpin12 = 0V, (fCLK/fO = 100) 80 dB Source 20 mA Sink 3.0 mA Dynamic Range (6) ISC Tested Limit (2) For 5V supplies the dynamic range is referenced to 2.82V rms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 200 V rms for the MF10-N with a 50:1 CLK ratio and 280 V rms for the MF10-N with a 100:1 CLK ratio. The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting that output to the positive supply. These are the worst case conditions. Logic Input Characteristics Boldface limits apply for TMIN to TMAX; all other limits TA = TJ = 25C MF10ACN, MF10CCN, MF10CCWM Parameter Min Logical "1" CMOS Clock Input Voltage Max Logical "0" Min Logical "1" Max Logical "0" Min Logical "1" TTL Clock Input Voltage Max Logical "0" Min Logical "1" Max Logical "0" (1) (2) (3) 4 Conditions V+ = +5V, V- = -5V, VLSh = 0V V+ = +10V, V- = 0V, VLSh = +5V V+ = +5V, V- = -5V, VLSh = 0V V+ = +10V, V- = 0V, VLSh = 0V Typical (1) Tested Limit (2) Design Limit (3) Units +3.0 +3.0 V -3.0 -3.0 V +8.0 +8.0 V +2.0 +2.0 V +2.0 +2.0 V +0.8 +0.8 V +2.0 +2.0 V +0.8 +0.8 V Typicals are at 25C and represent most likely parametric norm. Tested limits are ensured to AOQL (Average Outgoing Quality Level). Design limits are specified but not 100% tested. These limits are not used to calculate outgoing quality levels. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N MF10-N www.ti.com SNOS547C - JUNE 1999 - REVISED APRIL 2013 Typical Performance Characteristics Power Supply Current vs. Power Supply Voltage Positive Output Voltage Swing vs. Load Resistance (N/AP/HP Output) Figure 1. Figure 2. Negative Output Voltage Swing vs. Load Resistance (N/AP/HP Output) Negative Output Swing vs. Temperature Figure 3. Figure 4. Positive Output Swing vs. Temperature Crosstalk vs. Clock Frequency Figure 5. Figure 6. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N 5 MF10-N SNOS547C - JUNE 1999 - REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) 6 Q Deviation vs. Temperature Q Deviation vs. Temperature Figure 7. Figure 8. Q Deviation vs. Clock Frequency Q Deviation vs. Clock Frequency Figure 9. Figure 10. fCLK/fO Deviation vs. Temperature fCLK/fO Deviation vs. Temperature Figure 11. Figure 12. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N MF10-N www.ti.com SNOS547C - JUNE 1999 - REVISED APRIL 2013 Typical Performance Characteristics (continued) fCLK/fO Deviation vs. lock Frequency fCLK/fO Deviation vs. Clock Frequency Figure 13. Figure 14. Deviation of fCLK/fO vs. Nominal Q Deviation of fCLK/fO vs. Nominal Q Figure 15. Figure 16. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N 7 MF10-N SNOS547C - JUNE 1999 - REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS LP(1,20), BP(2,19), N/AP/HP(3,18) The second order lowpass, bandpass and notch/allpass/highpass outputs. These outputs can typically sink 1.5 mA and source 3 mA. Each output typically swings to within 1V of each supply. INV(4,17) The inverting input of the summing op-amp of each filter. These are high impedance inputs, but the non-inverting input is internally tied to AGND, making INVA and INVB behave like summing junctions (low impedance, current inputs). S1(5,16) S1 is a signal input pin used in the allpass filter configurations (see modes 4 and 5). The pin should be driven with a source impedance of less than 1 k. If S1 is not driven with a signal it should be tied to AGND (mid-supply). SA/B(6) This pin activates a switch that connects one of the inputs of each filter's second summer to either AGND (SA/B tied to V-) or to the lowpass (LP) output (SA/B tied to V+). This offers the flexibility needed for configuring the filter in its various modes of operation. VA+(7),VD+(8) Analog positive supply and digital positive supply. These pins are internally connected through the IC substrate and therefore VA+ and VD+ should be derived from the same power supply source. They have been brought out separately so they can be bypassed by separate capacitors, if desired. They can be externally tied together and bypassed by a single capacitor. VA-(14), VD-(13) Analog and digital negative supplies. The same comments as for VA+ and VD+ apply here. LSh(9) Level shift pin; it accommodates various clock levels with dual or single supply operation. With dual 5V supplies, the MF10-N can be driven with CMOS clock levels (5V) and the LSh pin should be tied to the system ground. If the same supplies as above are used but only TTL clock levels, derived from 0V to +5V supply, are available, the LSh pin should be tied to the system ground. For single supply operation (0V and +10V) the VA-, VD-pins should be connected to the system ground, the AGND pin should be biased at +5V and the LSh pin should also be tied to the system ground for TTL clock levels. LSh should be biased at +5V for CMOS clock levels in 10V single-supply applications. CLKA(10), CLKB(11) Clock inputs for each switched capacitor filter building block. They should both be of the same level (TTL or CMOS). The level shift (LSh) pin description discusses how to accommodate their levels. The duty cycle of the clock should be close to 50% especially when clock frequencies above 200 kHz are used. This allows the maximum time for the internal op-amps to settle, which yields optimum filter operation. 50/100/CL(12) By tying this pin high a 50:1 clock-to-filter-center-frequency ratio is obtained. Tying this pin at midsupplies (i.e. analog ground with dual supplies) allows the filter to operate at a 100:1 clock-to-centerfrequency ratio. When the pin is tied low (i.e., negative supply with dual supplies), a simple current limiting circuit is triggered to limit the overall supply current down to about 2.5 mA. The filtering action is then aborted. AGND(15) This is the analog ground pin. This pin should be connected to the system ground for dual supply operation or biased to mid-supply for single supply operation. For a further discussion of mid-supply biasing techniques see the Applications Information. For optimum filter performance a "clean" ground must be provided. Definition of Terms fCLK: the frequency of the external clock signal applied to pin 10 or 11. fO: center frequency of the second order function complex pole pair. fO is measured at the bandpass outputs of the MF10-N, and is the frequency of maximum bandpass gain (Figure 17). fnotch: the frequency of minimum (ideally zero) gain at the notch outputs. fz: the center frequency of the second order complex zero pair, if any. If fz is different from fO and if QZ is high, it can be observed as the frequency of a notch at the allpass output (Figure 26). Q: "quality factor" of the 2nd order filter. Q is measured at the bandpass outputs of the MF10-N and is equal to fO divided by the -3 dB bandwidth of the 2nd order bandpass filter (Figure 17). The value of Q determines the shape of the 2nd order filter responses as shown in Figure 22. 8 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N MF10-N www.ti.com SNOS547C - JUNE 1999 - REVISED APRIL 2013 QZ: the quality factor of the second order complex zero pair, if any. QZ is related to the allpass characteristic, which is written: (1) where QZ = Q for an all-pass response. HOBP: the gain (in V/V) of the bandpass output at f = fO. HOLP: the gain (in V/V) of the lowpass output as f 0 Hz (Figure 18). HOHP: the gain (in V/V) of the highpass output as f fCLK/2 (Figure 19). HON: the gain (in V/V) of the notch output as f 0 Hz and as f fCLK/2, when the notch filter has equal gain above and below the center frequency (Figure 20). When the low-frequency gain differs from the high-frequency gain, as in modes 2 and 3a (Figure 27 and Figure 24), the two quantities below are used in place of HON. HON1: the gain (in V/V) of the notch output as f 0 Hz. HON2: the gain (in V/V) of the notch output as f fCLK/2. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N 9 MF10-N SNOS547C - JUNE 1999 - REVISED APRIL 2013 www.ti.com (a) (b) Figure 17. 2nd-Order Bandpass Response 10 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N MF10-N www.ti.com SNOS547C - JUNE 1999 - REVISED APRIL 2013 (a) (b) Figure 18. 2nd-Order Low-Pass Response Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N 11 MF10-N SNOS547C - JUNE 1999 - REVISED APRIL 2013 www.ti.com (a) (b) Figure 19. 2nd-Order High-Pass Response 12 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N MF10-N www.ti.com SNOS547C - JUNE 1999 - REVISED APRIL 2013 (a) (b) Figure 20. 2nd-Order Notch Response Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N 13 MF10-N SNOS547C - JUNE 1999 - REVISED APRIL 2013 www.ti.com (a) (b) Figure 21. 2nd-Order All-Pass Response (a) Bandpass (b) Low Pass (d) Notch (c) High-Pass (e) All-Pass Figure 22. Response of various 2nd-order filters as a function of Q. Gains and center frequencies are normalized to unity. 14 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N MF10-N www.ti.com SNOS547C - JUNE 1999 - REVISED APRIL 2013 Modes of Operation The MF10-N is a switched capacitor (sampled data) filter. To fully describe its transfer functions, a time domain approach is appropriate. Since this is cumbersome, and since the MF10-N closely approximates continuous filters, the following discussion is based on the well known frequency domain. Each MF10-N can produce a full 2nd order function. See Table 1 for a summary of the characteristics of the various modes. MODE 1: Notch 1, Bandpass, Lowpass Outputs: fnotch = fO (See Figure 23) (2) fO= center frequency of the complex pole pair (3) fnotch= center frequency of the imaginary zero pair = fO. (4) (5) = quality factor of the complex pole pair BW = the -3 dB bandwidth of the bandpass output. Circuit dynamics: (6) MODE 1a: Non-Inverting BP, LP (See Figure 24) (7) Figure 23. MODE 1 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N 15 MF10-N SNOS547C - JUNE 1999 - REVISED APRIL 2013 www.ti.com VIN should be driven from a low impedance (<1 k) source. Figure 24. MODE 1a MODE 2: Notch 2, Bandpass, Lowpass: fnotch < fO (See Figure 25) (8) MODE 3: Highpass, Bandpass, Lowpass Outputs (See Figure 26) (9) 16 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N MF10-N www.ti.com SNOS547C - JUNE 1999 - REVISED APRIL 2013 Figure 25. MODE 2 *In Mode 3, the feedback loop is closed around the input summing amplifier; the finite GBW product of this op amp causes a slight Q enhancement. If this is a problem, connect a small capacitor (10 pF - 100 pF) across R4 to provide some phase lead. Figure 26. MODE 3 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N 17 MF10-N SNOS547C - JUNE 1999 - REVISED APRIL 2013 www.ti.com MODE 3a: HP, BP, LP and Notch with External Op Amp (See Figure 27) (10) MODE 4: Allpass, Bandpass, Lowpass Outputs (See Figure 28) (11) *Due to the sampled data nature of the filter, a slight mismatch of fz and fO occurs causing a 0.4 dB peaking around fO of the allpass filter amplitude response (which theoretically should be a straight line). If this is unacceptable, Mode 5 is recommended. 18 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N MF10-N www.ti.com SNOS547C - JUNE 1999 - REVISED APRIL 2013 Figure 27. MODE 3a Figure 28. MODE 4 MODE 5: Numerator Complex Zeros, BP, LP (See Figure 29) (12) Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N 19 MF10-N SNOS547C - JUNE 1999 - REVISED APRIL 2013 www.ti.com MODE 6a: Single Pole, HP, LP Filter (See Figure 30) (13) MODE 6b: Single Pole LP Filter (Inverting and Non-Inverting) (See Figure 31) (14) Figure 29. MODE 5 Figure 30. MODE 6a Figure 31. MODE 6b 20 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N MF10-N www.ti.com SNOS547C - JUNE 1999 - REVISED APRIL 2013 Table 1. Summary of Modes. Realizable filter types (e.g. low-pass) denoted by asterisks. Unless otherwise noted, gains of various filter outputs are inverting and adjustable by resistor ratios. Mode BP LP HP N AP Adjustable fCLK/fO 3 No 2 No 3 Yes (above fCLK/50 or fCLK/100) 4 Yes Universal State-Variable Filter. Best general-purpose mode. 7 Yes As above, but also includes resistortuneable notch. No Gives Allpass response with HOAP = -1 and HOLP = -2. Notes 1 * * 1a HOBP1 = -Q HOBP2 = +1 HOLP + 1 2 * * 3 * * * 3a * * * * * * 3 * * * 4 Gives flatter allpass response than above if R1 = R2 = 0.02R4. 3 Single pole. 2 Single pole. 4 5 6a * 6b HOLP1 = +1 HOLP2 = -R3/R2 * Number of Resistors * * * May need input buffer. Poor dynamics for high Q. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N 21 MF10-N SNOS547C - JUNE 1999 - REVISED APRIL 2013 www.ti.com APPLICATIONS INFORMATION The MF10-N is a general-purpose dual second-order state variable filter whose center frequency is proportional to the frequency of the square wave applied to the clock input (fCLK). By connecting pin 12 to the appropriate DC voltage, the filter center frequency fO can be made equal to either fCLK/100 or fCLK/50. fO can be very accurately set (within 6%) by using a crystal clock oscillator, or can be easily varied over a wide frequency range by adjusting the clock frequency. If desired, the fCLK/fO ratio can be altered by external resistors as in Figure 25, Figure 26, Figure 27, Figure 29, Figure 30, and Figure 31. The filter Q and gain are determined by external resistors. All of the five second-order filter types can be built using either section of the MF10-N. These are illustrated in Figure 17 through Figure 21 along with their transfer functions and some related equations. Figure 22 shows the effect of Q on the shapes of these curves. When filter orders greater than two are desired, two or more MF10-N sections can be cascaded. DESIGN EXAMPLE In order to design a second-order filter section using the MF10-N, we must define the necessary values of three parameters: f0, the filter section's center frequency; H0, the passband gain; and the filter's Q. These are determined by the characteristics required of the filter being designed. As an example, let's assume that a system requires a fourth-order Chebyshev low-pass filter with 1 dB ripple, unity gain at DC, and 1000 Hz cutoff frequency. As the system order is four, it is realizable using both secondorder sections of an MF10-N. Many filter design texts include tables that list the characteristics (fO and Q) of each of the second-order filter sections needed to synthesize a given higher-order filter. For the Chebyshev filter defined above, such a table yields the following characteristics: f0A = 529 Hz QA = 0.785 f0B = 993 Hz QB = 3.559 For unity gain at DC, we also specify: H0A = 1 H0B = 1 The desired clock-to-cutoff-frequency ratio for the overall filter of this example is 100 and a 100 kHz clock signal is available. Note that the required center frequencies for the two second-order sections will not be obtainable with clock-to-center-frequency ratios of 50 or 100. It will be necessary to adjust (15) externally. From Table 1, we see that Mode 3 can be used to produce a low-pass filter with resistor-adjustable center frequency. In most filter designs involving multiple second-order stages, it is best to place the stages with lower Q values ahead of stages with higher Q, especially when the higher Q is greater than 0.707. This is due to the higher relative gain at the center frequency of a higher-Q stage. Placing a stage with lower Q ahead of a higher-Q stage will provide some attenuation at the center frequency and thus help avoid clipping of signals near this frequency. For this example, stage A has the lower Q (0.785) so it will be placed ahead of the other stage. For the first section, we begin the design by choosing a convenient value for the input resistance: R1A = 20k. The absolute value of the passband gain HOLPA is made equal to 1 by choosing R4A such that: R4A = -HOLPAR1A = R1A = 20k. If the 50/100/CL pin is connected to mid-supply for nominal 100:1 clock-to-center-frequency ratio, we find R2A by: (16) The resistors for the second section are found in a similar fashion: 22 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N MF10-N www.ti.com SNOS547C - JUNE 1999 - REVISED APRIL 2013 (17) The complete circuit is shown in Figure 32 for split 5V power supplies. Supply bypass capacitors are highly recommended. Figure 32. Fourth-Order Chebyshev Low-Pass Filter from Example in 3.1. 5V Power Supply. 0V-5V TTL or -5V 5V CMOS Logic Levels. Figure 33. Fourth-Order Chebyshev Low-Pass Filter from Example in 3.1. Single +10V Power Supply. 0V-5V TTL Logic Levels. Input Signals Should be Referred to Half-Supply or Applied through a Coupling Capacitor. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N 23 MF10-N SNOS547C - JUNE 1999 - REVISED APRIL 2013 www.ti.com Resistive Divider with Decoupling Capacitor Operational Amplifier with Divider Voltage Regulator Figure 34. Three Ways of Generating V+/2 for Single-Supply Operation SINGLE SUPPLY OPERATION The MF10-N can also operate with a single-ended power supply. Figure 33 shows the example filter with a single-ended power supply. VA+ and VD+ are again connected to the positive power supply (8V to 14V), and VA- and VD- are connected to ground. The AGND pin must be tied to V+/2 for single supply operation. This half-supply point should be very "clean", as any noise appearing on it will be treated as an input to the filter. It can be derived from the supply voltage with a pair of resistors and a bypass capacitor (See Figure 34), or a low-impedance halfsupply voltage can be made using a three-terminal voltage regulator or an operational amplifier (See Figure 34 and Figure 34). The passive resistor divider with a bypass capacitor is sufficient for many applications, provided that the time constant is long enough to reject any power supply noise. It is also important that the half-supply reference present a low impedance to the clock frequency, so at very low clock frequencies the regulator or opamp approaches may be preferable because they will require smaller capacitors to filter the clock frequency. The main power supply voltage should be clean (preferably regulated) and bypassed with 0.1 F. DYNAMIC CONSIDERATIONS The maximum signal handling capability of the MF10-N, like that of any active filter, is limited by the power supply voltages used. The amplifiers in the MF10-N are able to swing to within about 1V of the supplies, so the input signals must be kept small enough that none of the outputs will exceed these limits. If the MF10-N is operating on 5V, for example, the outputs will clip at about 8 Vp-p. The maximum input voltage multiplied by the filter gain should therefore be less than 8 Vp-p. Note that if the filter Q is high, the gain at the lowpass or highpass outputs will be much greater than the nominal filter gain (Figure 22). As an example, a lowpass filter with a Q of 10 will have a 20 dB peak in its amplitude response at fO. If the nominal gain of the filter HOLP is equal to 1, the gain at fO will be 10. The maximum input signal at fO must therefore be less than 800 mVp-p when the circuit is operated on 5V supplies. Also note that one output can have a reasonable small voltage on it while another is saturated. This is most likely for a circuit such as the notch in Mode 1 (Figure 23). The notch output will be very small at fO, so it might appear safe to apply a large signal to the input. However, the bandpass will have its maximum gain at fO and can clip if overdriven. If one output clips, the performance at the other outputs will be degraded, so avoid overdriving any filter section, even ones whose outputs are not being directly used. Accompanying Figure 23 through Figure 31 are equations labeled "circuit dynamics", which relate the Q and the gains at the various outputs. These should be consulted to determine peak circuit gains and maximum allowable signals for a given application. OFFSET VOLTAGE The MF10-N's switched capacitor integrators have a higher equivalent input offset voltage than would be found in a typical continuous-time active filter integrator. Figure 35 shows an equivalent circuit of the MF10-N from which the output DC offsets can be calculated. Typical values for these offsets with SA/B tied to V+ are: Vos1 = opamp offset = 5 mV 24 Vos2 = -150 mV @ 50:1 -300 mV @ 100:1 Vos3 = -70 mV @ 50:1 -140 mV @ 100:1 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N MF10-N www.ti.com SNOS547C - JUNE 1999 - REVISED APRIL 2013 When SA/B is tied to V-, Vos2 will approximately halve. The DC offset at the BP output is equal to the input offset of the lowpass integrator (Vos3). The offsets at the other outputs depend on the mode of operation and the resistor ratios, as described in the following expressions. (18) (19) Figure 35. MF10-N Offset Voltage Sources Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N 25 MF10-N SNOS547C - JUNE 1999 - REVISED APRIL 2013 www.ti.com Figure 36. Method for Trimming VOS For most applications, the outputs are AC coupled and DC offsets are not bothersome unless large signals are applied to the filter input. However, larger offset voltages will cause clipping to occur at lower AC signal levels, and clipping at any of the outputs will cause gain nonlinearities and will change fO and Q. When operating in Mode 3, offsets can become excessively large if R2 and R4 are used to make fCLK/fO significantly higher than the nominal value, especially if Q is also high. An extreme example is a bandpass filter having unity gain, a Q of 20, and fCLK/fO = 250 with pin 12 tied to ground (100:1 nominal). R4/R2 will therefore be equal to 6.25 and the offset voltage at the lowpass output will be about +1V. Where necessary, the offset voltage can be adjusted by using the circuit of Figure 36. This allows adjustment of VOS1, which will have varying effects on the different outputs as described in the above equations. Some outputs cannot be adjusted this way in some modes, however (VOS(BP) in modes 1a and 3, for example). SAMPLED DATA SYSTEM CONSIDERATIONS The MF10-N is a sampled data filter, and as such, differs in many ways from conventional continuous-time filters. An important characteristic of sampled-data systems is their effect on signals at frequencies greater than onehalf the sampling frequency. (The MF10-N's sampling frequency is the same as its clock frequency.) If a signal with a frequency greater than one-half the sampling frequency is applied to the input of a sampled data system, it will be "reflected" to a frequency less than one-half the sampling frequency. Thus, an input signal whose frequency is fs/2 + 100 Hz will cause the system to respond as though the input frequency was fs/2 - 100 Hz. This phenomenon is known as "aliasing", and can be reduced or eliminated by limiting the input signal spectrum to less than fs/2. This may in some cases require the use of a bandwidth-limiting filter ahead of the MF10-N to limit the input spectrum. However, since the clock frequency is much higher than the center frequency, this will often not be necessary. Another characteristic of sampled-data circuits is that the output signal changes amplitude once every sampling period, resulting in "steps" in the output voltage which occur at the clock rate (Figure 37). If necessary, these can be "smoothed" with a simple R-C low-pass filter at the MF10-N output. The ratio of fCLK to fC (normally either 50:1 or 100:1) will also affect performance. A ratio of 100:1 will reduce any aliasing problems and is usually recommended for wideband input signals. In noise sensitive applications, however, a ratio of 50:1 may be better as it will result in 3 dB lower output noise. The 50:1 ratio also results in lower DC offset voltages, as discussed in OFFSET VOLTAGE. The accuracy of the fCLK/fO ratio is dependent on the value of Q. This is illustrated in Typical Performance Characteristics. As Q is changed, the true value of the ratio changes as well. Unless the Q is low, the error in fCLK/fO will be small. If the error is too large for a specific application, use a mode that allows adjustment of the ratio with external resistors. It should also be noted that the product of Q and fO should be limited to 300 kHz when fO < 5 kHz, and to 200 kHz for fO > 5 kHz. 26 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N MF10-N www.ti.com SNOS547C - JUNE 1999 - REVISED APRIL 2013 Figure 37. The Sampled-Data Output Waveform Connection Diagram Figure 38. SOIC and PDIP Packages (Top View) See Package Numbers DW and NFH0020A Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N 27 MF10-N SNOS547C - JUNE 1999 - REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision B (April 2013) to Revision C * 28 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 27 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: MF10-N PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) MF100CCM NRND SOIC DW 20 TBD Call TI Call TI 0 to 70 MF10CCWM MF100CCWM NRND SOIC DW 20 TBD Call TI Call TI 0 to 70 MF10CCWM MF10CCN NRND PDIP NFH 20 18 TBD Call TI Call TI 0 to 70 MF10CCN MF10CCN/NOPB ACTIVE PDIP NFH 20 18 Pb-Free (RoHS) CU SN Level-1-NA-UNLIM 0 to 70 MF10CCN MF10CCWM/NOPB ACTIVE SOIC DW 20 36 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 0 to 70 MF10CCWM MF10CCWMX NRND SOIC DW 20 TBD Call TI Call TI 0 to 70 MF10CCWM MF10CCWMX/NOPB ACTIVE SOIC DW 20 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 0 to 70 MF10CCWM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2015 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 10-Sep-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device MF10CCWMX/NOPB Package Package Pins Type Drawing SOIC DW 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 10.9 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.3 3.25 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 10-Sep-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MF10CCWMX/NOPB SOIC DW 20 1000 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA NFH0020A N0020A N20A (Rev G) www.ti.com PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 TYP 9.97 SEATING PLANE PIN 1 ID AREA A 0.1 C 20 1 13.0 12.6 NOTE 3 18X 1.27 2X 11.43 10 11 B 7.6 7.4 NOTE 4 20X 0.51 0.31 0.25 C A B 2.65 MAX 0.33 TYP 0.10 SEE DETAIL A 0.25 GAGE PLANE 0 -8 0.3 0.1 1.27 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.07 MAX ALL AROUND 0.07 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 11 10 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 TYP 9.97 SEATING PLANE PIN 1 ID AREA A 0.1 C 20 1 13.0 12.6 NOTE 3 18X 1.27 2X 11.43 10 11 B 7.6 7.4 NOTE 4 20X 0.51 0.31 0.25 C A B 2.65 MAX 0.33 TYP 0.10 SEE DETAIL A 0.25 GAGE PLANE 0 -8 0.3 0.1 1.27 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.07 MAX ALL AROUND 0.07 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 11 10 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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