MMC2114CEHPU33 - Freescale Semiconductor / Motorola

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M•CORE

Microcontrollers

MMC2114/D

Rev. 1, 4/2002

MMC2114

Advance Information

MMC2113

MMC2112

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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Information

MOTOROLA 3

MMC2114

MMC2113

MMC2112

Adva nce Information

To provide the most up-to-date information, the revision of our

documents on the World Wide Web will be the most current. Your printed

copy may be an earlier revision. To verify you have the latest information

available, refer to:

http://www.motorola.com/semiconductors/

The following revision history table summarizes changes contained in

this document. For your convenience, the page number designators

have been linked to the appropriate location.

Motorola and the Stylized M Logo are register ed trademar ks of Motoro la, Inc.

DigitalDNA is a trademark of Motorola, Inc. © Motorola, Inc., 2002

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Advance Informa tion MM C2114 • MMC 2113 • MMC21 12 — Rev. 1.0

4MOTOROLA

Advance I n fo rmatio n

Revision History

Date Revision

Level Description Page

Number(s)

March, 2002 N/A Original release N/A

April, 2002 1.0

Figur e 4-4. Chip Identification Register (CIR) —

C orrrected reset condition for bits 11 and 8 131

20.9.3 Show Strobe (SHS) — Corrected description in first

paragraph 542

23.5 Junction Temperature Determination — Changed

subsec ti o n title fro m Power Dissi p a ti o n to Junc tion

Temperature Det ermination 614

23.7 DC Electrical Specifications — Under operating

sup p ly current, external os c illa tor c lock ing changed stop

mode maximum value from 10 µA to 200 µA616

23.7 DC Electrical Specifications — Under operating

supply current, crystal/PLL clock changed maximum value

for OSC and PLL disabled from 150 µA to 200 µA617

A ppendi x A. Secu rity — Updated fo r c lari ty 649

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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0  Advance Information
MOTO ROLA List of S ect ions  5
Advance Inf o rmation — MMC2 114, MMC2113, and MMC2112
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . .45
Section 2. System Memory Map  . . . . . . . . . . . . . . . . . . .53
Section 3. Signal Description. . . . . . . . . . . . . . . . . . . . . .95
Section 4. Chip Configuration Module (CCM)  . . . . . . .121
Section 5. Reset Controller Module. . . . . . . . . . . . . . . .139
Section 6. Power Management  . . . . . . . . . . . . . . . . . . .155
Section 7. M•CORE M210 Central Processor 
Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . .165
Section 8. Interrupt Controller Module . . . . . . . . . . . . .177
Section 9. Static Random Access Memory 
(SRAM). . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
Section 10. Second Generation FLASH 
for M•CORE (SGFM) . . . . . . . . . . . . . . . . . .203
Section 11. Clock Module. . . . . . . . . . . . . . . . . . . . . . . .243
Section 12. Ports Module . . . . . . . . . . . . . . . . . . . . . . . .271
Section 13. Edge Port Module (EPORT) . . . . . . . . . . . .285
Section 14. Watchdog Timer Module  . . . . . . . . . . . . . .295
Section 15. Programmable Interrupt Timer 
Modules (PIT1 and PIT2)  . . . . . . . . . . . . . .305
Section 16. Timer Modules (TIM1 and TIM2). . . . . . . . .317
    
  
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Advance Information MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
6 List of S ec tions MOTOR OLA
Li st of  Sec ti o ns
Section 17. Serial Communications Interface 
Modules (SCI1 and SCI2) . . . . . . . . . . . . . .353
Section 18. Serial Peripheral Interface 
Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . .397
Section 19. Queued Analog-to-Digital 
Converter (QADC). . . . . . . . . . . . . . . . . . . .425
Section 20. External Bus Interface Module (EBI) . . . . .527
Section 21. Chip Select Module. . . . . . . . . . . . . . . . . . .547
Section 22. JTAG Test Access Port and OnCE . . . . . .559
Section 23. Preliminary Electrical Specifications  . . . .611
Section 24. Mechanical Specifications . . . . . . . . . . . . .639
Section 25. Ordering Information  . . . . . . . . . . . . . . . . .647
Appendix A. Security . . . . . . . . . . . . . . . . . . . . . . . . . . .649
    
  
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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0  Advance Information
MOTOROLA Table of Contents  7
Advance Info rmation — MMC2114, MMC2113, and MMC2112
Table of Contents
Section 1. General Description
1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
1.4 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Section 2. S ystem  Memo ry Map
2.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
2.3 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
2.4 Register Ma p  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Section 3. Signal Description
3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
3.3 Package Pinout Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
3.4 Chip Specific Implementation Signal Issues. . . . . . . . . . . . . .109
3.4.1 RSTOUT Signal Functions. . . . . . . . . . . . . . . . . . . . . . . . .109
3.4.2 INT Signal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
3.4.3 Serial Peripheral Interface (SPI) Pin Functions . . . . . . . . .110
3.4.4 Serial  Communications Interface (SCI1 and SCI2) 
Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
3.4.5 Timer 1 and Timer 2 Pin Functions  . . . . . . . . . . . . . . . . . .112
3.4.6 Queued Analog-to-Digital Converter (QADC) 
Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
    
  
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Advance Information MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
Table of Contents M OTOROLA
Table of Contents
5 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
5.1 Reset Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
5.1.1 Reset In (RESET)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
5.1.2 Reset Out (RS TOUT). . . . . . . . . . . . . . . . . . . . . . . . . . .113
5.2 Phase-Lock Loop (PLL ) and Clock Signals . . . . . . . . . . . .113
5.2.1 External Clock In (EXTAL). . . . . . . . . . . . . . . . . . . . . . .113
5.2.2 Crystal (XTAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
5.2.3 Clock Out (CLKOUT). . . . . . . . . . . . . . . . . . . . . . . . . . .114
5.2.4 PLL Enable (PLLEN) . . . . . . . . . . . . . . . . . . . . . . . . . . .114
5.3 External Memory Interface Signals  . . . . . . . . . . . . . . . . . .114
5.3.1 Data Bus (D[31:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
5.3.2 Show Cycle Strobe (SHS) . . . . . . . . . . . . . . . . . . . . . . .114
5.3.3 Transfer Acknowledge (TA). . . . . . . . . . . . . . . . . . . . . .115
5.3.4 Transfer Error Acknowledge (TEA) . . . . . . . . . . . . . . . .115
5.3.5 Emulation Mode Chip Selects (CSE [1:0]) . . . . . . . . . . .115
5.3.6 Transfer Code (TC[2:0]). . . . . . . . . . . . . . . . . . . . . . . . .115
5.3.7 Read/Write (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
5.3.8 Address Bus (A[22:0]) . . . . . . . . . . . . . . . . . . . . . . . . . .115
5.3.9 Enable Byte (EB[3:0])  . . . . . . . . . . . . . . . . . . . . . . . . . .116
5.3.10 Chip Sele ct (CS[3:0]). . . . . . . . . . . . . . . . . . . . . . . . . . .116
5.3.11 Output Enable (OE) . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
5.4 Edge Port Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
5.4.1 External Interrupts (INT[7:6] ) . . . . . . . . . . . . . . . . . . . . .116
5.4.2 External Interrupts (INT[5:2] ) . . . . . . . . . . . . . . . . . . . . .116
5.4.3 External Interrupts (INT[1:0] ) . . . . . . . . . . . . . . . . . . . . .116
5.5 Serial Peripheral Interface Module Signals  . . . . . . . . . . . .117
5.5.1 Master Out/Slave In (MOSI). . . . . . . . . . . . . . . . . . . . . .117
5.5.2 Master In/Slave Out (MISO). . . . . . . . . . . . . . . . . . . . . .117
5.5.3 Serial Clock (SCK). . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
5.5.4 Slave Select (SS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
5.6 Serial Communications Interface Module Signals . . . . . . .117
5.6.1 Receive Data (RXD1 and RXD2). . . . . . . . . . . . . . . . . .117
5.6.2 Transmit Data (TXD1 and TXD2). . . . . . . . . . . . . . . . . .118
5.7 Timer Signals (ICOC1[3:0] and ICOC2[3:0]) . . . . . . . . . . .118
    
  
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Table of Contents
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Informa tion 
MOTOROLA Table of Contents  9
5.8 Analog-to-Digital Converter Signals. . . . . . . . . . . . . . . . . .118
5.8.1 Analog Inputs (PQA[4:3], PQA[1:0], and PQB[3:0]). . . .118
5.8.2 Analog Reference (V RH and VRL) . . . . . . . . . . . . . . . . .118
5.8.3 Analog Supply (VDDA  and VSSA) . . . . . . . . . . . . . . . . . .118
5.8.4 Positive Supply (VDDH)  . . . . . . . . . . . . . . . . . . . . . . . . .118
5.9 Debug and Emulation S upport Signals  . . . . . . . . . . . . . . .119
5.9.1 Test Reset (TRST). . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
5.9.2 Test Clock (TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
5.9.3 Test Mode Select (TMS) . . . . . . . . . . . . . . . . . . . . . . . .119
5.9.4 Test Data Input (TDI). . . . . . . . . . . . . . . . . . . . . . . . . . .119
5.9.5 Test Data Output (TDO). . . . . . . . . . . . . . . . . . . . . . . . .119
5.9.6 Debug Event (DE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
5.10 Test Signal (TEST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
5.11 Power and Ground Signals  . . . . . . . . . . . . . . . . . . . . . . . .120
5.11.1 Standby Power (VSTBY) . . . . . . . . . . . . . . . . . . . . . . . . .120
5.11.2 Positive Supply (VDD). . . . . . . . . . . . . . . . . . . . . . . . . . .120
5.11.3 Ground (VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
Section 4. Chip Configuration Module (CCM)
1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
4.1 Master Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
4.2 Single-Chip Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
4.3 Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
4.4 Factory Access Slave Test (FAST) Mode . . . . . . . . . . . . .123
5 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
6 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
7 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .125
7.1 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
7.2 Memory Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
7.3 Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
7.3.1 Chip Configuration Register. . . . . . . . . . . . . . . . . . . . . .126
7.3.2 Reset Configuration Register. . . . . . . . . . . . . . . . . . . . .129
7.3.3 Chip Identification Register . . . . . . . . . . . . . . . . . . . . . .131
7.3.4 Chip Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
    
  
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Advance Information MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
Table of Contents M OTOROLA
Table of Contents
8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
8.1 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
8.2 Chip Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
8.3 Boot Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
8.4 Output Pad Strength Configuration . . . . . . . . . . . . . . . . . .137
8.5 Clock Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
8.6 Internal FLASH Configuration  . . . . . . . . . . . . . . . . . . . . . .138
9 Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
10 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Section 5. Reset Controller Module
1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
4 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
5 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
5.1 RESET  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
5.2 RSTOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
6 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .142
6.1 Reset Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .143
6.2 Reset Status Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
7.1 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
7.1.1 Power-On Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
7.1.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
7.1.3 Watchdog Timer Reset  . . . . . . . . . . . . . . . . . . . . . . . . .148
7.1.4 Loss of Clock Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .148
7.1.5 Loss of Lock Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
7.1.6 Software Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
7.1.7 LVD Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
7.2 Reset Control Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
7.2.1 Synchronous Re set Requests . . . . . . . . . . . . . . . . . . . .151
7.2.2 Internal Reset Request  . . . . . . . . . . . . . . . . . . . . . . . . .151
7.2.3 Power-On Reset/Low-V oltage Detect Reset . . . . . . . . .151
    
  
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Table of Contents
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Informa tion 
MOTOROLA Table of Contents  11
7.3 Concurrent Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
7.3.1 Reset Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
7.3.2 Reset Status Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
Sect i o n 6. P o wer Mana gement
1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
3.1 Run Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
3.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
3.3 Doze Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
3.4 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
3.5 Peripheral Shut Down  . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
4 Peripheral Behavior in Low-Power Modes . . . . . . . . . . . . . . .158
4.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
4.2 Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
4.3 OnCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
4.4 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
4.5 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
4.6 Edge Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
4.7 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . .160
4.8 FLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
4.9 Queued Analog-to-Digital Converter (QADC)  . . . . . . . . . .161
4.10 Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
4.11 Programmable Interrupt Timers (PIT1 and PIT2). . . . . . . .162
4.12 Serial Peripheral Interface (SPI). . . . . . . . . . . . . . . . . . . . .162
4.13 Serial Communication Interfaces (SCI1 and SCI2) . . . . . .162
4.14 Timers (TIM1 and TIM2). . . . . . . . . . . . . . . . . . . . . . . . . . .163
5 Summary of Peripheral State During Low-Power Modes. . . .163
Section 7. M•CORE M210 Central Processor
Unit (CPU)
1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
4 Microarchitecture Summary . . . . . . . . . . . . . . . . . . . . . . . . . .167
    
  
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5 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
6 Data Format Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
7 Operand Addressing Capabilities. . . . . . . . . . . . . . . . . . . . . .172
8 Instruction Set Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
Section 8. Interrupt Controller Module
1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
4 Low-Power Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . .178
5 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
6 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
7 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .179
7.1 Memory Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
7.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
7.2.1 Interrupt Control Register. . . . . . . . . . . . . . . . . . . . . . . .181
7.2.2 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . .183
7.2.3 Interrupt Force Registers . . . . . . . . . . . . . . . . . . . . . . . .184
7.2.4 Interrupt Pending Register. . . . . . . . . . . . . . . . . . . . . . .186
7.2.5 Normal Interrupt Enable Register. . . . . . . . . . . . . . . . . .187
7.2.6 Normal Interrupt Pending Register. . . . . . . . . . . . . . . . .188
7.2.7 Fast Interrupt Enable Register. . . . . . . . . . . . . . . . . . . .189
7.2.8 Fast Interrupt Pending Register. . . . . . . . . . . . . . . . . . .190
7.2.9 Priority Level Select Registers. . . . . . . . . . . . . . . . . . . .191
8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
8.1 Interrupt Sources and Prioritization . . . . . . . . . . . . . . . . . .192
8.2 Fast and Normal Interrupt Requests . . . . . . . . . . . . . . . . .192
8.3 Autovectored and Vectored Interrupt Requests . . . . . . . . .193
8.4 Interrupt Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
8.4.1 CPU Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
8.4.2 Interrupt Controller Configuration. . . . . . . . . . . . . . . . . .195
8.4.3 Interrupt Source Configuration. . . . . . . . . . . . . . . . . . . .196
8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
    
  
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Section 9. Static Random Access Memory (SRAM)
1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
4 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
5 Standby Power Supply Pin (VSTBY) . . . . . . . . . . . . . . . . . . . .200
6 Standby Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
7 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
Sect io n 10.  Sec on d Gene rat i o n FLA SH
for M•CORE (SGFM)
1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
3 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
6 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
7 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
7.1 Unbanked R egister Descriptions . . . . . . . . . . . . . . . . . . . .213
7.1.1 SGFM Configuration Register . . . . . . . . . . . . . . . . . . . .213
7.1.2 SGFM Clock Divider Register . . . . . . . . . . . . . . . . . . . .215
7.1.3 SGFM Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . .216
7.1.4 SGFM Security Register . . . . . . . . . . . . . . . . . . . . . . . .217
7.1.5 SGFM Monitor Data Register. . . . . . . . . . . . . . . . . . . . .219
7.2 Banked Register Descriptions . . . . . . . . . . . . . . . . . . . . . .220
7.2.1 SGFM Protection Register. . . . . . . . . . . . . . . . . . . . . . .220
7.2.2 SGFM Supervisor Access Register . . . . . . . . . . . . . . . .222
7.2.3 SGFM Data Access R egister. . . . . . . . . . . . . . . . . . . . .223
7.2.4 SGFM Test Status Register. . . . . . . . . . . . . . . . . . . . . .224
7.2.5 SGFM User Status Register. . . . . . . . . . . . . . . . . . . . . .224
7.2.6 SGFM Command R egister. . . . . . . . . . . . . . . . . . . . . . .226
7.2.7 SGFM Contro l Register . . . . . . . . . . . . . . . . . . . . . . . . .227
7.2.8 SGFM Address Register . . . . . . . . . . . . . . . . . . . . . . . .228
7.2.9 SGFM Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . .229
    
  
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8 SGFM User Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
8.1 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
8.2 Write Operations  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
8.3 Program and Er ase Operations . . . . . . . . . . . . . . . . . . . . .231
8.3.1 Se tting the SGFMCLKD Register. . . . . . . . . . . . . . . . . .231
8.3.2 Pr ogram, Erase, and Verify Sequences. . . . . . . . . . . . .232
8.3.3 FLASH User Mode Valid Commands. . . . . . . . . . . . . . .234
8.3.4 FLASH User Mode Illegal Operations . . . . . . . . . . . . . .236
8.4 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
8.5 Master Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
8.6 Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
8.7 Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
9 FLASH Security Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .238
9.1 Back Door Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
9.2 Erase Verify Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
10 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
11 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
Section 11. Clock Module
1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
4.1 Normal PLL Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
4.2 1:1 PLL Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
4.3 External Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
4.4 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
4.4.1 Wait and Doze Modes . . . . . . . . . . . . . . . . . . . . . . . . . .245
4.4.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
5 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
6 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
6.1 EXTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
6.2 XTAL  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
6.3 CLKOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
6.4 PLLEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
6.5 RSTOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
    
  
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7 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .249
7.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
7.2 Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
7.2.1 Synthesizer Control Register . . . . . . . . . . . . . . . . . . . . .250
7.2.2 Synthesizer Status Register. . . . . . . . . . . . . . . . . . . . . .253
7.2.3 Synthesizer Test Register . . . . . . . . . . . . . . . . . . . . . . .256
7.2.4 Synthesizer Test Register 2. . . . . . . . . . . . . . . . . . . . . .257
8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
8.1 System Clock Modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
8.2 System Clocks Generation. . . . . . . . . . . . . . . . . . . . . . . . .259
8.3 PLL Lock Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
8.3.1 PLL Loss of Lock Conditions . . . . . . . . . . . . . . . . . . . . .261
8.3.2 PLL Loss of Lock Reset. . . . . . . . . . . . . . . . . . . . . . . . .261
8.4 Loss of Clock Detection . . . . . . . . . . . . . . . . . . . . . . . . . . .261
8.4.1 Alternate Clock Selection. . . . . . . . . . . . . . . . . . . . . . . .262
8.4.2 Loss-of-Clock Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .265
8.5 Clock Operation During Reset . . . . . . . . . . . . . . . . . . . . . .266
8.6 PLL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266
8.6.1 Phase and Frequency Detector (PFD). . . . . . . . . . . . . .268
8.6.2 Charge Pump/Loop Filter. . . . . . . . . . . . . . . . . . . . . . . .268
8.6.3 Vo ltage Control Output (VCO) . . . . . . . . . . . . . . . . . . . .269
8.6.4 Multiplication Factor Divider (MFD) . . . . . . . . . . . . . . . .269
9 Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
10 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
Section 12. Ports Module
1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272
3 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
4 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .273
4.1 Memory Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274
4.2 Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .275
4.2.1 Po rt Output Data Registers . . . . . . . . . . . . . . . . . . . . . .275
4.2.2 Po rt Data Direction Registers. . . . . . . . . . . . . . . . . . . . .276
4.2.3 Po rt Pin Data/Set Data Registers  . . . . . . . . . . . . . . . . .277
4.2.4 Po rt Clear Output Data Registers . . . . . . . . . . . . . . . . .278
    
  
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4.2.5 Po rt C/D Pin Assignment Register. . . . . . . . . . . . . . . . .279
4.2.6 Po rt E Pin Assignment Register. . . . . . . . . . . . . . . . . . .280
5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
5.1 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
5.2 Port Digital I/O Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
Section 13. Edge Port Module (EPORT)
1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285
3 Low-Power Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . .286
3.1 Wait and Doze Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .286
3.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287
4 Interrupt/General-Purpose I/O Pin Descriptions. . . . . . . . . . .287
5 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .287
5.1 Memory Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287
5.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288
5.2.1 EPORT Pin Assignment Register . . . . . . . . . . . . . . . . .288
5.2.2 EPORT Data Direction Register. . . . . . . . . . . . . . . . . . .290
5.2.3 Edge Port Interrupt Enable Register . . . . . . . . . . . . . . .291
5.2.4 Edge Port Data Register . . . . . . . . . . . . . . . . . . . . . . . .292
5.2.5 Edge Port Pin Data Register . . . . . . . . . . . . . . . . . . . . .292
5.2.6 Edge Port Flag Register. . . . . . . . . . . . . . . . . . . . . . . . .293
Section 14. Watchdog Timer Module
1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
3.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
3.2 Doze Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
3.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
3.4 Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
4 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
5 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
6 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .298
    
  
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6.1 Memory Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
6.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
6.2.1 Watchdog Control Register . . . . . . . . . . . . . . . . . . . . . .299
6.2.2 Watchdog Modulus Register . . . . . . . . . . . . . . . . . . . . .301
6.2.3 Watchdog Count Register . . . . . . . . . . . . . . . . . . . . . . .302
6.2.4 Watchdog Service Register . . . . . . . . . . . . . . . . . . . . . .303
Section 15. Programmable Interrupt Timer Modules
(PIT1 and PIT2)
1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
3 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
4.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
4.2 Doze Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
4.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
4.4 Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
5 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
6 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .308
6.1 Memory Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
6.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
6.2.1 PIT Control and Status Register  . . . . . . . . . . . . . . . . . .309
6.2.2 PIT Modulus Register  . . . . . . . . . . . . . . . . . . . . . . . . . .312
6.2.3 PIT Count Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
7.1 Set-and-Forget Timer Operation . . . . . . . . . . . . . . . . . . . .314
7.2 Free-Running Timer Operation  . . . . . . . . . . . . . . . . . . . . .315
7.3 Timeout Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . .315
8 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316
Section 1 6. Timer Module s (TIM1 and TIM2)
1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319
4 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320
    
  
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5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
5.1 Supervisor and User Modes. . . . . . . . . . . . . . . . . . . . . . . .321
5.2 Run Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
5.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
5.4 Wait, Doze, and Debug Modes  . . . . . . . . . . . . . . . . . . . . .321
5.5 Test Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
6 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
6.1 ICOC[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
6.2 ICOC3  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
7 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .323
7.1 Timer Input Capture/Output Compare Select Register  . . .324
7.2 Timer Compare Force Register . . . . . . . . . . . . . . . . . . . . .325
7.3 Timer Output Compar e 3 Mask Register . . . . . . . . . . . . . .326
7.4 Timer Output Compar e 3 Data Register. . . . . . . . . . . . . . .327
7.5 Timer Counter Registers  . . . . . . . . . . . . . . . . . . . . . . . . . .328
7.6 Timer System Control Register 1. . . . . . . . . . . . . . . . . . . .329
7.7 Timer To ggle-On-Overflow Register  . . . . . . . . . . . . . . . . .330
7.8 Timer Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . .331
7.9 Timer Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . .332
7.10 Timer Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . .333
7.11 Timer System Control Register 2. . . . . . . . . . . . . . . . . . . .334
7.12 Timer F lag Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
7.13 Timer F lag Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
7.14 Timer Channel Registers  . . . . . . . . . . . . . . . . . . . . . . . . . .338
7.15 Pulse Accumulator Control Register  . . . . . . . . . . . . . . . . .339
7.16 Pulse Accumulator Flag Register. . . . . . . . . . . . . . . . . . . .341
7.17 Pulse Accumulator Counter Registers . . . . . . . . . . . . . . . .342
7.18 Timer Port Data Register . . . . . . . . . . . . . . . . . . . . . . . . . .343
7.19 Timer Port Data Direction Register  . . . . . . . . . . . . . . . . . .344
7.20 Timer T e st Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
8.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
8.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
8.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346
8.4 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347
8.4.1 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .347
8.4.2 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . .348
    
  
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8.5 General-Purpose I/O Ports. . . . . . . . . . . . . . . . . . . . . . . . .349
9 Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351
10 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351
10.1 Timer Channel Interrupts (CxF) . . . . . . . . . . . . . . . . . . . . .351
10.2 Pulse Accumulator Overflow (PAOVF). . . . . . . . . . . . . . . .352
10.3 Pulse Accumulator Input (PAIF). . . . . . . . . . . . . . . . . . . . .352
10.4 Timer Overflow (TOF)  . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
Section 17. S erial Communicatio n s Interface Modules 
(SCI1 and SCI2)
1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
4 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356
5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
5.1 Doze Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
6 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
6.1 RXD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
6.2 TXD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
7 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .358
7.1 SCI Baud Rate Register s . . . . . . . . . . . . . . . . . . . . . . . . . .360
7.2 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .361
7.3 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
7.4 SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .366
7.5 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .369
7.6 SCI Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .370
7.7 SCI Pullup and Reduced Drive Register . . . . . . . . . . . . . .371
7.8 SCI Port Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .372
7.9 SCI Data Direction Register. . . . . . . . . . . . . . . . . . . . . . . .373
8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
9 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
10 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
11 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376
11.1 Frame Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377
    
  
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11.2 Transmitting a Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . .378
11.3 Break Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380
11.4 Idle Frames  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380
12 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381
12.1 Frame Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381
12.2 Receiving a Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381
12.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382
12.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387
12.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387
12.5.1 Slow Data T o lerance . . . . . . . . . . . . . . . . . . . . . . . . . . .388
12.5.2  Fast Data T o lerance . . . . . . . . . . . . . . . . . . . . . . . . . . .389
12.6 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .390
12.6.1 Idle Input Line Wakeup (WAKE = 0) . . . . . . . . . . . . . . .390
12.6.2 Address Mark Wakeup (WAKE = 1). . . . . . . . . . . . . . . .391
13 Single-Wire Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392
14 Loop Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
15 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394
16 Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395
17 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395
17.1 Transmit Data Register E mpty. . . . . . . . . . . . . . . . . . . . . .395
17.2 Transmission Complete . . . . . . . . . . . . . . . . . . . . . . . . . . .395
17.3 Receive Data Register Full. . . . . . . . . . . . . . . . . . . . . . . . .396
17.4 Idle Receiver Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396
17.5 Overrun  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396
Sect ion 18. Serial Peripheral Interface Module ( SPI)
1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398
4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
5 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
6 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400
6.1 MISO (Master In/Slave Out). . . . . . . . . . . . . . . . . . . . . . . .400
6.2 MOSI (Master Out/Slave In). . . . . . . . . . . . . . . . . . . . . . . .400
6.3 SCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401
6.4 SS (Slave Select). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401
    
  
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MOTOROLA Table of Contents  21
7 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .401
7.1 SPI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .402
7.2 SPI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .405
7.3 SPI Baud Rate Register. . . . . . . . . . . . . . . . . . . . . . . . . . .406
7.4 SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .408
7.5 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .409
7.6 SPI Pullup and Reduced Drive Re gister  . . . . . . . . . . . . . .410
7.7 SPI Port Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .411
7.8 SPI Port Data Direction Register . . . . . . . . . . . . . . . . . . . .412
8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .413
8.1 Master Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .414
8.2 Slave Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415
8.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . .416
8.3.1 Transfer Format When CPHA = 1 . . . . . . . . . . . . . . . . .416
8.3.2 Transfer Format When CPHA = 0 . . . . . . . . . . . . . . . . .417
8.4 SPI Baud Rate Generatio n. . . . . . . . . . . . . . . . . . . . . . . . .420
8.5 Slave-Select Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420
8.6 Bidirectional Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .421
8.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422
8.7.1 Write Collision Error. . . . . . . . . . . . . . . . . . . . . . . . . . . .422
8.7.2 Mode Fault Erro r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422
8.8 Low-Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . .423
8.8.1 Run Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .423
8.8.2 Doze Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .423
8.8.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .424
9 Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .424
10 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .424
10.1 Mode Fault (MODF) Flag . . . . . . . . . . . . . . . . . . . . . . . . . .424
10.2 SPI Interrupt Flag (SPIF) . . . . . . . . . . . . . . . . . . . . . . . . . .424
Section 19. Queued Analog-to-Digital
Converter (QADC)
1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .428
4 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .429
    
  
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5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .430
5.1 Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .430
5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431
6 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431
6.1 Port QA Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . .432
6.1.1 Po rt QA Analog Input Pins. . . . . . . . . . . . . . . . . . . . . . .432
6.1.2 Po rt QA Digital Input/Output Pins  . . . . . . . . . . . . . . . . .433
6.2 Port QB Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . .433
6.2.1 Po rt QB Analog Input Pins. . . . . . . . . . . . . . . . . . . . . . .433
6.2.2 Po rt QB Digital Input Pins  . . . . . . . . . . . . . . . . . . . . . . .433
6.3 External Trigger Input Pins. . . . . . . . . . . . . . . . . . . . . . . . .434
6.4 Multiplexed Address Output Pins. . . . . . . . . . . . . . . . . . . .434
6.5 Multiplexed A n alog Input Pins . . . . . . . . . . . . . . . . . . . . . .435
6.6 Voltage Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . .435
6.7 Dedicated Analog Supply Pins. . . . . . . . . . . . . . . . . . . . . .435
6.8 Dedicated Digital I/O Port Supply Pin . . . . . . . . . . . . . . . . .435
7 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .436
8 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .437
8.1 QADC Module Configuration Register (QADCMCR) . . . . .437
8.2 QADC Test Register (QADCTEST) . . . . . . . . . . . . . . . . . .438
8.3 Port Data Registers (P ORTQA and PORTQB)  . . . . . . . . .438
8.4 Port QA and QB Data Direction Register 
(DDRQA and DDRQB) . . . . . . . . . . . . . . . . . . . . . . . . .440
8.5 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .442
8.5.1 QADC Control Register 0 (QACR0). . . . . . . . . . . . . . . .442
8.5.2 QADC Control Register 1 (QACR1). . . . . . . . . . . . . . . .445
8.5.3 QADC Control Register 2 (QACR2). . . . . . . . . . . . . . . .448
8.6 Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .453
8.6.1 QADC Status Register 0 (QASR0). . . . . . . . . . . . . . . . .453
8.6.2 QADC Status Register 1 (QASR1). . . . . . . . . . . . . . . . .462
8.7 Conversion Command Word Table (CCW) . . . . . . . . . . . .463
8.8 Result Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .468
8.8.1 Right-Justified Unsigned Result Register (RJURR). . . .468
8.8.2 Left-Justified Signed Result Register (LJSRR) . . . . . . .469
8.8.3 Left-Justified Unsigned Result Register (LJURR) . . . . .470
    
  
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MOTOROLA Table of Contents  23
9 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .470
9.1 Result Coherency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .470
9.2 External Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .471
9.2.1 External Multiplexing Operation. . . . . . . . . . . . . . . . . . .471
9.2.2 Module Version Options. . . . . . . . . . . . . . . . . . . . . . . . .473
9.3 Analog Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .474
9.3.1 Analog-to-Digital Converter Operation. . . . . . . . . . . . . .474
9.3.2 Conversion Cycle Times . . . . . . . . . . . . . . . . . . . . . . . .475
9.3.3 Channel Decode and Multiplexer. . . . . . . . . . . . . . . . . .476
9.3.4 Sa mple Buffer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .476
9.3.5 Digital-to-Analog Converter (DAC) Array. . . . . . . . . . . .476
9.3.6 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .477
9.3.7 Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .477
9.3.8 Successive Approximation Register. . . . . . . . . . . . . . . .477
9.3.9 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .477
10 Digital Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .478
10.1 Queue Priority Timing Examples . . . . . . . . . . . . . . . . . . . .478
10.1.1 Queue Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .478
10.1.2 Queue Priority Schemes . . . . . . . . . . . . . . . . . . . . . . . .481
10.2 Boundary Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .492
10.3 Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .493
10.4 Disabled Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .494
10.5 Reserved Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .494
10.6 Single-Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .494
10.6.1 Software-Initiated Single-Scan Mode. . . . . . . . . . . . . . .495
10.6.2 Externally Triggered Single-Scan Mode. . . . . . . . . . . . .496
10.6.3 Externally Gated Single-Scan Mode . . . . . . . . . . . . . . .497
10.6.4 Interval Timer Single-Scan Mode. . . . . . . . . . . . . . . . . .497
10.7 Continuous-Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . .499
10.7.1 Software-Initiated Continuous-Scan Mode. . . . . . . . . . .500
10.7.2 Externally Triggered Continuous-Scan Mode  . . . . . . . .501
10.7.3 Externally Gated Continuous-Scan Mode . . . . . . . . . . .501
10.7.4 Periodic Timer Continuous-Scan Mode . . . . . . . . . . . . .502
10.8 QADC Clock (QCLK) Generation. . . . . . . . . . . . . . . . . . . .503
10.9 Periodic/Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . .504
10.10 Conversion Command Word Table . . . . . . . . . . . . . . . . . .505
10.11 Result Word Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .509
    
  
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11 Pin Connection Considerations  . . . . . . . . . . . . . . . . . . . . . . .509
11.1 Analog Reference Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . .509
11.2 Analog Power Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .510
11.3 Conversion Timing Schemes . . . . . . . . . . . . . . . . . . . . . . .512
11.4 Analog Supply Filtering and Grounding . . . . . . . . . . . . . . .515
11.5 Accommodating Positive/Negative Stress Conditions . . . .517
11.6 Analog Input Considerations . . . . . . . . . . . . . . . . . . . . . . .519
11.7 Analog Input Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .521
11.7.1 Settling Time for the External Circuit . . . . . . . . . . . . . . .522
11.7.2 Error Resulting from Leakage . . . . . . . . . . . . . . . . . . . .523
12 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .524
12.1 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .524
12.2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .525
Section 20. External Bus Interface Module (EBI)
1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .527
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .528
3 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .529
3.1 Data Bus (D[31:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .530
3.2 Show Cycle Strobe (SHS) . . . . . . . . . . . . . . . . . . . . . . . . .530
3.3 Transfer Acknowledge (TA) . . . . . . . . . . . . . . . . . . . . . . . .530
3.4 Transfer Error Acknowledge (TEA) . . . . . . . . . . . . . . . . . .530
3.5 Emulation Mode Chip S e lects (CSE[1:0])  . . . . . . . . . . . . .530
3.6 Transfer Code (TC[2:0]). . . . . . . . . . . . . . . . . . . . . . . . . . .531
3.7 Read/Write (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .531
3.8 Address Bus (A[22:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . .531
3.9 Enable Byte (EB[3:0]). . . . . . . . . . . . . . . . . . . . . . . . . . . . .531
3.10 Chip Sele cts (CS[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . .531
3.11 Output Enable (OE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .531
3.12 Transfer Size (TSIZ[1:0]) . . . . . . . . . . . . . . . . . . . . . . . . . .532
3.13 Processor Status (PSTAT[3:0]) . . . . . . . . . . . . . . . . . . . . .532
4 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .532
5 Operand Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .532
6 Enable Byte Pins (EB[3:0]). . . . . . . . . . . . . . . . . . . . . . . . . . .534
    
  
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7 Bus Master Cycl es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .534
7.1 Read Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .535
7.1.1 State 1 (X1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .536
7.1.2 Optional Wait States (X2W). . . . . . . . . . . . . . . . . . . . . .536
7.1.3 State 2 (X2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .536
7.2 Write Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .537
7.2.1 State 1 (X1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538
7.2.2 Optional Wait States (X2W). . . . . . . . . . . . . . . . . . . . . .538
7.2.3 State 2 (X2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538
8 Bus Exception Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .540
8.1 Transfer Error Termination. . . . . . . . . . . . . . . . . . . . . . . . .540
8.2 Transfer Abort Termination  . . . . . . . . . . . . . . . . . . . . . . . .540
9 Emulation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .540
9.1 Emulation Chip-Selects (CSE[1:0]) . . . . . . . . . . . . . . . . . .540
9.2 Internal Data Transfer Display (Show Cycles) . . . . . . . . . .541
9.3 Show Strobe (SHS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .542
9.4 Transfer Code (TC[2:0]). . . . . . . . . . . . . . . . . . . . . . . . . . .543
9.5 Processor Status (PSTAT). . . . . . . . . . . . . . . . . . . . . . . . .543
10 Bus Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .545
11 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .545
Section 21. Chip Select Module
1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .547
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .547
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .548
4 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .549
5 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .550
6 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .550
6.1 Memory Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .550
6.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .551
7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .556
8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .557
    
  
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Section 22. JTAG Test Access Port and OnCE

22.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .559

22.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .561

22.3 Top-Level Test Access Port (TAP). . . . . . . . . . . . . . . . . . . . .563

22.3.1 Test Clock (TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .564

22.3.2 Test Mode Select (TMS) . . . . . . . . . . . . . . . . . . . . . . . . . .564

22.3.3 Test Data Input (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .564

22.3.4 Test Data Output (TDO). . . . . . . . . . . . . . . . . . . . . . . . . . .564

22.3.5 Test Reset (TRST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .564

22.3.6 Debug Event (DE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .564

22.4 Top-Level TAP Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . .566

22.5 Instruction Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .567

22.5.1 EXTEST Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .567

22.5.2 IDCODE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .568

22.5.3 SAMPLE/PRELOAD Instruction. . . . . . . . . . . . . . . . . . . . .569

22.5.4 ENABLE_MCU_ONCE Instruction. . . . . . . . . . . . . . . . . . .569

22.5.5 HIGHZ Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570

22.5.6 CLAMP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570

22.5.7 BYPASS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570

22.6 IDCODE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .571

22.7 Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .572

22.8 Boundary Scan Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .572

22.9 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .572

22.10 Non-Scan Chain Operation. . . . . . . . . . . . . . . . . . . . . . . . . . .573

22.11 Boundary Scan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .573

22.12 Low-Level TAP (OnCE) Module . . . . . . . . . . . . . . . . . . . . . . .579

22.13 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .581

22.13.1 Debug Serial Input (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . .581

22.13.2 Debug Serial Clock (TCLK) . . . . . . . . . . . . . . . . . . . . . . . .581

22.13.3 Debug Serial Output (TDO) . . . . . . . . . . . . . . . . . . . . . . . .581

22.13.4 Debug Mode Select (TMS). . . . . . . . . . . . . . . . . . . . . . . . .582

22.13.5 Test Reset (TRST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .582

22.13.6 Debug Event (DE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .582

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14 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .582
14.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .583
14.2 OnCE Controller and Serial Interface. . . . . . . . . . . . . . . . .584
14.3 OnCE Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . .585
14.3 . 1 In terna l  Debug Request Input (ID R)  . . . . . . . . . . . . . . .585
14.3.2 CPU Debug Request (DBGRQ). . . . . . . . . . . . . . . . . . .586
14.3.3 CPU Debug Acknowledge (DBGACK). . . . . . . . . . . . . .586
14.3.4 CPU Breakpoint Request (BRKRQ). . . . . . . . . . . . . . . .586
14.3.5 CPU A ddress, Attributes (ADDR, ATTR). . . . . . . . . . . .587
14.3.6 CPU Status (PSTAT). . . . . . . . . . . . . . . . . . . . . . . . . . .587
14.3.7 OnCE Debug Output (DEBUG) . . . . . . . . . . . . . . . . . . .587
14.4 OnCE Controller Registers. . . . . . . . . . . . . . . . . . . . . . . . .587
14.4.1 OnCE Command Register . . . . . . . . . . . . . . . . . . . . . . .588
14.4.2 OnCE Control Register  . . . . . . . . . . . . . . . . . . . . . . . . .590
14.4.3 OnCE Status Register . . . . . . . . . . . . . . . . . . . . . . . . . .594
14.5 OnCE Decoder (ODEC). . . . . . . . . . . . . . . . . . . . . . . . . . .596
14.6 Memory Breakpoint Logic. . . . . . . . . . . . . . . . . . . . . . . . . .596
14.6.1 Memory Address Latch (MAL) . . . . . . . . . . . . . . . . . . . .597
14.6.2 Breakpoint Address Base Registers  . . . . . . . . . . . . . . .597
14.7 Breakpoint Address Mask Registers . . . . . . . . . . . . . . . . .597
14.7.1 Breakpoint Address Comparators . . . . . . . . . . . . . . . . .598
14.7.2 Memory Breakpoint Counters  . . . . . . . . . . . . . . . . . . . .598
14.8 OnCE Tr ace Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .598
14.8.1 OnCE Trace Counter. . . . . . . . . . . . . . . . . . . . . . . . . . .599
14.8.2 Trace Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .600
14.9 Methods of Entering Debug Mode . . . . . . . . . . . . . . . . . . .600
14.9.1 Debug Request During RESET . . . . . . . . . . . . . . . . . . .600
14.9.2 Debug Request During Normal Activity . . . . . . . . . . . . .601
14.9.3 Debug Request During Stop, Doze, or Wait Mode  . . . .601
14.9.4 Software Request During Normal Activity . . . . . . . . . . .601
14.10 Enabling OnCE Trace Mode  . . . . . . . . . . . . . . . . . . . . . . .601
14.11 Enabling OnCE Memo ry Breakpoints. . . . . . . . . . . . . . . . .602
14.12 Pipeline Information and Write-Back Bus Register  . . . . . .602
14.12.1 Program Counter Register. . . . . . . . . . . . . . . . . . . . . . .603
14.12.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .603
14.12.3 Control State Register . . . . . . . . . . . . . . . . . . . . . . . . . .603
14.12.4 Writeback Bus Register . . . . . . . . . . . . . . . . . . . . . . . . .605
    
  
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22.14.12.5 Processor Status Register . . . . . . . . . . . . . . . . . . . . . . .605

22.14.13 Instruction Address FIFO Buffer (PC FIFO). . . . . . . . . . . .606

22.14.14 Reserved Test Control Registers. . . . . . . . . . . . . . . . . . . .607

22.14.15 Serial Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .607

22.14.16 OnCE Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .608

22.14.17 Target Site Debug System Requirements . . . . . . . . . . . . .608

22.14.18 Interface Connector for JTAG/OnCE Serial Port . . . . . . . .608

Section 23. Preliminary Electrical Specifications

23.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .611

23.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .612

23.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .613

23.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .614

23.5 Junction Temperature Determination . . . . . . . . . . . . . . . . . . .614

23.6 Electrostatic Discharge (ESD) Protection. . . . . . . . . . . . . . . .615

23.7 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .616

23.8 PLL Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . .618

23.9 QADC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . .620

23.10 FLASH Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . .624

23.11 External Interface Timing Characteristics. . . . . . . . . . . . . . . .625

23.12 General Purpose I/O Timing. . . . . . . . . . . . . . . . . . . . . . . . . .630

23.13 Reset and Configuration Override Timing . . . . . . . . . . . . . . .631

23.14 SPI Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .632

23.15 OnCE, JTAG, and Boundary Scan Timing . . . . . . . . . . . . . . .635

Section 24. Mechanical Specif ications

24.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .639

24.3 Bond Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .640

24.4 Package Information for the 144-Pin LQF P . . . . . . . . . . . . . .641

24.5 Package Information for the 100-Pin LQF P . . . . . . . . . . . . . .641

24.6 Package Information for the 196-Ball MAPBGA. . . . . . . . . . .642

24.7 144-Pin LQFP Mechanical Drawing . . . . . . . . . . . . . . . . . . . .643

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24.8 100-Pin LQFP Mechanical Drawing . . . . . . . . . . . . . . . . . . . .644
24.9 196-Ball MAPBGA Mechanical Drawing. . . . . . . . . . . . . . . . .645
Section 25. Ordering Information
25.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .647
25.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .647
25.3 MC Order Numbers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .647
Appendix A. Security
A.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .649
A.2 Security Philosophy/Strategy . . . . . . . . . . . . . . . . . . . . . . . . .649
A.3 MCU Operation with Security Enabled. . . . . . . . . . . . . . . . . .650
A.4 FLASH Access Blocking Mechanisms . . . . . . . . . . . . . . . . . .650
A.4.1 Forced Operating Mode Selection . . . . . . . . . . . . . . . . . . .650
A.4.2 Disabled OnCE Access . . . . . . . . . . . . . . . . . . . . . . . . . . .651
    
  
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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0  Advance Information
MOTO ROLA List of Figures  31
Advance Info rmation — MMC2114, MMC2113, and MMC2112
List of Figures
Figure Title Page
1-1 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
2-1 MMC2112 Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
2-2 MMC2113 Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
2-3 MMC2114 Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
2-4 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
3-1 196-Ball MAPBGA Assignments. . . . . . . . . . . . . . . . . . . . . . .103
3-2 144-Pin LQFP Assignments . . . . . . . . . . . . . . . . . . . . . . . . . .104
3-3 100-Pin LQFP Assignments . . . . . . . . . . . . . . . . . . . . . . . . . .105
4-1 Chip Configuration Module Block Diagram. . . . . . . . . . . . . . .124
4-2 Chip Configuration Register (CCR)  . . . . . . . . . . . . . . . . . . . .126
4-3 Reset Configuration Register (RCON) . . . . . . . . . . . . . . . . . .129
4-4 Chip Identification Register (CIR). . . . . . . . . . . . . . . . . . . . . .131
4-5 Chip Test Register (CTR). . . . . . . . . . . . . . . . . . . . . . . . . . . .132
5-1 Reset Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . .141
5-2 Reset Contro l Re gister (RCR) . . . . . . . . . . . . . . . . . . . . . . . .143
5-3 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . .145
5-4 Reset Control Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
7-1 M•CORE Processor Block Diagram . . . . . . . . . . . . . . . . . . . .167
7-2 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
7-3 Data Organization in Memory. . . . . . . . . . . . . . . . . . . . . . . . .171
7-4 Data Organization in Registers. . . . . . . . . . . . . . . . . . . . . . . .171
8-1 Interrupt Controller Block Diagram. . . . . . . . . . . . . . . . . . . . .179
8-2 Interrupt Control Register (ICR) . . . . . . . . . . . . . . . . . . . . . . .181
    
  
Freescale Semiconductor, I
                                               
Freescale Semiconductor, Inc.
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Advance Information MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
32 List of Figures M OTOROLA
Li st of  Figu r es
Figure Title Page
8-3 Interrupt Status Register (ISR) . . . . . . . . . . . . . . . . . . . . . . . .183
8-4 Interrupt Force Register High (IFRH) . . . . . . . . . . . . . . . . . . .184
8-5 Interrupt Force Register Low (IFRL). . . . . . . . . . . . . . . . . . . .185
8-6 Interrupt Pending Register (IPR)  . . . . . . . . . . . . . . . . . . . . . .186
8-7 Normal Interrupt Enable Register (NIER). . . . . . . . . . . . . . . .187
8-8 Normal Interrupt Pending Register (NIPR). . . . . . . . . . . . . . .188
8-9 Fast Interrupt Enable Register (FIER) . . . . . . . . . . . . . . . . . .189
8-10 Fast Interrupt Pending Register (FIPR) . . . . . . . . . . . . . . . . .190
8-11 Priority Level Select Registers (PLSR0–PLSR39) . . . . . . . . .191
10-1 SGFM Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .208
10-2 SGFM Array Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . .209
10-3 SGFM Module Configuration Register (SGFMCR). . . . . . . . .213
10-4 SGFM Clock Divider Register (SGFMCLKD) . . . . . . . . . . . . .215
10-5 SGFM Test Register (SGFMTST)  . . . . . . . . . . . . . . . . . . . . .216
10-6 SGFM Security Register (SGFMSEC) . . . . . . . . . . . . . . . . . .217
10-7 SGFM Monitor Data Register (SGFMMNTR). . . . . . . . . . . . .219
10-8 SGFM Protection Register (SGFMPROT) . . . . . . . . . . . . . . .220
10-9 SGFMPROT Protection Diagram . . . . . . . . . . . . . . . . . . . . . .221
10-10 SGFM Supervisor Access Register (SGFMASACC) . . . . . . .222
10-11 SGFM Data Access Register (SGFMDACC) . . . . . . . . . . . . .223
10-12 SGFM Test Status Register (SGFMTSTAT). . . . . . . . . . . . . .224
10-13 SGFM User Status Register (SGFMUSTAT) . . . . . . . . . . . . .224
10-14 SGFM Command Register (SGFMCMD) . . . . . . . . . . . . . . . .226
10-15 SGFM Control Register (SGFMCTL) . . . . . . . . . . . . . . . . . . .227
10-16 SGFM Address Register (SGFMADR) . . . . . . . . . . . . . . . . . .228
10-17 SGFM Data R egister (SGF MDATA). . . . . . . . . . . . . . . . . . . .229
10-18 Example Program Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . .235
10-19 SGFM Interrupt Implementation . . . . . . . . . . . . . . . . . . . . . . .241
11-1 Clock Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .247
11-2 Synthesizer Control Register (SYNCR) . . . . . . . . . . . . . . . . .250
11-3 Synthesizer Status Register (SYNSR) . . . . . . . . . . . . . . . . . .253
11-4 Synthesizer Test Register (SYNTR). . . . . . . . . . . . . . . . . . . .256
11-5 Synthesizer Test Register 2 (SYNTR2) . . . . . . . . . . . . . . . . .257
11-6 Lock Detect Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260
    
  
Freescale Semiconductor, I
                                               
Freescale Semiconductor, Inc.
For More Information On This Product,
   Go to: www.freescale.com
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List of Figures
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Informa tion 
MOTO ROLA List of Figures  33
Figure Title Page
11-7 PLL Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
11-8 Crystal Oscillator Example . . . . . . . . . . . . . . . . . . . . . . . . . . .2 6 7
12-1 Ports Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .272
12-2 Port Output Data Registers (PORTx) . . . . . . . . . . . . . . . . . . .275
12-3 Port Data Direction Registers (DDRx) . . . . . . . . . . . . . . . . . .276
12-4 Port P in Data/Set Data Registers (PORTxP/SETx) . . . . . . . .277
12-5 Port Clear Output Data Registers (CLRx). . . . . . . . . . . . . . . .278
12-6 Port C, D, I7, and I6 Pin Assignment
Register (PCDPAR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279
12-7 Port E Pin Assignment Register (PEPAR) . . . . . . . . . . . . . . .280
12-8 Digital Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
12-9 Digital Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
13-1 EPORT Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286
13-2 EPORT Pin Assignment Register (EPPAR) . . . . . . . . . . . . . .288
13-3 EPORT Data Direction Register (EPDDR). . . . . . . . . . . . . . .290
13-4 EPORT Port Interrupt E n able Register (EPIER). . . . . . . . . . .291
13-5 EPORT Po rt Data Register (EPDR) . . . . . . . . . . . . . . . . . . . .292
13-6 EPORT Po rt Pin Data Register (EPPDR). . . . . . . . . . . . . . . .292
13-7 EPORT Port Flag Register (EPFR)  . . . . . . . . . . . . . . . . . . . .293
14-1 Watchdog Timer Block Diagram. . . . . . . . . . . . . . . . . . . . . . .297
14-2 Watchdog Control Register (WCR). . . . . . . . . . . . . . . . . . . . .299
14-3 Watchdog Modulus Register (WMR) . . . . . . . . . . . . . . . . . . .301
14-4 Watchdog Count Register (WCNTR) . . . . . . . . . . . . . . . . . . .302
14-5 Watchdog Service Register (WSR)  . . . . . . . . . . . . . . . . . . . .303
15-1 PIT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
15-2 PIT C ontrol and Status Register (PCSR) . . . . . . . . . . . . . . . .309
15-3 PIT Modulus Register (PMR) . . . . . . . . . . . . . . . . . . . . . . . . .312
15-4 PIT Count Register (PCNTR) . . . . . . . . . . . . . . . . . . . . . . . . .313
15-5 Counter Reloading from the Modulus Latch. . . . . . . . . . . . . .314
15-6 Counter in Free-Running Mode . . . . . . . . . . . . . . . . . . . . . . .315
16-1 Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320
16-2 Timer Input Capture/Output Compare
Select Register  (TIMIOS). . . . . . . . . . . . . . . . . . . . . . . . . .324
    
  
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Advance Information MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
34 List of Figures M OTOROLA
Li st of  Figu r es
Figure Title Page
16-3 Timer Compare Force Register (TIMCFORC) . . . . . . . . . . . .325
16-4 Timer Output Compare 3 Mask Register (TIMOC3M) . . . . . .326
16-5 Timer Output Compare 3 Data Register (TIMOC3D) . . . . . . .327
16-6 Timer Counter Register High (TIMCNTH)  . . . . . . . . . . . . . . .328
16-7 Timer Counter Register Low (TIMCNTL) . . . . . . . . . . . . . . . .328
16-8 Timer System Control Register (TIMSCR1) . . . . . . . . . . . . . .329
16-9 Fast Clear Flag Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330
16-10 Timer T oggle-On-Overflow Register (TIMTOV) . . . . . . . . . . .330
16-11 Timer Control Register 1 (TIMCTL1) . . . . . . . . . . . . . . . . . . .331
16-12 Timer Control Register 2 (TIMCTL2) . . . . . . . . . . . . . . . . . . .332
16-13 Timer Interrupt Enable Register (TIMIE). . . . . . . . . . . . . . . . .333
16-14 Timer System Control Register 2 (TIMSCR2)  . . . . . . . . . . . .334
16-15 Timer Flag Register 1 (TIMFLG1). . . . . . . . . . . . . . . . . . . . . .336
16-16 Timer Flag Register 2 (TIMFLG2). . . . . . . . . . . . . . . . . . . . . .337
16-17 Timer Channel [0:3] Register High (TIMCxH). . . . . . . . . . . . .338
16-18 Timer Channel [0:3] Register Low (TIMCxL) . . . . . . . . . . . . .338
16-19 Pulse Accumulator Control Register (TIMPACTL) . . . . . . . . .339
16-20 Pulse Accumulator Flag Register (TIMPAFLG) . . . . . . . . . . .341
16-21 Pulse Accumulator Counter Register High
(TIMPACNTH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342
16-22 Pulse Accumulator Counter Register Low
(TIMPACNTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342
16-23 Timer Port Data Register (TIMPORT)  . . . . . . . . . . . . . . . . . .343
16-24 Timer Port Data Direction Register (TIMDDR) . . . . . . . . . . . .344
16-25 Timer T e st Register (TIMTST) . . . . . . . . . . . . . . . . . . . . . . . .345
16-26 Channel 3 Output Compare/Pulse Accumulator Logic. . . . . .348
17-1 SCI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356
17-2 SCI Baud Rate Register High (SCIBDH) . . . . . . . . . . . . . . . .360
17-3 SCI Baud Rate Register Low (SCIBDL) . . . . . . . . . . . . . . . . .360
17-4 SCI Control Register 1 (SCICR1). . . . . . . . . . . . . . . . . . . . . .361
17-5 SCI Control Register 2 (SCICR2). . . . . . . . . . . . . . . . . . . . . .364
17-6 SCI Status Register 1 (SCISR 1). . . . . . . . . . . . . . . . . . . . . . .366
17-7 SCI Status Register 2 (SCISR 2). . . . . . . . . . . . . . . . . . . . . . .369
17-8 SCI Data Register High (SCIDRH). . . . . . . . . . . . . . . . . . . . .370
17-9 SCI Data Register Low (SCIDRL). . . . . . . . . . . . . . . . . . . . . .370
    
  
Freescale Semiconductor, I
                                               
Freescale Semiconductor, Inc.
For More Information On This Product,
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List of Figures
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Informa tion 
MOTO ROLA List of Figures  35
Figure Title Page
17-10 SCI Pullup and Reduced Drive Register (SCIPURD). . . . . . .371
17-11 SCI Port Data Register (SCIPORT) . . . . . . . . . . . . . . . . . . . .372
17-12 SCI Data Direction Register (SCIDDR)  . . . . . . . . . . . . . . . . .373
17-13 SCI Data F o rmats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
17-14 Transmitter Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .376
17-15 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .381
17-16 Receiver Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . .382
17-17 Start Bit Sear ch Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . .384
17-18 Start Bit Sear ch Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . .385
17-19 Start Bit Sear ch Example 3. . . . . . . . . . . . . . . . . . . . . . . . . . .385
17-20 Start Bit Sear ch Example 4. . . . . . . . . . . . . . . . . . . . . . . . . . .386
17-21 Start Bit Sear ch Example 5. . . . . . . . . . . . . . . . . . . . . . . . . . .386
17-22 Start Bit Sear ch Example 6. . . . . . . . . . . . . . . . . . . . . . . . . . .387
17-23 Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .388
17-24 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389
17-25 Single-Wire Oper ation (LOOPS = 1, RSRC = 1) . . . . . . . . . .392
17-26 Loop Operation (LOOPS = 1, RSRC = 0). . . . . . . . . . . . . . . .393
18-1 SPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
18-2 SPI Control Register 1 (SPICR1) . . . . . . . . . . . . . . . . . . . . . .402
18-3 SPI Control Register 2 (SPICR2) . . . . . . . . . . . . . . . . . . . . . .405
18-4 SPI Baud Rate Register (SPIBR) . . . . . . . . . . . . . . . . . . . . . .406
18-5 SPI Status Register (SPISR) . . . . . . . . . . . . . . . . . . . . . . . . .408
18-6 SPI Data Register (SPIDR). . . . . . . . . . . . . . . . . . . . . . . . . . .409
18-7 SPI Pullup and Reduced Drive Register (SPIPURD) . . . . . . .410
18-8 SPI Port Data Register (SPIPORT) . . . . . . . . . . . . . . . . . . . .411
18-9 SPI Port Data Direction Register (SPIDDR). . . . . . . . . . . . . .412
18-10 Full-Duplex Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .413
18-11 SPI Clock Format 1 (CPHA = 1). . . . . . . . . . . . . . . . . . . . . . .417
18-12 SPI Clock Format 0 (CPHA = 0). . . . . . . . . . . . . . . . . . . . . . .418
18-13 Transmission Error Due to Master/Slave Clock Skew . . . . . .419
19-1 QADC Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .429
19-2 QADC Input and Output Signals. . . . . . . . . . . . . . . . . . . . . . .432
19-3 QADC Module Configuration Register (QADCMCR) . . . . . . .437
19-4 QADC Test Register (QADCTEST) . . . . . . . . . . . . . . . . . . . .438
    
  
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Freescale Semiconductor, Inc.
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Advance Information MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
36 List of Figures M OTOROLA
Li st of  Figu r es
Figure Title Page
19-5 QADC Port QA Data Register (PORT QA) . . . . . . . . . . . . . . .439
19-6 QADC Port QB Data Register (PORT QB) . . . . . . . . . . . . . . .439
19-7 QADC Port QA Data Direction Register (DDRQA) 
and Port QB Data Direction Register (DDRQB)  . . . . . . . .441
19-8 QADC Contro l Register 0 (QACR0) . . . . . . . . . . . . . . . . . . . .442
19-9 QADC Contro l Register 1 (QACR1) . . . . . . . . . . . . . . . . . . . .445
19-10 QADC Control Register 2 (QACR2) . . . . . . . . . . . . . . . . . . . .448
19-11 QADC Status Register 0 (QASR0). . . . . . . . . . . . . . . . . . . . .453
19-12 Queue Status Transition. . . . . . . . . . . . . . . . . . . . . . . . . . . . .461
19-13 QADC Status Register 1 (QASR1). . . . . . . . . . . . . . . . . . . . .462
19-14 Conversion Command Word Table (CCW)  . . . . . . . . . . . . . .464
19-15 Right-Justified Unsigned Result Register (RJURR) . . . . . . . .468
19-16 Left-Justified Signed Result Register (LJSRR). . . . . . . . . . . .469
19-17 L eft-Justified Unsigned Result Register ( LJURR). . . . . . . . . .470
19-18 External Multiplexing Configuration . . . . . . . . . . . . . . . . . . . .472
19-19 QADC Analog Subsystem Block Diagram . . . . . . . . . . . . . . .474
19-20 Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .475
19-21 Bypass Mode Conversion  Timing. . . . . . . . . . . . . . . . . . . . . .476
19-22 QADC Queue Operation with Pause . . . . . . . . . . . . . . . . . . .480
19-23 CCW Priority Situation 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .483
19-24 CCW Priority Situation 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .483
19-25 CCW Priority Situation 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .484
19-26 CCW Priority Situation 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . .484
19-27 CCW Priority Situation 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . .485
19-28 CCW Priority Situation 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . .486
19-29 CCW Priority Situation 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . .486
19-30 CCW Priority Situation 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .487
19-31 CCW Priority Situation 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . .487
19-32 CCW Priority S ituation 10. . . . . . . . . . . . . . . . . . . . . . . . . . . .488
19-33 CCW Priority S ituation 11. . . . . . . . . . . . . . . . . . . . . . . . . . . .488
19-34 CCW Freeze Situation 12. . . . . . . . . . . . . . . . . . . . . . . . . . . .489
19-35 CCW Freeze Situation 13. . . . . . . . . . . . . . . . . . . . . . . . . . . .489
19-36 CCW Freeze Situation 14. . . . . . . . . . . . . . . . . . . . . . . . . . . .490
19-37 CCW Freeze Situation 15. . . . . . . . . . . . . . . . . . . . . . . . . . . .490
19-38 CCW Freeze Situation 16. . . . . . . . . . . . . . . . . . . . . . . . . . . .490
19-39 CCW Freeze Situation 17. . . . . . . . . . . . . . . . . . . . . . . . . . . .491
    
  
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For More Information On This Product,
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List of Figures
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Informa tion 
MOTO ROLA List of Figures  37
Figure Title Page
19-40 CCW Freeze Situation 18. . . . . . . . . . . . . . . . . . . . . . . . . . . .491
19-41 CCW Freeze Situation 19. . . . . . . . . . . . . . . . . . . . . . . . . . . .491
19-42 QADC Clock Subsystem Functions . . . . . . . . . . . . . . . . . . . .503
19-43 QADC Conversion Queue Operation . . . . . . . . . . . . . . . . . . .506
19-44 Equivalent Analog Input Circuitry . . . . . . . . . . . . . . . . . . . . . .510
19-45 Errors Resulting from Clipping . . . . . . . . . . . . . . . . . . . . . . . .511
19-46 External Positive Edge Trigger Mode Timing with Pause. . . .512
19-47 Gated Mode, Single S can Timing. . . . . . . . . . . . . . . . . . . . . .514
19-48 Gated Mode, Continuous Scan Timing. . . . . . . . . . . . . . . . . .514
19-49 Star-Ground at the Point of Po wer Supply Origin. . . . . . . . . .516
19-50 Input Pin Subjected to Negative Stress . . . . . . . . . . . . . . . . .518
19-51 Input Pin Subjected to Positive Stress . . . . . . . . . . . . . . . . . .518
19-52 External Multiple xing of Analog Signal Sour ces. . . . . . . . . . .520
19-53 Electrical Model of an A/D Input Pin. . . . . . . . . . . . . . . . . . . .521
20-1 Read Cycle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .535
20-2 Write Cycle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .537
20-3 M aster Mode  — 1-Clock Read and Write Cycle. . . . . . . . . . .539
20-4 M aster Mode  — 2-Clock Read and Write Cycle. . . . . . . . . . .539
20-5 Internal (Show) Cycle Followed by External 1-Clock Read . .542
20-6 Internal (Show) Cycle Followed by External 1-Clock Write  . .543
21-1 Chip Select Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .549
21-2 Chip Select Control Register 0 (CSCR0) . . . . . . . . . . . . . . . .551
21-3 Chip Select Control Register 1 (CSCR1) . . . . . . . . . . . . . . . .552
21-4 Chip Select Control Register 2 (CSCR2) . . . . . . . . . . . . . . . .552
21-5 Chip Select Control Register 3 (CSCR3) . . . . . . . . . . . . . . . .553
22-1 Top-Level Tap Module and Low-Level (OnCE)
TAP Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .562
22-2 Top-Level TAP Controller State Machine. . . . . . . . . . . . . . . .566
22-3 IDCODE Register  Bit Specification. . . . . . . . . . . . . . . . . . . . .571
22-4 OnCE Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .579
22-5 Low-Level (OnCE) Tap Module Data Registers (DRs). . . . . .580
22-6 OnCE Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .583
22-7 OnCE Controller and Serial Interface. . . . . . . . . . . . . . . . . . .585
    
  
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Advance Information MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
38 List of Figures M OTOROLA
Li st of  Figu r es
Figure Title Page
22-8 OnCE Interface Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . .586
22-9 OnCE Command Register (OCMR) . . . . . . . . . . . . . . . . . . . .588
22-10 OnCE Control Register (OCR) . . . . . . . . . . . . . . . . . . . . . . . .590
22-11 OnCE Status Register (OSR). . . . . . . . . . . . . . . . . . . . . . . . .594
22-12 OnCE Memory Breakpo int Logic . . . . . . . . . . . . . . . . . . . . . .596
22-13 OnCE Trace Logic Block Diagram . . . . . . . . . . . . . . . . . . . . .599
22-14 CPU Scan Chain Register (CPUSCR) . . . . . . . . . . . . . . . . . .602
22-15 Control State Register (CTL) . . . . . . . . . . . . . . . . . . . . . . . . .604
22-16 OnCE PC FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .606
22-17 Recommended Connector Interface to JTAG/OnCE Port . . .609
23-1 CLKOUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .626
23-2 Clock Read/Wr ite Cycle Timing . . . . . . . . . . . . . . . . . . . . . . .627
23-3 Read/Write Cycle Timing with Wa it States. . . . . . . . . . . . . . .628
23-4 Show Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .629
23-5 GPIO Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .630
23-6 RESET and Configuration Override Timing . . . . . . . . . . . . . .631
23-7 SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .633
23-8 Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .635
23-9 Boundary Scan (JTAG) Timing. . . . . . . . . . . . . . . . . . . . . . . .636
23-10 Test Access Port Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .636
23-11 TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .636
23-12 Debug Event Pin Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .637
    
  
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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0  Advance Information
MOTO ROLA List of Tables  39
Advance Info rmation — MMC2114, MMC2113, and MMC2112
List of Tables
Table Title Page
1-1 Package Option Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
2-1 Register Address Location Map . . . . . . . . . . . . . . . . . . . . . . . .56
3-1 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
3-2 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
4-1 Signal Properties  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
4-2 Write-Once Bits Read/Write Accessibility. . . . . . . . . . . . . . . .125
4-3 Chip Configuration Module Memory Map. . . . . . . . . . . . . . . .126
4-4 Chip Configuration Mode Se lection . . . . . . . . . . . . . . . . . . . .127
4-5 Bus Monitor Timeout Va lues. . . . . . . . . . . . . . . . . . . . . . . . . .129
4-6 Reset Configuration Pin States During Reset. . . . . . . . . . . . .133
4-7 Configuration During Reset . . . . . . . . . . . . . . . . . . . . . . . . . .134
4-8 Chip Configuration Mode Se lection . . . . . . . . . . . . . . . . . . . .135
4-9 Chip Sele ct CS0 Configuration Encoding. . . . . . . . . . . . . . . .136
4-10 Boot Device Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
4-11 Output Pad Driver Strength Selection. . . . . . . . . . . . . . . . . . .137
4-12 Clock Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
5-1 Reset Controller Signal Properties . . . . . . . . . . . . . . . . . . . . .141
5-2 Reset Controller Address Map . . . . . . . . . . . . . . . . . . . . . . . .142
5-3 Reset Source S u mmary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
6-1 CPU and Peripherals in Low-Power Modes . . . . . . . . . . . . . .164
7-1 M•CORE Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
    
  
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Advance Information MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
40 List of Tables MOTOROLA
Li st of  Tab les
Table Title Page
8-1 Interrupt Controller Module Memory Map. . . . . . . . . . . . . . . .180
8-2 MASK Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
8-3 Priority Select Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
8-4 Fast Interrupt Vector Number. . . . . . . . . . . . . . . . . . . . . . . . .194
8-5 Vector Table Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
8-6 Interrupt Source Assignment . . . . . . . . . . . . . . . . . . . . . . . . .197
10-1 SGFM Configuration Field . . . . . . . . . . . . . . . . . . . . . . . . . . .211
10-2 SGFM Register Address Map. . . . . . . . . . . . . . . . . . . . . . . . .212
10-3 Register Bank Select Decoding . . . . . . . . . . . . . . . . . . . . . . .215
10-4 Security States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
10-5 SGFMCMD User Mode Commands. . . . . . . . . . . . . . . . . . . .226
10-6 FLASH User Mode Commands . . . . . . . . . . . . . . . . . . . . . . .234
10-7 SGFM Interrupt Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
11-1 Signal Properties  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
11-2 Clock Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . .249
11-3 System Frequency Multiplier of the Reference 
Frequency in Normal PLL Mode . . . . . . . . . . . . . . . . . . . .251
11-4 STPMD[1:0] Operation in Stop Mode. . . . . . . . . . . . . . . . . . .253
11-5 System Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254
11-6 Clock-Out and Clock-In Relationships . . . . . . . . . . . . . . . . . .258
11-7 Loss of Clock Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
11-8 Stop Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
11-9 Charge Pump Current and MFD
in Normal Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . .268
12-1 I/O Port Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . .274
12-2 PEPAR Reset Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280
12-3 Ports A–I Supported Pin Functions. . . . . . . . . . . . . . . . . . . . .282
13-1 Edge P ort Module Memory Map. . . . . . . . . . . . . . . . . . . . . . .287
13-2 EPPAx Field Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
14-1 Watchdog Timer Module Memory Map. . . . . . . . . . . . . . . . . .298
    
  
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List of Tables
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Informa tion 
MOTO ROLA List of Tables  41
Table Title Page
15-1 Programmable Interrupt Timer Modules Memory Map. . . . . .308
15-2 Prescaler Select Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . .310
15-3 PIT Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316
16-1 Signal Properties  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
16-2 Timer Modules Memory Map . . . . . . . . . . . . . . . . . . . . . . . . .323
16-3 Output Compare Action Selection  . . . . . . . . . . . . . . . . . . . . .331
16-4 Input Capture Edge Selection. . . . . . . . . . . . . . . . . . . . . . . . .332
16-5 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
16-6 Clock Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340
16-7 Timer Settings and Pin Functions. . . . . . . . . . . . . . . . . . . . . .350
16-8 Timer Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . .351
17-1 Signal Properties  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
17-2 Serial Communications Interface Module Memory Map. . . . .359
17-3 SCI Normal, Loop, and Single-Wire Mode 
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362
17-4 Example Baud Rates (System Clock = 33 MHz) . . . . . . . . . .375
17-5 Example 10-Bit and 11-Bit Frames. . . . . . . . . . . . . . . . . . . . .377
17-6 Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383
17-7 Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383
17-8 Stop B it Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .384
17-9 SCI Port Control Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .394
17-10 SCI Interrupt Request Sources. . . . . . . . . . . . . . . . . . . . . . . .395
18-1 Signal Properties  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400
18-2 SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402
18-3 SS Pin I/O Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . .404
18-4 Bidirectional Pin Configurations . . . . . . . . . . . . . . . . . . . . . . .405
18-5 SPI Baud Rate Selection (33-MHz Module Clock) . . . . . . . . .407
18-6 SPI Port Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411
18-7 Normal Mode and Bidirectional Mode. . . . . . . . . . . . . . . . . . .421
18-8 SPI Interrupt Request Sources. . . . . . . . . . . . . . . . . . . . . . . .424
19-1 Multiplexed Analog Input Channels . . . . . . . . . . . . . . . . . . . .435
19-2 QADC Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .436
    
  
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Advance Information MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
42 List of Tables MOTOROLA
Li st of  Tab les
Table Title Page
19-3 Prescaler fSYS Divide-by Values. . . . . . . . . . . . . . . . . . . . . . .444
19-4 Queue 1 Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . .446
19-5 Queue 2 Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . .449
19-6 CCW Pause Bit Response . . . . . . . . . . . . . . . . . . . . . . . . . . .455
19-7 Queue Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .458
19-8 Input Sample Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .465
19-9 Non-Multiplexed Channel Assignments
and Pin Designations. . . . . . . . . . . . . . . . . . . . . . . . . . . . .466
19-10 Mul tiplexed C hanne l Assignment s
and Pin Designations. . . . . . . . . . . . . . . . . . . . . . . . . . . . .467
19-11 Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .473
19-12 Trigger Events  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .481
19-13 Status Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .482
19-14 External Circuit Settling Time to 1/2 LSB . . . . . . . . . . . . . . . .523
19-15 Error Resulting from Input Leakage (IOff) . . . . . . . . . . . . . . . .524
19-16 QADC Status Flags and Interrupt Sources. . . . . . . . . . . . . . .524
20-1 Signal Properties  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .529
20-2 Data Transfer Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .533
20-3 EB[3:0] Assertion Encoding . . . . . . . . . . . . . . . . . . . . . . . . . .534
20-4 Emulation Mode Chip-Select Summary . . . . . . . . . . . . . . . . .541
20-5 Transfer Code Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . .544
20-6 Processor Status Encoding  . . . . . . . . . . . . . . . . . . . . . . . . . .544
21-1 Signal Properties  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .550
21-2 Chip Select Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . .550
21-3 Chip Select Wait States Encoding . . . . . . . . . . . . . . . . . . . . .555
21-4 Chip Select Address Range Encoding . . . . . . . . . . . . . . . . . .557
22-1 JTAG Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .568
22-2 List of Pins Not Scanned in JTAG Mode  . . . . . . . . . . . . . . . .574
22-3 Boundary Scan Register Definition. . . . . . . . . . . . . . . . . . . . .575
22-4 OnCE Register Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . .589
22-5 Sequential Control Field Settings. . . . . . . . . . . . . . . . . . . . . .591
22-6 Memory Breakpoint Control Field Settings. . . . . . . . . . . . . . .593
22-7 Processor Mode Field Settings. . . . . . . . . . . . . . . . . . . . . . . .595
    
  
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List of Tables
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Informa tion 
MOTO ROLA List of Tables  43
Table Title Page
23-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .613
23-2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .614
23-3 ESD Protection Characteristics  . . . . . . . . . . . . . . . . . . . . . . .615
23-4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .616
23-5 PLL Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . .618
23-6 QADC Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . .620
23-7 QADC Electrical Specifications (Operating) . . . . . . . . . . . . . .621
23-8 QADC Conversion Specifications (Operating) . . . . . . . . . . . .622
23-9 SGFM FLASH Program and Erase Characteristics . . . . . . . .624
23-10 SGFM FLASH Module Life Characteristics  . . . . . . . . . . . . . .624
23-11 External Interface Timing Characteristics  . . . . . . . . . . . . . . .625
23-12 GPIO Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .630
23-13 Reset and Configuration Override Timing  . . . . . . . . . . . . . . .631
23-14 SPI Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .632
23-15 OnCE, JTAG, and Boundary Scan Timing . . . . . . . . . . . . . . .635
25-1 MC Order Numbers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .647
    
  
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Advance Information MMC2114 • MMC2113 • MMC2112 — Rev. 1.0

44 List of Tables MOTOROLA

Li st of Tab les

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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Information

MOTOROLA General Description 45

Advance Info rmation — MMC2114, MMC2113, and MMC2112

Section 1. General Descrip tion

1.1 Contents

1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

1.2 Introduc tion

The MMC2114, MMC2113, and MMC2112 are members of a family of

general-purpose microcontrollers (MCU) based on the M•CORE M210

central pr ocessor unit (CPU).

These are low-voltage devices that operate between 2.7 volts and

3.6 volts. They are well suited for use in battery-powered applications.

The m aximum op erat ing freque ncy is 33 M Hz over a temp erature rang e

of –40°C to 85°C.

Avail able package s are:

•100-pin low-profile quad flat pack (LQFP) for single-chip mode

operation

•144-pin LQFP for applications requiring an external memory

interface or a large number of general-purpose inputs/outputs

(GPIO)

•196-ball plastic mold array process ball grid array (MAPBGA)

provi ding the same fun ctionality as the 14 4-pin LQFP in a smaller

form factor

Table 1-1 summarizes the memory sizes, package options, and

operating modes of the MMC2112, MMC2113, and MMC2114.

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Advance Information MMC2114 • MMC2113 • MMC2112 — Rev. 1.0

46 Gen eral D es cri ptio n MOTOR OLA

General Description

NOTE: The MMC2113 may contain more than 8K of interna l SRAM, bu t only the

8K range from 0x0080_0000 to 0x0080_1fff is tested and guara nteed to

be ope rational. It is recommended that internal SRAM outside this range

not be used. Accesses to SRAM outside this range terminate without a

transfer error exception.

1.3 Features

Features include:

• M•CORE M210 integer processor:

–32-bit reduced instruction set computer (RISC) architecture

–Low power and high performance

•OnCE debug support

•128 Kbytes (MMC2113) or 256 Kbytes (M MC2114) FLASH

memory(1):

–Single cycle byte, half-word (16-bit) and word (32-bit) reads

–Fast automated program and erase cycles

–Ability to program one FLASH bank while executing from

another (MMC2114 only)

–Interrupt on program/erase command completion

–Flexible protection scheme for accidental program/erase

–Access restriction controls for both superviso r/user and

data/program spaces

Table 1-1. Package Option Summary

Device On-Chip SRA M

(Kbytes) On -Chi p FLASH

(Kbytes) Packages Operating

Modes(1)

1. See 4.4 Modes of Operat ion for descriptio ns of t he dif ferent MCU operating modes.

MMC2112 32 —144 LQFP

196 MAPBGA Master only

MMC2113 8 128 100 LQFP

144 LQFP

196 MAPBGA

Single chip

Master

Emulation

MMC2114 32 256

1. The MMC21 12 has no integrated FLASH memory and is intended for use wit h external

non-volatile memory devices.

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General Description

Features

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Informa tion

MOTOROLA General Description 47

–Enhanced security feature prevents unauthorized access to

contents of FLASH (protects company IP)

–Single supply operation (no need for separate, high voltage

program/erase supply)

•8 Kbytes (M MC2113) or 32 K bytes (MMC211 2 a nd MMC2114) of

static random -access memory (SRAM):

–Single cycle byte, half-word (16-bit), and word (32-bit) reads

and writes

–Standby power supply support

•Serial peripheral interface (SPI):

–Master mode and slave mode

–Wired-OR mode

–Slave select output

–Mode fault error flag with CPU interrupt capability

–Double-buffered receiver

–Serial clock with programmable polarity and phase

–Control of SPI operation during wait mode

–Reduced drive control

–General-purpose input/output (I/O) capability

•Two serial communications interfaces (SCI):

–Full- duplex operation

–Standard mark/space non-return-to- zero (NRZ) format

–13-bit baud rate prescaler

–Programmable 8-bit or 9-bit data format

–Separately enabled transmitter and receiver

–Separate receiver and transmitter CPU interrupt requests

–Two receiver wakeup methods (idle line and address mark)

–Receiver framing error detection

–Hardwa re parity checking

–1/16 bit-time noise detection

–Reduced drive control

–General-purpose I/O capability

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48 Gen eral D es cri ptio n MOTOR OLA

General Description

•Two timers:

–Four 16-bit input capture/output compare channels

–16-bit architecture

–16-bit pulse accumulator

–Pulse widths variab le from microseconds to seconds

–Eight selectable prescalers

–Toggle-on-overflow feature for pulse-width modulation

•Queued analog-to-digital converter (QADC):

–Eight analog input channels

–10-bit resolution ±2 counts accuracy

–Minimum 7 µs conversion tim e

–Internal sample and hold

–Programmable input sample time for various source

impedances

–Two conversion command queues with a total of 64 entries

–Subqueues possible usi ng pause mechanism

–Queue complete and pause interrupts available on both

queues

–Queue pointers indicate current location for each queue

–Automated queue modes initiated by:

External edge trigger and gated trigger

Periodic/interval timer, within queued analog-to-digital

converter (QADC) module {queue1 and queue2}

Software command

–Single-scan or continuous-scan of queues

–Output data readable in three formats:

Right-justified unsigned

Left-justified signed

Left-justified unsigned

–Unused analog channels can be used as digital I/O

–Minimum pin set configuration implemented

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General Description

Features

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Informa tion

MOTOROLA General Description 49

•Interrupt controller:

–Up to 40 interrupt sources

–32 unique programmable priority levels for each interrupt

source

–Independent enable/disable of pending interrupts based on

priority level

–Normal or fast i nterrupt request for each priority level

–Fast interrupt requests always have priority over normal

interrupts

–Ability to mask interrupts at and below a defined priority level

–Ability to select between autovectored or vectored interrupt

requests

–Vectored interrupts generated based on priority level

–Ability to generate a separate vector number for normal and

fast interrupts

–Ability for software to self-schedule interrupts

–Softwar e visibility of pending inte rrupts an d interr upt signals t o

core

–Asynchronous operation to support wakeup from low-power

modes

•External interrupts supported:

–Rising/falling edge select

–Low-level sensitive

–Ability for software generation of external interrupt event

–Interrupt pins configurable as general-purpose I/O

•Two periodic interval timers:

–16-bit counter with modulus "initial count" register

–Selectable as free running or count down

–16 selectable prescalers — 20 to 215

•Watchdog timer:

–16-bit counter with modulus "initial count" register

–Pause option for low-power modes

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50 Gen eral D es cri ptio n MOTOR OLA

General Description

•Phase-lock loop (PLL):

–Reference crystal from 2 to 10 MHz

–Low- power modes supported

–Separate clock-out signal

•Integrated low-voltage detector (LVD):

–Can be enabled and disabled under software control

–Sets flag when VDD drops below internal bandgap reference

threshold

–Reset and interrupt request enable bits

–Optional automatic disabling in low-power stop mode

• Reset:

–Sepa rate reset in and reset out sign als

–Seven sources of reset:

Power- on reset (P OR )

External

Software

Watchdog timer

Loss of clock

Loss of PLL lock

Low- voltage detect

–Status flag indicates source of last reset

•Chip configur ations:

–Support for single-chip, master, emulation, and test modes

–System configuration during reset

–Bus monitor

–Configurable output pad drive strength control

•General-purpose input/output (GPIO):

–Up to 72 bits of GPIO

–Coherent 32-bit control

–Bit manipulation supported via set/clear functions

–Unused peripheral pins may be used as extra GPIO.

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General Description

Block Diagram

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Informa tion

MOTOROLA General Description 51

•External bus interface:

–Provides for direct support of asynchronous random-access

memory (RAM), read-only memory (ROM), FLASH, and

memory mapped peripherals

–Bidirectional data bus with wide (32-bit) and narrow (16-bi t)

modes

–23-bit address bus with four chip selects provide access to

32 Mbytes of external memory

–Byte/write enables

–Boot from on-chip FLASH or external memories

–Internal bus activity is visible via show -cycle mode

–Special chip selects support replacement of GPIO with

ext erna l port replacement logic

•Joint Test Action Group (JTAG) support for system-level board

testing

1.4 Block Diagram

The basic structure of these devices is shown in Figure 1-1.

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52 Gen eral D es cri ptio n MOTOR OLA

General Description

Figure 1-1. Block Diagram

FLASH

CONTR OLL E R OSC/PLL

RESET

SPI

SRAM

SCI1 SCI2

INTERRUPT

IPBUS

INTERFACE

TMS

TDI

TDO

TCLK

TRST

INT[7:0]

MISO

TXD2

RXD2

TIM1 TIM2

ICOC1[3:0]

PQB[3:0]

VRL, VRH

VDDA, VSSA

EXTAL

XTAL

PLLEN

CLKOUT

RESET

RSTOUT

D[31:0]

VSS x 8

VDD x 8

PORTS

128 KBYT ES (MMC21 13)8 KBYTES (MMC2113)

STBY

ICOC2[3:0]

TXD1

RXD1

POR

PROGRAMMABLE

INTERVAL

TIMER 2

WATCHDOG

TIMER

ADC

MOSI

SCK

TEST

PROGRAMMABLE

INTERVAL

TIMER 1

EDGE

PORT

PSTAT[3:0]

CPU

A[22:0]

R/W

EB[3:0]

CS[3:0]

TC[2:0]

SHS

CSE[1:0]

TEA

TEST

PQA[4:3]

PQA[1:0]

VDDH

CPU BUS

E X TERNAL M E MORY INTERFACE

IPBUS

OnCE

JTAG

TAP

32 KBYT ES (M MC 2112/4) 256 KBYT ES (MMC21 14)

DDF

SSF

LVD

0 KBYTE (MMC2112)

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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Information

MOTOROLA System Mem ory Map 53

Advance Info rmation — MMC2114, MMC2113, and MMC2112

Section 2. System Memory Ma p

2.1 Contents

2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

2.3 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

2.4 Register Ma p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

2.2 Introduc tion

The address maps, shown in Figure 2-1, Figure 2-2, and Figure 2-3,

include:

•Internal FLASH:

–256 Kbytes (MMC2114)

–128 Kbytes (MMC2113)

–0 Kbytes (MMC211 2)

•Internal static random-access memory (SRAM):

–32 Kbytes (MMC2112 and MMC2114)

–8 Kbytes (MMC211 3)

•Internal memory mapped registers

•External address space

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54 System Memory Map MOTOR OLA

System Memory Map

2.3 Address Map

Figure 2-1. MMC2112 Ad dress Map

Figure 2-2. MMC2113 Ad dress Map

INTER N AL SR AM

EXTERNAL MEMORY

0x00c0_0000

0x0080_0000 32 KBY TE S

0x0080_7fff

REGISTERS

SEE TABLE 2-1

0x8000_0000

0xffff_ffff

0x00d0_002f

0x0000_0000

INTERNAL FLASH

INTER N AL SR AM

EXTERNAL MEMORY

0x00c0_0000

0x0000_0000

8 KBYTES

128 KBYTES

0x0080_1fff

REGISTERS

SEE TABLE 2-1

0x8000_0000

0x0080_0000

0xffff_ffff

0x00d0_002f

0x0001_ffff

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System Memory Map

Address Map

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Informa tion

MOTOROLA System Mem ory Map 55

NOTE: The MMC2113 may contain more than 8K of interna l SRAM, bu t only the

8K range from 0x0080_0000 to 0x0080_1fff is tested and guara nteed to

be ope rational. It is recommended that internal SRAM outside this range

not be used. Accesses to SRAM outside this range terminate without a

transfer error exception.

Figure 2-3. MMC2114 Ad dress Map

INTE RNAL FLASH

INTER N AL SR AM

EXTERNAL MEMORY

0x00c0_0000

0x0000_0000

32 KBYTE S

256 KBYTES

0x0080_0000

REGISTERS

SEE TABLE 2-1

0x8000_0000

0x0080_7fff

0x0003_ffff

0x00d0_002f

0xffff_ffff

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56 System Memory Map MOTOR OLA

System Memory Map

Table 2-1. Register Address Location Map(1)

1. See modul e sect ions fo r details of how much of each blo ck is bein g decode d. Accesses to

addresses outside the module memory maps (and also the reserved area

0x00d1_0000–0x7fff_ffff) will not be responded to and wil l result in a bus monitor transfe r

error exception.

Base Address

(Hex) Maximum

Size Usage

0x00c0_000 0 64 Kb yte Ports(2) (PORTS)

2. The port register space is mirrored/repeated in the 64-Kbyte block. This allows th e full 64-

Kbyte block to be decoded and used to execu te an external access to a port replacement

unit in emulati on mode.

0x00c1_0000 64 Kbyte Chip configuration (CCM)

0x00c2_0000 64 Kbyte Chip selects (CS)

0x00c3_0000 64 Kbyte Clocks (CLOCK )

0x00c4_000 0 64 Kb yte Reset (RESET)

0x00c5_000 0 64 Kb yte Interrupt controller (INTC)

0x00c6_000 0 64 Kb yte Edge port (EPORT)

0x00c7_000 0 64 Kb yte Watc hd og timer (WDT)

0x00c8_000 0 64 Kb yte Program mab le interrupt timer 1 (PIT1)

0x00c9_000 0 64 Kb yte Program mab le interrupt timer 2 (PIT2)

0x00ca_000 0 64 Kb yte Que ued analo g-to-digital converter (QADC)

0x00cb_000 0 64 Kb yte Serial peripheral interface (SPI)

0x00cc_0000 64 Kbyte Serial commun ications interface 1 (SCI1)

0x00cd_000 0 64 Kb yte Serial commun ications interface 2 (SCI2)

0x00ce_0000 64 Kbyte T i mer 1 (TIM1)

0x00cf_0000 64 Kbyte T i mer 2 (TIM2)

0x0 0d0_00 00 64 Kb yte FL ASH regist ers (SGFM)

0x8 000_00 00 2 Gbyte External Memory

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System Memory Map

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Informa tion

MOTOROLA System Mem ory Map 57

2.4 Register Map

Address Register Name Bit Number

Ports (PORTS)

Bit 7654321Bit 0

0x00c0 _0000 Port A Output Data

See page 275.

Read: PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0

Write:

Reset:11111111

Bit 7654321Bit 0

0x00c0 _0001 Port B Output Data

See page 275.

Read: PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0

Write:

Reset:11111111

Bit 7654321Bit 0

0x00c0 _0002 Port C Output Data

See page 275.

Read: PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0

Write:

Reset:11111111

Bit 7654321Bit 0

0x00c0 _0003 Port D Output Data

See page 275.

Read: PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0

Write:

Reset:11111111

Bit 7654321Bit 0

0x00c0 _0004 Port E Output Data

See page 275.

Read: PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0

Write:

Reset:11111111

Bit 7654321Bit 0

0x00c0_0005 Port F Output Data

See page 275.

Read: PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0

Write:

Reset:11111111

Bit 7654321Bit 0

0x00c0_0006 Port G Output Data

See page 275.

Read: PORTG7 PORTG6 PORTG5 PORTG4 PORTG3 PORTG2 PORTG1 PORTG0

Write:

Reset:11111111

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 1 of 37)

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System Memory Map

Bit 7654321Bit 0

0x00c0 _0007 Port H Output Data

See page 275.

Read: PORTH7 PORTH6 PORTH5 PORTH4 PORTH3 PORTH2 PORTH1 PORTH0

Write:

Reset:11111111

Bit 7654321Bit 0

0x00c0 _0008 Port I Output D ata

See page 275.

Read: PORTI7 PORTI6 PORTI5 PORTI4 PORTI3 PORTI2 PORTI1 PORTI0

Write:

Reset:11111111

Bit 7654321Bit 0

0x00c0_0009

↓

0x00c0_000b

Reserved Writes have no effect, reads return 0s, and the access terminates

without a t rans fer error exception.

Bit 7654321Bit 0

0x00c0_0 00c Port A Data Direction

See page 276.

Read: DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c0 _000d Port B Data Direction

See page 276.

Read: DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c0 _000e Port C Data Direction

See page 276.

Read: DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c0_000f Port D Data Direction

See page 276.

Read: DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c0 _0010 Port E Data Direction

See page 276.

Read: DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0

Write:

Reset:00000000

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 2 of 37)

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System Memory Map

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MOTOROLA System Mem ory Map 59

Bit 7654321Bit 0

0x00c0_0011 Port F Data Direction

See page 276.

Read: DDRF7 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c0_0012 Port G Data Direction

See page 276.

Read: DDRG7 DDRG6 DDRG5 DDRG4 DDRG3 DDRG2 DDRG1 DDRG0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c0 _0013 Port H Data Direction

See page 276.

Read: DDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c0 _0014 Port I Data Direction

See page 276.

Read: DDRI7 DDRI6 DDRI5 DDRI4 DDRI3 DDRI2 DDRI1 DDRI0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c0_0015

↓

0x00c0_0017

Reserved Writes have no effect, reads return 0s, and the access terminates

without a t rans fer error exception.

Bit 7654321Bit 0

0x00c0 _0018 Por t A Pin Data/Set

Data Register

(PORTAP/SETA)

See page 277.

Read: PORTAP7 PORTAP6 PORTAP5 PORTAP4 PORTAP3 PORTAP2 PORTAP1 PORTAP0

Write: SETA7 SETA6 SETA5 SETA4 SETA3 SETA2 SETA1 SETA0

Reset:PPPPPPPP

Bit 7654321Bit 0

0x00c0 _0019 Por t B Pin Data/Set

Data Register

(PORTBP/SETB)

See page 277.

Read: PORTBP7 PORTBP6 PORTBP5 PORTBP4 PORTBP3 PORTBP2 PORTBP1 PORTBP0

Write: SETB7 SETB6 SETB5 SETB4 SETB3 SETB2 SETB1 SETB0

Reset:PPPPPPPP

Bit 7654321Bit 0

0x00c0 _001a Port C Pin Data/Set

Data Register

(PORTCP/SETC)

See page 277.

Read: PORTCP7 PORTCP6 PORTCP5 PORTCP4 PORTCP3 PORTCP2 PORTCP1 PORTCP0

Write: SETC7 SETC6 SETC5 SETC4 SETC3 SETC2 SETC1 SETC0

Reset:PPPPPPPP

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 3 of 37)

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System Memory Map

Bit 7654321Bit 0

0x00c0 _001b Port D Pin Data/Set

Data Register

(PORTDP/SETD)

See page 277.

Read: PORTDP7 PORTDP6 PORTDP5 PORTDP4 PORTDP3 PORTDP2 PORTDP1 PORTDP0

Write: SETD7 SETD6 SETD5 SETD4 SETD3 SETD2 SETD1 SETD0

Reset:PPPPPPPP

Bit 7654321Bit 0

0x00c0_0 01c Port E Pin Data/Set

Data Register

(PORTEP/SETE)

See page 277.

Read: PORTEP7 PORTEP6 PORTEP5 PORTEP4 PORTEP3 PORTEP2 PORTEP1 PORTEP0

Write: SETE7 SETE6 SETE5 SETE4 SETE3 SETE2 SETE1 SETE0

Reset:PPPPPPPP

Bit 7654321Bit 0

0x00c0 _001d Port F Pin Data/S et

Data Register

(PORTFP/SETF)

See page 277.

Read: PORTFP7 PORTFP6 PORTFP5 PORTFP4 PORTFP3 PORTFP2 PORTFP1 PORTFP0

Write: SETF7 SETF6 SETF5 SETF4 SETF3 SETF2 SETF1 SETF0

Reset:PPPPPPPP

Bit 7654321Bit 0

0x00c0 _001e Port G Pin Data/Set

Data Register

(PORTGP/SETG)

See page 277.

Read: PORTGP7 PORTGP6 PORTGP5 PORTGP4 PORTGP3 PORTGP2 PORTGP1 PORTGP0

Write: SETG7 SETG6 SETG5 SETG4 SETG3 SETG2 SETG1 SETG0

Reset:PPPPPPPP

Bit 7654321Bit 0

0x00c0_001f Port H Pin Data/Set

Data Register

(PORTHP/SETH)

See page 277.

Read: PORTHP7 PORTHP6 PORTHP5 PORTHP4 PORTHP3 PORTHP2 PORTHP1 PORTHP0

Write: SETH7 SETH6 SETH5 SETH4 SETH3 SETH2 SETH1 SETH0

Reset:PPPPPPPP

Bit 7654321Bit 0

0x00c0 _0020 Port I Pin Data/Set

Data Register

(PORTIP/SETI)

See page 277.

Read: PORTIP7 PORTIP6 PORTIP5 PORTIP4 PORTIP3 PORTIP2 PORTIP1 PORTIP0

Write: SETI7 SETI6 SETI5 SETI4 SETI3 SETI2 SETI1 SETI0

Reset:PPPPPPPP

Bit 7654321Bit 0

0x00c0_0021

↓

0x00c0_0023

Reserved Writes have no effect, reads return 0s, and the access terminates

without a t rans fer error exception.

Bit 7654321Bit 0

0x00c0_0024 Port A Clear Output

Data Register (CLRA)

See page 278.

Write: CLRA7 CLRA6 CLRA5 CLRA4 CLRA3 CLRA2 CLRA1 CLRA0

Reset:00000000

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 4 of 37)

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System Memory Map

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MOTOROLA System Mem ory Map 61

Bit 7654321Bit 0

0x00c0_0025 Port B Clear Output

Data Register (CLRB)

See page 278.

Write: CLRB7 CLRB6 CLRB5 CLRB4 CLRB3 CLRB2 CLRB1 CLRB0

Reset:00000000

Bit 7654321Bit 0

0x00c0_0026 Port C Clear Output

Data Register (CLRC)

See page 278.

Write: CLRC7 CLRC6 CLRC5 CLRC4 CLRC3 CLRC2 CLRC1 CLRC0

Reset:00000000

Bit 7654321Bit 0

0x00c0_0027 Port D Clear Output

Data Register (CLRD)

See page 278.

Write: CLRD7 CLRD6 CLRD5 CLRD4 CLRD3 CLRD2 CLRD1 CLRD0

Reset:00000000

Bit 7654321Bit 0

0x00c0_0028 Port E Clear Output

Data Register (CLRE)

See page 278.

Write: CLRE7 CLRE6 CLRE5 CLRE4 CLRE3 CLRE2 CLRE1 CLRE0

Reset:00000000

Bit 7654321Bit 0

0x00c0 _0029 Po rt F Clear Output

Data Register (CLRF)

See page 278.

Write: CLRF7 CLRF6 CLRF5 CLRF4 CLRF3 CLRF2 CLRF1 CLRF0

Reset:00000000

Bit 7654321Bit 0

0x00c0 _002a Port G Clear O ut put

Data Register (CLRG)

See page 278.

Write: CLRG7 CLRG6 CLRG5 CLRG4 CLRG3 CLRG2 CLRG1 CLRG0

Reset:00000000

Bit 7654321Bit 0

0x00c0_002b Port H Clear Output

Data Register (CLRH)

See page 278.

Write: CLRH7 CLRH6 CLRH5 CLRH4 CLRH3 CLRH2 CLRH1 CLRH0

Reset:00000000

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 5 of 37)

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System Memory Map

Bit 7654321Bit 0

0x00c0_0 02c Port I Clear Output

Data Register (CLRI)

See page 278.

Write: CLRI7 CLRI6 CLRI5 CLRI4 CLRI3 CLRI2 CLRI1 CLRI0

Reset:00000000

Bit 7654321Bit 0

0x00c0_002d

↓

0x00c0_002f

Reserved Writes have no effect, reads return 0s, and the access terminates

without a t rans fer error exception.

Bit 7654321Bit 0

0x00c0_0030 Port C/D Pin

Assignment Register

(PCDPAR)

See page 279.

Read: PCDPA 0000000

Write:

Reset:See note0000000

Note: Reset state determined during reset configuration. P CDPA = 1 exc ept in single-chip

mode or when an e xternal boot device is selected with a 16- bit port size in mas ter mode.

Bit 7654321Bit 0

0x00c0 _0031 Port E Pin

Assignment Register

(PEPAR)

See page 280.

Read: PEPA7 PEPA6 PEPA5 PEPA4 PEPA3 PEPA2 PEPA1 PEPA0

Write:

Reset : Reset state determined during reset configuration as shown in Table 12-2. PEPAR Reset Values.

Bit 7654321Bit 0

0x00c0_0032

↓

0x00c0_003f

Reserved Writes have no effect, reads return 0s, and the access terminates

without a t rans fer error exception.

Bit 7654321Bit 0

0x00c0_0040

↓

0x00c0_ffff

Reserved Ports register space (block of 0x00c0_0000 through 0x00c0_003f) is mi r rored/repeated.

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 6 of 37)

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MOTOROLA System Mem ory Map 63

Chip Configuration Module (CCM)

Bit 15 14 13 12 11 10 9 Bit 8

0x00c1_0000

0x00c1_0001 Chip Configuration

(CCR)

See page 126.

Read: LOAD 0SHEN EMINT 0 MODE2 MODE1 MODE0

Write:

Reset : Note 1 0 Note 2 Note 2 0 Note 1 Note 1 Note 1

Bit 7654321Bit 0

Read: 0 SZEN PSTEN SHINT BME BMD BMT1 BMT0

Write:

Reset : 0 Note 3 Note 2 0 1 0 0 0

Notes:

1. Determined during reset configuration

2. 0 for all configurations except emulation mode, 1 f or emulation mode

3. 0 for all configurations except emulation and master modes, 1 for emulation and master modes

Bit 7654321Bit 0

0x00c1_0002 Reserved Writes have no effect, reads return 0s, and the access terminates

without a t rans fer error exception.

Bit 7654321Bit 0

0x00c1_0003 Reserved Writes have no effect, reads return 0s, and the access terminates

without a t rans fer error exception.

Bit 15 14 13 12 11 10 9 Bit 8

0x00c1_0004

0x00c1_0005 Reset Configuration

See page 129.

Write:

Reset:00000000

Bit 7654321Bit 0

RPLLSEL 1

RPLLREF 0

RLOAD 01

BOOTPS 0

BOOTSEL 00

MODE

Write:

Reset:11001000

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 7 of 37)

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System Memory Map

Bit 15 14 13 12 11 10 9 Bit 8

0x00c1_0006

0x00c1_0007 Chip Identification

See page 131.

PIN7 0

PIN6 0

PIN5 1

PIN4 0

PIN3 1

PIN2 1

PIN1 1

PIN0

Write:

Reset:00010111

Bit 7654321Bit 0

PRN7 0

PRN6 0

PRN5 0

PRN4 0

PRN3 0

PRN2 0

PRN1 0

PRN0

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

0x00c1_0008

0x00c1_0009 Chip Test Register

(CTR)

See page 132.

Write:

Reset:00000000

Bit 7654321Bit 0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c1_000a

0x00c1_000b Reserved Writes have no effect, reads return 0s, and the access terminates

without a t rans fer error exception.

Bit 7654321Bit 0

0x00c1_000c

↓

0x00c1_000f

Unimplemented Access results in the module generating an access termination tr ansfer error.

Bit 7654321Bit 0

0x00c1_0010

↓

0x00c1_ffff

Unimplemented A ccess results in a bus monitor timeout generating an access termination transfer error.

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 8 of 37)

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MOTOROLA System Mem ory Map 65

Chip Selects (CS)

Bit 15 14 13 12 11 10 9 Bit 8

0x00c2_0000

0x00c2_0001 Chip Select Control

See page 551.

Read: SO RO PS WWS WE WS2 WS1 WS0

Write:

Reset: 0 0 See note 1 1 1 1 1

Bit 7654321Bit 0

TAEN CSEN

Write:

Reset:0000001See note

Note: Reset state determined during reset configuration.

Bit 15 14 13 12 11 10 9 Bit 8

0x00c2_0002

0x00c2_0003 Chip Select Control

See page 552.

Read: SO RO PS WWS WE WS2 WS1 WS0

Write:

Reset:00111111

Bit 7654321Bit 0

TAEN CSEN

Write:

Reset:0000001See note

Note: Reset state determined during reset configuration

Bit 15 14 13 12 11 10 9 Bit 8

0x00c2_0004

0x00c2_0005 Chip Select Control

See page 552.

Read: SO RO PS WWS WE WS2 WS1 WS0

Write:

Reset:00111111

Bit 7654321Bit 0

TAEN CSEN

Write:

Reset:00000010

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 9 of 37)

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System Memory Map

Bit 15 14 13 12 11 10 9 Bit 8

0x00c2_0006

0x00c2_0007 Chip Select Control

See page 553.

Read: SO RO PS WWS WE WS2 WS1 WS0

Write:

Reset:00111111

Bit 7654321Bit 0

TAEN CSEN

Write:

Reset:00000010

Bit 7654321Bit 0

0x00c2_0008

↓

0x00c2_ffff

Unimplemented A ccess results in a bus monitor timeout generating an access termination transfer error.

Clocks (CLO C K)

Bit 15 14 13 12 11 10 9 Bit 8

0x00c3_0000

0x00c3_0001 Synthesizer Control

See page 250.

Read: LOLRE MFD2 MFD1 MFD0 LOCRE RFD2 RFD1 RFD0

Write:

Reset:00100001

Bit 7654321Bit 0

Read: LOCEN DISCLK FWKUP RSVD4 STMPD1 STMPD0 RSVD1 RSVD0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c3_0002 Synthesizer Status

See page 253.

Read: PLLMODE PLLSEL PLLREF LOCKS LOCK LOCS 0 0

Write:

Reset : Note 1 Note 1 Note 1 Note 2 Note 2 0 0 0

Notes:

1. Reset state determined during res et configuration

2. See the LOCKS and LOCK bit descriptions.

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 10 of 37)

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MOTOROLA System Mem ory Map 67

Bit 7654321Bit 0

0x00c3 _0003 Synthesizer Test Regist er

(SYNTR)

See page 256.

Write:

Reset:00000000

Bit 31 30 29 28 27 26 25 B it 24

0x00c3_0004

0x00c3_0005

0x00c3_0006

0x00c3_0007

Synthesizer Test

See page 257.

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 B it 16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

RSVD9 RSVD8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 RSVD2 RSVD0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c3_0008

↓

0x00c3_ffff

Unimplemented A ccess results in a bus monitor timeout generating an access termination transfer error.

Reset (RESET)

Bit 7654321Bit 0

0x00c4_0000 Reset Control Register

(RCR)

See page 143.

Read: SOFTRST FRC-

RSTOUT 0LVDF LVDIE LVDRE LVDSE LVDE

Write:

Reset : 0 0 0 See note 0 0 0 0

Note: Reset dependent

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 11 of 37)

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System Memory Map

Bit 7654321Bit 0

0x00c4_0001 Reset Status Register

(RSR)

See page 143.

Read: 0 LVD SOFT WDR POR EXT LOC LOL

Write:

Reset : 0 Reset dependent

Bit 7654321Bit 0

0x00c4 _0002 Reset Test Register

(RTR) Read:00000000

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c4_0003 Reserved Writes have no effect, reads return 0s, and the access terminates

without a t rans fer error exception.

Bit 7654321Bit 0

0x00c4_0004

↓

0x00c4_ffff

Unimplemented A ccess results in a bus monitor timeout generating an access termination transfer error.

Interrupt Cont roller (INTC)

Bit 15 14 13 12 11 10 9 Bit 8

0x00c5_0000

0x00c5_0001 Interrupt Control Register

(ICR)

See page 181.

Read: AE FVE ME MFI 0000

Write:

Reset:10000000

Bit 7654321Bit 0

Read: 0 0 0 MASK4 MASK3 MASK2 MASK1 MASK0

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

0x00c5_0002

0x00c5_0003 Interrupt Status Register

(ISR)

See page 183.

Read:000000INTFINT

Write:

Reset:00000000

Bit 7654321Bit 0

Read:0 VEC6VEC5VEC4VEC3VEC2VEC1VEC0

Write:

Reset:00000000

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 12 of 37)

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MOTOROLA System Mem ory Map 69

Bit 31 30 29 28 27 26 25 B it 24

0x00c5_0004

0x00c5_0005

0x00c5_0006

0x00c5_0007

Interrupt Force Register

High (IFRH)

See page 184.

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 B it 16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: IF39 IF38 IF37 IF36 IF35 IF34 IF33 IF32

Write:

Reset:00000000

Bit 31 30 29 28 27 26 25 B it 24

0x00c5_0008

0x00c5_0009

0x00c5_000a

0x00c5_000b

Interrupt Force Register

Low (IFRL)

See page 185.

Read: IF31 IF30 IF29 IF28 IF27 IF26 IF25 IF24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 B it 16

Read: IF23 IF22 IF21 IF20 IF19 IF18 IF17 IF16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Read: IF15 IF14 IF13 IF12 IF11 IF10 IF9 IF8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: IF7 IF6 IF5 IF4 IF3 IF2 IF1 IF0

Write:

Reset:00000000

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 13 of 37)

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Bit 31 30 29 28 27 26 25 B it 24

0x00c5_000c

0x00c5_000d

0x00c5_000e

0x00c5_000f

Interrupt Pending Register

(IPR)

See page 186.

Read:IP31IP30IP29IP28IP27IP26IP25IP24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 B it 16

Read:IP23IP22IP21IP20IP19IP18IP17IP16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Read:IP15IP14IP13IP12IP11IP10 IP9 IP8

Write:

Reset:00000000

Bit 7654321Bit 0

Read:IP7IP6IP5IP4IP3IP2IP1IP0

Write:

Reset:00000000

Bit 31 30 29 28 27 26 25 B it 24

0x00c5_0010

0x00c5_0011

0x00c5_0012

0x00c5_0013

Normal Interrupt Enable

See page 187.

Read: NIE31 NIE30 NIE29 NIE28 NIE27 NIE26 NIE25 NIE24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 B it 16

Read: NIE23 NIE22 NIE21 NIE20 NIE19 NIE18 NIE17 NIE16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Read: NIE15 NIE14 NIE13 NIE12 NIE11 NIE10 NIE9 NIE8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: NIE7 NIE6 NIE5 NIE4 NIE3 NIE2 NIE1 NIE0

Write:

Reset:00000000

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 14 of 37)

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MOTOROLA System Mem ory Map 71

Bit 31 30 29 28 27 26 25 B it 24

0x00c5_0014

0x00c5_0015

0x00c5_0016

0x00c5_0017

Normal Interrupt Pending

See page 188.

Read: NIP31 NIP30 NIP29 NIP28 NIP27 NIP26 NIP25 NIP24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 B it 16

Read: NIP23 NIP22 NIP21 NIP20 NIP19 NIP18 NIP17 NIP16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Read: NIP15 NIP14 NIP13 NIP12 NIP11 NIP10 NIP9 NIP8

Write:

Reset:00000000

Bit 7654321Bit 0

Read:NIP7NIP6NIP5NIP4NIP3NIP2NIP1NIP0

Write:

Reset:00000000

Bit 31 30 29 28 27 26 25 B it 24

0x00c5_0018

0x00c5_0019

0x00c5_001a

0x00c5_001b

Fast Interrupt Enable

See page 189.

Read: FIE31 FIE30 FIE29 FIE28 FIE27 FIE26 FIE25 FIE24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 B it 16

Read: FIE23 FIE22 FIE21 FIE20 FIE19 FIE18 FIE17 FIE16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Read: FIE15 FIE14 FIE13 FIE12 FIE11 FIE10 FIE9 FIE8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: FIE7 FIE6 FIE5 FIE4 FIE3 FIE2 FIE1 FIE0

Write:

Reset:00000000

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 15 of 37)

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System Memory Map

Bit 31 30 29 28 27 26 25 B it 24

0x00c5_001c

0x00c5_001d

0x00c5_001e

0x00c5_001f

Fast Interrupt Pending

See page 190.

Read: FIP31 FIP30 FIP29 FIP28 FIP27 FIP26 FIP25 FIP24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 B it 16

Read: FIP23 FIP22 FIP21 FIP20 FIP19 FIP18 FIP17 FIP16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Read: FIP15 FIP14 FIP13 FIP12 FIP11 FIP10 FIP9 FIP8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: FIP7 FIP6 FIP5 FIP4 FIP3 FIP2 FIP1 FIP0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c5_0040

↓

0x00c5_0067

Priority Leve l Select

Registers

(PLSR39–PLSR0)

See page 191.

Read: 0 0 0 PLS4 PLS3 PLS2 PLS1 PLS0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c5_0068

↓

0x00c5_007f

Unimplemented Access results in the module generating an access termination tr ansfer error.

Bit 7654321Bit 0

0x00c5_0080

↓

0x00c5_ffff

Unimplemented A ccess results in a bus monitor timeout generating an access termination transfer error.

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 16 of 37)

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MOTOROLA System Mem ory Map 73

Edge Port (EPO RT)

Bit 15 14 13 12 11 10 9 Bit 8

0x00c6_0000

0x00c6_0001 EPORT Pin Assignment

See page 288.

Read: EPPA7 EPPA6 EPPA5 EPPA4

Write:

Reset:00000000

Bit 7654321Bit 0

Read: EPPA3 EPPA2 EPPA1 EPPA0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c6 _0002 E PORT Data Direction

See page 290.

Read: EPDD7 EPDD6 EPDD5 EPDD4 EPDD3 EPDD2 EPDD1 EPDD0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c6 _0003 EPO RT Port Interrupt

Enable Register (EPIER)

See page 291.

Read: EPIE7 EPIE6 EPIE5 EPIE4 EPIE3 EPIE2 EPIE1 EPIE0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c6_0004 EPORT Port Data

See page 292.

Read: EPD7 EPD6 EPD5 EPD4 EPD3 EPD2 EPD1 EPD0

Write:

Reset:11111111

Bit 7654321Bit 0

0x00c6_0005 EPORT Port Pin Data

See page 292.

Read: EPPD7 EPPD6 EPPD5 EPPD4 EPPD3 EPPD2 EPPD1 EPPD0

Write:

Reset:PPPPPPPP

Bit 7654321Bit 0

0x00c6_0006 EPORT Port Flag Regiser

(EPFR)

See page 293.

Read: EPF7 EPF6 EPF5 EPF4 EPF3 EPF2 EPF1 EPF0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c6_0007 Reserved Writes have no effect, reads return 0s, and the access terminates

without a t rans fer error exception.

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 17 of 37)

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Bit 7654321Bit 0

0x00c6_0008

↓

0x00c6_ffff

Unimplemented A ccess results in a bus monitor timeout generating an access termination transfer error.

Watchdog Timer (WDT)

Bit 15 14 13 12 11 10 9 Bit 8

0x00c7_0000

0x00c7_0001 Watchdog Control

See page 299.

Write:

Reset:00000000

Bit 7654321Bit 0

WAIT DOZE DBG EN

Write:

Reset:00001111

Bit 15 14 13 12 11 10 9 Bit 8

0x00c7_0002

0x00c7_0003 Watchdog Modulus

See page 301.

Read: WM15 WM14 WM13 WM12 WM11 WM10 WM9 WM8

Write:

Reset:11111111

Bit 7654321Bit 0

Read: WM7 WM6 WM5 WM4 WM3 WM2 WM1 WM0

Write:

Reset:11111111

Bit 15 14 13 12 11 10 9 Bit 8

0x00c7_0004

0x00c7_0005 Watchdog Count Register

(WCNTR)

See page 302.

Read: WC15 WC14 WC13 WC12 WC11 WC10 WC9 WC8

Write:

Reset:11111111

Bit 7654321Bit 0

Read: WC7 WC6 WC5 WC4 WC3 WC2 WC1 WC0

Write:

Reset:11111111

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 18 of 37)

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MOTOROLA System Mem ory Map 75

Bit 15 14 13 12 11 10 9 Bit 8

0x00c7_0006

0x00c7_0007 Watchdog Service

See page 303.

Read: WS15 WS14 WS13 WS12 WS11 WS10 WS9 WS8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: WS7 WS6 WS5 WS4 WS3 WS2 WS1 WS0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c7_0008

↓

0x00c7_ffff

Unimplemented A ccess results in a bus monitor timeout generating an access termination transfer error.

Programmable Interrupt Timer 1 (PIT1) and Program ming Interrupt Timer 2 (PIT2)

Note: Addresses for PIT1 are at 0x00c8_#### and addresses for PIT2 are at 0x00c9_####.

Bit 15 14 13 12 11 10 9 Bit 8

0x00c8_0000

0x00c8_0001

0x00c9_0000

0x00c9_0001

PIT Control and Status

See page 309.

PRE3 PRE2 PRE1 PRE0

Write:

Reset:00000000

Bit 7654321Bit 0

Read: 0 PDOZE PDBG OVW PIE PIF RLD EN

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

0x00c8_0002

0x00c8_0003

0x00c9_0002

0x00c9_0003

PIT Modulus Register

(PMR)

See page 312.

Read: PM15 PM14 PM13 PM12 PM11 PM10 PM9 PM8

Write:

Reset:11111111

Bit 7654321Bit 0

Read: PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0

Write:

Reset:11111111

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 19 of 37)

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Bit 15 14 13 12 11 10 9 Bit 8

0x00c8_0004

0x00c8_0005

0x00c9_0004

0x00c9_0005

PIT Count Register

(PCNTR)

See page 313.

Read: PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8

Write:

Reset:11111111

Bit 7654321Bit 0

Read: PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

Write:

Reset:11111111

Bit 7654321Bit 0

0x00c8_0006

↓

0x00c8_0007

Unimplemented Access results in the module generating an access termination tr ansfer error.

Bit 7654321Bit 0

0x00ca_0008

↓

0x00ca_ffff

Unimplemented A ccess results in a bus monitor timeout generating an access termination transfer error.

Queued Analog-to- Dig it al Convert e r (QADC)

Bit 15 14 13 12 11 10 9 Bit 8

0x00ca_0000

0x00ca_0001 QA DC Module

Configuration Register

(QADCMCR)

See page 437.

Read: QSTOP QDBG 000000

Write:

Reset:00000000

Bit 7654321Bit 0

Read: SUPV 0000000

Write:

Reset:10000000

Bit 15 14 13 12 11 10 9 Bit 8

0x00ca_0002

0x00ca_0003 QA DC Test Register

(QADCTEST)

See page 438.

Access results in th e module generating an access ter mination transfer error if not in test mode.

Bit 7654321Bit 0

Access results in th e module generating an access ter mination transfer error if not in test mode.

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 20 of 37)

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0x00ca_0004

0x00ca_0005 Reserved Writes have no effect, reads return 0s, and the access terminates

without a t rans fer error exception.

Bit 7654321Bit 0

Writes have no effect, reads return 0s, and the access terminates

without a t rans fer error exception.

Bit 7654321Bit 0

0x00ca_0006 QADC Port A Data

See page 439.

Read: 0 0 0 PQA4 PQA3 0PQA1 PQA0

Write:

Reset:000PP0PP

Bit 7654321Bit 0

0x00ca_0007 QADC Port B Data

See page 439.

PQB3 PQB2 PQB1 PQB0

Write:

Reset:0000PPPP

Bit 7654321Bit 0

0x00ca_0008 QADC Port A Data

Direction Register

(DDRQA)

See page 441.

Read: 0 0 0 DDQA4 DDQA3 0DDQA1 DDQA0

Write:

Reset:00000000

QADC Port B Da ta

Direction Register

(DDRQB)

See page 441.

Bit 7654321Bit 0

0x00ca_0009 Read: 0000

DDQB3 DDQB2 DDQB1 DDQB0

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

0x00ca_000a

0x00ca_000b QA DC Control Register 0

(QACR0)

See page 442.

Read: MUX 00

TRG 0000

Write:

Reset:00000000

Bit 7654321Bit 0

Read: 0 QPR6 QPR5 QPR4 QPR3 QPR2 QPR1 QPR0

Write:

Reset:00010011

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 21 of 37)

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System Memory Map

Bit 15 14 13 12 11 10 9 Bit 8

0x00ca_000c

0x00ca_000d QA DC Control Register 1

(QACR1)

See page 445.

Read: CIE1 PIE1 0MQ112 MQ111 MQ110 MQ19 MQ18

Write: SSE1

Reset:00000000

Bit 7654321Bit 0

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

0x00ca_000e

0x00ca_000f QA DC Cont rol Register 2

(QACR2)

See page 448.

Read: CIE2 PIE2 0MQ212 MQ211 MQ210 MQ29 MQ28

Write: SSE2

Reset:00000000

Bit 7654321Bit 0

Read: RESUME BQ26 BQ25 BQ24 BQ23 BQ22 BQ21 BQ20

Write:

Reset:01111111

Bit 15 14 13 12 11 10 9 Bit 8

0x00ca_0010

0x00ca_0011 QA DC Status Register 0

(QASR0)

See page 453.

Read: CF1 PF1 CF2 PF2 TOR1 TOR2 QS9 QS8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: QS7 QS6 CWP5 CWP4 CWP3 CWP2 CWP1 CWP0

Write:

Reset:00000000

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 22 of 37)

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MOTOROLA System Mem ory Map 79

Bit 15 14 13 12 11 10 9 Bit 8

0x00ca_0012

0x00ca_0013 QA DC Status Register 1

(QASR1)

See page 462.

Read: 0 0 CWPQ15 CWPQ14 CWPQ13 CWPQ12 CWPQ11 CWPQ10

Write:

Reset:00111111

Bit 7654321Bit 0

Read: 0 0 CWPQ25 CWPQ24 CWPQ23 CWPQ22 CWPQ21 CWPQ20

Write:

Reset:00111111

Bit 7654321Bit 0

0x00ca_0014

↓

0x00ca_01ff

Reserved Writes have no effect, reads return 0s, and the access terminates

without a t rans fer error exception.

Bit 15 14 13 12 11 10 9 Bit 8

0x00ca_0200

0x00ca_027e Conversion Command

Word Register

(CCW0–CCW63)

See page 464.

Read:000000PBYP

Write:

Reset:000000UU

Bit 7654321Bit 0

Read: IST1 IST0 CHAN5 CHAN4 CHAN3 CHAN2 CHAN1 CHAN0

Write:

Reset:UUUUUUUU

Bit 15 14 13 12 11 10 9 Bit 8

0x00ca_0280

0x00ca_02fe Right-Justified Unsigned

Result Register

(RJURR0–RJURR63)

See page 468.

Read:000000 RESULT

Write:

Reset:000000

Bit 7654321Bit 0

Read: RESULT

Write:

Reset:

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 23 of 37)

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System Memory Map

Bit 15 14 13 12 11 10 9 Bit 8

0x00ca_0300

0x00ca_037e Left-Justified Signed

Result Register

(LJSRR0–LJSRR63)

See page 469.

Read: SRESULT

Write:

Reset:

Bit 7654321Bit 0

Read: RESULT 000000

Write:

Reset: 000000

Bit 15 14 13 12 11 10 9 Bit 8

0x00ca_0380

0x00ca_03fe Left-Justified Unsigned

Result Register

(LJURR0–LJURR63)

See page 470.

Read: RESULT

Write:

Reset:

Bit 7654321Bit 0

Read: RESULT 000000

Write:

Reset: 000000

Bit 7654321Bit 0

0x00ca_0400

↓

0x00ca_ffff

Unimplemented A ccess results in a bus monitor timeout generating an access termination transfer error.

Serial Peripheral Inter face (SPI )

Bit 7654321Bit 0

0x00cb_0000 SPI Control Register 1

(SPICR1)

See page 402.

Read: SPIE SPE SWOM MSTR CPOL CPHA SSOE LSBFE

Write:

Reset:00000100

Bit 7654321Bit 0

0x00cb_0001 SPI Control Register 2

(SPICR2)

See page 405.

SPISDOZ SPC0

Write:

Reset:00000000

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 24 of 37)

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MOTOROLA System Mem ory Map 81

Bit 7654321Bit 0

0x00cb_0002 SPI Baud Rate Register

(SPIBR)

See page 406.

Read: 0 SPPR6 SPPR5 SPPR4 0SPR2 SPR1 SPR0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00cb_0003 SPI Status Register

(SPISR)

See page 408.

Read: SPIF WCOL 0 MODF 0 0 0 0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00cb_0004 Reserved Writes have no effect, reads return 0s, and the access terminates

without a t rans fer error exception.

Bit 7654321Bit 0

0x00cb_0005 SPI Data Register

(SPIDR)

See page 409.

Read: Bit 7654321Bit 0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00cb _0006 SPI Pullup and Re duced

Drive Register

(SPIPURD)

See page 410.

Read: 0 0 RSVD5 RDPSP 00

RSVD1 PUPSP

Write:

Reset:00000000

Bit 7654321Bit 0

0x00cb _0007 SPI Port D ata Register

(SPIPORT)

See page 411.

Read: RSVD7 RSVD6 RSVD5 RSVD4 PORTSP3 PORTSP2 PORTSP1 PORTSP0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00cb _0008 SPI Port Data Direction

See page 412.

Read: RSVD7 RSVD6 RSVD5 RSVD4 DDRSP3 DDRSP2 DDRSP1 DDRSP0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00cb_0009

↓

0x00cb_000f

Reserved Writes have no effect, reads return 0s, and the access terminates

without a t rans fer error exception.

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 25 of 37)

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System Memory Map

Bit 7654321Bit 0

0x00cb_0010

↓

0x00cb_ffff

Unimplemented A ccess results in a bus monitor timeout generating an access termination transfer error.

Serial Communications I nterface 1 (S CI1) and Serial C omm unications In terface 2 (SCI2)

Note: Addresses for SCI1 are at 0x00c c_### # and addresses for SCI2 are at 0x00cd_# ###.

Bit 7654321Bit 0

0x00cc_0000

0x00cd_0000 SCI Baud Rate

See page 360.

Read: 0 0 0 SBR12 SBR11 SBR10 SBR9 SBR8

Write:

Reset:00000000

Bit 7654321Bit 0

0x00cc_0001

0x00cd_0001 SCI Baud Rate

See page 360.

Read: SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0

Write:

Reset:00000100

Bit 7654321Bit 0

0x00cc_0002

0x00cd_0002 SCI Control Regi ster 1

(SCICR1)

See page 361.

Read: LOOPS WOMS RSRC M WAKE ILT PE PT

Write:

Reset:00000000

Bit 7654321Bit 0

0x00cc_0003

0x00cd_0003 SCI Control Regi ster 2

(SCICR2)

See page 364.

Read: TIE TCIE RIE ILIE TE RE RWU SBK

Write:

Reset:00000000

Bit 7654321Bit 0

0x00cc_0004

0x00cd_0004 SCI Status Register 1

(SCISR1)

See page 366.

Read: TDRE TC RDRF IDLE OR NF FE PF

Write:

Reset:11000000

Bit 7654321Bit 0

0x00cc_0005

0x00cd_0005 SCI Status Register 2

(SCISR2)

See page 369.

Read:0000000RAF

Write:

Reset:00000000

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 26 of 37)

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MOTOROLA System Mem ory Map 83

Bit 7654321Bit 0

0x00cc_0006

0x00cd_0006 SCI Data Register High

(SCIDRH)

See page 370.

Read: R8 T8 000000

Write:

Reset:00000000

Bit 7654321Bit 0

0x00cc_0007

0x00cd_0007 SCI Data Register Low

(SCIDRL)

See page 370.

Read:R7R6R5R4R3R2R1R0

Write: T7 T6 T5 T4 T3 T2 T1 T0

Reset:00000000

Bit 7654321Bit 0

0x00cc_0008

0x00cd_0008 SCI Pullup and Reduced

Drive Register

(SCIPURD)

See page 371.

Read: SCISDOZ 0RSVD5 RDPSCI 00

RSVD1 PUPSCI

Write:

Reset:00000000

Bit 7654321Bit 0

0x00cc_0009

0x00cd_0009 SCI Po r t D a ta R e g ister

(SCIPORT)

See page 372.

Read: RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 PORTSC1 PORTSC0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00cc_000a

0x00cd_000a SCI D a ta Di re ction

See page 373.

Read: RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 DDRSC1 DDRSC0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00cc_000b

↓

0x00cc_000f

0x00cd_000b

↓

0x00cd_000f

Reserved

Writes have no effect, reads return 0s, and the access terminates

without a t rans fer error exception.

Bit 7654321Bit 0

0x00cc_0010

↓

0x00cc_ffff

0x00cd_0010

↓

0x00cd_ffff

Unimplemented

Access result s in a bus monitor timeout generating an access termination transfer error.

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 27 of 37)

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System Memory Map

Timer 1 (TIM1) and Timer 2 (TIM2)

Note: Addresses for TIM1 are at 0x00ce_#### and addresses for TIM2 are at 0x00cf_####.

Bit 7654321Bit 0

0x00ce_0000

0x00cf_0000 Timer Input Capture/

Output Compare Select

See page 324.

IOS3 IOS2 IOS1 IOS0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_0001

0x00cf_0001 T imer Compare Force

See page 325.

Write: FOC3 FOC2 FOC1 FOC0

Reset:00000000

Bit 7654321Bit 0

0x00ce_0002

0x00cf_0002 Timer Output Compare 3

Ma sk Re gi st e r

(TIMOC3M)

See page 326.

OC3M3 OC3M2 OC3M1 OC3M0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_0003

0x00cf_0003 Timer Output Compare 3

Data Register (TIMOC3D)

See page 327.

OC3D3 OC3D2 OC3D1 OC3D0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_0004

0x00cf_0004 Timer Counter Register

High (TIMCNTH)

See page 328.

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_0005

0x00cf_0005 Timer Counter Register

Low (TIMCNTL)

See page 328.

Read:Bit 7654321Bit 0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_0006

0x00cf_0006 Timer System Control

See page 329.

Read: TIMEN 00

TFFCA 0000

Write:

Reset:00000000

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 28 of 37)

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MOTOROLA System Mem ory Map 85

Bit 7654321Bit 0

0x00ce_0007

0x00cf_0007 Reserved Writ es have no effect, reads return 0s, and the access terminates

without a t rans fer error exception.

Bit 7654321Bit 0

0x00ce_0008

0x00cf_0008 Timer Toggle on Overflow

See page 330.

TOV3 TOV2 TOV1 TOV0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_0009

0x00cf_0009 Timer Control

See page 331.

Read: OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_000a

0x00cf_000a Reserved Writ es have no effect, reads return 0s, and the access terminates

without a t rans fer error exception.

Bit 7654321Bit 0

0x00ce_000b

0x00cf_000b Timer Control

See page 332.

Read: EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG10

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_000c

0x00cf_000c Timer Interrupt Enable

See page 333.

C3I C2I C1I C0I

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_000d

0x00cf_000d Timer System Control

See page 334.

Read: TOI 0PUPT RDPT TCRE PR2 PR1 PR0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_000e

0x00cf_000e Timer Flag Register 1

(TIMFLG1)

See page 336.

C3F C2F C1F C0F

Write:

Reset:00000000

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 29 of 37)

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System Memory Map

Bit 7654321Bit 0

0x00ce_000f

0x00cf_000f Timer Flag Register 2

(TIMFLG2)

See page 337.

Read: TOF 0000000

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

0x00ce_0010

0x00cf_0010 Timer Channel 0 Register

High (TIMC0H)

See page 338.

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_0011

0x00cf_0011 Timer Channel 0 Register

Low (TIMC0L)

See page 338.

Read: Bit 7654321Bit 0

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

0x00ce_0012

0x00cf_0012 Timer Channel 1 Register

High (TIMC1H)

See page 338.

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_0013

0x00cf_0013 Timer Channel 1 Register

Low (TIMC1L)

See page 338.

Read: Bit 7654321Bit 0

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

0x00ce_0014

0x00cf_0014 Timer Channel 2 Register

High (TIMC2H)

See page 338.

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_0015

0x00cf_0015 Timer Channel 2 Register

Low (TIMC2L)

See page 338.

Read: Bit 7654321Bit 0

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

0x00ce_0016

0x00cf_0016 Timer Channel 3 Register

High (TIMC3H)

See page 338.

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 30 of 37)

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MOTOROLA System Mem ory Map 87

Bit 7654321Bit 0

0x00ce_0017

0x00cf_0017 Timer Channel 3 Register

Low (TIMC3L)

See page 338.

Read: Bit 7654321Bit 0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_0018

0x00cf_0018 Pulse Accumulator

Contro l Register

(TIMPACTL)

See page 339.

Read: 0 PAE PAMOD PEDGE CLK1 CLK0 PAOVI PAI

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_0019

0x00cf_0019 Pulse Accumulator Flag

See page 341.

PAOVF PAIF

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

0x00ce_001a

0x00cf_001a Pulse Accumulator

Counter Register High

(TIMPACNTH)

See page 342.

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_001b

0x00cf_001b Pulse Accumulator

Counter Register Low

(TIMPACNTL)

See page 342.

Read: Bit 7654321Bit 0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_001c

0x00cf_001c Reserved Writes have no effect, reads return 0s, and the access terminates

without a t rans fer error exception.

Bit 7654321Bit 0

0x00ce_001d

0x00cf_001d Timer Port Data Register

(TIMPORT)

See page 343.

PORTT3 PORTT2 PORTT1 PORTT0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_001e

0x00cf_001e T imer Port Data Direc tion

See page 344.

DDRT3 DDRT2 DDRT1 DDRT0

Write:

Reset:00000000

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 31 of 37)

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Bit 7654321Bit 0

0x00ce_001f

0x00cf_001f Timer Test Register

(TIMTST)

See page 345.

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_0020

↓

0x00ce_ffff

0x00cf_0030

↓

0x00cf_ffff

Unimplemented

Access results in t he module generating an access termination transfer error.

Second Generation FLASH for M•C ORE (SGFM)

Bit 15 14 13 12 11 10 9 Bit 8

0x00d0_0000

0x00d0_0001 S GFM Module

Configuration Register

(SGFMMCR)

See page 213.

Read: 0 FRZ 0EME 0LOCK 00

Write:

Reset:000Note 10000

Bit 7654321Bit 0

Read: CBEIE CCIE KEYACC 000 BKSEL

Write:

Reset:00000000

Note:

1. Reset state determined by chip reset configuration.

Bit 7654321Bit 0

0x00d0_0002 SGFM Cl ock Divider

See page 215.

Read: DIVLD PRDIVDIV5DIV4DIV3DIV2DIV1DIV0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00d0_0003 Unimplemen ted Access results in t he module generating an access termination transfer error.

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 32 of 37)

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MOTOROLA System Mem ory Map 89

Bit 7654321Bit 0

0x00d0_0004 S GFM Test Register

(SGFMTST)

See page 216.

Read: RSVD7 RSVD6 RSVD5 RSVD4 00

RSVD1 RSVD0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00d0_0005

↓

0x00d0_0007 Unim plemen ted Acc ess results in the module generating an access termination transfer error.

Bit 31 30 29 28 27 26 25 B it 24

0x00d0_0008

0x00d0_0009

0x00d0_000a

0x00d0_000b

SGFM Security Register

(SGFMSEC)

See page 217.

Read:KEYENSECSTAT000000

Write:

Reset: F(1) Note 2000000

Bit 23 22 21 20 19 18 17 B it 16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Read: SEC15 SEC14 SEC13 SEC12 SEC11 SEC10 SEC9 SEC8

Write:

Reset: F(1) F(1) F(1) F(1) F(1) F(1) F(1) F(1)

Bit 7654321Bit 0

Read:SEC7SEC6SEC5SEC4SEC3SEC2SEC1SEC0

Write:

Reset: F(1) F(1) F(1) F(1) F(1) F(1) F(1) F(1)

Notes:

1. Reset state loaded fro m FLASH array during reset.

2. Reset state determined by security state of module.

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 33 of 37)

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System Memory Map

Bit 31 30 29 28 27 26 25 B it 24

0x00d0_000c

0x00d0_000d

0x00d0_000e

0x00d0_000f

SGFM Monitor Data

See page 219.

Read: RSVD31 RSVD30 RSVD29 RSVD28 RSVD27 RSVD26 RSVD25 RSVD24

Write:

Reset: Note 1

Bit 23 22 21 20 19 18 17 B it 16

Read: RSVD23 RSVD22 RSVD21 RSVD20 RSVD19 RSVD18 RSVD17 RSVD16

Write:

Reset: Note 1

Bit 15 14 13 12 11 10 9 Bit 8

Read: RSVD15 RSVD14 RSVD13 RSVD12 RSVD11 RSVD10 RSVD9 RSVD8

Write:

Reset: Note 1

Bit 7654321Bit 0

Read: RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 RSVD1 RSVD0

Write:

Reset: Note 1

Note 1. SGFMMNTR does not have a default reset state.

Bit 15 14 13 12 11 10 9 Bit 8

0x00d0_0010

0x00d0_0011 SGFM Protection Register

(SGFMPROT)

See page 220.

Read: PROT15 PROT14 PROT13 PROT12 PROT11 PROT10 PROT9 PROT8

Write:

Reset: F(1) F(1) F(1) F(1) F(1) F(1) F(1) F(1)

Bit 7654321Bit 0

Read: PROT7 PROT6 PROT5 PROT4 PROT3 PROT2 PROT1 PROT0

Write:

Reset: F(1) F(1) F(1) F(1) F(1) F(1) F(1) F(1)

Note 1. Reset state loaded from FLASH configuration field during reset.

Bit 7654321Bit 0

0x00d0_0012

↓

0x00d0_0013

Unimplemented Access results in the module generating an access termination tr ansfer error.

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 34 of 37)

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MOTOROLA System Mem ory Map 91

Bit 15 14 13 12 11 10 9 Bit 8

0x00d0_0014

0x00d0_0015 SG F M Su pervi so r Access

See page 221.

Read: SUPV15 SUPV14 SUPV13 SUPV12 SUPV11 SUPV10 SUPV9 SUPV8

Write:

Reset: F(1) F(1) F(1) F(1) F(1) F(1) F(1) F(1)

Bit 7654321Bit 0

Read: SUPV7 SUPV6 SUPV5 SUPV4 SUPV3 SUPV2 SUPV1 SUPV0

Write:

Reset: F(1) F(1) F(1) F(1) F(1) F(1) F(1) F(1)

Note 1. Reset state loaded from FLASH array during reset.

Bit 15 14 13 12 11 10 9 Bit 8

0x00d0_0016

0x00d0_0017 SGFM Data Access

See page 223.

Read: DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8

Write:

Reset: F(1) F(1) F(1) F(1) F(1) F(1) F(1) F(1)

Bit 7654321Bit 0

Read: DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0

Write:

Reset: F(1) F(1) F(1) F(1) F(1) F(1) F(1) F(1)

Note 1. Reset state loaded from FLASH configuration field during reset.

Bit 7654321Bit 0

0x00d0_0018 SGFM Test Status

See page 224.

RSVD3 0RSVD1 RSVD0

Write:

Reset: 00000000

Bit 7654321Bit 0

0x00d0_0019

↓

0x00d0_001b

Unimplemented Access results in the module generating an access termination tr ansfer error.

Bit 7654321Bit 0

0x00d0_001c SGFM User Status

See page 224.

Read: CBEIF CCIF PVIOL ACCERR 0BLANK 00

Write:

Reset: 11000000

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 35 of 37)

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System Memory Map

Bit 7654321Bit 0

0x00d0_001d

↓

0x00d0_001f

Unimplemented A ccess results in a bus monitor timeout generating an access termination transfer error.

Bit 7654321Bit 0

0x00d0_0020 SG FM Command

Buffer and Register

(SGFMCMD)

See page 226.

Read: 0 CMD6 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0

Write:

Reset: 00000000

Bit 7654321Bit 0

0x00d0_0021

↓

0x00d0_0023

Unimplemented A ccess results in a bus monitor timeout generating an access termination transfer error.

Bit 15 14 13 12 11 10 9 Bit 8

0x00d0_0024

0x00d0_0025 SGFM Control Register

(SGFMCTL)

See page 227.

Read: RSVD15 0000000

Write:

Reset: 00000000

Bit 7654321Bit 0

Read: RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 RSVD1 RSVD0

Write:

Reset: 00000000

Bit 15 14 13 12 11 10 9 Bit 8

0x00d0_0026

0x00d0_0027 S GF M Address Register

(SGFMADR)

See page 228.

Read: 0 RSVD14 RSVD13 RSVD12 RSVD11 RSVD10 RSVD9 RSVD8

Write:

Reset: 00000000

Bit 7654321Bit 0

Read: RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 RSVD1 RSVD0

Write:

Reset: 00000000

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 36 of 37)

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System Memory Map

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MOTOROLA System Mem ory Map 93

Bit 31 30 29 28 27 26 25 B it 24

0x00d0_0028

0x00d0_0029

0x00d0_002a

0x00d0_002b

SGFM Data Register

(SGFMDATA)

See page 229.

Read: RSVD31 RSVD30 RSVD29 RSVD28 RSVD27 RSVD26 RSVD25 RSVD24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 B it 16

Read: RSVD23 RSVD22 RSVD21 RSVD20 RSVD19 RSVD18 RSVD17 RSVD16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Read: RSVD15 RSVD14 RSVD13 RSVD12 RSVD11 RSVD10 RSVD9 RSVD8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 RSVD1 RSVD0

Write:

Reset:00000000

Address Register Name Bit Number

P = Current pin stat e U = Unaffected = Writes have no ef fect and the access terminates without a transfer error exception.

Figure 2-4. Register Summary (Sheet 37 of 37)

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System Memory Map

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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0  Advance Information
MOTOROLA Signal Description  95
Advance Info rmation — MMC2114, MMC2113, and MMC2112
Section 3.   Signal Description
1  Contents
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
3 Package Pinout Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
4 Chip Specific Implementation Signal Issues. . . . . . . . . . . . . .109
4.1 RSTOUT Signal Functions. . . . . . . . . . . . . . . . . . . . . . . . .109
4.2 INT Signal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
4.3 Serial Peripheral Interface (SPI) Pin Functions . . . . . . . . .110
4.4 Serial Communications Interface (SCI1 and SCI2) 
Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
4.5 Timer 1 and Timer 2 Pin Functions  . . . . . . . . . . . . . . . . . .112
4.6 Queued Analog-to-Digital Converter (QADC) 
Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
5 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
5.1 Reset Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
5.1.1 Reset In (RESET)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
5.1.2 Reset Out (RS TOUT). . . . . . . . . . . . . . . . . . . . . . . . . . .113
5.2 Phase-Lock Loop (PLL ) and Clock Signals . . . . . . . . . . . .113
5.2.1 External Clock In (EXTAL). . . . . . . . . . . . . . . . . . . . . . .113
5.2.2 Crystal (XTAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
5.2.3 Clock Out (CLKOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . .114
5.2.4 PLL Enable (PLLEN) . . . . . . . . . . . . . . . . . . . . . . . . . . .114
5.3 External Memory Interface Signals  . . . . . . . . . . . . . . . . . .114
5.3.1 Data Bus (D[31:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
5.3.2 Show Cycle Strobe (SHS) . . . . . . . . . . . . . . . . . . . . . . .114
5.3.3 Transfer Acknowledge (TA). . . . . . . . . . . . . . . . . . . . . .115
5.3.4 Transfer Error Acknowledge (TEA) . . . . . . . . . . . . . . . .115
5.3.5 Emulation Mode Chip Selects (CSE[1:0]) . . . . . . . . . . .115
5.3.6 Transfer Code (TC[2:0]). . . . . . . . . . . . . . . . . . . . . . . . .115
5.3.7 Read/Write (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
    
  
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Signal Description MOTOROLA
Signal  Descript ion
5.3.8 Address Bus (A[22:0]) . . . . . . . . . . . . . . . . . . . . . . . . . .115
5.3.9 Enable Byte (EB[3:0])  . . . . . . . . . . . . . . . . . . . . . . . . . .116
5.3.10 Chip Sele ct (CS[3:0]). . . . . . . . . . . . . . . . . . . . . . . . . . .116
5.3.11 Output Enable (OE) . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
5.4 Edge Port Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
5.4.1 External Interrupts (INT[7:6] ) . . . . . . . . . . . . . . . . . . . . .116
5.4.2 External Interrupts (INT[5:2] ) . . . . . . . . . . . . . . . . . . . . .116
5.4.3 External Interrupts (INT[1:0] ) . . . . . . . . . . . . . . . . . . . . .116
5.5 Serial Peripheral Interface Module Signals  . . . . . . . . . . . .117
5.5.1 Master Out/Slave In (MOSI). . . . . . . . . . . . . . . . . . . . . .117
5.5.2 Master In/Slave Out (MISO). . . . . . . . . . . . . . . . . . . . . .117
5.5.3 Serial Clock (SCK). . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
5.5.4 Slave Select (SS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
5.6 Serial Communications Interface Module Signals . . . . . . .117
5.6.1 Receive Data (RXD1 and RXD2). . . . . . . . . . . . . . . . . .117
5.6.2 Transmit Data (TXD1 and TXD2). . . . . . . . . . . . . . . . . .118
5.7 Timer Signals (ICOC1[3:0] and ICOC2[3:0]) . . . . . . . . . . .118
5.8 Analog-to-Digital Converter Signals. . . . . . . . . . . . . . . . . .118
5.8.1 Analog Inputs (PQA[4:3], PQA[1:0], and PQB[3:0]). . . .118
5.8.2 Analog Reference (V RH and VRL) . . . . . . . . . . . . . . . . .118
5.8.3 Analog Supply (VDDA  and VSSA) . . . . . . . . . . . . . . . . . .118
5.8.4 Positive Supply (VDDH)  . . . . . . . . . . . . . . . . . . . . . . . . .118
5.9 Debug and Emulation S upport Signals  . . . . . . . . . . . . . . .119
5.9.1 Test Reset (TRST). . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
5.9.2 Test Clock (TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
5.9.3 Test Mode Select (TMS) . . . . . . . . . . . . . . . . . . . . . . . .119
5.9.4 Test Data Input (TDI). . . . . . . . . . . . . . . . . . . . . . . . . . .119
5.9.5 Test Data Output (TDO). . . . . . . . . . . . . . . . . . . . . . . . .119
5.9.6 Debug Event (DE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
5.10 Test Signal (TEST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
5.11 Power and Ground Signals  . . . . . . . . . . . . . . . . . . . . . . . .120
5.11.1 Standby Power (VSTBY) . . . . . . . . . . . . . . . . . . . . . . . . .120
5.11.2 Positive Supply (VDD). . . . . . . . . . . . . . . . . . . . . . . . . . .120
5.11.3 Ground (VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
    
  
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Signal Description

Introduction

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Informa tion

MOTOROLA Signal Description 97

3.2 Introduc tion

The MMC2114, MMC2113, and MMC2112 are available in three

packages:

•100-pin Joint-Electron Device Engineering Council (JEDEC) low-

profi le quad flat pack (LQFP ) — The 1 00-pin devic e is a mi nimum

pin set for single-chip mode implementation.

•144-pin JEDEC LQFP — The 144-pin implementation includes 44

optional pins as a bond-out option to:

–Accommodate an expanded set of features

–Allow expansion of the number of general-purpose

input/output (I/O)

–Utilize off-chip memory

–Provide enhanced support for development purposes

•196-pi n molde d array process (M AP) ball grid ar ray (BGA) — The

196-pin implementation includes:

–Single-chip operation with extra general-purpose input/output

–Expanded master mode for interfacing to external memories

–Emulation mode for development and debug

The optional group of pins includes:

•23 address output lines

•Four chip selects

•Two emulation chip selects

•Four byte/wr it e enables

•Read/write (R/W) signal

•Output enable signal

•Three transfer code signals

•Six power/ground pins

NOTE: The optional pins are either all present or none of them ar e present.

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98 Signal Description MOTOROLA

Signal Descript ion

3.3 Package Pinout Summary

Refer to:

•Table 3-1 for a summary of the pinouts for the 144-pin and 100-

pin LQFP packages.

•Figure 3-1, Figure 3-2, and Figure 3-3 for a graphic view of the

pinouts

•Table 3-2 for a brief description of each signal

Table 3-1. Package Pinouts (Sheet 1 of 5)

Pin Numb er Pin Name

144-Pin Package 100-Pin Package 196-Ball MAPBGA

1 1 B1 D30 / PA6

2 2 C2 D29 / PA5

3 3 C1 D28 / PA4

4 4 D3 D27 / PA3

5 5 D2 D26 / PA2

6 — D1 A11

7 6 E3 D25 / PA1

8—— VSS

9—— VDD

10 7 E2 D24 / PA0

11 —E1 A10

12 8 F3 D23 / PB7

13 —F2 A9

14 —F1 A8

15 9 G3 D22 / PB6

16 10 G2 D21 / PB5

17 11 G1 D20 / PB4

18 12 —VSS

19 13 —VDD

20 14 H3 D19 / PB3

21 15 H2 D18 / PB2

22 16 H1 D17 / PB1

23 —J3 A7

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Package P inou t Summary

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MOTOROLA Signal Description 99

24 —J2 A6

25 17 J1 D16 / PB0

26 —K3 A5

27 18 K2 D15 / PC7

28 —K1 A4

29 —L3 A3

30 19 L2 D14 / PC6

31 20 L1 D13 / PC5

32 21 —VSS

33 22 —VDD

34 23 M2 D12 / PC4

35 24 M1 D11 / PC3

36 25 N1 D10 / PC2

37 26 P2 D9 / PC1

38 27 M3 D8 / PC0

39 28 N3 D7 / PD7

40 29 P3 D6 / PD6

41 30 M4 D5 / PD5

42 31 N4 D4 / PD4

43 32 P4 D3 / PD3

44 —— VSS

45 —— VDD

46 33 M5 D2 / PD2

47 —N5 A2

48 34 P5 D1 / PD1

49 —M6 A1

50 —N6 A0

51 35 P6 D0 / PD0

52 36 M7 ICOC23

53 37 N7 ICOC22

54 38 P7 ICOC21

55 39 M8 ICOC20

56 40 N8 ICOC13

Table 3-1. Package Pinouts (Sheet 2 of 5)

Pin Numb er Pin Name

144-Pin Package 100-Pin Package 196-Ball MAPBGA

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100 Signal Description MOTOROLA

Signal Descript ion

57 41 P8 ICOC12

58 42 M9 ICOC11

59 —N9 R/W

60 —P9 CSE1

61 43 M10 ICOC10

62 —N10 CSE0

63 44 P10 TEST

64 —— VSS

65 —— VDD

66 45 M11 TXD2

67 —N11 TC2

68 46 P11 RXD2

69 47 N12 TXD1

70 48 P12 RXD1

71 49 N13 INT0

72 50 P13 INT1

73 51 P14 VSSF

74 52 M12 VDDF

75 53 N14 INT2

76 54 —VSS

77 55 —VDD

78 —M13 TC1

79 56 M14 INT3

80 —L12 TC0

81 —L13 CS3

82 57 L14 INT4

83 —K12 CS2

84 58 K13 INT5

85 —K14 CS1

86 —J12 CS0

87 59 J13 No connect

88 60 J14 INT6

89 61 H12 INT7

Table 3-1. Package Pinouts (Sheet 3 of 5)

Pin Numb er Pin Name

144-Pin Package 100-Pin Package 196-Ball MAPBGA

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Signal Description

Package P inou t Summary

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Informa tion

MOTOROLA Signal Description 101

90 62 H13 MOSI

91 63 H14 MISO

92 64 G12 VSTBY

93 65 G13 SCK

94 66 G14 SS

95 —F12 OE

96 —F13 EB3

97 67 F14 SHS / PE7

98 —E12 EB2

99 68 E13 TA / PE6

100 —E14 EB1

101 —D12 EB0

102 69 D13 TEA / PE5

103 70 E11 VDDH

104 71 D14 PQB3

105 72 C12 PQB2

106 73 C13 PQB1

107 74 C14 PQB0

108 75 B14 PQA4

109 76 A13 PQA3

110 77 B12 PQA1

111 78 A12 PQA0

112 79 C11 VRL

113 80 B11 VRH

114 81 E10 VSSA

115 82 E9 VDDA

116 —A11 A22

117 —C10 A21

118 83 B10 RESET

119 —A10 A20

120 84 C9 RSTOUT

121 —B9 A19

122 —A9 A18

Table 3-1. Package Pinouts (Sheet 4 of 5)

Pin Numb er Pin Name

144-Pin Package 100-Pin Package 196-Ball MAPBGA

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102 Signal Description MOTOROLA

Signal Descript ion

123 85 D8 PLLEN

124 86 A8 XTAL

125 87 A7 EXTAL

126 88 —VSS

127 89 —VSS

128 90 E8 CLKOUT

129 91 —VDD

130 92 B7 TCLK

131 —A6 A17

132 —B6 A16

133 93 A5 TDI

134 —C6 A15

135 94 B5 TDO

136 —A4 A14

137 —C5 A13

138 95 B4 TMS

139 —A3 A12

140 96 —VSS

141 97 —VDD

142 98 B3 TRST

143 99 A2 DE

144 100 C3 D31 / PA7

——

A1, B2, C4, C7, C8, D4–D7 , E4–E7,

F4–F6 , G 4, G 5 , H4, H 5 , J4 , K4 ,–K11,

L4–L11, N2, P 1 VDD

——

A14, B8, B13, D9–D11, F7–F11,

G6–G11, H6–H11, J5–J11 VSS

Table 3-1. Package Pinouts (Sheet 5 of 5)

Pin Numb er Pin Name

144-Pin Package 100-Pin Package 196-Ball MAPBGA

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MMC2 114 • MM C 2 11 3 • MMC2112 — Rev. 1.0 Advance Information

MOTOROLA Sign al Description 103

Sig nal Description

Package Pinout Summary

12345678910 11 12 13 14

AVDD DE A12 A14 TDI A17 EXTAL XTAL A18 A20 A22 PQA0 PQA3 VSS A

BD30 VDD TRST TMS TDO A16 TCLK VSS A19 RESET VRH PQA1 VSS PQA4 B

CD28 D29 D31 VDD A13 A15 VDD VDD RSTOUT A21 VRL PQB2 PQB1 PAB0 C

DA11 D26 D27 VDD VDD VDD VDD PLLEN VSS VSS VSS EB0 TEA PQB3 D

EA10 D24 D25 VDD VDD VDD VDD CLKOUT VDDA VSSA VDDH EB2 TA EB1 E

FA8 A9 D23 VDD VDD VDD VSS VSS VSS VSS VSS OE EB3 SHS F

GD20 D21 D22 VDD VDD VSS VSS VSS VSS VSS VSS VSTBY SCK SS G

HD17 D18 D19 VDD VDD VSS VSS VSS VSS VSS VSS INT7 MOSI MISO H

JD16A6 A7V

DD VSS VSS VSS VSS VSS VSS VSS CS0 N/C INT6 J

KA4 D15 A5 VDD VDD VDD VDD VDD VDD VDD VDD CS2 INT5 CS1 K

LD13 D14 A3 VDD VDD VDD VDD VDD VDD VDD VDD TC0 CS3 INT4 L

MD11 D12 D8 D5 D2 A1 ICOC23 ICOC20 ICOC11 ICOC10 TXD2 VDDF TC1 INT3 M

ND10 VDD D7 D4 A2 A0 ICOC22 ICOC13 R/W CSE0 TC2 TXD1 INT0 INT2 N

PVDD D9 D6 D3 D1 D0 ICOC21 ICOC12 CSE1 TEST RXD2 RXD1 INT1 VSS P

12345678910 11 12 13 14

Figu re 3-1. 196- Ball MAPBGA Assignmen ts

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104 Signal Description MOTOROLA

Signal Descript ion

Figure 3-2. 144-Pin LQFP Assignments

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

PQA4

PQB0

PQB1

PQB2

PQB3

VDDH

TEA

EB0

EB1

EB2

SHS

EB3

SCK

VSTBY

MISO

MOSI

INT7

INT6

NO CONNECT

CS0

CS1

INT5

CS2

INT4

CS3

TC0

INT3

TC1

VDD

VSS

INT2

VDDF

VSSF

D30

D29

D28

D27

D26

A11

D25

VSS

VDD

D24

A10

D23

D22

D21

D20

VSS

VDD

D19

D18

D17

D16

D15

D14

D13

VSS

VDD

D12

D11

D10

ICOC23

ICOC22

ICOC21

ICOC20

ICOC13

ICOC12

ICOC11

R/W

CSE1

ICOC10

CSE0

TEST

TXD2

TC2

RXD2

TXD1

RXD1

INT0

INT1

D31

TRST

A12

TMS

A13

A14

TDO

A15

TDI

A16

A17

TCLK

CLKOUT

EXTAL

XTAL

PLLEN

A18

A19

RSTOUT

A20

RESET

A21

A22

DDA

SSA

PQA0

PQA1

PQA3

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Signal Description

Package P inou t Summary

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Informa tion

MOTOROLA Signal Description 105

Figure 3-3. 100-Pin LQFP Assignments

100

PA6

PA5

PA4

PA3

PA2

PA1

PA0

PB7

PB6

PB5

PB4

VSS

VDD

PB3

PB2

PB1

PB0

PC7

PC6

PC5

VSS

VDD

PC4

PC3

PC2

PC1

PC0

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

ICOC23

ICOC22

ICOC21

ICOC20

ICOC13

ICOC12

ICOC11

ICOC10

TEST

TXD2

RXD2

TXD1

RXD1

INT0

INT1 PQA3

PQA1

PQA0

SSA

DDA

RESET

RSTOUT

PLLEN

XTAL

EXTAL

CLKOUT

TCLK

TDI

TDO

TMS

TRST

PA7

VSSF

VDDF

INT2

VSS

VDD

INT3

INT4

INT5

NO CONNECT

INT6

INT7

MOSI

MISO

VSTBY

SCK

PE7

PE6

PE5

VDDH

PQB3

PQB2

PQB1

PQB0

PQA4

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106 Signal Description MOTOROLA

Signal Descript ion

Table 3-2. Signal Descriptions (Sheet 1 of 3)

Name(1) Alternate Qty. Dir. Input

Hyst. Input

Sync.(2)

Drive

Strength

Control(3) Pullup(4) Output

Driver

(ST/OD/SP)(5)

Reset

RESET — 1 I/O(6) YY —Pullup —

RSTOUT SHOWINT 1I/O(6) — — LOAD —ST

Clock

EXTAL — 1 I N N — — SP

XTAL — 1 O — — — — SP

CLKOUT — 1 I/O(6) — — LOAD —ST

PLLEN — 1 I — — — Pullup —

External Memory Interface an d Ports

D[31:0] PA[7:0], PB[7:0]

PC[7:0], PD[7:0] 32 I/O Y Y LOAD —ST

SHS RCON / PE7 1I/O Y Y LOAD Pullup ST

TA PE6 1I/O Y Y LOAD Pullup ST

TEA PE5 1I/O Y Y LOAD Pullup ST

CSE[1:0] PE[4:3] 2I/O Y Y LOAD Pullup ST

TC[2:0] PE[2:0] 3I/O Y Y LOAD Pullup ST

R/W PF7 1I/O Y Y LOAD Pullup ST

A[22:0] PF[6:0], PG[7:0]

PH[7:0] 23 I/O Y Y LOAD Pullup ST

EB[3:0] PI[7:4] 4I/O Y Y LOAD Pullup ST

CS[3:0] PI[3:0] 4I/O Y Y LOAD Pullup ST

OE — 1 I/O(6) — — LOAD —ST

Edge Port

INT[7:6] TSIZ[1:0] / GPIO 2I/O Y Y LOAD — —

INT[5:2] P STAT [3:0 ] / G P IO 4I/O Y Y LOAD — —

INT[1:0] GPIO 2I/O Y Y LOAD — —

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Signal Description
Package P inou t Summary
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Informa tion 
MOTOROLA Signal Description  107
Serial Peripher al Interface (SPI)
MOSI GPIO 1I/O Y Y RDPSP0 Pullup(4) ST / OD(7)
MISO GPIO 1I/O Y Y RDPSP0 Pullup(4) ST / OD(7)
SCK GPIO 1I/O Y Y RDPSP0 Pullup(4) ST / OD (7)
SS GPIO 1I/O Y Y RDPSP0 Pullup(4) ST / OD (7)
Serial Communication Interface (SCI1 and SCI2)
TXD1 GPIO 1I/O Y Y RDPSCI0 Pullup(4) ST / OD (7)
RXD1 GPIO 1I/O Y Y RDPSCI0 Pullup(4) ST / OD(7)
TXD2 GPIO 1I/O Y Y RDPSCI0 Pullup(4) ST / OD (7)
RXD2 GPIO 1I/O Y Y RDPSCI0 Pullup(4) ST / OD(7)
Timer 1 and Timer 2
ICOC13 IC / O C  / PAI / G P IO 1I/O Y Y RDPT Pullup(4) ST
ICOC1[2:0] IC / OC / GPIO 3I/O Y Y RDPT Pullup(4) ST
ICOC23 IC / O C  / PAI / G P IO 1I/O Y Y RDPT Pullup(4) ST
ICOC2[2:0] IC / OC / GPIO 3I/O Y Y RDPT Pullup(4) ST
Queued Analog-to- Digital Converter (QADC)
PQA4–PQA3, 
PQA1–PQA0 GPIO 4I/O Y Y — — ST
PQB[3:0] GPI 4I/O Y Y — — ST
VRH — 1 I — — — — —
VRL — 1 I — — — — —
VDDA — 1 I — — — — —
VSSA — 1 I — — — — —
VDDH — 1 I — — — — —
Table 3-2. Signal Descriptions (Sheet 2 of 3)
Name(1) Alternate Qty. Dir. Input
Hyst. Input
Sync.(2)
Drive
Strength
Control(3) Pullup(4) Output
Driver
(ST/OD/SP)(5)
    
  
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108 Signal Description MOTOROLA

Signal Descript ion

Debug and JTAG Test Port Control

TRST — 1 I Y N — Pullup —

TCLK — 1 I Y N — Pullup —

TMS — 1 I Y N — Pullup —

TDI — 1 I Y N — Pullup —

TDO — 1 O(8) — — LOAD —ST

DE — 1 I/O Y N LOAD Pullup OD

Test

TEST — 1 I Y N — — —

Pow er Sup plies

VDDF — 1 I — — — — —

VSSF — 1 I — — — — —

VSTBY — 1 I — — — — —

VDD — 5 I — — — — —

VSS — 6 I — — — — —

VDD — 3 I — — — — —

VSS — 3 I — — — — —

Total 100

Total with optional pins 144

1. Shaded signals are for opti onal bond-ou t for 144-pin packag e.

2. Synchronized input used only if signal configured as a digi tal I/O. RESET signal is always synch ronized, except in low-

power stop mode.

3. LOAD (Chip Configuration Register bit), RDPSP0 (PURD register bit in SPI), RDPSCI0 (SCIPURD register bit in both

SC Is ), RDP T (T IMSCR 2 re g is te r bit in bot h time rs)

4. All pullups are disconnected when the signal is programmed as an outpu t.

5. Output driver ty pe: ST = standar d, OD = standard driver with open-drain pul ldown option selected, SP = speci al

6. Di gital i nput f uncti on for RST OUT, CLKOUT, OE, and digital output function for RESET used only f or JTAG bo undary s can

7. Open-drain and pull up function selectable via pr ogrammer’s model in mo dule conf iguration registers

8. Three-state output with no input function

Table 3-2. Signal Descriptions (Sheet 3 of 3)

Name(1) Alternate Qty. Dir. Input

Hyst. Input

Sync.(2)

Drive

Strength

Control(3) Pullup(4) Output

Driver

(ST/OD/SP)(5)

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Signal Description

Chip Specific Impleme ntation Signal Issues

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Informa tion

MOTOROLA Signal Description 109

3.4 Chip Specific Implementation Signal Issues

Most modules are designed to allo w expanded capabilities if all the

module signals to the pads are implemented. This subsection discusses

how these mo dules are im pleme nted on t he MMC211 4, MMC211 3, and

MMC2112.

3.4.1 RSTOUT Signal Functions

The RSTOUT signal has these multiple functions:

•Whenever the internal system reset is asserted, the RSTOUT

signal will always be asserted to indicate the reset condition to the

system.

•If the internal reset is not asserted, then setting the FRCRSTOUT

bit in the Reset Control Register (RCR) will assert the RSTOUT

signal for as long a s the F RCRSTOUT bit is set. See 5. 6.1 Res et

Control Registe r.

•If the intern al reset is not asserted a nd the FR CRST OUT bit i s not

set, then setting the SHOWINT bit in the Chip Configuration

signal.

•If the intern al reset is not asserted a nd the FR CRST OUT bit i s not

set and the SHOWINT bit is not set, then the RSTOUT signal will

be negated to indicate to the system that there is no reset

condition.

CAUTION: External logic used to drive reset configuration data during reset needs

to be considered when using the RSTOUT signal for a function other

than an indication of reset.

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Signal Descript ion

3.4.2 INT Signal Functions

The INT signals have these multiple functions:

•If the SZEN bit in the Chip Configuration Register is set, then

INT[7:6] will be used to reflect the state of the TSIZ[1:0] signals

from the CPU. See 4.7.3.1 Chip Configuration Register.

•If the PSTEN bit in the Chip Configuration Register (CCR) is set,

then INT[5:2] will be used to reflect the state of the PST AT[3:0]

sign als fro m th e CP U. S ee 4.7.3.1 Chip Co nfi gu ration Reg ister .

NOTE: If the SZEN or P STEN bits are set during emulation mode, then the

corresp onding edge por t I N T functions are lost and will not be emulated

externally.

The default reset value for the PUPSC1 bit in SCIPURD is 0. Thus, the

pullup function is disabled by default.

3.4.3 Serial Peripheral Interface (SPI) Pin Functions

The SPI module can support up to eight external pins, but only the four

pins required for the SPI interface are implemented.

Full SPI interface capabilities and GPIO functions using the MISO,

MOSI, SCK, and SS pins are supported.

•SWOM register bit controls whether output buffers behave as

open-drain outputs. Default is not open-drain outputs.

•PUPSP0 register bit enables internal weak pad pullup devices.

Default is pullups disabled.

•RDPSP0 register bit controls reduced drive function of output

buffers. Default is full drive.

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Chip Specific Impleme ntation Signal Issues

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MOTOROLA Signal Description 111

GPIO [7:4] of SPI module not implemented.

•Writes to bits [7:4] of the SPIPORT and SPIDDR registers have no

effect except to change the register bit values.

•Reads of bits [7:4] of the SPIPORT when the corresponding

SPIDDR bits are set for inputs always return 0.

•PUPSP and RDPSP register bits have no effect.

The default reset values for the PUPSP b it in SPIPURD is 0. Thus, the

pullup function is disabled by default.

3.4.4 Serial Communications Interface (SCI1 and SCI2) Pin Functions

Full SCI interface capabilities and GPIO functions u sing the TXD1/2 and

RXD1/2 pins are supported.

•WOMS register bit controls whether output buffers behave as

open-drain outputs. Default is not open-drain outputs.

•PUPSCI register bit enables internal weak pad pullup devices.

Default is pullups disabled.

•RDPSCI register bit controls reduced drive function of output

buffers. Default is full drive.

GPIO [7:2] of SCI modules not implemented.

•Writes to bits [7:2] of the SCIPORT and SCIDDR regi sters have

no effect except to change the register bit values.

•Reads of bits [7:2] of the SCIPORT w hen the corresponding

SCIDDR bits are set for inputs always return 0.

•PUPSCI and RDPSCI register bits have no effect.

The default reset value for PUPSCI is 0. Thus, the pullup function is

disabled by default.

NOTE: Only the pins associated with each SCI are controlled by the register bits

for the corresponding SCI. Thu s, the W OM S regi ster bi t fro m SCI 1 only

affects TXD1 and RXD1 and has no effect on TXD2 and RXD2.

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112 Signal Description MOTOROLA

Signal Descript ion

3.4.5 Timer 1 and Timer 2 Pin Functions

The timer modules can support up to four external pins each.

NOTE: Onl y the pins associated with each timer are controlled by the register

bits for the corresponding timer.

Full timer port pin functions are supported.

•PUPT register bit enables internal weak pad pullup devices.

Default disables pullups.

•RDPT register bit controls reduced drive function of output buffers.

Default is full drive.

The default reset value for PUPT is 0. Thus, the pullup function is

disabled by default.

The sync input is tied off and this function is not supported.

3.4.6 Queued Analog-to-Digital Converter (QADC) Pin Functions

This implem entation is a limited pin out version of the original QADC.

Lim iting the num ber of pins l owers the over all pin count of th e complete

package. T he low e r pin co unt is ach ieved by u ti lizing 8 of 1 6 pi ns of the

ori ginal ful l pin set. The a v ailabl e pins a re, P QA4 –PQ A3 , PQ A1 –PQA0,

and PQB3–PQB0. All of the original functionality of the module is

implemented with exception of limiting the total number of multiplexed

channels. By using four external multiplexer chips, the maximum

number of channels is 18. In nonmultiplexed mode, the maximum

number of channels is eight.

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Signal Description

Sig nal Descriptions

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Informa tion

MOTOROLA Signal Description 113

3.5 Signal Descriptions

This subsection provides a brief description of the signals. For more

detailed information, reference the specific module section.

3.5.1 Reset Signals

These signals are used to either reset the chip or as a reset indication.

3.5.1.1 Reset In (RESET)

This acti ve -low i np ut signa l is used as th e exte rnal reset req uest. R e set

places the CPU in supervisor mode with default settings for all register

bits.

3.5.1.2 Reset Out (RSTOUT)

This active-low output signal is an indication that the internal reset

controller has reset the chip. When RSTO UT is active, the user may

drive override configur ation options on the data bus. See Table 4-7.

Configuration During Reset. RSTOUT is three-stated in phase-lock

loop (PLL) test mode.

RSTOUT may also be used to reflect an indication of an internal interrupt

request.

3.5.2 Phase-Lock Loop (PLL) and Clock Signals

These sign als are used to support the on-chip clock generation circuitry.

3.5.2.1 External Clock In (EXTAL )

This input signal is always driven by an external clock input except when

used as a connection to an external crystal when the internal oscillator

circuit is used. The clock source is configured during reset.

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114 Signal Description MOTOROLA

Signal Descript ion

3.5.2.2 Crystal (XTAL)

This output signal is used as a connection to drive an external crystal

when the internal oscillator circuit is used. XTAL should be grounded

when using an external clock input on EXTAL.

3.5.2.3 Clock Out (CLKOUT)

This output signal reflects the inter n al system clock.

3.5.2.4 PLL Enable (PLLEN)

This is an active high signal only required during reset if chip

conf iguration is perform ed. If this sign al is pulled hi gh during reset, then

the PLL will be used to clock the device. Pu lling this signal low during

reset selects external clock mode. See Table 4-7. Configuration

During Reset.

3.5.3 External Memory Interface Signals

In addition to the functions stated here, these signal s can also be

configured for discrete I/O.

3.5.3.1 Data Bus (D[31:0])

These three-state bidirectional signals provide the general-purpose data

path between the microcontroller unit (MCU) and all other devices.

Some of these pins are used during reset for chip configuration.

3.5.3.2 Show Cycle Strobe (SHS)

This output signal is used in emulation mode as a strobe for capturing

addresses, controls, and data during show cycles. T his signal is also

used as RCON.

NOTE: The RCON signal, used only during reset, indicates whether the states

on the external signals affect the chip configuration.

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Signal Description

Sig nal Descriptions

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Informa tion

MOTOROLA Signal Description 115

3.5.3.3 Transfer Acknowledge (TA)

This input signal indicates that the external data transfer is complete.

During a read cycle, when the processor recognizes TA, it latches the

data and then terminates the bus cycle. During a write cycle, when the

processor recognizes TA, the bus cycle is term inated. This signal is an

inp ut in master and emula tion modes. T his function is not used i n single-

chip mode and its pin defaults to digital I/O.

3.5.3.4 Transfer Error Acknowledge (TEA)

This signal indicates an error condition exists for the bus transfer. The

bus cycle is terminated and the central processor unit (CPU) begins

execution of the access error exception. This signal is an input in master

and em ulation modes. Th is function is not used in single-chi p mode a nd

its pin defaults to digital I/O.

3.5.3.5 Emulation Mode Chip Selects (CSE[1:0])

These output signals provide chip sele ct support in emulation mode.

3.5.3.6 Transfer Code (TC[2:0])

These outp ut signal s indicate the dat a transfe r code for the current bus

cycle. These signals are enabled by default only in emulation mode. See

Table 12-2. PEPAR Reset Values.

3.5.3.7 Read/Write (R/W)

This output signal indi cates the direct io n of the data tran sfer on the bus.

A logic 1 indicates a read from a slave device and a logic 0 indicates a

write to a slave device.

3.5.3.8 Address Bus (A[22:0])

These output signals provide the address for the current bus transfer.

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Signal Descript ion

3.5.3.9 Enable Byte (EB[3:0])

These outpu t signals indi cate which byt e of data is valid during exter nal

cycles.

3.5.3.10 Chip Select (CS[3:0])

These output signals select external devices for external bus

transactions.

3.5.3.11 Output Enable (OE)

This output signal indicates when an external device can drive data

during external read cycles.

3.5.4 Edge Port Signals

These signals are used by the edge port module.

3.5.4.1 External Interrupts (INT[7:6])

These bidirectional signals function as either external interrupt sources

or GPIO. Also, these signals may be used to reflect the internal TSIZ[1:0]

signals and externally to provide an indication of the CPU transfer size.

See 4.7.3.1 Chip Configuration Register and Section 20. External

Bus Interface Module (EBI).

3.5.4.2 External Interrupts (INT[5:2])

These bidirectional signals function as either external interrupt sources

or GPIO. Also, these signal s may be used to reflect the internal

PSTAT[3:0] signals and externally to provide an indication of the CPU

processor status.See 4.7.3.1 Chip Configur ation Register and

Section 20. External Bus Interface Module (EBI).

3.5.4.3 External Interrupts (INT[1:0])

These bidirectional signals function as either external interrupt sources

or GPIO.

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Sig nal Descriptions

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MOTOROLA Signal Description 117

3.5.5 Serial Peripheral Interface Module Signals

These signals are used by the SPI module and may also be configured

to be discrete I/O signals.

3.5.5.1 Master Out/Slave In (MOSI)

This signal is the serial data output from the SPI in master mode and the

serial data input in slave mode.

3.5.5.2 Master In/Slave Out (MISO)

This signal is the serial data input to the SPI in master mode and the

serial data output in slave mode.

3.5.5.3 Serial Clock (SCK)

The serial clock synchronizes data transmissions between master and

slave devices. SCK is an output if the SPI is configured as a master. SCK

is an input if the SPI is configured as a slave.

3.5.5.4 Slave Select (SS)

This I/O sign al is the periph eral chip select sign al in master m ode and is

an active-l ow slave select in slave mode.

3.5.6 Serial Communications Interface Module Signals

These signals are used by the two SCI modu les.

3.5.6.1 Receive Data (RXD1 and RXD2)

These signals are used for the SCI receiver data input and are also

available for GPIO when not configured for receiver operation.

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Signal Descript ion

3.5.6.2 Transmit Data (TXD1 and TXD2)

These signals are us ed for the SCI tra nsmi tter data output and ar e also

available for GPIO when not configured for transmitter operation.

3.5.7 Timer Signals (ICOC1[3:0] and ICOC2[3:0])

These sig nals provi de the exter nal interface to the timer functions. T hey

may be configu red as ge nera l-pur pose I/O if t he tim er o utput functio n is

not needed. The default state at reset is general- purpose input.

3.5.8 Analog-to-Digital Converter Signals

These signals are used by the analog-to-digital converter (QADC)

module.

3.5.8.1 Analog Inputs (PQA[4:3], PQA[1:0], and PQB[3:0])

These signals provide the anal og inputs to the QADC. The PQA and

PQB signals may also be used as general-purpose digital I/O.

3.5.8.2 Analog Reference (VRH and VRL)

These signals serve as the high (VRH) and low (VRL) reference potentials

for the analog converter.

3.5.8.3 Analog Supply (VDDA and VSSA)

These dedicated power supply signals isolate the sensitive analog

circuitry from the normal levels of noise present on the digital power

supply.

3.5.8.4 Positive Supply (VDDH)

This signal supplies positive power to the ESD structures in the QADC

pads.

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Sig nal Descriptions

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MOTOROLA Signal Description 119

3.5.9 Debug and Emulation Support Signals

These signal s are used as the interface to the on-chi p JTAG (Joint Test

Action Group) controller and also to interface to the OnCE logic.

3. 5.9.1 Test Reset (TRS T)

This a ctive-low input signal is used to initialize the JTAG and OnCE logic

asynchronously.

3. 5.9.2 Test Clock (TCLK)

This input signal is the test clock used to synchronize the JTAG and

OnCE logic.

3.5.9.3 Test Mode Select (TMS)

This input signal is used to sequence the JTAG state machine. TMS is

sampled on the rising edge of TCLK.

3.5.9.4 Test Data Input (TDI)

This input signal is the seri al input for test instructions and data. TDI is

sampled on the rising edge of TCLK.

3.5.9.5 Test Data Output (TDO)

This output signal is the seria l output for te st instru ctions and data . TDO

is three-stateable and is actively driven in the shift-IR and shift-DR

controller states. TDO changes on the falling edge of TCLK.

3. 5.9.6 Debug Event (DE)

This is a bidire ctional, act ive-low signa l. As an output , this signal will be

asserted for three system clocks, synchronous to the rising CLKOUT

edge, to acknowledge that the CPU has entered debug mode as a result

of a debug request or a breakpoint condition. As an input, this signal

provides multiple functions.

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Signal Descript ion

3.5.10 Test Signal (TEST)

This input signal (TEST) is reserved for factory testing only and should

be con nected to V SS to preven t u nintent io nal activation of test fun c tions.

3.5.11 Power and Ground Signals

These signals provide system power and ground to the chip. Multiple

signals are provided for adequate current capability. All power supply

signals must have adequate bypass capaci tance for high-frequency

noise suppression.

3.5.11.1 Standby Power (VSTBY)

This signal is used to provide stan dby voltage t o the RAM array if VDD is

lost. Typically, if used, this signal would be connected to a battery.

3.5.11.2 Positive Supply (VDD)

This signal supplies positive power to the core logic and I/O pads.

3.5.11.3 Ground (VSS)

This signal is the negative supply (ground) to the chip.

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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0  Advance Information
MOTOROLA Chip Configurat ion Module (CCM)  121
Advance Info rmation — MMC2114, MMC2113, and MMC2112
Section 4. Chip Configuration Module (CCM)
1  Contents
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
4.1 Master Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
4.2 Single-Chip Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
4.3 Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
4.4 Factory Access Slave Test (FAST) Mode . . . . . . . . . . . . .123
5 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
6 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
7 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .125
7.1 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
7.2 Memory Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
7.3 Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
7.3.1 Chip Configuration Register. . . . . . . . . . . . . . . . . . . . . .126
7.3.2 Reset Configuration Register. . . . . . . . . . . . . . . . . . . . .129
7.3.3 Chip Identification Register . . . . . . . . . . . . . . . . . . . . . .131
7.3.4 Chip Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
8.1 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
8.2 Chip Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
8.3 Boot Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
8.4 Output Pad Strength Configuration . . . . . . . . . . . . . . . . . .137
8.5 Clock Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
8.6 Internal FLASH Configuration  . . . . . . . . . . . . . . . . . . . . . .138
9 Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
10 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
    
  
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122 Chip Configurat ion Module (CCM ) MOTOROLA

Chip Configuration Module (CCM)

4.2 Introduc tion

The chip configuration module (CCM) controls the chip configuration and

mode of operation.

4.3 Features

The CCM performs these operations.

•Selects the chip operating mode:

–Master mode

–Single-chip mode

–Emulation mode

–Factory access slave test (FAST) mode for factory test only

•Selects external clock or phase-lock loop (PLL) mode with internal

or external reference

•Selects output pad strength

•Selects boot device

•Selects module configur ation

•Selects bus monitor configuration

4.4 Modes of Operation

The CCM configures the chip for four modes of operation:

•Master mode

•Single-chip mode

•Emulation mode

•FAST mode for factory test only

The operating mode is determined at reset and cannot be changed

thereafter.

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Modes of Op eration

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4.4.1 Master Mode

In master mode, the internal central processor unit (CPU) can access

external memories and peripherals. Full master mode functionality

requires the bonding out of the optional pins. The external bus consists

of a 32-bit data bus and 23 address lines. Available bus control signals

include R/W, TC[2:0], TSIZ[1:0], TA, TEA, OE, and EB[3:0]. Up to four

chip selects can be programmed to select and control external devices

and to provide bus cycle termination. When interfacing to 16-bit ports,

the ports C and D pins and EB[3:2] can be configured as

general-purpose input/output (I/O).

4.4.2 Single-Chip Mode

In si ngle-chip m ode, all memory is internal to the chip . External bus pins

are configured as digital I/O.

4.4.3 Emulation Mode

Emulation mode supports external port replacement logic. All ports are

emulated and all primary pin functions are enabled. Since the full

external bus must be visible to support the external port replacement

logic, the emulation mode pin configuration resembles master mode.

Full emulation mode functionality requires bonding out the optional pins.

Emula tion mode chi p selects are provide d to give addition al informati on

about the bus cycle. Also, the signal SHS is provided as a strobe for

capturing addresses and data during show cycles.

4.4.4 Factory Access Slave Test (FAST) Mode

FAST mode is for factory test only.

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Chip Configuration Module (CCM)

4.5 Block Diagram

Figure 4-1. Chip Configuration Module Block Diagram

4.6 Signal Descriptions

Table 4-1 provides an overview of the CCM signals. For more detailed

information, refer to Section 3. Signal Description.

RESET

CHIP MODE

SELECTION

BOOT DEVICE

SELECTION

OU T PUT PAD

STRENGTH SELE CTI ON

CLOCK MO DE

SELECTION

MODULE

CONFIGURATION

RESET CONFIGURATION REGISTER

CHIP CO NFIGURATIO N RE G IS TE R

CHIP IDENTIFICATION REGISTER

CHIP TEST REG ISTER

Table 4-1. Signal Properties

Name Function Reset State

RCON Reset configuration select I nternal weak

pullu p devic e

PLLEN Clock mode select —

D[26, 23, 22, 21, 19, 18, 17, 16] Reset configuration overrides —

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Mem ory Map and Registers

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MOTOROLA Chip Configurat ion Module (CCM) 125

4.7 Memory Map and Registers

This subsection provides a description of the memory map and registers.

4.7.1 Programming Model

The CCM programming model consists of these registers:

•The Chip Configuration Register (CCR) controls the main chip

configuration. See 4.7.3.1 Chip Configuration Register.

•The Reset Configuration Register (RCON) indicates the default

chip configuration. See 4.7.3.2 Reset Configuration Register.

•The Chip Identification Register (CIR) contains a unique part

number. See 4.7.3.3 Chip Identification Register.

•The Chip Te st Register (CTR) contains chip-specific test

functions. See 4.7.3.4 Chip Test Register.

Some control register bits are implemented as write-once bits. These

bits are always readable, but once the bit has been written, additional

writes have no effect, except during debug and test operations.

Some write-once bits and test bits can be read and written while in debug

mode or test mode. When debug or test mode is exited, the chip

configuration module resumes operation based on the current register

valu es. If a write to a wr ite-once r egister bit occurs whi le in debug or test

mode, the re gister bit rem ains writable on exit from debug or t est mode.

Table 4-2 shows th e accessibility of write-once bits.

Table 4-2. Write-Once Bits Read/Write Accessibility

Configuration Read/Write Access

All configurations Read-always

Debug operation (all modes) Write-always

Test operation (all modes) Write-always

Master mode Write-once

Single-chip mode Write-once

FAST mode Wr ite- once

Emulation mode Write-once

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Chip Configuration Module (CCM)

4.7.2 Memory Map

4.7.3 Register Descriptions

The following subsection describes the CCM registers.

4.7.3.1 Chip Configuration Register

Table 4-3. Chip Configuration Module Memory Map

Address Bits 31–16 B its 15–0 Access(1)

0x00c1_0000 Chip Configuration Register (CCR) Reserved(2) S

0x00 c1_0004 R eset Configuration Register (RCON) Ch ip Identification Register (CIR) S

0x00c1_0008 Chip Test Register (CTR) Reserved(2) S

0x00c1_000c Unimplemented(3) —

1. S = CPU supervisor mode access only. User mode accesses to supervisor only addresses have no effect and result in a

cycle terminati on transfer err o r.

2. Writ ing to reserved addresses has no effect; reading returns 0s.

3. Accessing an unimp lemented address has no effect and causes a cycle terminati on transfe r err or.

Address: 0x00c1_0000 and 0x00c1_0001

Bit 15 14 13 12 11 10 9 B it 8

Read: LOAD 0SHEN EMINT 0 MODE2 MODE1 MODE0

Write:

Reset: Note 1 0 Note 2 Note 2 0 Note 1 Note 1 Note 1

Bit 7654321Bit 0

Read: 0 SZEN PSTEN SHINT BME BMD BMT1 BMT0

Write:

Reset:0Note 3Note 201000

= Writes have no effect and the access terminates without a transfer error exception.

Notes:

1. Determined during reset configuration

2. 0 for all configurations except emulation mode, 1 for emul ation mode

3. 0 for all configurations except emulation and master modes, 1 for emulation and master

modes

Figure 4-2. Chip Configuration Register (CCR)

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MOTOROLA Chip Configurat ion Module (CCM) 127

LOAD — Pad Driver Load Bit

The LOAD bit selects full or default drive strength for selected pad

output drivers. For maximum capacitive load, set the LOAD bit to

select full drive strength. For reduced power consumption, clear the

LOAD bit to select default drive strength.

1 = Fu ll drive strength

0 = Default drive strength

Table 4-2 shows th e read/write accessibility of this write-once bit.

SHEN — Show Cycle Enable Bit

The SHE N bit enables the external memory interface to drive the

external bus during internal transfer operations.

1 = Show cycles enabled

0 = Show cycles disabled

In emul ation mod e, the SHE N bit is rea d-only. In all other mo des, it is

a read/w rite bit.

EMINT — Emulate Internal Address Space Bit

The EM INT bit enables chip select 1 (CS1) to decode the internal

memory address space.

1 = CS1 decodes internal memory address space.

0 = CS1 decodes external memory address space.

The EMINT bit is read-always but can be written only in emulation

mode.

MODE[2:0] — Chip Configuration Mode Field

This read-onl y field refl ects the chip configuration mode, as shown in

Table 4-4.

Table 4-4. Chip Configuration Mode Selection

MODE[2:0] Chip Configuration Mode

111 Master mode

110 Sin gle- c h ip mod e

10X FA S T m ode

0XX Emulation m ode

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Chip Configuration Module (CCM)

SZEN — TSIZ[1:0] Enable Bits

This rea d/write bit ena bles the TSIZ[1 :0] fu nction o f the e xterna l pins.

1 = TSIZ[1:0] function enabled

0 = TSIZ[1:0] function disabled

PSTEN — PSTAT[3:0] Signal Enable Bits

This read/write bit enables the PSTAT[3:0] function of the external

pins.

1 = PST AT[3:0] function enabled

0 = PSTAT[3:0] function disabled

SHINT — Show Interrupt Bit

The SHINT bit allows visibility to any active interrupt request to the

processor. If the SHINT bit is set, the RS TOUT pin is the OR of the

fast and normal interrupt signals.

1 = Internal requests reflected on RSTOUT pin

0 = Normal RSTOUT pin function

The SHINT bit is read/write always.

NOTE: The FRCRSTOUT function in the reset controller has a higher priority

than the SHINT function.

BME — Bus Monitor External Enable Bit

The BM E bit enables the bus monitor to operate during external bus

cycles.

1 = Bus monitor enabled for external bus cycles

0 = Bus monitor disabled for external bus cycles

Table 4-2 shows th e read/write accessibility of this write-once bit.

BMD — Bus Monitor Debug Mode Bit

The BM D bit controls how the bus monitor responds during debug

mode.

1 = Bus monitor enabled in debug mode

0 = Bus monitor disabl ed in debug mode

This bit is read/write always.

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MOTOROLA Chip Configurat ion Module (CCM) 129

BMT[1:0] — Bus Moni tor Timing Field

The BM T field sele cts the timeout time for the bus monito r as shown

in Table 4-5.

Table 4-2 shows th e read/write accessibility of these write-once bits.

4.7.3.2 Reset Configuration Register

The Reset Configuration Register (RCON) is a read-only register; writing

to RCON has no effect. At reset, RCON determines the default operation

of certain chip functions. All default functions defined by the RCON

values may be overridden during reset configuration (see 4.8.1 Reset

Configuration) only if the external RCON pin is asserted.

Table 4-5. Bus Monitor Timeout Values

BMT[1:0] Timeout Period

(in System C l ocks)

00 64

01 32

10 16

11 8

Address: 0x00c1_0004 and 0x00c1_0005

Bit 15 14 13 12 11 10 9 B it 8

Write:

Reset:00000000

Bit 7654321Bit 0

RPLLSEL 1

RPLLREF 0

RLOAD 01

BOOTPS 0

BOOTSEL 00

MODE

Write:

Reset:11001000

= Writes have no effect and the access terminat es without a transfer error exception.

Figu re 4-3. Re set Conf igu ra tio n Regi ste r (RCO N)

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Chip Configuration Module (CCM)

RPLLSEL — PLL Mode Select Bit

When the PLL is enabled, the read-only RPLLSEL bit reflects the

default PLL mode.

1 = No rma l PLL mode

0 = 1:1 PLL mode

The default PLL mode can be overridden during reset configuration.

If the default mod e is o verr idden, the PLL SEL b it in t he cl ock mod ule

SYNSR reflects the PLL mode.

RPLLREF — P L L Reference Bit

When the PLL is enabled in normal PLL mode, the read-only

RPLLREF bit reflects the default PLL reference.

1 = Crystal oscillator is PLL reference.

0 = External clock is PLL reference .

The default PLL reference can be overridden during reset

configuration. If the default mode is overridden, the PLLREF bit in the

clock module SYNSR reflects the PLL reference.

RLOAD — Pad Driver Load Bit

The read-only RLOAD bit reflects the pad driver strength

configuration.

1 = Fu ll drive strength

0 = Default drive strength

The default function of the pad driver strength can be overridden

during reset configuration. If the default mode is overridden, the

LOAD bit in CCR reflects the pad driver strength configuration.

BOOTPS — Boo t Port Siz e Bit

If the boot device is configured to be external, the read-only BOOTPS

bit reflects the default selection for the boot port size.

1 = Boot device uses 32-bit port.

0 = Boot device uses 16-bit port.

The default function of the boot port size can be overridden during

reset configuration. If the default mode is overridden, the PS bit in

CSCR0 reflects the boot device port size configuration.

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MOTOROLA Chip Configurat ion Module (CCM) 131

BOOTSEL — Boot Select Bit

This read-only bit reflects the default selection for the boot device.

1 = Boot from external boot device

0 = Boot from internal boot device

The de fault functi on of the b oot select can b e overridde n during r eset

configuration. If the default mode is overridden, the CSEN bit in

CSCR0 bit reflects the boot device configuration.

MODE — Chip Conf iguration Mode Bit

The read-only MODE bit reflects the chip configuration mode.

1 = Master mode

0 = Single-chip mode

The defa ult mode can be over ridden during reset confi guration. If the

default mode is overridden, the MODE bits in CCR re flect the m ode

configuration.

4.7.3.3 Ch ip Identification R egister

The Chip Identification Register (CIR) is a read-only register; writing to

CIR has no effect.

Address: 0x00c1_0006 and 0x00c1_0007

Bit 15 14 13 12 11 10 9 B it 8

PIN7 0

PIN6 0

PIN5 1

PIN4 1

PIN3 1

PIN2 1

PIN1 0

PIN0

Write:

Reset:00011110

Bit 7654321Bit 0

PRN7 0

PRN6 0

PRN5 0

PRN4 0

PRN3 0

PRN2 0

PRN1 0

PRN0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfer error exception.

Figure 4-4. Chip Identification Register (CIR)

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Chip Configuration Module (CCM)

PIN[7:0] — Part Identification Number Field

This read-only field contains a unique identification number for the

part.

PRN[7:0] — Part Revision Number Field

This read-o nly field conta ins the full-layer mask revision number. This

number is increased by one for each new full-layer mask set of this

part. The revision numbers are assigned in chronological order.

4.7.3.4 Chip Test Register

The Chip Test Register (CTR) is reserved for factory testing.

NOTE: T o safeguard agains t unintentionall y activati ng test logic, write $0000 to

the lo ck out test features. Setting any bit in CTR may lead to

unpredictable results.

Address: 0x00c1_0008 and 0x00c1_0009

Bit 15 14 13 12 11 10 9 B it 8

Write:

Reset:00000000

Bit 7654321Bit 0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfer error exception.

Figure 4-5. Chip Test Register (CTR)

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Functional Description

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4.8 Functional Des cription

Six functi ons are defined within the chip configuration module:

1. Reset configuration

2. Chip mode selection

3. Boot devic e selection

4. Output pad strength configuration

5. Clock mode selection

6. Module configuration

These functions are described here.

4.8.1 Reset Configuration

During reset, the pins for the reset override functions are immediately

configured to known states. Table 4-6 shows the states of the external

pins while in reset.

If the RCON pin is not asse rted du ri ng re set, the chip con fi gura tion and

the reset configuration pin functions after reset are determined by RCON

or fixed defaults, regardle ss of the states of the external data pins. The

internal configuration signals are driven to levels specified by the RCON

Table 4-6. Reset Configuration Pin States During Reset

Pin Pin

Function(1)

1. If the exte rnal RCO N p in i s not asserted during reset, pin f unctions are determined by the

defau lt operation mode de fined in the RCON regi ster. If the e xternal RCON pin is as serted,

pin functions are determined by the chip operation mode defined by the overri de values

driven on th e external data bus pin s.

I/O Output

State Input

State

D[26, 23:21, 19:16],

PA[4, 2], PB[7:5, 3:0] Digital I/O or primary

function Input —Mus t be driven

by external logic

RCON RCON function for all

modes(2)

2. During reset, the external RCON pin assum es its RCON pin function, but this pin changes

to t he funct ion def ined by the chip oper atio n mode i mmediate ly aft er res et. See Table 4-7.

Input —Internal weak

pullup device

PLLEN Not aff ected Input —Must be driven by

external logic

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Chip Configuration Module (CCM)

If the external RCON pin is asserted during reset, then various chip

functi ons, includi n g the reset configura ti on pin functio ns after re set, are

configured according to the levels driven onto the external data pins.

(See Table 4-7.) The internal configuration signals are driven to reflect

the levels on the external configuration pins to allow for module

configuration.

Table 4-7. Conf igura tion Durin g Reset(1)

Pin(s) Affected Default

Configuration Override Pins

in Reset(2),(3) Function

D[31 :0], SHS , TA , TEA,

CSE[1:0], TC[2:0], OE,

A[22:0], EB[3:0] , CS[3:0 ] RCO N0 = 0

D[26,17:16] Chip Mode Selected

111 Master mode

110 Sing le-chip mode(4)

10X FA S T m ode

0XX Em ulation m ode

CS[1:0] RCON[3:2] = 10

D[19:18] Boot Device

X0 Internal with 32-bit port(4)

01 Exte rnal with 16-bit port

11 External with 32-bit port

All output pins RCON5 = 0

D21 Output Pad Drive Strength

0Default strength(4)

1 Full strength

Clock mode RCON[7:6] = 11

PLLEN, D[23:22] Clock Mode

0XX Exte rnal clock mode (PLL disabled)

10X 1:1 PLL mode

110 Normal P LL mode with external

clock reference

111 Normal PLL mo de w/crystal

oscillator reference(4)

1. Modif ying the default configurati ons is possible only if the exter nal RCON pin is asserted.

2. The D[31:29, 28, 27, 25:24, 20, 15: 0] pi ns do not aff ect rese t configurati on.

3. The external reset overri de circuitry drives the data bus pins wit h the override values whil e RSTOUT is asserted. It must

stop drivi ng the da ta bus pi ns within one CLKOUT cyc le aft er RSTOUT is negated. To p revent content ion wi th the e xternal

reset override circuitry, the reset override pins are forced to inputs during reset and do not become outputs until at least

one CLKO UT cyc le after RSTOUT is negate d.

4. Default configurati on

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4.8.2 Chip Mode Selection

The chip mode is selected dur ing reset and refl ected in the MODE field

of the Chip Configuration Register (CCR). (See 4.7.3.1 Chip

Configuration Register.) Once reset is exited, the operating mode

cannot be changed. Table 4-8 shows the mode selection during reset

configuration.

During reset, certain module configurations depend on whether

emulation mode is active as determined by the state of the internal

emulation signal.

4.8.3 Boot Device Selection

During reset configuration, the CS0 chip select pin is optionally

configured to select an external boot device. In this case, the CSEN bit

in CSCR0 is set, enabling CS0 after reset. CS0 will be asserted for the

initial boot fetch accessed from address 0x0. It is assumed that the reset

vect or loaded fro m address 0x0 causes the CPU to start exe cuting fr om

ext erna l memor y space deco ded by CS 0. Also, the P S bit is configu red

for either a 16-bit or 32-bit port size depending on the external boot

device. See Table 4-9.

In emulation mode, the CS1 chip select pin is optionally configured for

emulating an internal memory. In emulation mode and booting from

internal memory, the CSEN bit in CSCR1 is set, enabling CS1 after

reset.

Table 4-8. Chip Configuration Mode Selection(1)

1. Modif ying the default configurati ons is possible onl y if the exter nal RCON pin is asserted.

Chip Configuration

Mode CCR Register MODE Field

MODE2 MODE1 MODE0

Mast er mode D26 driven high D17 driven high D16 driven high

Sing le-chip mode D26 driven high D17 driven high D16 driven low

FA S T mode D26 driven high D17 driven low D16 don’t c a r e

Em ulation mode D26 driv en low D 17 don’t care D16 don’t c a r e

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Once r eset i s exited, the state s of the CSEN an d P S bits in CS CR 0 an d

the CSEN bit in CSCR1 remain , but can be modified by software.

The boot device selection during reset configuration is summarized in

Table 4-10.

Table 4-9. Chip Select CS0 Configuration Encod ing

Chip Select CS0 Control CSCR0

CSEN Bit PS Bit CSEN Bit

Chip select disabled ( 32-bit port size) 0 1 1(1)

1. CSCR1 CSEN is init ially set only in emulation mode when booting from internal memory

and is cl eared otherwise.

Chip select enabled with 16-bit port s ize 1 0 0

Chip select enabled with 32-bit port s ize 1 1 0

Table 4-10. Boot Device Selection(1)

1. Modif ying the default configurati ons is possible onl y if the exter nal RCON pin is asserted.

Boot Device Selection CSCR0

CSEN Bit PS Bit CSEN Bit

Internal boot device;

default 32-bit port D18 driven low D19 don’t care D18 driven l ow

Exte rnal boot device

with 16-bit port D18 driven high D19 driven low D18 driven high

Exte rnal boot device

with 32-bit port D18 driven high D19 driven high D18 driven high

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Chip Configuration Module (CCM)

Functional Description

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MOTOROLA Chip Configurat ion Module (CCM) 137

4.8.4 Outpu t Pad Strength Configuration

Output pad strength is determined during reset configuration as shown

in Table 4-11. See 23.7 DC Electrical Specifications for drive

capability fo r ea ch settin g. On ce re set is e xited, t he ou tput pad st reng th

confi guration ca n be change d by progr amming th e LOAD bit o f the C hip

Configuration Register .

4.8.5 Clock Mode Selection

The clock mode i s selected dur ing reset a nd reflected in the PL LMODE,

PLLSEL, and PLLREF bits of SYNSR. Once reset is exited, the clock

mode cannot be changed.

Table 4-12 summarizes clock mode selection during reset configuration.

Table 4-11. Output Pad Driver Strength Selection(1)

1. Modifying the default configurations is possible only if the external RCON pin is asser ted

low.

Optional Pi n Function Selection CC R Register LO AD Bit

Outp ut pads configured for default strength D21 driven low

Outp ut pads configured for full strength D21 driven high

Table 4-12. Clock Mode Selection(1)

Clock Mode Syn thesizer Statu s Register (SYNS R)

MODE Bit PL LSEL Bit PLLREF Bit

Exte rnal clock mode; PLL disab led PLLEN driven low D23 don’t care D22 don’t care

1:1 PLL mode PLLEN driven high D23 driven low D22 don’t care

Normal PLL mode; external clock reference PLLEN driven high D23 driven high D22 driven low

Nor m a l P L L mod e ; cr y sta l os c illator refere n c e PL LEN driv en h i g h D23 driv e n hig h D 22 d riv e n h igh

1. Modif ying the default configurati ons is possible only if the exter nal RCON pin is as serted low.

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138 Chip Configurat ion Module (CCM ) MOTOROLA

Chip Configuration Module (CCM)

4.8.6 Internal FLASH Configuration

The inter nal FLAS H in the M MC211 3 and M MC211 4 i s alw ays ena bled.

4.9 Reset

Rese t initial izes CC M reg i sters to a known sta rtup state as de scribed in

4. 7 Memory Ma p an d R eg ister s . T he CCM con trol s chip co nfigur ation

at reset as described in 4.8 Fun ctio na l Descript ion .

4.10 Interrupts

The CCM does not generate interrupt requests.

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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0  Advance Information
MOTOROLA Re set Controller Module  139
Advance Info rmation — MMC2114, MMC2113, and MMC2112
Section 5. Reset Controller Module
1  Contents
2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
4 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
5 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
5.1 RESET  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
5.2 RSTOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
6 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .142
6.1 Reset Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .143
6.2 Reset Status Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
7.1 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
7.1.1 Power-On Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
7.1.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
7.1.3 Watchdog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . .148
7.1.4 Loss of Clock Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .148
7.1.5 Loss of Lock Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
7.1.6 Software Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
7.1.7 LVD Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
7.2 Reset Control Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
7.2.1 Synchronous Reset Requests . . . . . . . . . . . . . . . . . . . .151
7.2.2 Internal Reset Request  . . . . . . . . . . . . . . . . . . . . . . . . .151
7.2.3 Power-On Reset/Low-V oltage Detect Reset . . . . . . . . .151
7.3 Concurrent Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
7.3.1 Reset Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
7.3.2 Reset Status Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
    
  
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140 Rese t Controller Module MOTOR OLA

Reset Controller Module

5.2 Overview

The reset controller is provided to determine the cause of reset, assert

the appropriate reset signals to the system, and then to keep a history of

what caused the reset. The power management CPU (PMM) control

registers that generate low-voltage detect (LVD) bits are implemented in

the reset module.

5.3 Features

Module features include:

•Six sources of reset:

–External

–Power- on reset (P OR )

–Watchdog timer

–Phase locked-loop (PLL) loss of lock

–PLL loss of clock

–Software

–LVD reset

•Software-assertable RSTOUT pin independent of chip reset state

•Software-readable status flags indicating the cause of the last

reset

•LVD control and status bits for setup and use of LV D reset or

interrupt

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Reset Controller Module

Block Diagram

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MOTOROLA Re set Controller Module 141

5.4 Block Diagram

Figure 5-1 illustrates the reset controller and PMM controller and is

explained in the following sections.

Figure 5-1. Reset Controller Block Diagram

5.5 Signals

Table 5-1 provides a summary of the reset controller signal properties.

The signals are descri bed in the following paragraphs.

POWER-ON

RESET

WATCHDOG

TIMER TIMEOUT

PLL

LOSS OF CLOCK

PLL

LOSS OF LOCK

SOFTWARE

RESET

LVD

DETECT

RESET

CONTROLLER

AND

PMM

CONTROLLER

RSOUT

TO INTERNAL RESETS

TO PMM HARD BLOCK

Table 5-1. Reset Controller Signal Properties

Name Direction Input

Hysteresis Input

Synchronization

RESET pin I Y Y(1)

1. RESET is always synchroni zed except when in low-power stop mo de.

RSTOUT pin O ——

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142 Rese t Controller Module MOTOR OLA

Reset Controller Module

5.5.1 RESET

Asserting the external RESET pin for at least four rising CLKOUT edges

causes the external reset request to be recognized and latched.

5.5.2 RSTOUT

This active-low output signal is driven low when the internal reset

controller module resets the chip. When RSTOUT is active, the user can

drive override options on the data bus.

5.6 Memory Map and Registers

The reset controller programming model consists of these registers:

•Reset Control Register (RCR) — selects r eset cont roller fun ctions

•Rese t Status Reg ister ( R SR) — re flects the state of the last re set

source

See Table 5-2 for the address map and the following paragraphs for a

descrip tion of the registers.

Table 5-2. Reset Cont ro ller Addre ss Map

Address Bits 7:0 Access(1)

1. S/U = supervisor or user mode access.

0x00c4_0000 RCR — Reset Control Register S/U

0x00c4_0001 RSR — Reset Status Register S/U

0x00c4_0002 Reserved(2) —

0x00c4_0003 Reserved(2)

2. Writ es to reserved addre ss locations have no effect and reads return 0s.

—

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Mem ory Map and Registers

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MOTOROLA Re set Controller Module 143

5.6.1 Reset Control Register

The Reset Control Register (RCR) allows software control for requesting

a reset, for independently asserting the external RSTOUT pin, and for

controlling low-voltage detect (LVD) functions.

SOFTRST — Software Reset Request

The SOFTRST bit allows software to request a reset. The reset

caused by setting this bit clears this bit.

1 = Softw are reset request

0 = No software reset request

FRCRSTOUT — Force RSTO UT Pin

The FRCRSTOUT bit allows software to assert or negate the external

RSTOUT pin.

1 = Assert RSTOUT pin

0 = Negate RSTOUT pin

CAUTION: External logic driving reset configuration data during reset needs to be

considered when asserting the RSTOUT pin when setting

FRCRSTOUT.

Address: 0x00c4_0000

Bit 7654321Bit 0

Read: SOFTRST FRCR-

STOUT 0LVDF LVDIE LVDRE LVDSE LVDE

Write:

Reset:000 See note0111

Note: Reset dependent

= Writes have no effect and terminate without transfer error exception.

Figure 5-2. Reset Control Register (RCR)

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Reset Controller Module

LVDF — LVD Flag

The LVDF bit indicates the low-voltage detect status if LVDE is set.

Write a 1 to clear the LVDF bit.

1 = Low voltage has been detected

0 = Low voltage has not been detected

NOTE: The setting of this flag causes an LVD interrupt if LVDE and LVDIE bits

are set and LVDRE is cleared when the supply voltage VDD drops below

VDD (minimum). The vector for this interrupt is shared with INT0 of the

EPORT module. Interrupt arbitration in the interrupt service routine is

necessary if both of these interrupts are enabled.

LVDIE — LVD Interrupt Enable

The LVDIE bit controls the LVD interrupt if LVDE is set. This bit has

no effect if the LVDE bit is a logic 0.

1 = LVD interrupt enabled

0 = LVD interrupt disabled

LVDRE — LVD Reset Enable

The LV DRE bit contro ls the LVD reset if LVDE is set. This bit has no

effect if the LVDE bit is a logic 0. LVD reset has priority over LVD

interrupt, if both are enabled.

1 = LVD reset enabled

0 = LVD reset disabled

LVDSE — LVD Stop E nable

The LV DSE bit con t rols the behavior of the LV D w hen th e MCU stop

mode is entered if LVDE is set. This bit has no effect if the LVDE bit

is a logic 0.

1 = LVD enabled in MCU stop mode

0 = LVD disabled in MCU stop mode

LVDE — LVD Enable

The LVDE bit controls whether the LVD is enabled.

1 = LVD is enabled

0 = LVD is disabled

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Mem ory Map and Registers

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MOTOROLA Re set Controller Module 145

5.6.2 Reset Status Register

The Reset Status Register (RS R) contains a status bit for every reset

source. When reset is entered, the cause of the reset condition is latched

alo ng with a valu e of 0 for the o ther reset sou rces that were not pending

at the time of the reset condition. These values are then reflected in

RSR. One or more status bits may be set at the same time. The cause

of any subsequent reset is also re corded in the register, overwriting

statu s from the previous reset conditi on.

RSR can be read at any time. Writing to RSR has no effect.

LVD — Low-Voltage Detect

This bit indicates that the last reset state was caused by an LVD reset.

1 = Last reset state was caused by an LVD reset

0 = Last reset state was not caused by an LVD reset

SOFT — Software Reset Flag

SOFT indicates that the last reset was caused by software.

1 = Last reset caused by software

0 = Last reset not caused by software

WDR — Watchdog Timer Reset Flag

WDR indicates that the last reset was caused by a watchdog timer

timeout.

1 = Last reset caused by watchdog timer timeout

0 = Last reset not caused by watchdog timer timeout

Address: 0x00c4_0001

Bit 7654321Bit 0

Read: 0 LVD SOFT WDR POR EXT LOC LOL

Write:

Reset: 0 Reset dependent

= Writes have no effect and terminate without transfer error exception.

Figure 5-3. Reset Status Register (RSR)

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Reset Controller Module

POR — Power-On Reset Flag

POR indicates that the last reset was caused by a power-on reset.

1 = Last reset caused by power-on reset

0 = Last reset not caused by power-on reset

EXT — External Reset Flag

EXT indicates that the last reset was caused by an external device

asserting the external RESET pin.

1 = Last reset state caused by external reset

0 = Last reset not caused by external reset

LOC — Loss of Clock Reset Flag

LOC indicates that the last reset state was caused by a PLL los of

clock.

1 = La st reset caused by loss of clock

0 = Last reset not caused by loss of clock

LOL — Loss of Lock Reset Flag

LOL indicates that the last reset state was caused by a PLL loss of

lock.

1 = La st reset caused by a loss of lock

0 = Last reset not caused by loss of lock

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Functional Description

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MOTOROLA Re set Controller Module 147

5.7 Functional Des cription

5.7.1 Reset Sources

Table 5-3 defines the sources of reset and the signals driven by the reset

controller.

To protect data integrity, a synchronous reset source is not acted upon

by the reset contr ol logic until the end of the current bus cycle. Reset is

then asser ted on the next r ising edge of the system clock after the cycle

is terminated. Whenever the reset control logic must synchronize reset

to the end of the bus cycle, the internal bus monitor is autom atically

enabled regardless of the BME bit state in the chip configuration module

CCR register. Then, if the current bus cycle is not terminated normally

the bus monitor terminates the cycle based on the length of time

programmed in the BMT field of the CCR register.

Internal single-byte, half-word, or word writes are guaranteed to

complete without data corruption when a synchronous reset occurs.

External writes, including word writes to 16-bit ports, are also

guaranteed to compl ete.

Asynchronous reset sources usually indicate a catastrophic failure.

There fore , the reset contr ol logic do es not wait for the curr ent bu s cycle

to complete. Reset is asserted immediately to the system.

Table 5-3. Reset Source Summary

Source Type

Power on As yn chr o nous

Ex te r n a l RESET pin (not stop mode) Synchro nous

Ex te r n a l RESET pin (during stop mode) Asynchronous

Watchdog timer Synchronous

Loss of clock Asynchronous

Loss of lock Asyn ch ro nous

Software Synchronous

LVD reset Asynchronous

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Reset Controller Module

5.7.1.1 Power-On Reset

At power up, the reset controller asserts RSTOUT. RSTOUT continues

to be asserted until VDD has reached a minimum acceptable level and,

if PLL clock mode is selected, until the PLL achieves phase lock. Then

after approximately another 512 cycles, RSTOUT is negated and the

part begins operation.

5.7.1.2 External Reset

Asserting the external RESET pin for at least four rising CLKOUT edges

causes the external reset request to be recognized and latched. The bus

monitor is enabled and the current bus cycle is completed. The reset

controller asserts RSTOUT for approximately 512 cycles after the

RESET pin is negated and the PLL has acquired lock. The part then exits

reset and begins operation.

In low-power stop mode, the system clocks are stopped. Asserting the

external RESET pin in stop mode causes an external reset to be

recognized.

5.7.1.3 Watchdog Timer Reset

A watchdog timer timeout causes timer reset request to be recognized

and latched. The bus monitor is enabled and the current bus cycle is

completed . If th e RESET pin i s ne gated and the P LL has acq uired lock,

the reset controller asserts RSTOUT for approximately 51 2 cycles. Then

the part exits reset and begins operation.

5.7.1.4 Loss of Clock Reset

This reset condition occurs in PLL clock mode when the LOCRE bit in

the SYNCR register is se t and eithe r the PLL reference or the PLL fails.

The reset controller asserts RSTOUT for approximately 512 cycles after

the PLL has acquired lock. The part then exits reset and begins

operation.

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5.7.1.5 Loss of Lock Reset

This reset condition occurs in PLL clock mode when the LOLRE bit in the

SYNCR register is set and the PLL loses lock. The reset controller

asserts RSTOUT for approximately 512 cycl es after the PLL has

acquired lock. The part then exits reset and resumes operation.

5. 7.1.6 Softw are Reset

A software reset o ccurs the SOFTRST bit is set. If the RESET pin is

negated and the PLL has acquired lo ck, the reset controller asserts

RSTOUT for approximately 512 cycles. Then the part exits reset and

resumes operation.

5. 7.1.7 LVD Reset

The LVD reset will occur when the supply input voltage drops below VDD

(minimum).

5.7.2 Reset Control Flow

The reset logic control flow is shown in Figure 5-4. In this figure, the

control state boxes have been numbered, and these numbers are

referred to (within parentheses) in the flow description that follows. All

cycle counts given are approximate.

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150 Rese t Controller Module MOTOR OLA

Reset Controller Module

Fi gure 5-4. Re set Cont ro l Flow

RESET

PIN OR WD TIM EOU T

OR SW RESET?

LOSS OF CLOCK?

LOSS OF LOCK?

RESET NE GAT E D?

PLL MODE?

BU S C YCL E

COMPLETE?

RCON ASSERTED?

PLL LOCKED?

ENABLE BUS MONITOR

ASSERT RST OU T AND

LATCH RESET STATUS

WAIT 5 12 CLKOUT CYCLES

LATCH CO NFIGURATION

NEGAT E RSTO UT

POR OR LVD

ASSER T R STO UT AN D

LATCH RESET STATUS

11A

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5.7.2.1 Synchronous Reset Requests

In this discussion, the reference in parentheses refe r to the state

numbers in Figure 5-4. All cycle counts given are approximate.

If eit her th e exter nal RESE T pin is asse rted b y an external device fo r at

lea st fou r r ising CLK OUT edg es ( 3), or the watchdog timer times ou t, or

software requests a reset, the reset control logic latches the reset

request internally and enables the bus monitor (5). When the current bus

cycle is completed (6), RSTOUT is asserted (7). The reset control logic

waits until the RESET pin is negated (8) and for the PLL to attain lock

(9, 9A) before waiting 512 CLKOUT cycles (1).The reset control logic

may latch the configuration according to the RCON pin level (11, 11A)

before negating RSTOUT (12).

If the external RESET pin is asserted by an external device for at least

four ri sing CLKOUT edges during the 512 count (10) or during the wait

for P LL lock (9 A), the re set flow swit ches to (8 ) and waits for the RES ET

pin to be negated before continuing.

5.7.2.2 Internal Reset Request

If reset is asserted by an asynchronous internal reset source, such as

loss of clock (1) or loss of lock (2), the reset control logic asserts

RSTOUT (4). The reset control logic waits for the PLL to attain lock

(9, 9A) before waiting 512 CLKOUT cycles (1). Then the r e set control

logic may latch the configuration according to the RCON pin level (11,

11A) before negating RSTOUT (12).

If loss of lock occurs during the 512 count (10), the reset flow switches

to (9A) and waits for the PLL to lock before continuing.

5.7.2.3 Power-On Reset/Low-Voltage Detect Reset

When the reset sequence is initiated by power-on reset (0), the same

reset sequ ence is followed as for the other asynchr onous reset sources.

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152 Rese t Controller Module MOTOR OLA

Reset Controller Module

5.7.3 Concurrent Resets

This section describes the concurrent resets. As in the previous

discussion references in parentheses refer to the state numbers in

Figure 5-4.

5.7.3.1 Reset Flow

If a power-on reset or low-voltage detect condition is detected during any

reset sequence, the reset sequence starts immediately (0).

If the external RESET pin is asserted for at least four rising CLKOUT

edges while waiting for PLL lock or the 512 cycles, the exter nal reset is

recognized. Reset processing switches to wait for the external RESET

pin to negate (8).

If a l oss of clock or loss of lock condition is detected while wa iting fo r the

current bus cycle to complete (5, 6) for an external reset request, the

cycle is terminated. The reset status bits are latched (7) and reset

processing waits for the external RESET pin to negate (8).

If a loss of clock or loss of lock condition is detected during the 512 cycle

wait, the reset sequence continues after a PLL lock (9, 9A).

5.7.3.2 Reset Status Flags

For a POR r eset, the POR and LVD bits in the R SR regi ster are se t, and

the SOFT, WDR, EXT, LOC, and LOL bits are cleared even if another

type of reset condition is detected during the reset sequence for the

POR.

If a l oss of clock or loss of lock condition is detected while wa iting fo r the

current bus cycle to complete (5, 6) for an external reset request, the

EXT, SOFT, and/or WDR bits along with the LOC and/or LOL bits are

set.

If the RSR bits are latched (7) during the EXT, SOFT, and/or WDR reset

sequence with n o ot her reset conditions d etected , on ly the EXT, S OFT ,

and/or W DR bits are set.

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If the RSR bits are latched (4) during the internal reset sequence with the

RESET pin not asserted and no SOFT or WDR event, then the LOC

and/or LOL bits are the only bits set.

For a LVD reset, the LVD bit in the Reset Status Register (RSR) is set,

and the SOFT, WDR, EXT, LOC, and LOL bits are cl eared to 0 even if

another type of reset condition is detected during the reset sequence for

LVD.

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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0  Advance Information
MOTOROLA Power Management  155
Advance Info rmation — MMC2114, MMC2113, and MMC2112
Section 6. Power Management
1  Contents
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
3.1 Run Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
3.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
3.3 Doze Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
3.4 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
3.5 Peripheral Shut Down  . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
4 Peripheral Behavior in Low-Power Modes . . . . . . . . . . . . . . .158
4.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
4.2 Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
4.3 OnCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
4.4 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
4.5 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
4.6 Edge Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
4.7 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . .160
4.8 FLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
4.9 Queued Analog-to-Digital Converter (QADC)  . . . . . . . . . .161
4.10 Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
4.11 Programmable Interrupt Timers (PIT1 and PIT2). . . . . . . .162
4.12 Serial Peripheral Interface (SPI). . . . . . . . . . . . . . . . . . . . .162
4.13 Serial Communication Interfaces (SCI1 and SCI2) . . . . . .162
4.14 Timers (TIM1 and TIM2). . . . . . . . . . . . . . . . . . . . . . . . . . .163
5 Summary of Peripheral State During Low-Power Modes. . . .163
    
  
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6.2 Introduc tion

The following features support low power operation.

•Four modes of operation:

–Run

–Wait

–Doze

–Stop

•Ability to shut down most peripher als independently

•Ability to shut down the external CLKOUT pin

6.3 Low-Power Modes

The system enters a low-power mode by ex ecution of a STOP, WAIT, or

DOZE instruction.This idles the CPU with no cycles active. An internal

signal indicates to the system and clock controller to power down and

stop the clocks appropriately. During stop mode, the system clock is

stopped lo w.

A wakeup event is required to exit a low-power mode and return to run

mode. Wakeup events consist of any of these conditions:

•Any type of reset

•Assertion of the DE pin to request entry into debug mode

•Debug request bit set in the OnCE Control Register to request

entry into debug mode

•Any valid i nterrupt request

6.3.1 Run Mode

Run mode is the normal system operating mode. Current consumption

in this mode is related directly to the system clock frequency.

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6.3.2 Wait Mode

Wait mode is intended to be used to stop only the CPU and memory

clocks until a wakeup event is detected. In this mode, peripherals may

be programmed to continue operating and can generate interrupts,

which cause the CPU to exit from wait mode.

6.3.3 Doze Mode

Doze mode affects the CPU in the same manner as wait mode, except

that each peripheral defines individual operational characteristics in

doze mode. Peripherals which continue to run and have the capability of

producing in terrupts may cause the CPU to exit the doze mode and

return to run mode. Peripherals which are stopped will restart operation

on exit from doze mode as defined for each peripheral.

6.3.4 Stop Mode

Stop mode affects the CPU in the same manner as the wait and doze

modes, except that all clocks to the system are stopped and the

peripherals cease operation.

Stop mode must be entered in a controlled manner to ensure that any

curren t ope rati on is pro perl y term inated. W hen e xi ting sto p mo de, m ost

peripherals retain their pre-stop status and resume operation.

The fo llowing subse ctions spe cify the opera tion of each module while in

and when exiting low-power modes.

6.3.5 Peripheral Shut Down

Most peri phera ls may be disabled by software in ord er to cease interna l

clock generation and remain in a static state. Each peripheral has its own

specific disabling sequence (refer to each peripheral description for

further details). A peripheral may be disabled at any time and will remain

disabled during any low-power mode of operation.

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6.4 Peripheral Behavior in Low-Power Modes

6.4.1 Reset

A power-on reset (POR) will always cause a chip reset and exit from any

low-power mode.

In wait and doze modes, asserting the external RESET pin for at least

four clocks will cause an external reset that will reset the chip and exit

any low-power modes.

In stop m ode, the R ESET pin synch roni zat ion is di sab led and asser ting

the external RESET pin will asynchronously generate an internal reset

and exit any low-power modes. Registers will loose current values and

must be reconfigured from reset state if needed.

If the phase lock loop (PLL) is active, then any loss of clock or loss of

lock will reset the chip and exit any low-power modes.

If the watchdog timer is still enabled during wait or doze modes, then a

watchdog timer timeout may generate a reset to exit these low-power

modes.

When the CPU is in active, a software reset can not be gener ated to exit

any low-power mode.

6.4.2 Clocks

During the low power wait and doze modes, the clocks to the CPU,

FLASH, and random-access memory (RAM) will be stopped and the

system clo cks to the p eripherals are enabled. Each module may disable

the module clocks locally at the module level. During the low-power stop

mode, all clocks to the system will be stopped.

During stop mode, there are several options for enabling/disabling the

PLL and/or crystal oscillator (OSC) compromising between wakeup

recovery time and stop mode power. The PLL may be disabled during

stop. A wakeup time of up to 200 µs is required for the PLL to re-lock.

The OSC may also be disabled during STOP. A wakeup time required

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for the OSC to restart is dependent upon the startup time of the crystal

used. Power consumption can be reduced in stop mode by disabling

either or both of these functions via the STMPD bits of the Synthesizer

Control Register (SYNCR). See 11.7.2.1 S ynt hes izer Contro l

The exter nal CL KOUT sig nal may be enab led during low- power stop (if

the PLL is still enabled) to support systems using this signal as the clock

source.

The system clocks may be enabled during wakeup from stop mode

witho ut waiting for th e PLL to lock. This el iminates the wakeup re covery

time, but at the risk of sending a potentially unstable clock to the system.

It is reco mme nded, if this opt ion i s used, that th e PLL frequency di vider

is set so that the targeted system frequency is no more than half the

maximum allowed. This will allow for any frequency overshoot of the PLL

while still keeping the system clock within specification.

In external clock mode, there are no wait times for the OSC startup or

PLL lock.

During wakeup from stop mode, the FLASH clock will always clock

throug h 16 cycle s before the system clocks are enabled. This allows the

FLASH module time to recover from the low-power mode. Thus,

software may immediately continue to fetch instructions from the FLASH

memory.

The external CLKOUT output pin may be disabled in the lo w state to

lower power consumption via the disable CLKOUT (DISCLK) bit in the

SYNCR. The external CLKOUT pin function is enabled by default at

reset.

6.4.3 OnCE

The OnCE logic is clocked using the TCLK input and is not affected by

the syste m clo ck. E nter ing debug mo de via th e On CE port (o r asserting

the external DE pin) will cause the CP U to exit any low-power mode.

Toggling TCLK during any low- power mode will increase the system

current consumption.

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6.4.4 JTAG

The JT AG (Joint Te st Act ion Grou p) control ler logic i s clocked using the

TCLK input and is not affected by the system clock. The JTAG cannot

generate an event to cause the CPU to exit any lo w-power mode.

Toggling TCLK during any low- power mode will increase the system

current consumption.

6.4.5 Interrupt Controller

The interrupt controller is not affected by any of the low-power modes.

All logic between the input sources and generating the interrupt to the

M•CORE processor will be combinational to allow the ability to wakeup

the CP U processor dur ing low-power stop mode whe n all system clocks

are stopped.

A fast interrupt request will cause the CPU to exit a low-power mode only

if the FE b it in the CPU’s PSR re gister i s set. A no rma l inter rupt requ est

will cause the CPU to exit a low-power mode only if th e IE and EE bits in

the CPU’s PSR register are set.

6.4.6 Edge Po rt

In wait and doze modes, the edge port continues to operate normally and

may be configured to generate interrupts (either an edge transition or

low level on an external pin) to exit the low-power modes.

In stop mode, there are no clocks available to perform the edge detect

function. Thus, only the level detect logic is active (if conf igured) to allow

any low level on the external interrupt pin to generate an interrupt (if

enabled) to exit the stop mode.

6.4.7 Random -Access Memory (RAM)

The random-access memory (RAM) is disabled during any low-power

mode. No recovery time is required when exiting any low-power mode.

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6.4.8 FLASH

The FLASH is in a low-power state if not being accessed. No recovery

time is required after exit from any low-power mode.

6.4.9 Queued Analog-to-Digital Converter (QADC)

Setting the queued analog-to-digital converter (QADC) STOP bit

(QSTOP) will disable the QADC.

The QA DC is unaff ected by either wait or d oze mode an d may gener ate

an in terrupt to exit these modes.

Low- power stop mode (or setting the QSTOP bit), immediately freezes

operat ion, register values, state machines, and external pins. This stops

the clock signals to the digital electronics of the module and eliminates

the quiescent current draw of the analog electronics. Any conversion

sequence s in progr ess are stopped . Exit fr om low-p ow er stop mode (or

clearing the QSTOP bit), returns the QADC to operation from the state

pri or to stop mode entry, but any con version s in progre ss a re undefined

and the QADC requires recovery time (tSR in 23.9 QADC Electrical

Characteristics) to stabilize the analog circuits before new conversions

can be pe rformed.

6.4.10 Watchdog Timer

In stop mode (or in wait/doze mode, if so programmed), the watchdog

ceases operation and freezes at the current value.When exiting these

modes, the watchdog resumes operation from the stopped value. It is

the responsibility of software to avoid erroneous operation.

When not stopped, the watchdog may generate a reset to exit the

low-power modes.

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6.4.11 Programmable Interrupt Timers (PIT1 and PIT2)

In stop mode (or in doze mode, if so programmed), the programmable

inte rru pt time r (P IT ) cea ses ope ration, and freeze s at the curr ent va lue.

When exiting these modes, the PIT resumes operation from the stopped

value. It is the responsibility of software to avoid erroneous operation.

When not stopped, the PIT may generate an interrupt to exit the

low-power modes.

6.4.12 Serial Peripheral Interface (SPI)

When not stopped, the serial peripheral interface (SPI) may generate an

interrupt to exit the low-power modes.

•Clearing the SPI enable bit (SPE) disables the SPI function.

•The SPI is unaffected by wait mode and may generate an interrupt

to exit this mode.

SPI operation in doze mode is programmable. Depending on the state of

internal bits, the S PI can operate normally when the CPU is in doze

mode or the S PI clock gener ation can be turned off and the SPI modu le

enters a power conservation state during doze mode. During doze

mode, any master transmission in progress stops. Reception and

transmission of a byte as slave continues so that the slave is

synchronized to the master.

The SPI is inactive in stop mode for reduced power consumption.

6.4.13 Serial Communication Interfaces (SCI1 and SCI2)

When not stopped, the serial communications interface (SCI) may

generate an interrupt to exit the low-power modes.

•Clearing the transmit enable bit (TE) or the receiver enable bit

(RE) disables SCI functions.

•The SCIs are unaffected by wait mode and may generate an

interrupt to exit this mode.

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In stop mode (or doze mode, if so programmed), the SCIs stop

immedi ately and freeze the ir operat ion, r egister values, state machin es,

and external pins. During these modes, the SCI clocks are shut down.

Coming out of the doze or stop modes, returns the SCIs to operation

from the state prior to the low-power mode entry.

6.4.14 Timers (TIM1 and TIM2)

When not stopped, the timers may generate an interrupt to exit the

low-power modes.

Clearing the timer enable bit (TE) in the Timer System Control Register 1

(TIMSCR1) or the pulse accumulator enable bit (PAE) in the Pulse

Accumulator Control Register (TIMPACTL) disables timer functions.

Timer and pulse accumulator registers are still accessible by the CPU

and OnCE interface, but the remaining functions of the timer are

disabled. See 16.7.6 Timer System Control Register 1 and 16.7.15

Pulse Accumulator Control Register.

The timer is unaffected by either the wait or doze modes and may

generate an in terrupt to exit these modes.

In stop mode, the timers stop immediately and freeze their operation,

mode, the timer will resume operation unless stop mode was exited by

reset.

6.5 Summary of Peripheral State During Low-Power Modes

The funct io nality of each of the per i pher als and CPU du ring the vari ous

low-power modes is summarized in Tabl e 6-1. The status of each

peripheral during a given mode refers to the condition the peripheral

automa tically assumes when the parti cular i nstruction (WA IT, DO ZE, or

STOP) is executed. Indi vidual peripherals may be disabled by

programming its dedicated control bits. The wakeup capability field

refers to the ability o f an interr upt or r eset by that periphera l to force t he

CPU into run mode.

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Table 6-1. CPU and Peripherals in Low-Power Modes

Module Periphe ral Status(1) / Wakeup C apabi li t y

Ru n Mode Wait Mode D oz e Mod e Stop Mod e

CPU Enabled Stopped No Stopped No Stopped No

Reset Enabled Enabled Yes(2) Enabled Yes(2) Enabled Yes(2)

Clock Enabled Enabled Yes(2) Enabled Yes(2) Program Yes(2)

OnCE Enabled Enabled Yes(3) Enabled Yes(3) Enabled Yes(3)

JTAG Enabled Enabled No Enabled No Enabled No

Interrupt controller Enabled Enabled Yes(4) Enabled Yes(4) Enabled Yes(4)

Edge port Ena bled Enable d Yes(4) Enabled Yes(4) Stopped Yes(4)

RAM Enabled Stopped No Stopped No Stopped No

FLASH Enabled Stopped No Stopped No Stopped No

QADC Enabled Enabled Yes(4) Enabled Yes(4) Stopped No

Watchdog timer Enabled Program Yes(2) Program Yes(2) Stopped No

PIT1 and PIT2 Enabled Enabled Yes(4) Program Yes(4) Stopped No

SPI Enabled Enabled Yes(4) Program Yes(4) Stopped No

SCI1 and SCI2 Enabled Enable d Yes(4) Program Yes(4) Stopped No

TIM1 and TIM2 Enabled Enabled Yes(4) Enabled Yes(4) Stopped No

1. “Program” Indicates that the per ipheral funct ion during the low-power mode is dependent on programm able bits in the

peripheral register map.

2. These modules can generate a reset which will exit any low-power mode.

3. The OnCE lo gic i s clock ed by a separat e TCL K clock. Enteri ng debug mode vi a the O nCE port (or as serti on of t he e xternal

DE pin) exits any l ow-power mode. Upon exit from debug mode, t he previous low-power mode wil l be re-entered and the

changes made during debug mode will remain in effect.

4. These modules can generate a interrupt which will exit any low-power mode. The CPU will begin to service the interrupt

exception after wakeup.

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MOTOROLA M•CORE M210 Central Processor Unit (CPU) 165

Advance Info rmation — MMC2114, MMC2113, and MMC2112

Section 7. M•CORE M210 Central Processor Unit (CPU)

7.1 Contents

7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

7.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

7.4 Microarchitecture Summary . . . . . . . . . . . . . . . . . . . . . . . . . .167

7.5 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

7.6 Data Format Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

7.7 Operand Addressing Capabilities. . . . . . . . . . . . . . . . . . . . . .172

7.8 Instruction Set Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .172

7.2 Introduc tion

The M•CORE M210 central processor unit (CPU) architecture is one of

the most compact, full 32-bit core implementations available. The

pipelined reduced instruction set computer (RISC) execution unit uses

16-bit instructions to achieve maximum speed and code efficiency, while

conserving on-chip memory resources. The instruction set is designed

to suppor t high-le vel language i mplementat ion. A non-i ntrusive re sident

debuggi ng system supports product development and in-situ testing.

Total system power consumption is determined by all the system

components, rather than the CPU alone. In particular, memory power

consumption (both on-chip and external) is a dominant factor in total

power consumption of the CPU plus memory subsystem . With this in

mind, th e C PU instr uction set ar chitectu re t rade s abso lu te p erfor man ce

capability for reduced total energy consumption. This is accomplished

while maintaining a high level of performance at a given clock frequency.

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M•CORE M210 Central Processor Unit (CPU)

A strictly defined load/store architecture minimizes control complexity.

Use of a fixed, 16-bit instruction encoding significantly lowers the

memory bandwidth needed to sustain a high rate of in struction

execution, and careful selection of the instruction set allows the code

density and overall memory efficiency of the CPU architecture to

surpass t hose of comp lex instruction set comp uter (CISC) ar chitectures.

These factor s re duce system ener gy con sumption signif icantly, a nd th e

fully static CPU design uses other techniques to reduce power

cons umption even more . The CPU uses dynam ic clock mana gement to

automatically power-down internal functions that are not in use on a

clock-by-clock basis. It also incorporates three power-conservation

operating modes, which are invoked via dedicated instructions as

detailed in Section 6. Power Management.

7.3 Features

The main features of the CPU are:

•32-bit load/store RISC architecture

•Fixed 16-bit instruction length

•13 entry, 32-bit control register file

•16 entry, 32-bit general-purpose register file

•Efficient 4-stage execution pipeline

•Single-cycle execution for most instructions, 2-cycle branches and

memory accesses

•Support for byte/half-word/word memory access

•Fast interrupt support

•Availability of alternate general purpose register file

•Vectored and autovectored inte rrupt support

•On-chip emulation support (OnCE)

•Full static design for minimal power consumption

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Microarchitecture Summary

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MOTOROLA M•CORE M210 Central Processor Unit (CPU) 167

7.4 Microarchitecture Summary

Figure 7-1 is a block diagram of the M•CORE processor.

The processor utilizes a 4-stage pipeline for instruction execution. The

instruction fetch, instruction decode/register file read, execute, and

regi ster file writeb ack stages oper ate in an over lapped fashi on, allow ing

single clock instruction execution for most instru ctions.

The execution unit consists of a 32-bit arithmetic/logic unit (ALU), a

32-bit barrel shifter, a find-first-one unit, result feed-forward hardware,

support hardware for multiplication and division, and multiple-register

load and store instructions.

Figure 7-1. M•CORE Processor Block Diagram

SCALE

ADDRESS GENERATION

ADDRESS MUX

GENERAL-PURPOSE

32 BITS X 16

ALTERNATE

REG IST ER FILE

32 BITS X 16

CONTROL

32 BITS X 13

IMMEDIATE

MUX

SIGN EXT.

MUX

BARREL SHIFTER

MULTIPLIER

DIVIDER

AD DER/L O GICA L P RIORITY E NCODER/

ZER O DETE CT RES UL T MUX

DATA CALCU LATI ON

INCREMENT BRANCH

ADDER

INSTRUCTION PIPELINE

INS TRUCTION DECO DE

ADDRESS

BUS

DATA

X PORT Y PORT

MUX

WRITE BAC K BU S

H/W ACCELERATOR INTERFACE BUS BUS

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M•CORE M210 Central Processor Unit (CPU)

Arithmetic and logical operations are executed in a single cycle.

Multiplication is implemented with a 2-bit per clock, overlapped-scan,

modified Bo oth algorithm with early-out capability, to reduce execution

time for operations with small multipliers. Divide is implemented with a

1-bi t per clock ear ly-in al gorith m. The find-fi rst-one uni t op erate s in one

clock cycle.

The program counter unit incorporates a dedicated branch address

adder to minimize delays during change of flow operations. Branch

target addresses are calculated in parallel with branch instruction

decode. Taken bran ches and jumps require only two clocks; branches

which are not taken execute in one clock cycle.

Memory load and store operations are provided for 8-bit (byte), 16-bit

(halfword), and 32-bit (word) data, with automatic zero extension for byte

and ha lf-wor d load ope rations. T hese i nstructions ca n execute in as few

as two clock cycles. Load and store multiple register instructions allow

low overhead context save and restore operations. These instructions

can execut e in (N+1 ) clock cycles, where N is the number of registers to

transfer.

A conditi o n code/ carry ( C) bit i s pr ovided fo r cond i tion testing or for use

in imp lemen ti ng arith metic and log ical opera ti ons with oper ands/ resul ts

greate r than 32 bits. The C bit is typically set by explicit test /compa rison

operations, not as a side-effect of normal instruction operation.

Exceptions to this rule occur for specialized operations where it is

desirable to combine cond ition setting with actual computation.

The processor uses autovectors for both normal and fast interrupt

requests. Fast interrupts take precedence over normal interrupts. Both

types ha ve de di cated exceptio n sha dow r egi sters. F or se rvic e requests

of either kind, an automatic vector is generated when the request is

made.

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Programming Model

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7.5 Pro gramming Model

Figure 7-2 shows the M •CORE processor programming model. The

model is define d di ffer ently for superviso r and use r priv ileg e mode s. By

conv ention, in both mod es R15 ser ves as the link r egister for sub routine

calls. R0 is typically used as the stack pointer.

Figure 7-2. Programming Model

The user programming model consists of 16 general-purpose 32-bit

registers (R0–R15), the 32-bit PC, and the C bit. The C bit is

imp lemen ted a s bi t 0 o f the Processor S tatus Reg ister ( PSR ) and is the

only portion of the PSR accessible in the user model.

R0’

R12

R13

R14

R15

R11

R10

US ER PROGRAMMER ’S

MODEL

ALTER NATE FILE

SUPERV ISOR PROGRAMM E R’S

MODEL

PC PC

* BIT 0 OF PSR

PSR

VBR

EPSR

FPSR

EPC

FPC

SS0

SS1

SS2

CR0

CR1

CR2

CR3

CR4

CR5

CR6

CR7

CR8

CR9

SS4 CR10

GCR CR11

SS3

GSR CR12

R15

R12

R13

R14

R11

R10

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M•CORE M210 Central Processor Unit (CPU)

The supervisor programming model consists of the user model plus 16

additional 32-bit general-purpose registers (R0–R15), called the

alternate file and a set of status/control registers (CR0–CR12) which

includ es the entir e PSR. Se tting the S bit in the PSR en ables superviso r

mode operation.

The alternate file allows very low over head context switching for

real-time event handling. While the alternate file is enabled,

general-purpose registers are accessed from it.

The Vector Base Register (VBR) determines the base address of the

excepti on vector ta ble. E xcep tion s hadow reg isters EPC a nd E P SR are

used to save the states of the program counter and PSR, respectively,

when an exception occurs. Shadow registers FPC and FPSR save the

states of the program counter and PSR, respectively, when a fast

interrupt exception occurs.

Five scratch registers (SS 0–SS4) are used to h andl e e xception e vents.

The global control (GCR) and status (GSR) registers can be used for a

variety of system monitoring tasks at the discretion of the compiler used.

They serve no specific function by or for the CPU.

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M•CO RE M210 Central Processor Unit (CPU)

Data Format Summary

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7.6 Data Format Summa ry

The operand data formats supported by the integer unit are standard

two’s-complement data formats. The operand size for each instruction is

either explicitly encoded in the instruction (load/store instructions) or

implicitly defined by the instruction operation (index operations, byte

extraction). Typically, instructions operate on all 32 bits of the source

operand(s) and generate a 32-bit result.

Memory is viewed from a big-endian byte ordering perspective. The

most significant byte (byte 0) of word 0 is located at address 0. Bits are

numbered within a word starting with bit 31 as the most significant bit.

Figure 7-3. Data Organization in Memo ry

Figure 7-4. Data Organization in Registers

BYTE 0 BYTE 1 BYTE 2 BYTE 3 WORD AT 0x 0000 000 0

31 0

BYTE 4 BYTE 5 BYTE 6 BYTE 7 WORD AT 0x0000 000 4

BYTE 8 BYTE 9 BYTE A BYTE B W OR D AT 0x0000 000 8

BYTE C BYTE D BYTE E BYTE F WORD AT 0x 0000 000 C

BYTE SIGNED BYTE

S S S S SS SSSSSSSSSSSSSSS S S S

8 7

BYTE U NSIGNE D B Y TE

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

8 7

HALF-WORD SIGNED

S S S S S S S S S S S S S S S S

016 1531

HALF-WORD

HALF-WORD UNSIGNED

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

016 1531

HALF-WORD

WORD

BYTE 3 BYTE 2 BYTE 1 BYTE 0

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M•CORE M210 Central Processor Unit (CPU)

7.7 Operand Addressing Capabilities

The M•CORE processor accesses all memory operands through load

and store instructions, transferring data between the general-purpose

registers and memory. Register-plus-four-bit scaled displacement

addressing mode is used for load and store instructions addressing byte,

half-word, and word data.

Load and store multiple instructions allow a subset of the 16

general-purpose registers to be transferred to or from a base address

poin ted to by register R0 (the default stack pointer by convention).

Load and store register quadrant instructions use register indirect

addressing to transfer a register quadrant to or from memory.

7.8 Instructio n Set Overview

The instruction set is tailored to support high-level languages and is

optimized for those instructions most commonly executed. A standard

set of arithmetic and logical instructions is provided, as well as

instruction support for bit operations, byte extraction, data movement,

control flow modification, and a small set of conditionally executed

instructions which can be useful in elim inating short conditional

branches.

Table 7-1 is an alphabetized listing of the M•CORE instruction set. Refer

to the M•CORE Reference Manual (Motorola document order number

MCORERM/AD) for more details on instruction operation.

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In stru ction Set Overv iew

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MOTOROLA M•CORE M210 Central Processor Unit (CPU) 173

Table 7-1. M•CORE Instruction Set (Sheet 1 of 3)

Mnemonic Description Execution Time

(Cycles)

ABS

ADDC

ADDI

ADDU

AND

ANDI

ANDN

ASR

ASRC

Absolute V alue

Add with C Bit

Add Immediate

Add Unsigned

Logical AND

Logical AND Immediate

AND NOT

Arithmetic Shift Right

Arithmetic Shift Right, Update C Bit

BCLRI

BGENI

BGENR

BKPT

BMASKI

BREV

BSETI

BSR

BTSTI

Bit Clear Im media te

Branch on Condition False

Bit Generate Immedi ate

Bit Generate Register

Breakpoint

Bi t Mask Imme d i ate

Branch

Bi t R e vers e

Bi t Se t Imme di ate

Bra nch to Subroutine

Branch on Condition True

Bit Test Immediate

1/2(1)

Indet(2)

1/2(1)

CLRF

CLRT

CMPHS

CMPLT

CMPLTI

CMPNE

CMPNEI

Clear Register on Condition False

Clear Register on Condition Tr ue

Compare Higher or Same

Compare Less Than

Compare Less Than Immediate

Compare Not Equal

Compare Not Equal Immedia te

DECF

DECGT

DECLT

DECNE

DECT

DIVS

DIVU

DOZE

Decrement on Condition False

Decrement Register and Set Condition if Result Greater Than Zero

Decrement Register and Set Condition if Result Less Than Zero

Decrement Register and Set Condition if Result Not Equal to Zero

Decrement on Condition True

Divide Signed Integer

Divide Unsigned Integer

Doze

3–37(3)

Indet(2)

FF1 Find Fi rst On e 1

INCF

INCT

IXH

IXW

Increment on Condition False

Increment on Condition True

Index H a lf-W o r d

Index W o r d

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174 M•CORE M210 Central Processor Unit (CPU) MOTOROLA

M•CORE M210 Central Processor Unit (CPU)

JMP

JMPI

JSR

JSRI

Jump

Jump Indirect

Jump to Subroutine

Jump to Subroutine Indirect

LD.[BHW]

LDM

LDQ

LOOPT

LRW

LSL, LSR

LSLC, LS RC

LSLI, LSRI

Load

Load Multiple Registers

Load Register Quadrant

Decrement with C-Bit Update and Branch if Condition T rue

Load Relative Word

Logical Shift Left and Right

Logical Shift Left and Right, Update C Bit

Logical Shift Left and Right by Immediate

n+1(4)

1/2(1)

MFCR

MOV

MOVI

MOVF

MOVT

MTCR

MULT

MVC

MVCV

Move from Control Register

Move

Move Immedi ate

Move on Condition False

Move on Condition True

Move to Control Register

Multiply

Move C Bit to Re giste r

Move Inverted C Bit to Reg ister

3–18(3)

NOT Logical Complement 1

OR Logical Inclusive-OR 1

ROTLI

RSUB

RSUBI

RTE

RFI

Rotate Left by I m me diate

Reverse Subtract

Reverse Subtract Immediate

Return from Exception

Ret ur n from Interrupt

SEXTB

SEXTH

ST.[BHW]

STM

STQ

STOP

SUBC

SUBU

SUBI

SYNC

Sign-Extend Byte

Sign-Extend Half-Word

Store

Store Multiple Registers

Store Register Quadrant

Stop

Subtract with C Bit

Subtract

Subtract Immediate

Synchronize

n+1(4)

Indet(2)

TRAP

TST

TSTNBZ

Trap

Test Operand s

Te st for No Byte Equal Zero

WAIT Wait Indet(2)

Table 7-1. M•CORE Instruction Set (Sheet 2 of 3)

Mnemonic Description Execution Time

(Cycles)

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MOTOROLA M•CORE M210 Central Processor Unit (CPU) 175

XOR

XSR

XTRB0

XTRB1

XTRB2

XTRB3

Exclusive OR

Extended Shift Right

Extract Byte 0

Extract Byte 1

Extract Byte 2

Extract Byte 3

ZEXTB

ZEXTH Zero-Extend Byte

Zero-Extend Half-Word 1

1. 1 cycle if branch not taken, 2 cycles if branch t aken

2. Execution time of BKPT, DOZE, WAIT, and STOP is 1 cycle but execution does not take place until allcurrent bus trans-

actions have completed.

3. Cycle tim e is dependent upon magnitude of re sult.

4. Number of cycl es is equal to number of re gisters loaded/ stored plus 1.

Table 7-1. M•CORE Instruction Set (Sheet 3 of 3)

Mnemonic Description Execution Time

(Cycles)

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M•CORE M210 Central Processor Unit (CPU)

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MOTOROLA Interrupt Controller Module  177
Advance Info rmation — MMC2114, MMC2113, and MMC2112
S ectio n 8. Interrupt Controlle r Modu le
1  Contents
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
4 Low-Power Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . .178
5 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
6 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
7 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .179
7.1 Memory Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
7.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
7.2.1 Interrupt Control Register. . . . . . . . . . . . . . . . . . . . . . . .181
7.2.2 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . .183
7.2.3 Interrupt Force Registers . . . . . . . . . . . . . . . . . . . . . . . .184
7.2.4 Interrupt Pending Register. . . . . . . . . . . . . . . . . . . . . . .186
7.2.5 Normal Interrupt Enable Register. . . . . . . . . . . . . . . . . .187
7.2.6 Normal Interrupt Pending Register. . . . . . . . . . . . . . . . .188
7.2.7 Fast Interrupt Enable Register. . . . . . . . . . . . . . . . . . . .189
7.2.8 Fast Interrupt Pending Register. . . . . . . . . . . . . . . . . . .190
7.2.9 Priority Level Select Registers. . . . . . . . . . . . . . . . . . . .191
8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
8.1 Interrupt Sources and Prioritization . . . . . . . . . . . . . . . . . .192
8.2 Fast and Normal Interrupt Requests . . . . . . . . . . . . . . . . .192
8.3 Autovectored and Vectored Interrupt Requests . . . . . . . . .193
8.4 Interrupt Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
8.4.1 CPU Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
8.4.2 Interrupt Controller Configuration. . . . . . . . . . . . . . . . . .195
8.4.3 Interrupt Source Configuration. . . . . . . . . . . . . . . . . . . .196
8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
    
  
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178 Interrupt Controller Module MOTOROLA

Inter rup t Contro lle r Module

8.2 Introduc tion

The inter rupt controll er collects requests fr om multiple interru pt sources

and provides an interface to the CPU interrupt logic.

8.3 Features

Features of the interrupt controller module include:

•Up to 40 interrupt sources

•32 unique programmable priority levels for each interrupt source

•Independent enable/disable of pending interrupts based on

priority level

•Select normal or fast interrupt request for each priority level

•Fast interr upt requests al ways have priority over normal interr upts

•Ability to mask interrupts at and below a defined priority level

•Ability to select between autovectored or vectored interrupt

requests

•Vectored interrupts generated based on priority level

•Ability to generate a separate vector number for normal and fast

interrupts

•Ability for software to self-schedule interrupts

•Software visibility of pending interrupts and interrupt signals to

core

•Asynchronous operation to support wakeup from low-power

modes

8.4 Low-Power Mode Operation

The interrupt controller is not aff ected by any low-power modes. All logic

between the input sources and generating the raw interrupt to the CPU

is combinational. This allows the CPU to wake up during low-power stop

mode when all system clocks are stopped.

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Interrupt Controller Module

Block Diagram

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MOTOROLA Interrupt Controller Module 179

8.5 Block Diagram

Figure 8-1. Interrupt Controller Block Diagram

8.6 External Signals

No interrupt controller signals connect off-chip.

8.7 Memory Map and Registers

This subsection describes the memory map (see Table 8-1) and

registers.

INTERRUPT

SOURCES

ICR

VECTOR

32-to-5

PRIORITY

ENCODER

FVE

NORMAL

40 32

40 x 5 BITS 32

PLSR

AUTOVECTOR

OR PRIORITY

LEVEL

SELECT

ISR

5DECODE

MASK

MFI

32 32

FMASK

NMASK

NMASK &

FMASK

PLSR

SELECT

AND FAST

INTERRUPTS

NUMBER

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180 Interrupt Controller Module MOTOROLA

Inter rup t Contro lle r Module

8.7.1 Memory Map

Table 8-1. Interrupt Controller Module Memory Map

Address Bits 31–24 Bits 23–16 Bits 15–8Bits 7–0 Access(1)

0x00c5_000 0 Interrupt Control Register (ICR) Interrupt Status Register (ISR) S/ U

0x00c5_0004 Interrupt Force Register High (IFRH) S/U

0x00c5_0008 Interrupt Force Register Low (IFRL) S /U

0x00c5_000c Interrupt Pending Register (IPR) S/U

0x00c5_0010 Normal Interrupt Enable Register (NIER) S /U

0x00c5_001 4 Normal Interrupt Pend ing Register (NIPR) S/U

0x00c5_001 8 Fast Interrupt Enable Register (FIER) S/U

0x00c5_001c Fast Interrupt Pending Register (FIPR) S/U

0x00c5_0020

through

0x00c5_003c Unimplemented(2) —

Priority Level Select Registers (PLSR0–PLSR39)

0x00c5_0040 PLSR0 PLSR1 PLSR2 PLSR3 S

0x00c5_0044 PLSR4 PLSR5 PLSR6 PLSR7 S

0x00c5_0048 PLSR8 PLSR9 PLSR10 PLSR11 S

0x00c5_004c PLSR12 PLSR13 PLSR14 PLSR15 S

0x00c5_0050 PLSR16 PLSR17 PLSR18 PLSR19 S

0x00c5_0054 PLSR20 PLSR21 PLSR22 PLSR23 S

0x00c5_0058 PLSR24 PLSR25 PLSR26 PLSR27 S

0x00c5_005c PLSR28 PLSR29 PLSR30 PLSR31 S

0x00c5_0060 PLSR32 PLSR33 PLSR34 PLSR35 S

0x00c5_0064 PLSR36 PLSR37 PLSR38 PLSR39 S

0x00c5_0068

through

0x00c5_007c Unimplemented(2) —

1. S = CPU supervi sor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor

only addresses have no effect and result in a cycl e termination transfer error.

2. Accesses to unimplem ented address locations have no eff ect and result in a cycle terminat ion tr ansfer error.

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Mem ory Map and Registers

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MOTOROLA Interrupt Controller Module 181

8.7.2 Registers

This subsection contains a des cription of the interr upt control ler module

8.7.2.1 Interrupt Control Register

The 16-bit Interrupt Control Register (ICR) selects whether interrupt

requests are autovectored or vectored, and if vectored, whether fast

interrupts generate a different vector number than normal interrupts.

This register also controls the masking functions.

AE — Autovector Enable Bit

The r ead/ w rite AE bit enab l es fast and nor mal autove c tore d inte rrup t

requests. Reset sets AE.

1 = Autovectored interrupt requests

0 = Vecto red interr upt requests

FVE — Fast Vector Enable Bit

The read/write FVE bit enables fast vectored interrupt requests to

have vector numbers separate from normal vectored interrupt

requests. Reset clears FVE.

1 = Unique vector numbers for fast vectored interrupt requests

0 = Same vector number for fast and normal vectored interrupt

requests

Address: 0x00c5_0000 and 0x00c5_0001

Bit 15 14 13 12 11 10 9 B it 8

Read: AE FVE ME MFI 0000

Write:

Reset:10000000

Bit 7654321Bit 0

Read: 0 0 0 MASK4 MASK3 MASK2 MASK1 MASK0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfer error exception.

Figure 8-2. Interrupt Control Register (ICR)

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182 Interrupt Controller Module MOTOROLA

Inter rup t Contro lle r Module

ME — Mask Enable Bit

The read/write ME bit enables interrupt masking. Reset clears ME.

1 = Interrupt masking enabled

0 = Interrupt masking disabled

MFI — Mask Fast Interrupts Bit

The read/write MFI bit enables masking of fast interrupt requests.

Reset clears MFI.

1 = Fast interrupt requests masked by MASK value. All normal

interrupt requests are masked.

0 = Fast interrupt requests are not masked regardless of the MASK

value. The MASK only applies to normal interrupts. Reset

clears MFI.

MASK[4:0] — Interrupt Mask Fiel d

The read/write MASK[4:0] field determines which interrupt priority

levels are masked. When the ME bit is set, all pending interrupt

requests at priority levels at and below the current MASK value are

masked. To mask all normal interrupts without masking any fast

interrupts, set the MASK value to 31 with the MFI bit cleared. See

Table 8-2. Reset clears MASK[4:0].

Table 8-2. MASK Encoding

MASK[4:0] Masked Priority

Levels

Decimal Binary

0 00000 0

1 00001 1–0

2 00010 2–0

3 00011 3–0

•

31 11111 31–0

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MOTOROLA Interrupt Controller Module 183

8.7.2.2 Interrupt Status Register

The 16 -bit, read- only Interr upt Statu s Register (ISR) reflects th e state of

the interrupt controller outputs to the CPU. Writes to this register have

no effect and are terminated normally.

INT — Normal Interrupt Request Flag

The read-only INT flag indicates whether the normal interrupt request

signal to the CPU is asserted or negated. Reset clears INT.

1 = Normal interrupt request asserted

0 = Normal interrupt request negated

FINT — Fast Interrupt Request Flag

The read-only FINT flag indicates whether the fast interrupt request

signal to the CPU is asserted or negated. Reset clears FINT.

1 = Fast interrupt request asserted

0 = Fast interrupt request negated

VEC[6 :0] — Interrupt Vector Number Field

The read-only VEC[6:0] field contains the 7-bit interrupt vector

number (see Table 8-5). Reset clears VEC[6:0].

Address: 0x00c5_0002 and 0x00c5_0003

Bit 15 14 13 12 11 10 9 B it 8

Read: 0 0 0000INTFINT

Write:

Reset:00000000

Bit 7654321Bit 0

Read: 0 VEC6 VEC5 VEC4 VEC3 VEC2 VEC1 VEC0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfer error exception.

Figure 8-3. Int errupt Status Register (ISR)

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184 Interrupt Controller Module MOTOROLA

Inter rup t Contro lle r Module

8.7.2.3 Interrupt Force Registers

The two 32-bit read/write Interrupt Force Registers (IFRH and IFRL)

individually force interrupt source requests.

Address: 0x00c5_0004 through 0x00c5_0007

Bit 31 30 29 28 27 26 25 Bit 24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 Bit 16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 B it 8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: IF39 IF38 IF37 IF36 IF35 IF34 IF33 IF32

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfer error exception.

Figure 8-4. Interrupt Force Register High (IFRH)

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MOTOROLA Interrupt Controller Module 185

IF[39:0] — Interrupt Force Field

This read/write field forces interrupt requests at the corresponding

source numbers. Reference Table 8-6 for interrupt source numbers

to determine which bit(s) to set in this register. IFRH and IFRL allow

software generation of interrupt requests for functional or debug

purposes. Writing 0 to an IF bit negates the interrupt request. Reset

clears the IF[39:0] field.

1 = Force interrupt request

0 = Interrupt source not forced

Address: 0x00c5_0008 through 0x00c5_000b

Bit 31 30 29 28 27 26 25 Bit 24

Read: IF31 IF30 IF29 IF28 IF27 IF26 IF25 IF24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 Bit 16

Read: IF23 IF22 IF21 IF20 IF19 IF18 IF17 IF16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 B it 8

Read: IF15 IF14 IF13 IF12 IF11 IF10 IF9 IF8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: IF7 IF6 IF5 IF4 IF3 IF2 IF1 IF0

Write:

Reset:00000000

Figure 8-5. Interrupt Force Register Low (IFRL)

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Inter rup t Contro lle r Module

8.7.2.4 Interrupt Pending Register

The 32-bit, read-only Interrupt Pending Register (IPR) reflects any

currently pending interrupts which are assigned to each priority level.

Writes to this register have no effect and are terminated normally.

IP[31:0] — Interrupt Pending Field

A read-only IPx bit is set when at least one interrupt request is

asserted at priority level x. Reset clears IP[31:0].

1 = At le ast one interrupt request asserted at priority level x

0 = All interrupt requests at level x negated

Address: 0x00c5_000c through 0x00c5_000f

Bit 31 30 29 28 27 26 25 Bit 24

Read: IP31 IP30 IP29 IP28 IP27 IP26 IP25 IP24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 Bit 16

Read: IP23 IP22 IP21 IP20 IP19 IP18 IP17 IP16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 B it 8

Read: IP15 IP14 IP13 IP12 IP11 IP10 IP9 IP8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfer error exception.

Figure 8-6. Interru pt Pen ding Register (IPR)

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MOTOROLA Interrupt Controller Module 187

8.7.2.5 Normal Interrupt Enable Register

The read/write, 32-bit Normal Interrupt Enable Register (NIER)

individually enables any current pending interrupts which are assigned

to each pri ori ty level as a norm al i nter rupt source. E nabling an i nterrupt

source which has an asserted request causes that request to become

pending, and a request to the CPU is asserted if not already outstanding.

NIE[31:0] — Normal Interrupt Enable Field

The read/write NIE[31:0] field enables interrupt requests from sources

at the corresponding priority level as normal interrupt request s. Reset

clears NIE[31:0].

1 = Normal interrupt request enabled

0 = Normal interrupt request disabled

Address: 0x00c5_0010 through 0x00c5_0013

Bit 31 30 29 28 27 26 25 Bit 24

Read: NIE31 NIE30 NIE29 NIE28 NIE27 NIE26 NIE25 NIE24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 Bit 16

Read: NIE23 NIE22 NIE21 NIE20 NIE19 NIE18 NIE17 NIE16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 B it 8

Read: NIE15 NIE14 NIE13 NIE12 NIE11 NIE10 NIE9 NIE8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: NIE7 NIE6 NIE5 NIE4 NIE3 NIE2 NIE1 NIE0

Write:

Reset:00000000

Figure 8-7. No rmal Interrupt Enable Register (NIER)

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8.7.2.6 Normal Interr upt Pending Register

The rea d-only, 32-bit N ormal Interr upt Pending Registe r (NIPR) reflect s

any currently pending normal interrupts which are assigned to each

priority level. Writes to this register have no effect and are terminated

normally.

NIP[31:0] — Normal Interrupt Pending Field

A rea d-only NIPx bi t is set when at l east one nor mal interru pt request

is asserted at priority level x. Reset clears NIP[31:0].

1 = At least one norma l inte rrupt requ est asserted at prior ity level x

0 = All normal interrupt requests at prio rity level x negated

Address: 0x00c5_0014 through 0x00c5_0017

Bit 31 30 29 28 27 26 25 Bit 24

Read: NIP31 NIP30 NIP29 NIP28 NIP27 NIP26 NIP25 NIP24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 Bit 16

Read: NIP23 NIP22 NIP21 NIP20 NIP19 NIP18 NIP17 NIP16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 B it 8

Read: NIP15 NIP14 NIP13 NIP12 NIP11 NIP10 NIP9 NIP8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: NIP7 NIP6 NIP5 NIP4 NIP3 NIP2 NIP1 NIP0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfer error exception.

Figure 8-8. Normal Interrupt Pending Register (NIPR)

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8. 7.2.7 Fast Interrupt Enable Register

The read/write, 32-bit Fast Interrupt Enable Register (FIER) enables any

curren t pe nding interrupt s whi ch are assign ed at e ach p ri orit y level as a

fast interrupt source. Enabling an interrupt source which has an asserted

request causes that interrupt to become pending, and a request to the

CPU is asserted if not already outstanding.

FIE[31:0] — Fast Interrupt Enable Field

The read/write FIE[31:0] field enables interrupt requests from sources

at the corresponding priority level as fast interrupts. Reset clears

FIE[31:0].

1 = Fast interrupt enabled

0 = Fast interrupt disabled

Address: 0x00c5_0018 through 0x00c5_001b

Bit 31 30 29 28 27 26 25 Bit 24

Read: FIE31 FIE30 FIE29 FIE28 FIE27 FIE26 FIE25 FIE24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 Bit 16

Read: FIE23 FIE22 FIE21 FIE20 FIE19 FIE18 FIE17 FIE16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 B it 8

Read: FIE15 FIE14 FIE13 FIE12 FIE11 FIE10 FIE9 FIE8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: FIE7 FIE6 FIE5 FIE4 FIE3 FIE2 FIE1 FIE0

Write:

Reset:00000000

Figure 8-9. Fast Interrupt Enable Register (FIER)

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8. 7.2.8 Fast Interrupt Pending Register

The read-only, 32-bit Fast Interrupt Pending Register (FIPR) reflects any

currently pending fast i nterrupts which are assigned to each pri ority

level. Writes to this register have no effect and are terminated normally.

FIP[31:0] — Fast Interrupt Pending Field

A read-only FIP[x] bit is set when at least one interrupt request at

priority level x is pending and enabled as a fast interrupt. Reset clears

FIP[31:0].

1 = At least one fast interrupt request asserted at priority level x

0 = Any fast interrupt requests at priority level x negated

Address: 0x00c5_001c through 0x00c5_001f

Bit 31 30 29 28 27 26 25 Bit 24

Read: FIP31 FIP30 FIP29 FIP28 FIP27 FIP26 FIP25 FIP24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 Bit 16

Read: FIP23 FIP22 FIP21 FIP20 FIP19 FIP18 FIP17 FIP16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 B it 8

Read: FIP15 FIP14 FIP13 FIP12 FIP11 FIP10 FIP9 FIP8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: FIP7 FIP6 FIP5 FIP4 FIP3 FIP2 FIP1 FIP0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfer error exception.

Figure 8-10. Fast Interrupt Pending Register (FIPR)

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8.7.2.9 Priority Level Select Registers

The read/write 8-bit Priority Level Select Registers (PLSRx) are 40

read/write, 8-bit priority level select registers PLSR0–PLSR39, one for

each o f the inte rru pt so urce. Th e P LSR x r egister assign s a priority le vel

to interrupt source x.

PLS[4:0] — Priority Level Select Field

The PLS[4:0] field assigns a priority level from 0 to 31 to the

corresponding interrupt source. Reset clears PLS[4:0].

8.8 Functional Des cription

The interrupt controller collects interrupt requests from multiple interrupt

sources and provides an interface to the CPU interrupt logic. Interrupt

controller functions include:

•Interrupt source prioritization

•Fast and normal interrupt requests

•Autovectored and vectored interrupt requests

•Interrupt configuration

Address: 0x00c5_0040 through 0x00c5_0067

Bit 7654321Bit 0

Read: 0 0 0 PLS4 PLS3 PLS2 PLS1 PLS0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfer error exception.

Figure 8-11. Priority Level Select Registers (PLSR0–PLSR39)

Table 8-3. Priority Select Encoding

PLS[4:0] Prior ity Level Vector Number

00000 0 (lowest) 00000

00001–11110 1–30 00001–11110

11111 31 (highest) 11111

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8.8.1 Interrupt Sour ces and Prioritization

Each interrupt source in the system sends a unique signal to the interrupt

controller. Up to 40 interrupt sources are supported. Each interrupt

source can be programmed to one of 32 priority levels by programing the

PLS bits of the PLSR in the interrup t controller. The highest priority level

is 31 and lowest priority level is 0. By default, each interrupt source is

assigned to the priority level 0. Each interrupt source is associated with

a 5-bit priority level select value that selects one of 32 priority levels. The

interrupt controller uses the priority levels as the basis for the genera tion

of all interrupt signals to the CPU.

Interrupt requests may be forced by software by writing to IFRH and

IFRL. Each bit of IFRH and IFRL is logically ORed with the

corresponding interrupt source signal before the priority level select

logic. To negate the forced interrupt request, the interrupt handler can

clea r the app ropr iate IF R bit. IPR ref l ects the state of each pr iority level .

8.8.2 Fast and Normal Interrupt Requests

FIER allows individual enabling or masking of pending fast interrupt

requests. FIER is logically ANDed with IPR , and the result is stored in

FIPR. FIPR bits are bit-wise ORed together and inverted to form the fast

interrupt signal routed to the CPU (see Figure 8-1). The FIPR allows

sof tware to quickly determine the hi ghest pr iority pend i ng fast inter rupt.

The output of FIPR also feeds into a 32-to-5 priority encoder to generate

the vector number to present to the CPU if vectored interrupts are

required.

NIER allows individual enabling or masking of pending normal inter rupt

requests. NIER is logically ANDed with IPR, and the result is stored in

NIPR. NIPR bits are bit-wise ORed together and inverted to form the

norma l interru pt signal rou ted to the CPU. The nor mal interrup t sign al is

only asserted if the fast interrupt signal is negated. The NIPR allows

software to quickly determine the highest priority pending normal

interrupt. The output of NIPR also fee ds into a 32-to-5 priority encoder to

genera t e th e vecto r nu mber to present to the CPU i f vector ed inte rru pts

are required. If the fast interrupt signal is asserted, then the vector

number is determined by the highest priority fast interrupt.

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MOTOROLA Interrupt Controller Module 193

If an interrupt is pending at a given priority level and both the

corresp onding FIE R and N IER b its are set, th en both the correspond ing

FIPR and NIPR bits are set, assuming these bits are not masked.

Fast interrupt requests always have priority over normal interrupt

request s , even if the norm al i nter rup t req uest is a t a hi g her prior ity level

than the highest fast interrupt request.

If the fast in terrupt signal is asser ted w h en th e n orma l inter rup t signal is

already asserted, then the normal interrupt signal is negated.

IPR, NIPR, and FIPR are read-only. To clear a pending interrupt, the

interrupt must be cleared at the source using a special clearing

sequence defined by each source. All interrupt sources to the interrupt

controller are to be held until recognized and cleared by the interrupt

service routine. The interrupt controller does not have any edge-detect

logic. Edge-triggered interrupt sources are handled at the source

module.

In ICR, the MASK[4:0] bits can mask interrupt sources at and below a

selected priority level. The MFI bit determines whether the mask app lies

only to normal interrupts or to fast interrupts with all normal interrupts

being masked. The ME bit enables interr upt masking.

ISR reflects the current vector nu mber and the states of the signals to

the CPU.

The vector number and fast/normal interrupt sources are synchronized

before being sent to the CPU. Thus, the interrupt controller adds one

clock of latency to the interr upt sequence. The fast and norma l interrupt

raw sources are not synchronized and are used to wake up the CPU

during stop mode.

8.8.3 Autovectored and Vect ored Interrupt Requests

The AE bit in ICR enables autovectored interrupt requests to the CPU.

AE is set by default, and all interrupt requests are autovectored. An

inte rrupt hand le r may read FIPR or NIPR to determine t he priority of the

interrupt source. If multiple interrupt sources share the same priority

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level, then it is up to t he interrupt service routine to determine the correct

source of the interrupt.

If the AE bit is 0, then each interr upt request is presented with a vector

number. The low five bits of the vector number (4–0) are determined

based on the highest pending priority, with active fast interrupts having

pri ority over ac tive normal interru pts. The re maining tw o bits (vector bits

5 and 6) are deter mined base d on whethe r the i nterrup t request is a f ast

inte rrupt an d the set ting of the FVE bi t. If FVE is set, then a fa st interrup t

request has a vector number different from that of a normal interrupt

request as shown in Table 8-4.

If FVE is 0, both normal and fast interrupts have the same vector and

request s assign ed to pr iority l evels 0–3 1 are m apped to vector nu mbers

32–63 in the vector table.

If FVE is 1, normal inte rrupt requests a ssigned to priority levels 0 –31 are

mapped to vector numbers 32–63 and fast interrupt requests assigned

to priority levels 0–31 are mapped to vector numbers 64–95 in the vector

table. See Table 8-5.

Table 8-4. Fast Interrupt Vector Number

Fast In t errupt FV E Inte rru pt Vector

Bits 6:5

No X 01

X0 01

Yes 1 10

Table 8-5. Vector Table Mapping

Vector

Number Usage Interrupt Vector

Bits 6:5

0–31 Fixed exceptions (including autovectors) 00

32–63

Normal only (FVE = 1) or normal/fast (FV E = 0)

vectored interrupts

32 = lowe st priority

63 = hig hes t priority

64–95 Fast vectored interrupts (FVE = 1)

64 = lowe st priority

95 = hig hes t priority 10

96–127 Vectored interrupts (not used) 11

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8.8.4 Interrupt Configuration

After reset, all interrupts are disabled by default. To properly configure

the system to handle interrupt requests, configuration must be

performed at three levels:

•CPU

•Interrupt controller

•Local interrupt sources

Configure the CPU first, the interrupt controller second, and the local

interrupt sources last.

8.8.4.1 CPU Configuration

For fast interrupts, set the FIE[x] bit in FIER in the CPU. For normal

interrupts, set the NIE[x] bit. Both FIE and NIE are cleared at reset.

NOTE: To allow long latency, multicycle instructions to be interrupted before

completion, set the IC bit in the PSR.

VBR in th e CPU defin es the base addre ss o f the exception vector table.

If autovectors are to be used, then initialize the INT and FINT

autovectors (vector numbers 10 and 11, respectively). If vectored

interrupts are to be used, then initialize the vectored interrupts (vector

numbers 32–63 and/or 64–95). Whether 32 or 64 vectors are required

depends on whether the fast interrupts share vectors with the normal

interrupt sources based on the FVE bit in the interrupt controller ICR.

For each vector number, create an interrupt service routine to service

the interrupt, clear the local interrupt flag, and return from the interrupt

routine.

8.8.4.2 Interrupt Controller Configuration

By defau lt, each interrupt sou rce to the interru pt controll er is assigned a

priority level of 0 and disabled. Each interrupt source can be

programmed to one of 32 priority levels and enabled as either a fast or

normal interrupt source. Also, the FVE and AE bits in ICR can be

programmed to select autovectored/vectored interrupts and also

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determine if the fast interrupt vector number is to be separate from the

normal interrupt vector.

8.8.4.3 Interrupt Source Configuration

Each module that is capable of generating an interrupt request has an

interrupt request enable/disable bit. To allow the interrupt source to be

asserted, set the local interrupt enable bit.

Once an interrupt request is asserted, the module keeps the source

asserted unti l the inte rru pt servi ce routine perf orms a speci al sequ ence

to cl ear the inte rrupt flag. Clearing the fla g negates th e interrupt request.

8.8.5 Interrupts

The interrupt controller assigns a number to each interrupt source, as

Table 8-6 shows.

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Table 8-6. Interrupt S ource Assignment

Source Module Flag Source Description Flag Clearing Mechanism

ADC

PF1 Queue 1 conve rsion pause Writ e PF1 = 0 after reading PF1 = 1

1 CF1 Queue 1 conver sion complete Write CF1 = 0 after reading CF1 = 1

2 P F2 Queue 2 co nversion paus e Write PF2 = 0 af ter reading PF2 = 1

3 CF2 Queue 2 conve rsion complete Write CF2 = 0 after re ading CF2 = 1

4SPI MODF M ode f ault Writ e to SPICR1 after reading MODF = 1

5 SPIF Transfer complete Ac cess SPIDR after reading SPIF = 1

SCI1

TDRE Transmit Data Register empty Write SCIDRL after reading TDRE = 1

7 TC Transmit complete Writ e SC IDRL after reading TC = 1

8 RDRF Receive Data Register full Read SCIDRL after reading RDRF = 1

9 OR Recei ve r overrun Read SCIDRL after reading OR = 1

10 IDLE Recei ver line idle Read SCIDRL after reading IDLE = 1

SCI2

TDRE Transmit Data Register empty Write SCIDRL after reading TDRE = 1

12 TC Transm it complete Write SCIDRL after reading TC = 1

13 RDRF Receive Data Register full Read SCIDRL after reading RDRF = 1

14 OR Recei ver overrun Read S CIDRL after reading OR = 1

15 IDLE Recei ver line idle Read SCIDRL after reading IDLE = 1

TIM1

C0F Timer channel 0 Write C0F = 1 or access IC/OC if TFFCA = 1

17 C1F Timer channel 1 Write 1 to C1F or access IC/OC if T FF CA = 1

18 C2F Timer channel 2 Write 1 to C2F or access IC/OC if T FF CA = 1

19 C3F Timer channel 3 Write 1 to C3F or access IC/OC if T FF CA = 1

20 TOF Tim er overflow Write TOF = 1 or access TIMCNTH/L if TFFCA = 1

21 PAIF Pulse accumulator input Wri te PAIF = 1 or access PAC if TFFCA = 1

22 PA OVF Pulse accum ulator overflow Write PA O VF = 1 or access PA C if TFFC A = 1

Continued on nex t page

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TIM2

C0F Timer channel 0 Write C0F = 1 or access IC/OC if TFFCA = 1

24 C1F Timer channel 1 Write C1F = 1 or access IC/OC if TFFCA = 1

25 C2F Timer channel 2 Write C2F = 1 or access IC/OC if TFFCA = 1

26 C3F Timer channel 3 Write C3F = 1 or access IC/OC if TFFCA = 1

27 TOF Tim er overflow Write TOF = 1 or access TIMCNTH/L if TFFCA = 1

28 PAIF Pulse accumulator input Wri te PAIF = 1 or access PAC if TFFCA = 1

29 PA OVF Pulse accum ulator overflow Write PA O VF = 1 or access PA C if TFFC A = 1

30 PIT1 PIF PIT interrupt fl ag Write PIF = 1 or write PMR

31 PIT2 PIF PIT interrupt fl ag Write PIF = 1 or write PMR

32 EPORT/

PMM(1) EPF0/

LVDF Edge port flag 0/LVD Writ e EPF 0 = 1/write LVDF = 1

33 EPORT/

SGFM(2)

EPF1

CBEIF/

CCIF

Edge port flag 1/SGFM buffer

empty /SGF M com ma nd

complete

Writ e EPF 1 = 1/write CBEIF = 1; CCIF cleared

automatically

EPORT

EPF2 Edge port flag 2 Write EPF2 = 1

35 EPF3 Edge port flag 3 Write EPF3 = 1

36 EPF4 Edge port flag 4 Write EPF4 = 1

37 EPF5 Edge port flag 5 Write EPF5 = 1

38 EPF6 Edge port flag 6 Write EPF6 = 1

39 EPF7 Edge port flag 7 Write EPF7 = 1

1. I nterrupt so urce 32 is s hared by INT0 of the EPORT and low vol tage detect (LVD) of the power managemen t module (PMM),

a sub-m odu le of t h e r e s et m ode (se e Section 5. Reset Controller Module).

2. Interrupt source 33 is shared by INT1 of the EPORT and two i nt err upts from the second generation FLASH for M•CORE

(SGFM) module. See 10.7.2.5 SGFM User Status Register for a description of the flags set when these two interrupts

occur.

Table 8-6. Interrupt Source Assignment (Continued)

Source Module Flag Source Description Flag Clearing Mechanism

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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Information

MOTOROLA Static Random Access Memory (SRAM) 199

Advance Info rmation — MMC2114, MMC2113, and MMC2112

Section 9. Static Random Access Memory (SRAM)

9.1 Contents

9.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199

9.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

9.4 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

9.5 Standby Power Supply Pin (VSTBY) . . . . . . . . . . . . . . . . . . . .200

9.6 Standby Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

9.7 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

9.8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

9.2 Introduc tion

Features of the static random access memory (SRAM) include:

•On-chip 8-Kbyte SRAM (MMC2113) or on-chip 32-Kbyte SRAM

(MC2112 and MMC2114)

•Fixed address space

•Byte, half-word (16-bit), or word (32-bit) read/write accesses

•One clock per access (including bytes, half-words, and words)

•Supervisor or user mode access

•Stand by powe r sup pl y switch to support an exte rnal p ower supply

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200 Static Random Access Memory (SRAM) MOTOROLA

Static Random Access Memory (SRAM)

9.3 Modes of Operation

Access to the SRAM is not restricted in any way. The array can be

accessed in supervisor and user modes.

NOTE: The MMC2113 may contain more than 8K of interna l SRAM, bu t only the

8K range from 0x0080_0000 to 0x0080_1fff is tested and guara nteed to

be ope rational. It is recommended that internal SRAM outside this range

not be used. Accesses to SRAM outside this range terminate without a

transfer error exception.

9.4 Low-Power Modes

In wait, doze, and stop modes, clocks to the SRAM are disabled. No

recovery time is required when exiting these modes.

9.5 Stand by Power Supply Pi n (VSTBY)

The standby power supply pin (VSTBY) provides standby voltage to the

SRAM arra y if VDD is lost. VSTBY is isolated from all other VDD nodes.

9.6 Standby Operation

When the chip is powered down, the contents of the SRAM array are

maintained by the standby power supply, VSTBY. If the standby voltage

falls below the minimum required voltage, the SRAM contents may be

corrupted. The SR AM autom atically switches to standby operation with

no l oss o f dat a when the vol tage on VDD is below the voltage on V STBY.

In standby mode, the SRAM does not respond to any bus cycles.

Unexpected operation may occur if the central processor unit (CPU)

requests data from the SRAM in standby mode. If standby operation is

not needed, then the VSTBY pin should be connected to VDD.

The current on VSTBY may exceed its specified maximum value at some

time during the transition time during which VDD is at or below the

volta ge switch threshold to a threshold abo ve V SS. If the sta ndby pow er

supply cannot provide enough current to maintain VSTBY above the

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Static Random Ac cess Memo ry (SRAM)

Reset Operation

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Informa tion

MOTOROLA Static Random Access Memory (SRAM) 201

requi red minimu m value, th en a capacitor must be provi ded from V STBY

to VSS. The value of the capacitor, C, can be calculated as:

where:

I is the differe nce between the transitio n cur rent req ui rement a nd the

maximum power supply current,

t is the duration of the VDD transition near the voltage switch

thresh old, and

V is the difference between the minimum available supply voltage and

the required minimum VSTBY voltage.

9.7 Reset Operation

The SRA M contents are undefined immediately following a power-on

reset. SRAM contents are unaffected by system reset.

If a synchronous reset occurs during a read or write access, then the

access completes normally and any pipelined access in progress is

stopped without corruption of the SRAM contents.

9.8 Interrupts

The SRA M module does not generate interrupt requests.

----×=

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Static Random Access Memory (SRAM)

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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0  Advance Information
MOTOROLA Second Generation FLASH for M•CORE (SGFM)  203
Advance Info rmation — MMC2114, MMC2113, and MMC2112
Section 10. Second Generation FLASH for M•CORE
(SGFM)
1  Contents
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
3 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
6 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
7 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
7.1 Unbanked R egister Descriptions . . . . . . . . . . . . . . . . . . . .213
7.1.1 SGFM Configuration Register . . . . . . . . . . . . . . . . . . . .213
7.1.2 SGFM Clock Divider Register . . . . . . . . . . . . . . . . . . . .215
7.1.3 SGFM Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . .216
7.1.4 SGFM Security Register . . . . . . . . . . . . . . . . . . . . . . . .217
7.1.5 SGFM Monitor Data Register. . . . . . . . . . . . . . . . . . . . .219
7.2 Banked Register Descriptions . . . . . . . . . . . . . . . . . . . . . .220
7.2.1 SGFM Protection Register. . . . . . . . . . . . . . . . . . . . . . .220
7.2.2 SGFM Supervisor Access Register . . . . . . . . . . . . . . . .222
7.2.3 SGFM Data Access R egister. . . . . . . . . . . . . . . . . . . . .223
7.2.4 SGFM Test Status Register. . . . . . . . . . . . . . . . . . . . . .224
7.2.5 SGFM User Status Register. . . . . . . . . . . . . . . . . . . . . .224
7.2.6 SGFM Co mmand Register. . . . . . . . . . . . . . . . . . . . . . .226
7.2.7 SGFM Control Register . . . . . . . . . . . . . . . . . . . . . . . . .227
7.2.8 SGFM Address Register . . . . . . . . . . . . . . . . . . . . . . . .228
7.2.9 SGFM Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . .229
8 SGFM User Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
8.1 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
8.2 Write Operations  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
    
  
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Second Generation FLASH for M•CORE (SGFM)
10.8.3 Program and Er ase Operations . . . . . . . . . . . . . . . . . . . . .231
10.8.3.1 Setting the SGFMCLKD Register. . . . . . . . . . . . . . . . . .231
10.8.3.2 Program, Erase, and Verify Sequences. . . . . . . . . . . . .232
10.8.3.3 FLASH User Mode Valid Commands. . . . . . . . . . . . . . .234
10.8.3.4 FLASH User Mode Illegal Operations . . . . . . . . . . . . . .236
10.8.4 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
10.8.5 Master Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
10.8.6 Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
10.8.7 Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
10.9 FLASH Security Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .238
10.9.1 Back Door Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
10.9.2 Erase Verify Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
10.10 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
10.11 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
10.2  Introduction
The second generation FLASH for M•CORE (SGFM) is constructed with 
building blocks of 32,768 by 16 bits that can be used to generate 128-, 
256-, 384- and 512-Kbyte electrically erasable and programmable 
read-only memory arrays using two, four, six, and eight blocks 
respectively. The SGFM is ideal for program and data storage for 
single-chip applications and allows for field reprogramming without 
ext erna l high-voltage sources.
The voltages required to program and erase the FLASH is generated 
inte rnally  by on-chip char ge pumps. Progr am and erase  operation s are 
performed under CPU control through a command driven interface to an 
internal state machine. All FLASH physical blocks can be programmed 
or erased at the same time; however, it is not possible to read from a 
FLASH physical block while the same block is being programmed or 
erased. For 256-Kbyte and larger arrays, it is possible to program or 
erase one pair of FLASH physical blocks under the control of software 
routines executing out of another pair.
    
  
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Second Generation FLAS H for M•CORE (SGFM)

Glossary

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10.3 Glossary

SGFM — Second generation FLASH for M•CORE. Acr onym used

throughout this document to reference this module.

SGFM Module — Includes the bus interface, command controller,

built-in self test (BIST) controller, and the FLASH physical blocks.

FLASH Physical Blo ck — A 64-K byte F LASH hard blo ck or gani ze d a s

32,768 halfwords (32K x 16 bits) that includes high voltage generation

and parametric test features.

FLASH Logical Sector — An 8-Kbyte sector of contiguous FLASH

memory that can be protected from program and erase operations. A

logical sector can have supervisor/user and program/data space access

restrictions.

FLASH Erase Page — Eight rows of 64 bytes (512 bytes) in one FLASH

physical block. Two pages, one from each interleaving physical block,

are erased at one time.

Ban ked Reg ister — A reg ister that operates on two interleaved FLASH

physical blocks. Banked registers share the same contro l register

addresses as the equivalent registers for the other FLASH physical

blocks. The active re gister bank is selected by a bank select field in the

unbanked register space. The SGFM module contains one to four sets

of banked registers depending on the size of the array.

Unbanked Register — A register which operates upon all FLASH

physical blocks.

Command Sequence — A three step sequence to program, erase, or

verify the FLASH.

FLASH User Mode — The mode in wh ich the F LASH module op erate s

when executing user code and software controlled program and erase

operations.

SATO — Acron ym used for sens e amplifi e r timeo ut anal o g har d-ma cro

block. The SATO saves power at low system clock frequencies by

limiting the time during which sense amps are enabled.

Erased State — Bit state that reads as a 1.

Programmed State — Bit state that reads as a 0.

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10.4 Features

Features of the SGFM include:

•128- (MMC2113), 256- (MMC2114), 384-, or 512-Kbytes of

FLA SH me mory

•33 MHz singl e cycle reads of bytes, aligned halfwords (16 bits),

and aligned words (32 bits)

•Automated program and erase operation

•Concurrent verify, program, and erase of all array blocks

•Read-while-write capability for 256-Kbyte and larger arrays

•Optional interrupt on command completion

•Flexible scheme for protection against accidental program or

erase operations

•Access restriction controls for both superviso r/user and

data/program space operations

•Security for single-chip applications

•Single power supply (system VDD) used for all module operations

•Auto sense amplifier timeout for low-power , low-frequency read

operations

10.5 Modes of Operation

The SGFM has two operating modes:

1. FLASH User Mode — In this mode, the SGFM is used for

non-volatile program and data storage. FLASH program and

erase operations are controlled by user software.

2. FLASH Test Mode — This is used at the factory only to test the

SGFM.

Refer to 10.8 SGFM User Mode for a description of FLASH user mode

operations.

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Second Generation FLAS H for M•CORE (SGFM)

Block Diagram

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10.6 Blo ck Diag r am

The SGF M mod ule shown i n Figure 10-1 contains the FLAS H physical

blocks, the M•CORE local bus (MLB) an d IP bus interfa ces, FL ASH

interface, register blocks, and the BIST engine.

Each 64-Kbyte FLASH physical block is arranged as 32,768 halfwords

(16 bi ts) and may be read as either bytes or aligned halfwords. Aligned

word access is provided by concatenating the outputs of two FLASH

physical blocks. Reads of bytes, aligned halfwords, and aligned words

require one clock cycle. Misaligned read accesses are not supported

and will result in a cycle termination transfer error.

All FLASH program, erase, and verify commands operate on adjacent

FLASH physical blocks and are initiated with a single aligned 32-bit write

to the appropriate array location. Any other write operation will cause a

cycle termination transfer error. For erase purposes, a FLASH physical

block is organized as 1024 rows of 64 bytes with a single erase page

consisting of 8 rows (512 bytes). Page erase operates simultaneously on

two interleaving erase pages in adjacent FLASH physical blocks, making

the minimum effective erase size 1 Kbyte. Mass erase operates

simultaneously on two adjacent FLASH physical blocks in their entirety

and erases a total of 128 Kbytes of array space.

Each pair of FLASH physical blocks requires a banked set of registers to

cont rol pro gram and era se opera t ions. Fig ure 10- 1 shows a 512-Kbyte

module configured with four sets of banked registers. A 128 K-byte

module would only require one set, a 256-Kbyte module would require

two sets and a 384-Kbyte module would require three sets of banked

registers.

An erased FLASH bit reads 1 and a programmed FLASH bit reads 0.

The SGFM features a sense amplifier timeout block that automatically

reduces current consumption during reads at low clock frequencies.

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Second Generation FLASH for M•CORE (SGFM)

Figure 10-1. SGFM Module Block Diagram

FLASH INTERFACE

IP BUS INTER FA CE

MLB INTERFA CE

D[31:16] D[15:0] D[31:16] D[15:0]

•

SATOSATOSATOSATO

VSSF

VDDF

BIST

ENGINE

CONTROL

BANK 0

CONTROL

BANK 3

COMMON

REGISTERS

M•CORE LOCAL BUS (MLB)

BLOCK 0H

32 K x 16 BLOCK 0L

32 K x 16 BLOCK 3H

32 K x 16 BLOCK 3L

32 K x 16

IP BUS

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Second Generation FLAS H for M•CORE (SGFM)

Module Memo ry M ap

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MOTOROLA Second Generation FLASH for M•CORE (SGFM) 2 09

10.7 Module Memory Map

The SG FM me mor y array is mapped startin g at addre ss 0x0000_ 0000.

Fi gu re 10-2 shows how multiple 32,768 by 16-bit FLASH physical

blocks interleave to form a contiguous non-volatile memory space. Each

pair of blocks (upper and lower) interleave every 2 bytes to form

128 Kbytes of memory.

Figure 10-2. SGFM Array Memory Map

0x0000_0000

0x0007_ffff

0x0002_0000

BLOCK 0H ( 2BYT ES)

BLOCK 0L (2BY TES)

BLOCK 0H ( 2BYT ES)

BLOCK 0L (2BY TES)

BLOCK 1H ( 2BYT ES)

BLOCK 1L (2BY TES)

BLOCK 1H ( 2BYT ES)

BLOCK 1L (2BY TES)

BLOCK 2H ( 2BYT ES)

BLOCK 2L (2BY TES)

BLOCK 2H ( 2BYT ES)

BLOCK 2L (2BY TES)

BLOCK 3H ( 2BYT ES)

BLOCK 3L (2BY TES)

BLOCK 3H ( 2BYT ES)

BLOCK 3L (2BY TES)

0x0004_0000

0x0006_0000

128 KBYTES

•

CONF IGU R AT IO N FIE LD (0x000 0_0200–0x0000_022B)

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Second Generation FLASH for M•CORE (SGFM)

The SGFM module has hardware interlocks to protect data from

accidental corruption. The SGFM memory array is logically divided into

8-Kbyte sectors for the purpose of data protection and access control. A

flexible scheme allows the protection of any combination of logical

sectors (see 10.7.2.1 S GFM Protection Register). A similar

mechanism is available to control supervisor/user and program/data

space access to these sectors.

The SGFM configuration field comprises 44 bytes of reserved array

memory space that determines the module protection and access

restrictions out of reset. Data to secure the FLASH from unauthorized

access is also stored in the SGFM configuration field. Table 10-1

describes each byte used in this field.

The SGFM module also contains a set of control and status registers.

The memory map for these registers and their accessibility in supervisor

and user modes is shown in Ta ble 10-2.

The SGFM module contains one to four sets of banked registers

depending on the size of the array. The active register bank is selected

via the BKSEL field i n the unbanked Module Configuration Register

(SGFMCR). Each set of banked registers controls the operation of two

interleaving FLASH physical blocks such that Block 0L and Block 0H are

controlled with one register bank. Other blocks are controlled in a similar

fashion as shown in Figure 10-2.

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Table 10-1. SGFM Configuration Field
Address Size
in Bytes Description
0x0000_0200–0x0000_0 207 8 B ack door com parison key
0x0000_0208–0x0000_0209 2 FLASH program /erase secto r protection 
Blocks 0H/0L (see 10.7.2.1 SGFM Protection Register)
0x0000_020a–0x0000_020b 2 Reserved
0x0000_020c–0x0000_020d 2 FLAS H su pervisor/user space restrictions
Blocks 0H/0L (see 10.7.2.2 SGFM Supervisor Access Register)
0x0000_020e–0x0000_020f 2 FLASH program/data space restrictions
Blocks 0H/0L (see 10.7.2.3 SGFM Data Access Register)
0x0000_0210–0x0000_0211 2 FLASH program /erase secto r protection(1)
Blocks 1H/1L (see 10.7.2.1 SGFM Protection Register)
0x0000_0212–0x0000_0213 2 Reserved
0x0000_0214–0x0000_0215 2 FLASH su pervisor/user space restrictions(1)
Blocks 1H/1L (see 10.7.2.2 SGFM Supervisor Access Register)
0x0000_0216–0x0000_0217 2 FLASH program /da ta space restrictions(1)
Blocks 1H/1L (see 10.7.2.3 SGFM Data Access Register)
0x0000_0218–0x0000_0219 2 FLASH program /erase secto r protection(2)
Blocks 2H/2L (see 10.7.2.1 SGFM Protection Register)
0x0000_021a–0x0000_021b 2 Reserved
0x0000_021c–0x0000_021d 2 FLAS H su pervisor/user space restrictions(2)
Blocks 2H/2L (see 10.7.2.2 SGFM Supervisor Access Register)
0x0000_021e–0x0000_021f 2 FLASH program/data space restrictions(2)
Blocks 2H/2L (see 10.7.2.3 SGFM Data Access Register)
0x0000_021e–0x0000_0221 2 FLASH program /erase secto r protection(3)
Blocks 3H/3L (see 10.7.2.1 SGFM Protection Register)
0x0000_0222–0x0000_0223 2 Reserved
0x0000_0224–0x0000_0225 2 FLASH su pervisor/user space restrictions(3)
Blocks 3H/3L (see 10.7.2.2 SGFM Supervisor Access Register)
0x0000_0226–0x0000_0227 2 FLASH program /da ta space restrictions(3)
Blocks 3H/3L (see 10.7.2.3 SGFM Data Access Register)
0x0000_0228–0x0000_0 22b 4 FLAS H se curity word (see 10.7.1.4 SGFM Secu rity Register )
1. These confi guration bytes are onl y required for 256- Kbyte arrays and lar ger.
2. These confi guration bytes are onl y required for 384- Kbyte arrays and lar ger.
3. These confi guration bytes are onl y required for 512- Kbyte arrays.
    
  
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Table 10-2. SGFM Register Address Map

Addre ss Bits 31–24 Bits 23–16 Bits 15–8Bits 7–0 Access(1) Banked

0x00d0_0000 SGFMCR SGFMCLKD Reserved(2) SNo

0x00d0_0004 SGFMTST Reserved(2) SNo

0x00d0_0008 SGFMSEC S No

0x00d0_000c SGFMMNTR S No

0x00d0_0010 SGFMPROT Reserved(2) SYes

0x00d0_0014 SGFMSACC SGFMDACC S Yes

0x00d0_0018 SGFMTSTAT Reserved(2) SYes

0x00d0_001c SGFMUSTAT Reserved(2) SYes

0x00d0_0020 SGFMCMD Reserved(2) SYes

0x00d0_0024 SGFMCTL SGFMADR S Yes

0x00d0_0028 SGFMDATA S Yes

0x00d0_002c–

0x00d0_003c Unimplemented(3) —Yes

1. S = Supervi sor access only. User mode accesses to supe rvi sor only addresses have no effec t and result in a cycl e termi-

nation transfer error.

2. Writ es to reserved address locations have no effect and reads return 0s.

3. Accesses to unimplem ented address es have no effect and resul t in a cycl e termination t ransfer error.

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10.7.1 Unbanked Register Descriptions

The unbanked registers are described in this subsection.

10.7.1.1 SGFM Configuration Register

The S GF M Conf iguration Registe r ( SGFMC R) is unba nked and is u sed

to configure and control the operation of the SGFM array and bus

interface unit (BIU).

FRZ — Freeze Enable Bit

The F RZ bit is readabl e and wr itable in all modes. I n deb ug mode t he

SGFM behaves exactly as it does in user mode except that the LO CK

bit in SGFMCR and SGFMCLKD[6:0] bits are writable.

1 = Enter debug mode if debug signal on MLB is asserted

0 = Ignore debug mode if debug signal on MLB is asserted

EME — Emulation Enable Bit

The EM E bit is always readable and only writable when LOCK = 0.

EME places the SGFM in emulation mode, during which the SGFM

BIU will not assert TA or TEA to terminate read bus cycles of the

Address: 0x00d0_0000 and 0x00d0_0001

Bit 15 14 13 12 11 10 9 Bit 8

Read: 0 FRZ 0EME 0LOCK 00

Write:

Reset:000Note 10000

Bit 76 54321Bit 0

Read: CBEIE CCIE KEYACC 000

BKSEL1 BKSEL0

Write:

Reset:00000000

= Reserved

Note 1. Reset state determined by chip reset configurati on.

Figure 10-3. SGFM Module Configuration Register (SGFMCR)

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SGFM array. Instead, external memory that emulates the FLASH

must drive the data bus, and the EBI emulation chip select

mechanism terminates the bus cycle instead of the SGFM.

NOTE: In emulation mode, writes to the SGFM ar ray will generate an SGFM

access err or and set the A CCERR bit (see 10 .8.3.4 FLASH User Mode

Illegal Operations).

1 = Emulation mode

0 = User mode

LOCK — Write Lock Control Bit

The LOCK bit i s always readable but can only be set once in user

mode. In debug or test mode, the LOCK bit is always writable.

1 = The EME bit, SGFMPROT, SGFMSACC, and SGFMDACC

registers are write-locked

0 = The EME bit, SGFMPROT, SGFMSACC, and SGFMDACC

registers are writable

CBEIE — Command Buffer Empty Interrupt Enable Bit

The CBEIE bit is readable and writable in all modes. CBEIE enables

an interrupt request when the command buffer for the FLASH

physical blocks selected by BKSEL[1:0] is empty.

1 = Request an interr upt whenever the CBEIF flag is set.

0 = Command buffer empty interrupts disabled

CCIE — Command Complete Interrupt Enable Bit

The CC IE bit is r eadab le and wr itabl e in all mod es. CC IE enabl e s an

interrupt when the command executing for the FLASH physical blocks

selected by BKSEL[1:0] is complete.

1 = Request an interrupt whenever the CCIF fl ag is set.

0 = Command complete interrupts disabled

KEYACC — Enable Security Key Writing Bit

The KEYACC bit is readable in all modes and only writable if the

KEYEN bit in the SGFMSEC register is set.

1 = Writ es to the FLA S H arr ay are interp rete d as keys to open the

back door.

0 = Writes to the FLASH array are interpreted as the start of a

program, erase, or verify sequence.

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BKSEL[1:0] — Register Bank Select Field

The BKSEL bits are readable and writable in all modes and select

which set of bank registers is accessible.

Table 10-3 shows which set of banked registers is selected by the

BKSEL field depending on the size of the FLASH memory array.

10.7.1.2 SGFM Clock Divider Register

The SGFM Clock Divider Register (SGFMCLKD) is unbanked and is

used to set th e freq uency of th e cl ock used fo r time d events in p rogr am

and erase algorithms.

In user mode, all bits in SGFMCLKD are readable while bits 6–0 can only

be written once. In test and debug modes, all bits in SGFMCLKD are

readable and writable at anytime, except bit 7 which is a status-only bit

and is not writable in any mode.

Table 10-3. Regist er Bank Select Decoding

BKSEL[1:0] 128 Kbytes 256 Kbytes 3 84 Kbytes 512 Kbytes

00 Bank 0 Bank 0 Bank 0 Bank 0

01 Bank 0 Bank 1 Bank 1 Bank 1

10 Bank 0 Bank 0 Bank 2 Bank 2

11 Bank 0 Bank 1 Bank 2 Bank 3

Address: 0x00d0_0002

Bit 76 54321Bit 0

Read: DIVLD PRDIVDIV5DIV4DIV3DIV2DIV1DIV0

Write:

Reset:00000000

= Reserved

Figure 10-4. SGFM Clock Divider Register (SGFMCLKD)

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DIVLD — Clock Divider Loaded Bit

1 = SGFMCLKD has been written since the last reset.

0 = SGFMCLKD has not been written.

PRDIV8 — Enable Prescaler Divide by 8 Bit

1 = Enabl es a prescaler that di vides the SGFM clock by 8 be fore it

enters the SGFMCLKD divider.

0 = The SGFM clock is fed directly into the SGFMCLKD divider.

DIV[5:0] — Clock Divider Field

The combination of PRDIV8 and DIV[5:0] effectively divides the

SGFM input clock down to a frequency between 150 kHz and

200 kHz. The frequency range of the SGFM clock is 150 kHz to

102.4 MHz.

NOTE: SGFMCLKD must be written with an appropriate value before

programming or erasing the FLASH array. Refer to 10.8.3.1 Set ting the

SGFMCLKD Register.

10.7.1.3 SGFM Test Register

The S GFM Test Re gister (S GFMT ST) is u nbanke d and is u sed on ly f or

factory testing.

Accesses to SGFMTST when not in test mode will result in a cycle

termination transfer error.

Address: 0x00d0_0004

Bit 76 54321Bit 0

Read: RSVD7 RSVD6 RSVD5 RSVD4 00

RSVD1 RSVD0

Write:

Reset:00000000

= Reserved

Figure 10-5. SGFM Test Register (SGFMTST)

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10.7.1.4 SGFM Security Register

The SGFM Security Register (SGFMSEC) is unbanked and controls the

FLASH security features.

SGFMSEC is readable in all modes but is not writable in any mode.

Address: 0x00d0_0008 through 0x00d0_000b

Bit 31 30 29 28 27 26 25 Bit 24

Read: KEYEN SECSTAT 000000

Write:

Reset: F(1) Note 2000000

Bit 23 22 21 20 19 18 17 Bit 16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Read: SEC15 SEC14 SEC13 SEC12 SEC11 SEC10 SEC9 SEC8

Write:

Reset: F(1) F(1) F(1) F(1) F(1) F(1) F(1) F(1)

Bit 7654321Bit 0

Read: SEC7 SEC6 SEC5 SEC4 SEC3 SEC2 SEC1 SEC0

Write:

Reset: F(1) F(1) F(1) F(1) F(1) F(1) F(1) F(1)

= Reserved

Notes:

1. Reset state loaded from FLASH configuration field during reset.

2. Reset state determined by security state of module.

Figure 10-6. SGFM Security Register (SGFMSEC)

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SGFMSEC register bits with a reset state denoted by F in Figure 10-6

are loaded from the FLASH configuration at address 0x0000_0228

during the reset sequence.

KEYEN — Enable B a ck Door Key to Security Bit

1 = Back door to FLASH is enabled.

0 = Back door to FLASH is disabled.

SECSTAT — FLASH Security Status Bit

1 = FLASH security is enabled

0 = FLASH security is disabled

SEC[15:0] — Security Field

The SEC bits define the security state of the device. Table 10-4 lists

the single code that enables security.

The security features of the SGFM are described in 10.9 FLASH

Security Operation.

Table 10-4. Security States

SEC[15:0] Description

$000B FL ASH secured(1)

1. The $000B value was chosen because it represents the M•CORE TRAP #3 opcode,

maki ng i t unlikely that com pi led code accidentally programmed at the security word

in the FLASH conf iguration field location would unint entionally sec ure the devi ce.

All other combinations FLA SH unsecured

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10.7.1.5 SGFM Monitor Data Register

The SGFM Monitor Data Register (SGFMMNTR) is unbanked and is

used only for factory testing.

Accesses to SGFMMNTR when not in test mode will result in a cycle

termination transfer error.

Address: 0x00d0_000c through 0x00d0_000f

Bit 31 30 29 28 27 26 25 Bit 24

Read: RSVD31 RSVD30 RSVD29 RSVD28 RSVD27 RSVD26 RSVD25 RSVD24

Write:

Reset: Note 1

Bit 23 22 21 20 19 18 17 Bit 16

Read: RSVD23 RSVD22 RSVD21 RSVD20 RSVD19 RSVD18 RSVD17 RSVD16

Write:

Reset: Note 1

Bit 15 14 13 12 11 10 9 Bit 8

Read: RSVD15 RSVD14 RSVD13 RSVD12 RSVD11 RSVD10 RSVD9 RSVD8

Write:

Reset: Note 1

Bit 76 54321Bit 0

Read: RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 RSVD1 RSVD0

Write:

Reset: Note 1

= Reserved

Note 1. SGFMMNTR does not have a default r eset state.

Figure 10 -7. SGFM Monitor Da ta Regis ter (SGFMMNTR)

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10.7.2 Banked Register Descriptions

The banked registers are described in this subsection.

10.7.2.1 SGFM Protection Register

The SGFM Protection Register (SGFMPROT) is banked and specifies

which FLASH logical sectors are protected from program and erase

operations.

The SGFMPROT register is always readable and only writable when

LOCK = 0. To change which logical sectors are protected on a

tempor ary basi s, write SGFM PROT w ith a new valu e after the LOCK bi t

in SGFMCR has been c leared. To change the value of SGFMPROT that

will be loaded on reset, the pr otection byte in the FLASH configuration

field must be reprogrammed for the interleaved FLASH physical blocks

currently selected by BKSEL[1:0]. If necessary, the logical sector

containing the FLASH configuration field must be temporarily

unprotected usi ng the m ethod just de scri bed be fore re prog ram ming the

protection bytes.

PROT[15:0] — Sector Protection Bits

Each FLASH logical sector can be protected from program and erase

operations by setting its corresponding PROT bit.

1 = Logical sector is protected.

0 = Logical sector is not protected.

Address: 0x00d0_0010 and 0x00d0_0011

Bit 15 14 13 12 11 10 9 Bit 8

Read: PROT15 PROT14 PROT13 PROT12 PROT11 PROT10 PROT9 PROT8

Write:

Reset: F(1) F(1) F(1) F(1) F(1) F(1) F(1) F(1)

Bit 76 54321Bit 0

Read: PROT7 PROT6 PROT5 PROT4 PROT3 PROT2 PROT1 PROT0

Write:

Reset: F(1) F(1) F(1) F(1) F(1) F(1) F(1) F(1)

Note 1. Reset state l oaded from FLASH configuration field during res et.

Fi gu re 10-8 . SG FM Pr ot ectio n Re gist er (SGFM PR OT )

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Each banked SGFMPROT register controls the protection of sixteen

8-Kbyte FLASH logical sectors in a 128-Kbyte bank of memory (two

interleaved FLASH physical blocks). Figu re 10-9 shows the association

between each bit in the SGFMPROT register and its corresponding

logical sector.

Figure 10-9. SGFMPROT Protection Diagram

SECTOR 15

SECTOR 14

SECTOR 13

SECTOR 12

SECTOR 11

SECTOR 10

SECTOR 9

SECTOR 8

SECTOR 7

SECTOR 6

SECTOR 5

SECTOR 4

SECTOR 3

SECTOR 2

SECTOR 1

SECTOR 0

SECTOR 15

SECTOR 14

SECTOR 13

SECTOR 12

SECTOR 11

SECTOR 10

SECTOR 9

SECTOR 8

SECTOR 7

SECTOR 6

SECTOR 5

SECTOR 4

SECTOR 3

SECTOR 2

SECTOR 1

SECTOR 0

SECTOR 15

SECTOR 14

SECTOR 13

SECTOR 12

SECTOR 11

SECTOR 10

SECTOR 9

SECTOR 8

SECTOR 7

SECTOR 6

SECTOR 5

SECTOR 4

SECTOR 3

SECTOR 2

SECTOR 1

SECTOR 0

SECTOR 15

SECTOR 14

SECTOR 13

SECTOR 12

SECTOR 11

SECTOR 10

SECTOR 9

SECTOR 8

SECTOR 7

SECTOR 6

SECTOR 5

SECTOR 4

SECTOR 3

SECTOR 2

SECTOR 1

SECTOR 0

PROT1

PROT0

8-KBYT E LOGICAL SEC T OR

PROT13

PROT12

0x0001_e000

0x0001_ffff

{

0x0007_e000

0x0007_ffff

0x0005_e000

0x0005_ffff

0x0003_e000

0x0003_ffff

0x0006_0000

0x0006_2000

0x0004_0000

0x0004_2000

0x0002_0000

0x0002_2000

0x0000_0000

0x0000_2000

BKSEL[1:0]

= %11

BKSEL[1:0]

= %10

BKSEL[1:0]

= %01

BKSEL[1:0]

= %00

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10.7.2.2 SGFM Supervisor Access Register

The SGFM Supervisor Access Register (SGFMSACC) is banked and

specifies the supervisor/user access permissions of FLASH logical

sectors.

SUPV[15:0] — Supervisor Address Space Assignment Bits

The SUP V[15:0] bits are always readable and only writable when

LOCK = 0. Each FLASH logical sector can be mapped into supervisor

or unrestricted address space. SGFMSACC uses the same

correspondence between logical sectors and register bits as does

SGFMPROT. See Figure 10-9 for details.

When a logical sector is mapped into supervisor address space, only

CPU supervisor accesses will be allowed. A CPU user access to a

location in sup ervisor addr ess space will result in a cycle te rmin ation

transfer error. When a logical sector is mapped into unrestricted

address space both supervisor and user accesses ar e allowed.

1 = Logical sector is mapped in supervisor address space.

0 = Logical sector is mapped in unrestricted address space.

Address: 0x00d0_0014 and 0x00d0_0015

Bit 15 14 13 12 11 10 9 Bit 8

Read: SUPV15 SUPV14 SUPV13 SUPV12 SUPV11 SUPV10 SUPV9 SUPV8

Write:

Reset: F(1) F(1) F(1) F(1) F(1) F(1) F(1) F(1)

Bit 76 54321Bit 0

Read: SUPV7 SUPV6 SUPV5 SUPV4 SUPV3 SUPV2 SUPV1 SUPV0

Write:

Reset: F(1) F(1) F(1) F(1) F(1) F(1) F(1) F(1)

Note 1. Reset state l oaded from FLASH configuration field during res et.

Figure 10- 1 0. SGFM Supervisor Access Register (SGFMASACC)

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10.7.2.3 SGFM Data Access Register

The SGFM Data Access Register (SGFMDACC) is banked and specifies

the data/program access pe rmissions of FL ASH logical sectors.

DATA[15:0] — Data Address Space Assignment Bits

The DATA[15:0] bits are always readable and only writable when

LOCK = 0. Each FLASH logical sector can be mapped into data or

both data and program address space. SGFMDACC uses the same

correspondence between logical sectors and register bits as does

SGFMPROT. See Figure 10-9 for details.

When a logical sector is mapped into data address space, only CPU

data accesses will be allowed. A CPU program access to a location

in data addre ss space will result in a cycle termination transf er error.

When an arr ay sector is mapped i nto bo th data a nd program address

space both data and program accesses are allowed.

1 = Logical sector is mapped in data address space.

0 = Logical sector is mapped in data and program address space.

Address: 0x00d0_0016 and 0x00d0_0017

Bit 15 14 13 12 11 10 9 Bit 8

Read: DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8

Write:

Reset: F(1) F(1) F(1) F(1) F(1) F(1) F(1) F(1)

Bit 76 54321Bit 0

Read: DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0

Write:

Reset: F(1) F(1) F(1) F(1) F(1) F(1) F(1) F(1)

Note 1. Reset state l oaded from FLASH configuration field during res et.

Figure 10-11. SGFM Data Access Register (SGFMDACC)

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10.7.2.4 SGFM Test Status Register

The SGFM Test Status Register (SGFMTSTAT) is banked and is used

only for factory testing.

Accesses to SGFMSTAT when not in test mode will result in a cycle

termination transfer error.

10.7.2.5 SGFM User Status Register

The SGFM User S tatus Register (SGFMUSTAT) is banked reports

FLA SH stat e mach ine com mand status, a rray a ccess er rors, prote ction

violations, and blank check status.

SGFM UST AT bits 7, 5 , 4, and 2 ar e r eadab le and wri tab le i n a ll modes.

Bits 3, 1, and 0 always read 0 and writes have no effect. Bit 6 is a

read-only bit in all modes.

NOTE: Only one SGFMTUSTAT bit should be cleared at a time.

Address: 0x00d0_0018

Bit 76 54321Bit 0

Read: 0 0 0 0 RSVD3 0RSVD1 RSVD0

Write:

Reset:00000000

= Reserved

Figure 10-12. SGFM Test Status Register (SGFMT STAT)

Address: 0x00d0_001c

Bit 76 54321Bit 0

Read: CBEIF CCIF PVIOL ACCERR 0BLANK 00

Write:

Reset:11000000

= Reserved

Figure 10-13. SGFM User Status Register (SGFMUSTAT)

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CBEIF — Command Buffer Empty Interrupt Flag

The CB EIF flag in dicates that the co mmand bu ffer for the interlea ved

FLASH physical blocks selected by BKSEL[1:0] is empty and that a

new command sequence can be started. Clear CBEIF by writing it

to 1. Writing a 0 to CBEIF has no effect but can be used to abort a

command sequence. The CBEIF bit can trigger an interrupt request if

the CBEIE bit is set in SGFMMCR. While CBEIF is clear, the

SGFMCMD register is not writable.

1 = Command buffer is ready to accept a new command.

0 = Command buffer is full.

CCIF — Command Complete Interrupt Flag

The CCIF flag indicates that no commands are pending for the

FLASH physical blocks selected by BKSEL[1:0]. CCIF is set and

cleared automatically upon start and completion of a command.

Writing to CCIF has no effect. The CCIF bit can trigger an interrupt

request if the CCIE bit is set in SGFMCR.

1 = All commands are completed

0 = Command in progress

PVIOL — Protection Violation Flag

The PVIOL flag indicates an atte mpt was made to initiate a program

or e rase ope ration i n a FLASH logi cal secto r denote d as pr otected b y

SGFM PROT. Clea r PVIOL by w riting it to 1. Writ ing a 0 to PVIOL has

no effect. W hile PVIOL is set in any banked registe r, it is not possible

to launch another command.

1 = A protection violation has occurred

0 = No failure

ACCERR — Access Error Flag

The ACCE RR flag indicates an illegal access to the SGFM array or

registers caused by a bad program or erase sequence. ACCERR is

clea red by writing it to 1. Writing a 0 to A CCERR has no effect. While

ACCERR is set in any banked register, it is not possible to launch

another command. See 10.8.3.4 FLASH User Mode Illegal

Operations for details on what sets the ACCERR flag.

1 = Access error has occurred

0 = No failure

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BLANK — Erase Verified Flag

The BL ANK flag indic ates that the era se verify command (RDARY1)

has checked the two interleaved FLASH physical blocks selected by

BKSL[1:0] and found them to be blank. Clear BLANK by writing it to 1.

Writing a 0 has no effect.

1 = FLASH physical blocks verify as erased.

0 = If an erase verify comm and has bee n requeste d, and the CCIF

flag is set, then the selected FLASH physical blocks are not

blank.

10.7.2.6 SGFM Command Register

The SGFM Command Register (SGFMCMD) is banked and is the

written.

SGFMCMD is reada ble and writa ble in all modes. Writes to bit 7 have no

effect and reads return 0.

CMD[6:0] — Command Field

Valid FLASH use r mode commands are shown in Table 10-5. Writing

a command in user mode other than those listed in Table 10-5 will set

the ACCERR flag in SGFMUSTAT.

Address: 0x00d0_0020

Bit 76 54321Bit 0

Read: 0 CMD6 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0

Write:

Reset:00000000

= Reserved

Figure 10-14. SGFM Command Register (SGFMCMD)

Table 10-5. SGFMCMD User Mode Commands

Command Name Description

$05 RDARY1 Erase verify (all 1s)

$20 PGM Word program

$40 PGERS Page eras e

$41 MASERS Mass erase

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10.7.2.7 SGFM Control Register

The SG FM Control Register (SG FMCTL) is banke d a nd is u sed only for

factory testing.

Accesses to SGFMCTL when not in test mode will result in a cycle

termination transfer error.

Address: 0x00d0_0024 and 0x00d0_0025

Bit 15 14 13 12 11 10 9 Bit 8

Read: RSVD15 0000000

Write:

Reset:00000000

Bit 76 54321Bit 0

Read: RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 RSVD1 RSVD0

Write:

Reset:00000000

= Reserved

Figure 10-15. SGFM Control Register (SGFMCTL)

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10.7.2.8 SGFM Address Register

The SGFM Address Register (SGFMADR) is a banked register and is

used only for factory testing.

Access to SGFMADR when not in test mode will result in a cycle

termination transfer error.

Address: 0x00d0_0026 and 0x00d0_0027

Bit 15 14 13 12 11 10 9 Bit 8

Read: 0 RSVD14 RSVD13 RSVD12 RSVD11 RSVD10 RSVD9 RSVD8

Write:

Reset:00000000

Bit 76 54321Bit 0

Read: RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 RSVD1 RSVD0

Write:

Reset:00000000

= Reserved

Figure 10-16. SGFM Address Register (SGFMADR)

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10.7.2.9 SGFM Data Register

The SGFM Data Register (SGFMDATA) is a banked register and is used

only for factory testing.

Accesses to SGFMDATA when not in test mode will result in a cycle

termination transfer error.

Address: 0x00d0_0028 through 0x00d0_002b

Bit 31 30 29 28 27 26 25 Bit 24

Read: RSVD31 RSVD30 RSVD29 RSVD28 RSVD27 RSVD26 RSVD25 RSVD24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 Bit 16

Read: RSVD23 RSVD22 RSVD21 RSVD20 RSVD19 RSVD18 RSVD17 RSVD16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Read: RSVD15 RSVD14 RSVD13 RSVD12 RSVD11 RSVD10 RSVD9 RSVD8

Write:

Reset:00000000

Bit 76 54321Bit 0

Read: RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 RSVD1 RSVD0

Write:

Reset:00000000

Figure 10-17. SGFM Data Register (SGFMDATA)

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10.8 SGFM User Mode

Normal operation of the SGFM occurs in user mode. The SGFM

registers, subject to the restrictions previously noted, can generally be

read and written. Reads of the SGFM array generally occur normally and

writes behave according to the setting of the KEYACC bit in SGFMCR.

Prog ram , erase , and ver ify opera ti ons are i nitiated by th e C PU. Special

cases of user mode apply when the CPU is in low power or debug modes

and when the MCU boots in master mode or emulation mode.

10.8.1 Read Op erations

A vali d read oper ation o ccurs wheneve r a transfe r request is initiated by

the M•CORE, the MLB address is equal to an address within the valid

range of t he SGFM m emor y space, a nd the r ead/w rit e contr ol indi cates

a read cycle. A ligned read acce sses (byte , halfword, or wor d) com plete

in one system clock cycle. Misaligned accesses are not allowed and

result in a cycle termination transfer error.

In order to reduce power at low system clock frequencies, the sense

amplifier timeout (SATO) block minimizes the time during which the

sense amplifiers are enabled for read operations. The sense amplifier

enable signals to the FLASH timeout after approximately 50 ns.

10.8.2 Write Operations

A valid wr ite oper ation occur s whenever a tr ansfer r equest is initiated by

the M•CORE, the MLB address is equal to an address within the valid

range of t he SGFM m emor y space, a nd the r ead/w rit e contr ol indi cates

a write cycle.

The acti on taken on a valid SGFM array write depends on the

subsequent user command issued as part of a valid command

sequence . Only aligned 32-bit write operations are allowed to the SGFM

array. Byte and halfword write operations will result in a cycle termination

transfer error.

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10.8.3 Program and Erase Operations

Read and write operations are both used for the program and erase

algorithms described in this subsection. These algorithms are controlled

by a state machine whose timebase is derived from the SGFM module

clock via a programmable counter.

The command register and associated address and data buffers operate

as a two stage FIFO so that a new command along with the necessary

address and data can be stored while the previous command is still in

progress. This pipelining speeds when programming more than one

wor d on a specific row , as the charg e pumps can be kept on in between

two programming commands, thus saving the overhead needed to setup

the ch arge pumps. Buffer empty and command completion are indicated

by flags in the SGFM User Status Register . Interrupts will be requested

if enabled.

10.8.3.1 Setting the SGFMCLKD Register

Prior to issuing any progr am or erase commands, S GFMCLKD must be

written to set the FLASH state machine clock (FCLK). The SGFM

module runs at the system clock frequency, but FCLK must be divided

down from the system clock to a frequency between 150 kHz and

200 kHz. Use the following procedure to set the PRDIV8 and DIV[5:0]

bi ts in SG FM CLKD:

1. If fSYS is greater than 12.8 MHz, PRDIV8 = 1, otherwise

PRDIV8 = 0.

2. Determine DIV[5:0] by using the following equation. Keep only the

integer portion of the result and discard any fraction. Do not round

the result.

3. Thus the FLASH state machine clock will be:

fSYS

1 + (PRDIV8 x 7)

200 kHz

DIV[5:0] =

fSYS

1 + (PRDIV8 x 7)

DIV[5:0] + 1

FCLK =

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Consider the following example for fSYS = 33 MHz:

So, for fSYS = 33 MHz, writing $54 to SGFMCLKD will set FCLK to

196.43 kHz which is a valid frequency for the timing of program and

erase operations.

WARNING: For prope r pr og ra m and er ase o per ati ons , it is cr itica l to se t FC LK

betwe en 150 kHz and 200 kHz. Array damage due to overstress can

occur when FCLK is less than 150 kHz. Incomplete programming

and erasure can occur when FCLK is greater th an 200 kHz.

NOTE: Command execution time increases proportionally with the period of

FCLK.

When SGFMCLKD is written, the DIVLD bit is set automatically. If DIVLD

is 0, SGFMCLKD has not been written since the last reset. Program and

erase commands will not execute i f this register has not been written

(see 10.8.3.4 FLASH User Mode Illegal Operations).

10.8.3.2 Program, Erase, and Verify Sequences

A com man d state mac hine i s u sed to supe rvis e th e write sequ enci ng of

program, erase, and verify commands. Before any command write

sequence is sta rted, it is necessa ry to write the B KSEL fi eld SGFM MCR

to select the banked set of registers associated with the FLASH physical

blocks to be prog ram med or erase d (see Figure 10-2 for more details).

To prepare for a command, the CBEIF flag should be tested to ensure

that th e addre ss, da ta, and c ommand buffers ar e empty. If CBEIF is set ,

the command write sequence can be started.

fSYS

1 + (PRDIV8 x 7)

200 kHz

DIV[5:0] =

fSYS = 12.8 MHz, so PRDIV8 = 1

33 M Hz

1 + (1 x 7 )

200 kHz

== 20

fSYS

1 + (PRDIV8 x 7)

DIV[5:0] + 1

FCL K =

33 MHz

1 + (1 x 7)

20 + 1

= = 196.43 k Hz

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Second Generation FLAS H for M•CORE (SGFM)

SGFM User Mode

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Informa tion

MOTOROLA Second Generation FLASH for M•CORE (SGFM) 2 33

This three-step command write sequence must be strictly followed. No

intermediate writes to the SGFM module are permitted between these

three steps. The command write sequence is:

1. Write the 32-bit word to be programmed to its location in the

SGFM array. The address and data will be stored in internal

buffers. All address bits are valid for program commands. The

value of the data written for verify and erase commands is ignored.

For mass erase or verify, the address can be any location in the

SGFM array. For page erase, address bits [9:0] are ignored.

NOTE: The page erase command operates simultaneously on adjacent erase

pages in two interleaved FLAS H physical blocks. Thus, a single erase

page is effectively 1 Kbyte.

2. Write the program, erase, or verify command to SGFMCMD, the

command buffer. See 10.8.3.3 FLAS H User Mode Valid

Commands.

3. Launch the command by writing a 1 to the CBEIF flag. This will

clear CBEIF. When command execution is complete, the FLASH

state machine will set the CCIF flag. The CBEIF flag will also be

set again, in dicating that the address, data, an d comma nd buffer s

are ready for a new command sequence to begin.

NOTE: On devices with 256 Kbytes of FLASH or more, concurrent command

execution is possible. After a command is launched for the FLASH

physical blocks serviced by the current set of banked registers,

BKSEL[1:0] can be changed in order to launch a command for another

pair of FLASH physical blocks. A command launched for one pair of

FLASH physical blocks will not interfere with the execution of commands

launched for other FLASH physical blocks and will only set the CCIF flag

in the SGFMUSTAT register selected by BKSEL[1:0] at the time the

command was launched.

The FLASH state machine will flag errors in command write sequences

by means of the ACCERR and PVIOL flags in the SGFMUSTAT register.

An erroneous command write sequence will self-abort and set the

appropriate flag. The ACCERR or PVIOL flags must be cleared before

commencing another command write sequence.

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Second Generation FLASH for M•CORE (SGFM)

NOTE: B y wri ting a 0 to CBEIF , a command sequ ence can be aborted after the

word write to the SGFM array or the command write to the SGFMCMD

and before the command is launched. The ACCERR flag will be set on

aborted commands and must be cleared before a new command write

sequence.

A summary of the programming algorithm is shown in Figure 10-18. The

flow is similar for the erase and verify algorithms with the exceptions

noted in step 1 above.

10.8.3.3 FLASH User Mode Valid Commands

Table 10-6 summarizes the val id FLASH user commands.

Table 10-6. FLASH User Mode Commands

SGFMCMD Meaning Description

$05 Erase

verify

Verify that all 128 Kbytes of FLASH from two

interleavi ng physical blocks are erased. If both blocks

are e r as e d, the B LA N K bit w ill s e t in t he SG FMU S TAT

$20 Program Program a 32-bit word.

$40 Page

erase

Erase 1 Kbyte of FLASH. Two 512 byte pages from

interle aving physical blocks are erased in this

operation.

$41 Mass

erase

Erase all 128 Kbytes of FLASH from two interleaving

physical blocks. A mass erase is only possible when no

PROT E CT bits are set for t hat block.

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Second Generation FLAS H for M•CORE (SGFM)

SGFM User Mode

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Informa tion

MOTOROLA Second Generation FLASH for M•CORE (SGFM) 2 35

Figu re 10-1 8. Exam ple Prog ram Algor ith m

WRIT E SGF M C LKD

READ SGFM C LKD

DIVLD SET ?

WRITE PR OGRA M DA TA

WRITE PR OGRA M CO MMA ND $2 0

TO SGFMCMD

WRITE $80 TO CLEAR SGFMUSTAT

YES

CBEIF BI T

YES

CLOCK REGISTE R

WRITTE N CH E CK

SGFMUSTA T ACCERR B IT

WRITE $10 TO CLEAR

YES

PROTECTION

VIOL AT IO N CHE CK

ACCESS

ERROR CHE CK

READ SGFM U ST AT

ADDRESS, DATA,

COMMA ND BUFFER

EMPTY CHECK NEXT WRITE?

YES

TO ARRAY ADDRESS

SGFMUSTAT PVIOL BIT

WRITE $20 TO CLEAR

YES

BIT POLLING

FO R CO MMAND

COMPL ET IO N CHE CK

READ SGFMUSTAT

YES

NOTE: COMMAND SEQUENCE

ABORTED BY WRITING $00

TO SGFMUSTAT

NOTE: COMMAND SEQUENCE

ABORTED BY WRITING $00

TO SGFMUSTAT

EXIT

REA D SGFMUSTAT

START

YES

CBEIF

SET?

PVIOL

SET?

ACCERR

SET?

CBEIF

SET?

CCIF

SET?

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236 Second Generation FLASH for M•CORE (SGFM) MO TOROLA

Second Generation FLASH for M•CORE (SGFM)

10.8.3.4 FLASH User Mode Illegal Operations

The ACCERR flag will be set during a comm and write sequence if any

of the illegal operations below are performed. Such operations will cause

the command sequence to immediately abort.

1. Writing to the SGFM array before initializing SGFMCLKD.

2. Writing to the SGFM array while in emulation mode.

3. Writing a byte or a halfword to the SGFM array. Only 32-bit word

programming is allowed.

4. Writing to the SGFM array at a location that does not match

BKSEL[1:0]. Depending on the size of the FLASH array. MLB

address bits [18:17] must match BKSEL[1:0].

5. Writing to the SGFM array while CBEIF is not set.

6. Writing a second word to the SGFM array before executing a

command on the previously written word.

7. Writing an invalid user command to the SGFMCMD.

8. Writing to any SGFM other than SGFMCMD after writing a word to

the SGFM array.

9. Writing a second command to SGFMCMD before executing the

previously written command.

10. Writing to any SGFM register other than SGFMUSTAT (to clear

CBEIF) after writing to the command register.

11. Entering stop mode while a program or er ase command is in

progress.

12. Aborting a command sequence by writing a 0 to CBEIF after the

word write to the SGFM array or after writing a command to

SGFMCMD and before launching it.

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Second Generation FLAS H for M•CORE (SGFM)

SGFM User Mode

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Informa tion

MOTOROLA Second Generation FLASH for M•CORE (SGFM) 2 37

The PVIOL flag will be set during a command write sequence after the

word write to the SGFM array if any of the illegal operations below are

performed. Such operations will cause the command sequence to

immediately abort.

1. Writing to an address in a protected area of the SGFM array.

2. Writing a mass erase command to SGFMCMD while any logical

sector is protected (see 10.7.2.1 SGFM Protection Register).

If a FLASH physical block is read during a program or erase operation

on that block ( SG FMUSTAT bit CCIF = 0) , the read will ret urn non- valid

data and the ACCERR flag will not be set.

10.8.4 Stop Mode

If a comma nd is active (CC IF = 0) when the MCU enter s stop mod e, the

command sequence monitor will perform the following:

1. The command in progress will be aborted.

2. The FLASH high voltage circuitry will be switched off and any

pending command (CBEIF = 0) will not be executed when the

MCU exits stop mode.

3. The CCIF and ACCERR flags will be set if a command is active

when the MCU enters stop mode.

NOTE: The state of any word(s) being programmed or any erase pages/physical

blocks being erased is not guaranteed if the MCU enters stop mode with

a command in progress.

WARNING: Active commands are immediately aborted when the MCU enters

stop mode. Do not execute the STOP instruction during program

and erase operations.

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238 Second Generation FLASH for M•CORE (SGFM) MO TOROLA

Second Generation FLASH for M•CORE (SGFM)

10.8.5 Master Mod e

If the MC U is boot ed in ma ster m ode wi th a n exter nal mem ory se lected

as the boot device, the SGFM will not respond to the first transfer request

out of reset, even if the MLB address is equal to an address within the

SGFM array. Th is will allow the external boot device to pr ovide the reset

vector and terminate the bus cycle.

10.8.6 Emulation Mode

In emulation mode, the SGFM module will not terminate the bus cycles

by assertin g TA or TEA in response to array read requests. External

memory that emulates the FLASH will drive the data bus and the EBI

emulation chip mechanism will terminate the bus cycle instead of the

SGFM module.

NOTE: In emulation mode, write accesses to the SGFM array will generate an

SGFM access error and set the ACCERR bit.

10.8.7 Debug Mode

In debug mode, the SGFM module behaves exactly as it does in user

mode, except that the LOCK bit in SGFMMCR and the SGFMCLKD[6:0]

10.9 FLASH Security Operation

The SGFM arr ay provid es se curity infor mation to the inte gratio n module

and th e r est of the MCU . A wor d in the F LASH configur ation fi eld store s

this information. This word is read automatically after each reset and is

stored in the SGFMSEC register.

In user mode, security can be bypassed via a back door access scheme

using an 8-byte long key. Upon successful completion of the back door

access sequen ce, the module output signal and status bit indicating that

the chip is secure are cleared.

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Second Generation FLAS H for M•CORE (SGFM)

FLASH Security Operation

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Informa tion

MOTOROLA Second Generation FLASH for M•CORE (SGFM) 2 39

The SGFM may be unsecured via one of two methods:

1. Executing a back door access scheme.

2. Passing an erase verify check.

10.9.1 Back Door Access

If the KEYEN bit is set, security can be bypassed by:

1. Setting the KEYACC bit in the SGFM Configuration Register

(SGFMMCR).

2. Writin g the co rrect 8-byte back door com parison ke y to the SGFM

array at ad dresses 0 x0000_ 0200 to 0x0000_ 0207. T his oper ation

must consist of two 32-bit writes to address 0x0000_0200 and

0x0000_0204 in that order. The two back door write cycles can be

separated by any number of bus cycles.

3. Clearing the KEYACC bit.

4. If all 8 bytes written match the array contents at addresses

0x0000_ 0200 to 0x0000_02 07, then security is bypassed until the

next reset.

NOTE: The security of the FLASH as defined by the FLASH security word at

address 0x0000_0228 is not changed by the back door method of

unsecuring the device. After the next reset the device is again secured

and the same back door key remains in effect unless changed by

program or erase operations. The back door method of unsecuring the

device has no effect on the program and erase protections defined by

the SGFM Protection Register (SGFMP ROT).

10.9.2 Erase Verify Check

Security can be disabled by verifying that the SGFM array is blank. If

required, the mass erase command can be executed for each pair of

FLASH physical blocks that comprise the array. The erase verify

command must then be executed for all FLASH physical blocks within

the array. The SGFM will be unsecured if the erase verify command

determines that the entire array is blank. After the next reset, the security

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240 Second Generation FLASH for M•CORE (SGFM) MO TOROLA

Second Generation FLASH for M•CORE (SGFM)

state of the SGFM will be determined by the FLASH security word,

which, after being erased , will read 0xffff_ffff, thus unsecuring the

module.

10.10 Resets

The SGFM array is not accessible for any operations via the address and

data buses during reset. If a reset occurs while any command is in

progress that command will immediately abort. The state of any word

being programmed or any erase pages/physical blocks being erased is

not guaranteed.

10.11 Interrupts

The SGFM module can request an interrupt when all commands are

compl eted or when the ad dress, d ata, an d comm and bu ffers a re em pty.

Fi gure 10-1 9 shows the S GFM inte rru pt me chanism . Th is system uses

the CBEIE and CCIE bits as well as the register bank select signals to

enable interrupt requests. By taking into account the selected register

bank, false interrupt requests are not generated when the command

buffer is empty in an unselected register bank.

Table 10-7



SGFM Interrupt Sources

Interrupt

Source Interrupt

Flag Local

Enable Global Mask

(PSR)

Comma nd, data and address

buffers empty CBEIF

(SGFMUSTAT) CBEIE

(SGFMMCR) IE/FE bit

All commands are compl eted CCIF

(SGFMUSTAT) CCIE

(SGFMMCR) IE/FE bit

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Second Generation FLAS H for M•CORE (SGFM)

Interrupts

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Informa tion

MOTOROLA Second Generation FLASH for M•CORE (SGFM) 2 41

Figure 1 0-19 . SGFM Interr upt Implementation

•

BANK 0 CBEIF

BANK 0 SELE CT

BANK 1 CBEIF

BANK 1 SELE CT CBEIE

BANK 0 CCIF

BANK 0 SELE CT

BANK 1 CCIF

BANK 1 SELE CT CCIE

SGFM INTERRUPT

REQUEST

•

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242 Second Generation FLASH for M•CORE (SGFM) MO TOROLA

Second Generation FLASH for M•CORE (SGFM)

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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0  Advance Information
MOTOROLA Clock Module  243
Advance Info rmation — MMC2114, MMC2113, and MMC2112
Section 11. Cl ock Modu le
1  Contents
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
4.1 Normal PLL Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
4.2 1:1 PLL Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
4.3 External Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
4.4 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
4.4.1 Wait and Doze Modes . . . . . . . . . . . . . . . . . . . . . . . . . .245
4.4.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
5 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
6 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
6.1 EXTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
6.2 XTAL  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
6.3 CLKOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
6.4 PLLEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
6.5 RSTOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
7 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .249
7.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
7.2 Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
7.2.1 Synthesizer Control Register . . . . . . . . . . . . . . . . . . . . .250
7.2.2 Synthesizer Status Register. . . . . . . . . . . . . . . . . . . . . .253
7.2.3 Synthesizer Test Register . . . . . . . . . . . . . . . . . . . . . . .256
7.2.4 Synthesizer Test Register 2. . . . . . . . . . . . . . . . . . . . . .257
8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
8.1 System Clock Modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
8.2 System Clocks Generation. . . . . . . . . . . . . . . . . . . . . . . . .259
    
  
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244 Clock Module MOTOROLA
Clock Module
11.8.3 PLL Lock Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
11.8.3.1 PLL Loss of Lock Conditions . . . . . . . . . . . . . . . . . . . . .261
11.8.3.2 PLL Loss of Lock Reset. . . . . . . . . . . . . . . . . . . . . . . . .261
11.8.4 Loss of Clock Detection . . . . . . . . . . . . . . . . . . . . . . . . . . .261
11.8.4.1 Alternate Clock Selection. . . . . . . . . . . . . . . . . . . . . . . .262
11.8.4.2 Loss-of-Clock Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .265
11.8.5 Clock Operation During Reset . . . . . . . . . . . . . . . . . . . . . .266
11.8.6 PLL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266
11.8.6.1 Phase and Frequency Detector (PFD). . . . . . . . . . . . . .268
11.8.6.2 Charge Pump/Loop Filter. . . . . . . . . . . . . . . . . . . . . . . .268
11.8.6.3 Voltage Control Output (VCO). . . . . . . . . . . . . . . . . . . .269
11.8.6.4 Multiplication Factor Divider (MFD) . . . . . . . . . . . . . . . .269
11.9 Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
11.10 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
11.2  Introduction
The clock module contains:
•Crystal oscillator (OSC)
•Phase -locked loop (PLL )
•Redu ced frequency divider (RFD)
•Status and control registers
•Control logic
11.3  Features
Features of the clock module include:
•2- to 10-MHz reference crystal oscillator
•Support for low-power modes 
•Separate clock out signal
    
  
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Clock Module

Modes of Op eration

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MOTOROLA Clock Module 245

11.4 Modes of Operation

The clock module can be operated in normal PLL mode (default), 1:1

PLL mode, or external clock mode.

11.4.1 Normal PLL Mode

In normal PLL mode, the PLL is fully programmable. It can synthesize

frequencies ranging from 2x to 9x the reference frequency and has a

post divider capable of reducing this synthesized frequency without

disturbing the PLL. The PLL reference can be either a crystal oscillator

or an external clock.

11.4.2 1:1 PLL Mode

In 1:1 PL L mode, the P LL synthesizes a freq uency equal to the exte rnal

clock input reference frequency. The post divider is not active.

11.4.3 External Clock Mode

In external clock mode, the PLL is bypassed, and the external clock is

applied to EXTAL. The resulting operating frequency is one-half the

externa l clock frequency.

11.4.4 Low-Power Options

During wakeup from a low-power mode, the FLASH clock always clocks

through at least 16 cycles before the CPU clocks are enabled. This

allows the FLASH module time to recover from the low-power mode, and

software can immediately resume fetching instructions from the flash

memory.

11.4.4.1 Wait and Doze Modes

In wait and doze modes, the system clocks to the peripherals are

enabled, and the clocks to the CPU, FLASH, and SRAM are stopped.

Each module can disable the module clocks locally at the module level.

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246 Clock Module MOTOROLA

Clock Module

11.4.4.2 Stop Mode

In stop mo de, all syste m clocks ar e disab led. There are se veral options

for enabling/disabling the PLL and/or crystal oscillator in stop mode at

the price of increased wakeup recovery time. The PLL can be disabled

in stop mode, but then it requires a wakeup period before it can relock.

The OSC can also be disabled during stop mode, but then it requires a

wakeup period to restart.

When the PLL is enabled in stop mode (STPMD[1:0]), the external

CLKOUT signal can support systems using CLKOUT as the clock

source.

There is also a fast wakeup option for quickly enabling the system clocks

duri ng stop recovery. Th is elimina tes t he wakeup reco very time but at a

risk of sending a potentially unstable clock to the system. To prevent a

non-lo cked PLL frequency overshoot when usin g the fast wa keup

option, change the RFD divisor to the current RFD value plus one before

entering stop mode.

In external clock mode, there are no wakeup per iods for OSC startup or

PLL lock.

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Clock Module

Block Diagram

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MOTOROLA Clock Module 247

11.5 Blo ck Diag r am

Figure 11-1. Clock Module Block Diagram

CLKOUT

XTAL

EXT ER N AL CLOCK

OSC

PLLREF

REFERENCE

CLOCK PLL

MFD PLLMODE

LOCEN

PLLEN RSTOUT CLKOUT

LOCKS

LOCK

LOCS

RFD

TO RESET

MODULE

LOLRE LOCRE

STPMD[1:0]

STOP MODE

PLLSEL DISCLK

PLL CLOCK OUT

SCALED PLL CLOCK OU T

INTE RNAL CLOCK

PLLMODE

CLKGEN

(÷ 2)

ST OP MO D E

INTERNAL

CLOCKS

LOCK

FWKUP

EXTAL

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248 Clock Module MOTOROLA

Clock Module

11.6 Signal Descriptions

The clock module signals are summarized in Table 11-1 and a brief

description follows. For more detailed information, refer to Section 3.

Signal Description.

11.6.1 EXTAL

This input is driven by an external clock except when used as a

connection to the external crystal when using the internal oscillator .

11.6.2 XTAL

This output is an in ternal oscillator connection to the external crystal.

11.6.3 C LKOUT

This output reflects the internal system clock.

11.6.4 PLLEN

This input must be at VDD potential to enable the PLL.

Table 11-1. Signal Properties

Name Function

EXTA L O s cillator or clock input

XTAL O scillator output

CLKOUT System clock output

PLLEN PLL enable input

RSTOUT Re set signal from reset controller

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11.6.5 RSTOUT

The RSTOUT pin is asserted by:

•Internal system reset signal, or

•FRCRSTOUT bit in the Reset Control Status Register (RCR); see

5.6.1 Reset Control Register

11.7 Memory Map and Register s

The clock programming model consists of these registers:

•Synthesizer Control Register (SYNCR) — Defines clock

operation, refer to 11.7.2.1 Synthesizer Control Register

•Synthesizer Status Register (SYNSR) — Reflects clock status,

refer to 11.7.2.2 Synthesizer Status Register

•Synthe sizer Test Register ( SYNTR) — Used for factory test, refer

to 11.7.2.3 Synthesizer Test Register

•Synthesizer Test Register 2 (SYNTR2) — Used on ly for factory

test, refer to 11.7.2.4 Synthesizer Test Register 2

11.7.1 Module Memory Map

Table 11-2. Clock Module Memory Map

Address Register Nam e Access(1)

1. S = CPU supervisor mode access only.

0x00c3 _0000 Synthesizer Control Register (SY NCR) S

0x00 c3_0002 Sy nthes izer Status Register (SYNSR ) S

0x00c3_0003 Synthesizer Test Register (SYNTR) S

0x00c3_0004 Synthesizer Test Register 2 (SYNTR2) S

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11.7.2 Register Descriptions

This subsection provides a description of the clock module registers.

11.7.2.1 Synthesizer Control Register

The Synthesizer Contr o l Register (SYNCR) is read/write always.

LOLRE — Loss of Lock Reset Enable Bit

The LOLRE bit determines how the system handles a loss of lock

indication. When operating in normal mode or 1:1 PLL mode, the PLL

must be l ocked before setting the LOLRE bit. Otherwise reset is

immedi ately asserte d. To preve nt an immediate reset, the LOL RE bit

must be cl eared before writing the MFD[2:0] bits or entering stop

mode with the PLL disabled.

1 = Reset on loss of lock

0 = No reset on loss of lock

NOTE: In external clock mode, the LOLRE bit has no effect.

Address: 0x00c3_0000 and 0x00c3_0001

Bit 15 14 13 12 11 10 9 B it 8

Read: LOLRE MFD2 MFD1 MFD0 LOCRE RFD2 RFD1 RFD0

Write:

Reset:00100001

Bit 7654321Bit 0

Read: LOCEN DISCLK FWKUP 0STMPD1 STMPD0 00

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfe r error exception.

Figure 11-2. Synthesizer Control Register (SYNCR)

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MFD[2:0] — Multiplication Factor Divider Field

MFD[2:0] contain the binary value of the divider in the PLL feedback

loo p. See Ta bl e 1 1-3. The MFD[2 :0] val ue is t he mu lt iplica tion fact or

applied to the re ference frequency. When MFD[2:0] are changed or

the PLL is disabled in stop mode, the PLL loses lock. In 1:1 PLL

mode, MFD[2:0] are ignored, and the multiplication factor is one.

NOTE: In external clock mode, the MFD[2:0] bits have no effect.

See Table 11-6.

LOCRE — Lo ss of Clock Reset Enable Bit

The LOCRE bit determines how the system handles a loss of clock

condi tion. When the LOC EN bit is clear, LOCRE has no effect. If the

LOCS flag in SYNSR indicates a loss of clock condition, setting the

LOCRE bit causes an immediate reset. To prevent an immediate

reset, the LOCRE bit must be cleared before entering stop mode with

the PLL disabled.

1 = Reset on loss of clock

0 = No reset on loss of clock

NOTE: In external clock mode, the LOCRE bit has no effect.

Table 11-3. System Frequency Multiplier of the Reference

Frequency(1) in Normal PLL Mode

1. fsys = fref x (MFD + 2)/2 exp RFD; fref x (MFD + 2) <= 80 MHz, fsys <= 33 MHz

MFD[2:0]

000(2)

(2x)

2. MFD = 000 not val id f or fref < 3 MHz

001

(3x) 010

(4x)(3) 011

(5x) 100

(6x) 101

(7x) 110

(8x) 111

(9x)

RFD[2:0]

000 (÷ 1) 23456789

001 (÷ 2)(3)

3. Default value out of reset

1 3/2 2 5/2 3 7/2 4 9/2

010 (÷ 4) 1/2 3/4 1 5/4 3/2 7/4 2 9/4

011 (÷ 8) 1/4 3/8 1/2 5/8 3/4 7/8 1 9/8

100 (÷ 16) 1/8 3/16 1/4 5/16 3/8 7/16 1/2 9/16

101 (÷ 32) 1/16 3/32 1/8 5/32 3/16 7/32 1/4 9/32

110 (÷ 64) 1/32 3/64 1/16 5/64 3/32 7/64 1/8 9/64

111 (÷ 128) 1/64 3/128 1/32 5/128 3/64 7/128 1/16 9/128

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RFD[2:0] — Reduced Frequency Divider Field

The binary value written to RFD[2:0] is the PLL frequency divisor. See

Table 11-3. Changing RFD[2:0] does not affect the PLL or cause a

relock delay. Changes in clock fr equency are synchronized to the

next falling edge of the current system clock. To avoid surpassing the

allowable system operating frequency, write to RFD[2:0] only when

the LOCK bit is set.

NOTE: In external clock mode, the RFD[2:0] bits have no effect.

See Table 11-6.

LOCEN — Loss of Clock Enable Bit

The LOCEN bit enables the loss of clock function. LOCEN does not

affect the loss of lock function.

1 = Loss of clock function enabled

0 = Loss of clock function disabled

NOTE: In external clock mode, the LOCEN bit has no effect.

DISCLK — Disable CLKOUT Bit

The DISCLK bit determines whether CLKOUT is driven. Setting the

DISCLK bit holds CLKOUT low.

1 = CLK OUT disabled

0 = CLKOUT enabled

FWKUP — Fast Wakeup Bit

The FWKUP bit determines when the system clocks are enabled

during wakeup from stop mode.

1 = System clocks enabled on wakeup regardless of PLL lock

status

0 = System clocks enabled only when PLL is locked or operating

normally

NOTE: When FWKUP = 0, if the PLL or OSC is enabled and unintentionally lost

in stop mode, the PLL wakes up in self-clocked mode or reference clock

mode depending on the clock that was lost.

In external clock mode, the FWKUP bit has no effect on the wakeup

sequence.

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STPMD[1:0] — Stop Mode Bits

STPMD[1:0] control PLL and CLKOUT operation in stop mode as

shown in Table 11-4.

11.7.2.2 Synthesizer Status Register

The Synthesizer Status Register (SYNSR) is a read-only register that

can be read at any time. Writing to the SYNSR has no effect and

terminates the cycle normally.

Table 11-4. STPMD[1:0] Operation in Stop Mode

STPMD[1:0] Ope r a t io n Duri ng Stop Mo de

System

Clocks PLL OSC CLKOUT

00 Disabled Enabled Enabled Enabled

01 Disabled Enabled Enabled Disabled

10 Disabled Disabled Enabled Disabled

11 Disabled Disabled Disabled Disabled

Address: 0x00c3_0002

Bit 7654321Bit 0

Read: PLLMODE PLLSEL PLLREF LOCKS LOCK LOCS 0 0

Write:

Reset: Note 1 Note 1 Note 1 Note 2 Note 2 0 0 0

= Writes have no effect and the access terminates without a transfe r error exception.

Notes:

1. Reset state determined during reset configuration.

2. See the LOCKS and LOCK bit descriptions.

Figure 11-3. Synthesizer Status Register (SYNSR)

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Clock Module

PLLMODE — Clock Mode Bit

The MODE bit is configured at reset and reflects the clock mode as

shown in Table 11-5.

1 = PLL clock mode

0 = External clock mode

PLLSEL — PLL Select Bit

The PLLSEL bit is configured at reset and re flects the PLL mode as

shown in Table 11-5.

1 = No rma l PLL mode

0 = 1:1 PLL mode

PLLREF — PLL Reference Bit

The PLL REF bi t is configured at rese t and re flects t he P LL ref eren c e

source in normal PLL mode as shown in Table 11-5.

1 = Crystal clock reference

0 = External clock reference

LOCKS — Sticky PLL Lock Bit

The LOCKS flag is a sticky indication of PLL lock status.

1 = No unintentional PLL loss of lock since last system reset or

MFD change

0 = PLL loss of lock since last system reset or MFD change or

currently not locked due to exit from STOP with FWKUP set

The lock detect function sets the LOCKS bit when the PLL achieves

lock after:

–A system reset, or

–A write to SYNCR that changes the MFD[2:0] bits

Table 11-5. System Clock Modes

PLLM OD E:P LLS E L: P LLREF Cl ock Mode

000 Ex t ernal clock mode

100 1 :1 PLL mod e

110 Normal PLL mode with external clock reference

111 Normal PLL mode with crystal oscillator

reference

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When the PLL loses lock, LOCKS is cleared. When the PLL r e locks,

LOCKS remain s cleared until one of the two listed events occurs.

In stop m ode, i f the PLL i s in tenti ona lly di sabled , then the LO CKS bit

refl ects the value pr ior to en teri ng stop mo de. However, if FWK UP is

set, then LOCKS is cleared until the PLL regains lo ck. Once lock is

regained, the LOCKS bit reflects the value pri or to entering stop

mode. Fu rthermor e, readi ng the LOCKS bit at the same time that the

PLL loses lock does not return the current loss of lock condition.

In external clock mode, LOCKS remains cleared after reset. In normal

PLL mode and 1:1 PLL mode, LOCKS is set after reset.

LOCK — PLL Lock Flag

1 = PLL locked

0 = PLL not locked

The LOCK flag is set when the PLL is locked. PLL lock occurs when

the synthesized frequency is within appro ximately 0.75 percent of the

programmed frequency. The PLL loses lock when a frequency

deviation of greater than approximately 1.5 percent occurs. Reading

the LOCK flag at the same time that the PLL loses lock or acquires

lock does not return the current condition of the PLL. The power-on

reset circuit uses the LOCK bit as a condition for releasing reset.

If operating in external clock mode, LOCK remains cleared after reset.

LOCS — Sticky Loss Of Clock Flag

1 = Loss of clock detected since exiting reset or oscillator not yet

recovered from exit from stop mode with FWKUP = 1

0 = Lo ss of clock not detected since exiting reset

The LOCS flag is a sticky indication of whether a loss of clock

condition has occurred at any time since exiting reset in normal PLL

and 1:1 PLL modes. LOCS = 0 when the system clocks are operating

normal ly. LOCS = 1 when system clocks have failed due to a

reference failure or PLL failure.

After entering stop mode with FWKUP set a nd the PLL and oscillator

inte ntiona lly disabled (S TP MD[ 1:0] = 11 ), t he PLL exits st op m ode in

SCM while the oscillator starts up. During this time, LOCS is

tempor arily set regardless of LOCEN. It is cleared once the oscillator

comes up and the PLL is attempting to lock.

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If a read of the LOCS flag and a loss of clock condition occur

simultaneously, the flag does not reflect the current loss of clock

condition.

A loss of clock condition can be detected only if LOCEN = 1 or the

oscillator has not yet returned from exit from stop mode with

FWKUP = 1.

NOTE: The LOCS flag is always 0 in external clock mode.

11.7.2.3 Synthesizer Test Register

The Synthesizer Test Register (SYNTR) is only for factory testing. When

not in test mode, SYNTR is read-only.

Address: 0x00c3_0003

Bit 7654321Bit 0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfe r error exception.

Figure 11-4. Synthesizer Test Register (SYNTR)

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11.7.2.4 Synthesizer Test Register 2

The Synthesizer Test Register 2 (SYNTR2) is only for factory testing.

Bits 31–10

Bits 31–10 are read-only. Writing to bits 31–10 has no effect.

RSVD9–RSVD0 — Reserved

The RSVD bits can be read at any time. Writes to these bits update

the register values but have no effect on functionality.

Address: 0x00c3_0004 through 0x00c3_0007

Bit 31 30 29 28 27 26 25 Bit 24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 Bit 16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 B it 8

RSVD9 RSVD8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 RSVD1 RSVD0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfe r error exception.

Figure 11-5. Synthesizer Test Register 2 (SYNTR2)

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Clock Module

11 .8 Fun cti on al Descr iptio n

This subsection provides a functional descrip tion of the clock module.

11.8.1 System Clock Modes

The system clock source is determined during reset (see Table 4-7.

Configuration During Reset). The value of PLLEN is latched during

reset and is of no importance after reset is negated. If PLLEN is changed

during a reset other than power-on reset, the internal clocks may glitch

as the clock source is changed between external clock mode and PLL

clock mode. Whenever PLLEN is changed in reset, an immediate loss of

lock condition occurs.

Table 11-6 shows the clock-out frequency to clock-in frequency

relationships for the possible clock modes.



CAUTION: XTAL must be tied low in external clock mode when rese t is asserte d. If

it is not, clocks could be suspended indefinitely.

The external clock is divided by two internally to produce the system

clocks.

Table 11-6. Clock-Out and Clock-In Relationships

Clock Mode PL L Op tions(1)

1. fref = input reference fre quency

fsys = CLKOUT frequency

MFD ranges fr om 0 to 7.

RFD ranges from 0 to 7.

Normal PLL clock mode fsys = fref × (M FD + 2 )/2RFD

1:1 PLL clock mo de fsys = fref

External clock mode fsys = fref/2

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11.8.2 System Clocks Generation

In normal PLL clock mode, the default system freq uency is two times the

reference frequency after reset. The RFD[2:0] and MFD[2:0] bits in

SYNCR select the frequency multiplier.

When prog ramming the PLL, do not exce ed the maximum system clock

frequency listed in the electrical specifications. Use this procedure to

accommodate the frequency overshoot that occurs when the MFD bits

are changed:

1. Determine the appropriate value for the MFD and RFD fields in

SYNCR. The amount of jitter in the system clocks can be

minimized by selecting the maximum MFD factor that can be

pair ed with an RFD factor to provide the required frequency.

2. Write a value of RFD (fr om step 1) + 1 to the RFD field of SYNCR.

3. Write the MFD value from step 1 to SYNCR.

4. Monitor the LOCK flag in SYNSR. When the PLL achieves lock,

write the RFD value from step 1 to the RFD field of SYNCR. This

changes the system clocks frequency to the required frequency.

NOTE: Keep the maximum system clock frequency below the limit given in

Section 23. Preliminary Electrical Specifications.

11.8.3 PLL Lock Detection

The lock detect logic monitors the reference frequency and the PLL

feedback frequency to determine when frequency lock is achieved.

Phase lock is inferred by the frequency relationship, but is not

guaranteed. The LOCK flag in SYNSR reflects the PLL lock status. A

sticky lock flag, LOCKS, is also pr ovided.

The lock detect function uses two counters. One is clocked by the

reference and the other is clocked by the PLL feedback. When the

refere nce counter has counte d N cycles, its coun t is compared to that of

the feedback counter. If the feedback counter has also counted N cycles,

the process is repeated for N + K counts. Then, if the two counters still

match, the lock criteria is relaxed by 1/2 and the system is notified that

the PLL has achieved frequency lock.

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After lock is dete cted, the lock circuit continues to m onitor the refer ence

and feedback frequencies using the alternate count and compare

process. If the counters do not match at any comparison time, then the

LOCK flag i s cleare d to indi ca te that the PLL ha s l ost lock. At thi s p oint,

the lo ck criteria is tightened and the lock detect process is repeated.

The alternate count sequences prevent false lock detects due to

frequency aliasing while the PLL tries to lock. Alternating between tight

and relaxed lock criteria prevents the lock detect function from randomly

toggling between locked and non-locked status due to phase

sensitivities. Figure 11-6 shows the sequence for detecting locked and

non-locked conditions.

In external clock mode, the PLL is disabled and cannot lock.

Figure 11-6. Lock Detect Sequence

COUNT N

REFERENCE CYCLES

AND COMP A RE

NUMBER O F FEE DB A CK

CYCLES ELAPSED

START

WITH TIGHT LO CK

CRITERIA REFERE NCE COUNT

≠ FEEDBACK COU NT

LOSS OF LOCK DETECTED

SET TIG HT L OC K CRI TE RIA

AND NOTIFY SYSTEM OF LOSS

OF LOCK CONDITION

COUNT N + K

RE FERE NCE CYCLES

AND COMPARE NUMBER

OF FEEDBACK CYCLES

ELAPSED

LOCK DETECTE D.

SET RELAXED LOCK

CONDITION AND NOTIFY

SYSTEM OF LOCK

CONDITION

REFERE NCE CO UNT

≠ FEED BACK COUNT

REFERE NCE CO UNT =

FEEDBACK COU N T = N

IN SAME CO UNT /COM PARE SEQU EN CE

REFERE NCE COUNT =

FEEDBACK COU NT = N + K

IN SAME C OU NT/ CO M PAR E SEQU EN C E

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11.8.3.1 PLL Loss of Lock Conditions

Once the P LL acquires lock after reset, the LOCK and LOCK S fla gs are

set. If the MFD is changed, or if an unexpected loss of lock condition

occurs, the LOCK and LOCKS flags are negated. While the PLL is in the

non-locked condition, the system clocks continue to be sourced from the

PLL as the PLL attempts to relock. Consequently, during the relocking

process, the system clocks frequency is not w ell defined and may

exceed the maximum system frequency, violating the system clock

timing specifications.

Howeve r, once the PLL has relo cked, the LOCK fl ag is set. The LOCKS

flag remains cleared if the loss of lock is unexpected. The LOCKS flag is

set when the loss of lock is caused by changing MFD. If the PLL is

inte ntiona lly disa bled dur ing stop m ode, th en afte r exi t fro m stop mode,

the LOC KS flag r eflects th e val ue prio r to enter ing stop mod e once l ock

is regained.

11.8.3.2 PLL Loss of Lock Reset

If the LOLRE bit in SYNCR is set, a loss of lock conditio n asserts reset.

Reset reinitializes the LOCK and LOCKS flags. Therefore, software

must read the LOL bit in Reset Status Register (RSR) to determine if a

loss of lock caused the reset. See 5.6.2 Reset Status Register.

To exit reset in PLL mode, the reference must be present, and the PLL

must achieve lock.

In external clock mode, the PLL cannot lock. Therefore, a loss of lock

condition cannot occur, and the LOLRE bit has no effect.

11.8.4 Loss of Clock Detection

The LOCEN bit in SYNCR enables the loss of clock detection circuit to

monitor the input clocks to the phase and frequency detector (PFD).

When either the reference or feedback clock frequency falls below the

minimum frequency, the lo ss of clock circuit se ts the sticky LOCS flag in

SYNSR.

NOTE: In external clock mode, the loss of clock circuit is disabled.

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11.8.4.1 Alternate Clock Selection

Dependi ng on which clock source fa ils, the loss-of-clo ck circuit swi tches

the system clocks source to the remaining operational clock. The

alternate clock source generates the system clocks until reset is

asserted. As Table 11-7 shows, if the reference fails, the PLL goes out

of lock and into self-clocked mode (SCM). The PLL remains in SCM until

the next reset. When the PLL is operating in SCM, the system frequency

depends on the value in the RFD field. The SCM system frequency

stated in electrical specifications assumes that the RFD has been

programmed to binary 000. If the loss-of-clock condition is due to PLL

failure, the PLL reference become s the system clocks source until the

next reset, even if the PLL regains and relocks.

A special loss-of-clock condition occurs when both the reference and the

PLL fail. The failures may be simultaneous, or the PLL may fail first. In

either case, the reference clock failure takes priority and the PLL

at tempts to ope rate in SCM . If successful, the P LL remain s in SCM until

the next reset. If the PLL cannot operate in SCM, the system remains

static until the next reset. Both the reference and the PLL must be

functioning properly to exit reset.

Table 11-7. Loss of Clock Summary

Clock

Mode System Clock

Source

Before Failure

Reference Failure

Alternate Clock

Selected by LOC

Circuit(1) Until Reset

1. The LOC cir cuit moni tors the ref erence and f eedback inp uts to the PFD. See Figur e 11-8.

PLL Failure

Alternate Clock

Selected by

LOC Circuit

Until Reset

PLL PLL PLL self-clocked mode PLL reference

External External clock None NA

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Table 11-8. Stop Mode Operation (Sheet 1 of 3)

MODE

LOCEN

LOCRE

LOLRE

PLL

OSC

FWKUP

Exp ec ted PL L

Acti on a t Stop PLL Act ion

During Stop MODE

Out

LOCKS

LOCK

LOCS

Comments

EXT XXX X X X ——EXT 000

Lose reference clock Stuck ———

NRM 0 0 0 Off Off 0 Lose lock,

f.b. clock,

reference clock

Regain NRM ‘LK 1 ‘LC

No regain Stuck ———

NRM X 0 0 Off Off 1 Lose lock,

f.b. clock,

reference clock

Regain clocks, but

don’t regain lock SCM–>

unstable NRM 0–>‘LK 0–>1 1–>‘LC

Block LOCS and LOCKS until

clock and lock respectively

regain; enter SCM regardless

of LOCEN bi t until reference

regained

No reference clock

regain SCM–>0–>0–>1–>

Block LOCS and LOCKS until

clock and lock respectively

regain; enter SCM regardless

of LOCEN bit

No f.b. clock regain Stuck ———

NRM 0 0 0 Off On 0 Lose lock

Regain NRM ‘LK 1 ‘LC Block LOCKS from being

cleared

Lose reference clock

or no loc k regain Stuck ———

Lose reference clock,

regain NRM ‘LK 1 ‘LC Block LOCKS from being

cleared

NRM 0 0 0 Off On 1 Lose lock

No lock regain Unstable NRM 0–>‘LK 0–>1 ‘LC Block LOCKS until lock

regained

Lose reference clock

or no f .b . clock regain Stuck ———

Lose reference clock,

regain Unstable NRM 0–>‘LK 0–>1 ‘LC LOCS not set because

LOCEN = 0

NRM 0 0 0 On On 0 —

—NRM ‘LK 1 ‘LC

Lose lock or cloc k S tuck ———

Lose lock, regain NRM 0 1 ‘LC

Lose clock and lock,

regain NRM 0 1 ‘LC LOCS not set because

LOCEN = 0

NRM 0 0 0 On On 1 —

—NRM ‘LK 1 ‘LC

Lose lock Unstable NRM 0 0–>1 ‘LC

Lose lock, regain NRM 0 1 ‘LC

Lose clock S tuc k ———

Lose clock, regain

wi th ou t loc k Uns table NRM 0 0–>1 ‘LC

Lose clock, regain

with lock NRM 0 1 ‘LC

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NRM X X 1 Off X X Lose lock,

f.b. clock,

reference clock RESET RESET ———Reset imm ediately

NRM 0 0 1 On On X ——NRM ‘LK 1 ‘LC

Lose lock or cloc k RE SET ———Res et immediately

NRM 1 0 0 Off Off 0 Lose lock,

f.b. clock,

reference clock

Regain NRM ‘LK 1 ‘LC RE F not entered during stop;

SCM entered during stop only

during OSC startup

No regain Stuck ———

NRM 1 0 0 Off On 0 Lose lock,

f.b. clock

Regain NRM ‘LK 1 ‘LC RE F mode not entered during

stop

No f.b. clock or lock

regain Stuck ———

Lose reference clock SCM 0 0 1 Wakeup without lock

NRM 1 0 0 Off On 1 Lose lock,

f.b. clock

Regain f.b. clock Uns table NRM 0–>‘LK 0–>1 ‘LC REF mode not enter ed during

stop

No f.b. clock regain Stuck ———

Lose reference clock SCM 0 0 1 Wakeup without lock

NRM 1 0 0 On On 0 —

—NRM ‘LK 1 ‘LC

Lose reference clock SCM 0 0 1 Wakeup without lock

Lose f.b. clock REF 0 X 1 W akeup without lock

Lose lock Stuck ———

Lose lock, regain NRM 0 1 ‘LC

NRM 1 0 0 On On 1 —

—NRM ‘LK 1 ‘LC

Lose reference clock SCM 0 0 1 Wakeup without lock

Lose f.b. clock REF 0 X 1 W akeup without lock

Lose lock Unstable NRM 0 0–>1 ‘LC

NRM 1 0 1 On On X ——NRM ‘LK 1 ‘LC

Lose lock or cloc k RE SET ———Res et immediately

NRM 11XOffXXLose lock,

f.b. clock,

reference clock RESET RESET ———Reset imm ediately

NRM 1 1 0 On On 0 —

—NRM ‘LK 1 ‘LC

Lose clock RE SE T ———Reset imm ediately

Lose lock Stuck ———

Lose lock, regain NRM 0 1 ‘LC

Table 11-8. Stop Mode Operation (Sheet 2 of 3)

MODE

LOCEN

LOCRE

LOLRE

PLL

OSC

FWKUP

Exp ec ted PL L

Acti on a t Stop PLL Act ion

During Stop MODE

Out

LOCKS

LOCK

LOCS

Comments

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Clock Module

Functional Description

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MOTOROLA Clock Module 265

11.8.4.2 Loss-of-Clock Reset

When a loss-of-clock condition is recognized, reset is asserted if the

LOCRE bit in SYNCR is set. The LOCS bit in SYNSR is cleared after

reset. Therefore, the LOC bit must be read in RSR to determine that a

loss of clock condition occu rred . LOC RE has no effect in external clo ck

mode.

NRM 1 1 0 On On 1 —

—NRM ‘LK 1 ‘LC

Lose clock RE SE T ———Reset imm ediately

Lose lock Unstable NRM 0 0–>1 ‘LC

Lose lock, regain NRM 0 1 ‘LC

NRM 1 1 1 On On X ——NRM ‘LK 1 ‘LC

Lose clock or lock RESET ———Reset imm ediately

REF 1 0 0 X X X ——REF 0 X 1

Lose reference clock Stuck ———

SCM 1 0 0 Off X 0 PLL disabled Regain SCM SCM 0 0 1 Wakeup without lock

SCM 1 0 0 Off X 1 PLL disabled Regain SCM SCM 0 0 1

SCM 1 0 0 On On 0 ——SCM 0 0 1 Wakeup without lock

Lose reference clock SCM

SCM 1 0 0 On On 1 ——SCM 001

Lose reference clock SCM

PLL = PLL enabled during STOP mode. PLL = On when STP MD[1: 0] = 00 or 01

OSC = OSC enabled during STOP mode. OSC = On when ST PMD[ 1:0] = 00, 01, or 10

MODES

NRM = normal PLL crystal clock reference or normal P LL external reference or PLL 1:1 mode. During PLL 1:1 or norm al external reference

mode, the oscillator is n ever enabled. Therefore, during these modes, ref er to the OSC = On c ase regardless of STPMD values.

EXT = external clock mode

REF = P LL reference mode due to losing PLL clock or lock from NRM mode

SCM = PLL self-clocked mode due to losing reference clock from NRM mode

RESET = immediate reset

LOCKS

‘LK = expecting previous value of LOCKS before entering stop

0–>‘LK = current value is 0 until lock is r egained which then will be the previous value before entering stop

0–> = c urrent value is 0 until lock is r egained but lock is never expe cted to regain

LOCS

‘LC = expecting previous value of LOCS before entering stop

1–>‘LC = c urrent value is 1 until clock is regained which th en will be the previous value before entering stop

1–> = current value is 1 until clock is regained but CLK is never expected to regain

Table 11-8. Stop Mode Operation (Sheet 3 of 3)

MODE

LOCEN

LOCRE

LOLRE

PLL

OSC

FWKUP

Exp ec ted PL L

Acti on a t Stop PLL Act ion

During Stop MODE

Out

LOCKS

LOCK

LOCS

Comments

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Clock Module

To exit reset in PLL mode, the reference must be present, and the PLL

must acquire lock.

11.8.5 Clock Operation During Reset

In ext ernal clock mode, the system is static and does not recognize reset

until a clock is applied to EXTAL.

In PLL mode, the PLL operates in self-clocked mode (SCM) during reset

until the input reference clock to the PLL begins operating within the

limits given in the electrical specifications.

If a PLL failure causes a reset, the system enters reset using the

refere nce cl o ck. Th en th e clock s ource chang es to the PLL ope rating in

SCM. I f SCM is not functio nal, the system becomes stat ic . Alternat ely, if

the LOCEN bit in SYNCR is clear when the PLL fails, the system

becomes static. If external reset is asserted, the system cannot enter

reset unless the PLL is capable of operating in SCM.

11.8.6 PLL Operation

In PLL m o de, the PLL synthesizes the system clocks. The PLL can

multiply the reference clock frequency by 2x to 9x, provided that the

system clock (CLKOUT) frequency remains within the range listed in

electrical specifications. For example, if the reference frequency is

2 MHz, the PLL can synthesize frequencies of 4 MHz to 18 MHz. In

addition, the RFD can reduce the system frequency by dividing the

output of the PLL. The RFD is not in the feedback loop of the PLL, so

changing the RFD divisor does not affect PLL operation.

Figure 11-8 shows the external support circuitry for the crystal oscillator

with example component values. Actual component values depend on

crystal specifications.

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Figure 11-7. PLL Block Diagram

Figure 11-8. Crystal Oscillator Example

STPMD

PLLEN RSTOUT

÷ MFD

(2–9)

LOCKS

LOCK

LOCS

TO RESET

MODULE

CLKOUT

PLLSEL

DISCLK MDF[2:0]

PHASE AND

FREQUENCY

DETECT

LOSS OF

CLOCK

DETECT

LOCK

DETECT

CHARGE

PUMP FILTER VCO RFD[2:0]

SCALED PLL

CLOCK OUT

PLL CLO CK

OUT

REFERENCE

CLOCK

LOCEN

LOLRE

PLLMODE

LOCRE

666<1

EXTAL XTAL

C1 C2

ON-CHIP

8-MHz CRY ST AL CO NF I GU RA TION

C1 = C2 = 16 pF

RF = 1 MΩ

RS = 470 Ω

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Clock Module

11.8.6.1 Phase and Frequency Detector (PFD)

The P FD is a dual-l atch phase-freq uency detect or. It compares bo th the

phase and frequency of the reference and feedback clocks. The

reference clock co mes from either the crystal oscillator or an exte rnal

clock source. The feedback clock comes from:

•CLKOUT in 1:1 PLL mode, or

•VCO output divided by two if CLKOUT is disabled in 1:1 PLL

mode, or

•VCO output divided by the MFD in normal PLL mode

When the frequency of the feedback clock equals the frequency of the

reference clock, the PLL is frequency-locked. If the falling edge of the

feedback cl ock lags the falling edge of the re ference clock, the PFD

pulses the UP signal. If the falling edge of the feedback clock leads the

falling edge of the reference clock, the PFD pulses the DOWN signal.

The width of these pulses relative to the reference clock depends on how

much the two clocks lead or lag each other. Once phase lock is

achieved, the PFD continues to pulse the UP and DOWN signals for very

short durations during each reference clock cycle. These short pulses

continually update the PLL and prevent the frequency drift phenomenon

known as dead-banding.

11.8.6.2 Charge Pump/Loop Filter

In 1:1 PLL mode, th e charge pump u ses a fixed current . In nor mal mode

the current magnitude of the charge pump varies with the MFD as shown

in Table 11-9.

Table 11-9. Charge Pump Current and MFD

in Normal Mode Operation

Charge Pump Current MFD

1X 0 ≤ MFD < 2

2X 2 ≤ MFD < 6

4X 6 ≤ MFD

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The UP and DOWN signals from the PFD control whether the charge

pump applies or removes charge, respectively, from the loop filter. The

filter is integrated on the chip.

11.8.6.3 Voltage Control Output (VCO)

The voltage across the loop filter controls the frequency of the V CO

output. The frequency-to-voltage relationship (VCO gain) is positive, and

the output frequency is four times the target system frequency.

11.8.6.4 Multiplication Factor Divider (MFD)

When the PLL is n ot in 1:1 PLL mode, the MFD di vides the ou tput of the

VCO and feeds it back to the PFD. The PFD controls the VCO frequency

via the charge pump and loop filter such that the reference and feedback

clocks have the sam e frequ ency and phase. T hus, the freque ncy of the

input to the MFD, which is also the output of the VCO, is the reference

frequency multiplied by the same amount that the MFD divides by. For

example, if the MFD divides the VCO frequency by six, the PLL is

frequency locked when the VCO frequency is six times the reference

frequency. The presence of the MFD in the loop allows the PLL to

perform frequency multiplication, or synthesis.

In 1:1 PLL mode, the MFD is bypassed, and the effective multiplication

factor is one.

11.9 Reset

The clock m odule can asser t a rese t whe n a loss of cl o ck or l oss of lock

occurs as descr ibed in 11.8 Function al Description.

Reset initializes the clock module registers to a known startup state as

described in 11.7 Memory Map and Registers.

11.10 Interrupts

The clock module does not generate interrupt requests.

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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0  Advance Information
MOTOROLA Ports Module  271
Advance Info rmation — MMC2114, MMC2113, and MMC2112
Section 12. Ports Module
12.1  Contents
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272
12.3 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
12.4 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .273
12.4.1 Memory Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274
12.4.2 Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .275
12.4.2.1 Port Output Data Registers . . . . . . . . . . . . . . . . . . . . . .275
12.4.2.2 Port Data Direction Registers. . . . . . . . . . . . . . . . . . . . .276
12.4.2.3 Port Pin Data/Set Data Registers  . . . . . . . . . . . . . . . . .277
12.4.2.4 Port Clear Output Data Registers  . . . . . . . . . . . . . . . . .278
12.4.2.5 Port C/D Pin A ssignment Register. . . . . . . . . . . . . . . . .279
12.4.2.6 Port E Pin Assignment Register. . . . . . . . . . . . . . . . . . .280
12.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
12.5.1 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
12.5.2 Port Digital I/O Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
12.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
    
  
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Ports Module

12.2 Introduction

Many of the pins associat ed wi th the ext erna l i nterf ace ma y be u sed fo r

several different functions. Their primary function is to provide an

ext ernal inter face to access off- chip reso urces. When not used for their

primary functions, many of the pins may be used as general purpose

digita l input/output (I/O) pins. In some cases, the pin function is set by

the operating mode, and the alternate pin functions ar e not supported.

To facilitate the general purpose digital I/O function, these pins are

grouped into 8-bit ports. Each port has registers that configure the pins

for the desi re d fu nction, mo nitor the pi n s, an d co ntro l the pi n s wi thin the

ports.

Figure 12-1. Ports Module Block Diagram

CSE[1:0] / PE[4: 3] (1)

SHS / RCO N / PE7

TC[2:0] / PE[2:0](1)

TA / PE6

TEA / PE5

D[7 :0 ] / PD [7 :0 ]

D[15:8] / PC[7:0]

D[23:16] / PB[7: 0]

D[31:24] / PA[7: 0]

EB[3:0] / PI[7:4 ](1)

A[7:0] / PH[7:0](1)

A[15:8] / PG[7:0](1)

R/W / PF7(1)

A[22:16] / PF[6:0](1)

CS[3:0]/ PI[3 :0 ](1)

PORT E

PORT D

PORT C

PORT B

PORT A

PORT I

PORT H

PORT G

PORT F

Note 1. These pin s are fo und only on the 144-pin package.

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Signals

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12.3 Signals

See Table 12- 3 in 12.5 Functional Description for signal location and

naming convention.

12.4 Memory Map and Register s

The ports programming model consists of these registers:

•The port output data registers (PORTx) store the data t o be driven

on the corresponding port pins when the pins are configured for

digital output.

•The port data directio n registers (DDRx) control the direction of

the port pin drivers when the pins are configured for digital I/O.

•Port pin data/set data registers (PORTxP/SETx):

–Reflect the current state of the port pins

–Allow for setting individual bits in PORTx

•The port clear output data registers (CLRx) allow for clearing

individual bits in PORTx.

•The por t pin assignment re gisters ( PCDPAR an d PEPAR) control

the function of each pin of the C, D, E, I7, and I6 ports.

In emulation mode, accesses to the port registers are ignored and the

port access goes external so that emulation hardware can satisfy the

port access request. The cycle termination is always provided by the port

logic, even in emulation mode.

All port registers are word-, half-word, and byte-accessible and are

grouped to allow coherent access to port data register groups. Writing to

reserved bits in the port registers has no effect and reading returns 0s.

The I/O ports have a base address of 0x00c0_0000.

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12.4.1 Memory Map

Table 12-1. I/O Port Module Memory Map

Address Bits 31–24 Bi ts 23–16 Bits 15–8Bits 7–0 Access(1)

0x00c0_0000 PORTA PORTB PORTC PORTD S/U

0x00c0_0004 PORTE PORTF PORTG PORTH S/U

0x00c0_0008 PORTI Reserved(2) S/U

0x00c0_000c DDRA DDRB DDRC DDRD S/U

0x00c0_0010 DDRE DDRF DDRG DDRH S/U

0x00c0_0014 DDRI Reserved(2) S/U

0x00c0_0018 PORTAP/SETA PORTBP/SETB PORTCP/SETC PORTDP/SETD S/U

0x00c0_001c PORTEP/SETE PORTFP/SETF PORTGP/SETG PORTHP/SETH S/U

0x00c0_0020 PORTIP/SETI Reserved(2) S/U

0x00c0_0024 CLRA CLRB CLRC CLRD S/U

0x00c0_0028 CLRE CLRF CLRG CLRH S/U

0x00c0_002c CLRI Reserved(2) S/U

0x00c0_0030 PCDPAR PEPAR Reserved(2) S/U

0x00c0_0034–

0x00c0_003c Reserved(2) S/U

1. S/U = CPU supervisor or user mode access. User mod e accesses to sup ervisor only addresses have no effect and result

in a cycl e termination transfe r err or.

2. Writ es have no effect, reads re turn 0s, and the access terminates wit hout a transfer error exception.

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12.4.2 Register Descriptions

This subsection provides a description of the I/O port registers.

12.4.2.1 Port Output Data Registers

The port output data registers (PORTx) store the data to be driven on the

corresponding port x pins when the pins are configured for digital output.

Reading PORTx returns the current value in the register, no t the port x

pin values.

The SETx and CLRx registers also affect the PORTx register bits. To set

bits in PORTx, write 1s to the corresponding bits in PORTxP/SETx. To

clear bits in PORTx, write 0s to the corresponding bits in CL Rx.

PORTx are read/write registers when not in emulation mode. Reset sets

PORTx.

Address: 0x00c0_0000 — PORTA

0x00c0_0001 — PORTB

0x00c0_0002 — PORTC

0x00c0_0003 — PORTD

0x00c0_0004 — PORTE

0x00c0_0005 — PORTF

0x00c0_0006 — PORTG

0x00c0_0007 — PORTH

0x00c0_0008 — PORTI

7654321Bit 0

Read: PORTx7 PORTx6 PORTx5 PORTx4 PORTx3 PORTx2 PORTx1 PORTx0

Write:

Reset:11111111

Figure 12-2. Port Output Data Registers (PORTx)

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12.4.2.2 Port Data Direction Registers

A port data direction registers (DDRx) control the direction of th e port x

pin drive rs when the pins are configured for digital I/O. Setting an y bit in

DDRx configures the corresponding port x pin as an output. Clearing any

bit in DDRx configu res the correspon ding pin as an input. When a pin is

not configured for digital I/O, its corresponding data direction bit has no

effect.

DDRx are read/write registers when not in emulation mode. Reset clears

DDRx.

DDRx[7:0] — Port x Data Direction Bits

1 = Pin configured as output

0 = Pin configured as input

Address: 0x00c0_000c — DDRA

0x00c0_000d — DDRB

0x00c0_000e — DDRC

0x00c0_000f — DDRD

0x00c0_0010 — DDRE

0x00c0_0011 — DDRF

0x00c0_0012 — DDRG

0x00c0_0013 — DDRH

0x00c0_0014 — DDRI

Bit 76 54321Bit 0

Read: DDRx7 DDRx6 DDRx5 DDRx4 DDRx3 DDRx2 DDRx1 DDRx0

Write:

Reset:00000000

Figure 12-3. Port Data Direction Registers (DDRx)

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12.4.2.3 Port Pin Data/S et Data Registers

Rea ding a Port Pin Data/S et Data R egister (POR TxP/SETx) re turns the

current state of the port x pins.

Writing 1s to PORTxP/SETx sets the corresponding bits in PORTx.

Writing 0s has no effect.

PORTxP/SETx are read/write registers when not in emulation mode.

Address: 0x00c0_0018 — PORTAP/ SETA

0x00c0_0019 — PORTBP/ SETB

0x00c0_001a — PORTCP/ SETC

0x00c0_001b — PORTDP/ SETD

0x00c0_001c — PORTEP/SETE

0x00c0_001d — PORTFP/ SETF

0x00c0_001e — PORTGP/SETG

0x00c0_001f — PORTHP/SETH

0x00c0_0020 — PORTIP/ SETI

Bit 76 54321Bit 0

Read: PORTxP7 PORTxP6 PORTxP5 PORTxP4 PORTxP3 PORTxP2 PORTxP1 PORTxP0

Write: SETx7 SETx6 SETx5 SETx4 SETx3 SETx2 SETx1 SETx0

Reset:PPPPPPPP

P = Current pin state

Figure 12-4. Port Pin Data/Set Data Registers (PORTxP/SETx)

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12.4.2.4 Port Clear Output Data Registers

Writing 0s to a Port Clear Output Data Register (CLRx) clears the

corresponding bits in PORTx. Writing 1s has no effect. Reading CLRx

returns 0s.

CLRx are read/write registers w hen not in emulation mode.

Address: 0x00c0_0024 — CLRA

0x00c0_0025 — CLRB

0x00c0_0026 — CLRC

0x00c0_0027 — CLRD

0x00c0_0028 — CLRE

0x00c0_0029 — CLRF

0x00c0_002a — CLRG

0x00c0_002b — CLRH

0x00c0_002c — CLRI

Bit 76 54321Bit 0

Write: CLRx7 CLRx6 CLRx5 CLRx4 CLRx3 CLRx2 CLRx1 CLRx0

Reset:00000000

Figure 12-5. Port Clear Output Data Registers (CLR x)

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12.4.2.5 Port C/D Pin Assignment Register

The Port C/D Pin Assignment Register (PCDPAR) controls the pin

function of ports C, D, I7, and I6.

PCDPAR is a read/write register when not in emulation mode.

PCDPA — Port C, D, I7, and I6 P in Assignment Bit

1 = Port C, D, I7, and I6 pins configured for primary function

0 = Port C, D, I7, and I6 pins configured for digital I/O

Address: 0x00c0_0030

Bit 7654321Bit 0

Read: PCDPA 0000000

Write:

Reset:See note0000000

= Writes have no effect and t he access ter m inates without a transfer er ro r except ion.

Note: Reset state determined during reset configur ati on. PCDPA = 1 except in single-chip

mode or when an external boot device is selected with a 16-bit port size in master mode.

Figure 12-6. Port C, D, I7, an d I6 Pin Assignmen t

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12.4.2.6 Port E Pin Assignment Register

The Port E Pin Assignment Register (PEPAR) controls the pin function

of port E.

PEPAR is a read/write register when not in emulation mode.

PEPA[7:0] — Port E Pin Assignment Bits

1 = Port E pins configured for primary function

0 = Port E pins configured for digital I/O

Address: 0x00c0_0031

Bit 76 54321Bit 0

Read: PEPA7 PEPA6 PEPA5 PEPA4 PEPA3 PEPA2 PEPA1 PEPA0

Write:

Reset: See note

Note: Reset state determined during r eset configuration as shown in Table 12-2.

Figure 12-7. Port E Pin Assignment Register (PEPAR)

Table 12-2. PEPAR Reset Values

PEPAR Pin Master

Mode Single-Chip

Mode Emulation

Mode

PEPA7 SHS 10 1

PEPA6 TA 10 1

PEPA5 TEA 10 1

PEPA[4:3] CSE[1:0] 0 0 1

PEPA[2:0] TC[2:0] 0 0 1

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Ports Module

Functional Description

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MOTOROLA Ports Module 2 81

12 .5 Fun cti on al Descr iptio n

The initial pin function is determined during reset configuration (see

Section 4. Chip Configuration Module (CCM)). The pin assignment

registers (PCDPAR and PEPAR) allow the user to select between digital

I/O or another pin function after reset.

In single-chip mode, all pins are configured as digital I/O by default.

Every digita l I/O pin is individually configur able as an input or an outpu t

via a data direction register (DDRx).

Every port has an output data register (PORTx) and a pin data register

(PORT xP/SETx) to moni tor and control the state of its pin s. Data writte n

to PORTx is stored and then driven to the corresponding PORTx pins

configured as outputs.

Read ing PORTx returns the current state of the register regardless of

the state of the corresponding pins.

Reading PORTxP returns the current state of the corresponding pins,

regardless of whether the pins are input or output.

Every port has a set register (PORTxP/SETx) and a clear register

(CLRx) for setting or clearing individual bits in PORTx.

In master mode and emulation mode, ports A and B function as the

upper external data bus, D[31:16]. When the PCDPA bit is set, ports C

and D function as the lower external data bus, D[15:0]. Ports E–I are

configured to support external memory and emulation functions.

In master mode, the function of EB[3:2] is determined by the PCDPA bit.

The function of CS[3:0] is determined by the individual chip select enable

(CSENx ) bits.

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282 Ports Module MOTOR OLA

Ports Module

12.5.1 Pin Functions

Table 12-3. Ports A–I Supported Pin Functions

Port

Ma st er M ode Sing le-C hi p Mode Em ul a ti on Mode(1)

D[31:24] A D[31:2 4] (I/O) PA[7:0] (I/O) D[31:2 4] (I/O)

D[23:16] B D[23:1 6] (I/O) P B [7:0](I/O) D[23:1 6](I/O)

D[15:8] C D[15:8 ] (I/O) (PCDPA = 1)

PC[7:0] (I/O) (PCDPA = 0) PC[7:0] (I/O) (PCDPA = 0)(2) D[15:8] (I/O) (PCDPA = 1)

D[7:0] D D[7:0] (I/O) (PCDPA = 1)

PD[7:0] (I/O) (PCDPA = 0) PD[7:0] (I/O) (PCDPA = 0)(2) D[7:0] (I/O) (PCDPA = 1)

SHS(3)

SHS (O) (PEPAR7 = 1)

PE7 (I/O) (PEPAR7 = 0) PE7 (I/O) (PEPAR7 = 0)(4) SHS (O) (PEPAR7 = 1)

TA TA (I) (PE PAR6 = 1)

PE6 (I/O) (PEPAR6 = 0) PE6 (I/O) (PEPAR6 = 0)(4) TA (I) (PEPAR6 = 1)

TEA TEA (I) (PEPAR5 = 1)

PE5 (I/O) (PEPAR5 = 0) PE5 (I/O) (PEPAR5 = 0)(4) TEA (I) (PEPAR5 = 1)

CSE[1:0]

CSE[1:0] (O)

(PEPAR[4:3] = 1)(5)

PE[4 :3 ] ( I/O) (PEPAR[4:3] = 0)

PE[4:3] (I/ O) (PEPAR[4:3] = 0)(4) CSE[1:0] (O) (PEPAR[4:3] = 1)

TC[2:0] TC[2:0] (O) (PEPAR[2:0] = 1)

PE[2 :0 ] ( I/O) (PEPAR[2:0] = 0) PE[2:0 ] ( I/O) (PEPAR[2 :0] = 0)(4) TC[2:0] (O) (PE PAR[2:0] = 1)

R/W FR/W (O) PF7 (I/O) R/W (O)

A[22:16] A[22 :16] (O) PF[6:0] (I/O) A[22:16] (O)

A[15:8] G A[15:8] (O) PG[7:0] (I/O) A[15:8] (O)

A[7 :0 ] H A[7:0] ( O) PH[7:0] ( I/O ) A[7 :0 ] ( O )

EB[3:2]

EB[3:2] (O) (PCDPA = 1)

PI[7:6] (I/O) (PCDPA = 0) PI[7:6] (I/O) (PCDPA = 0)(2) EB[3:2] (O) (PCDPA = 1 )

EB[1:0] EB[1:0] (O) PI[5:4] (I/O) EB[1:0] (O)

CS[3:0] CS[3:0] (O) (CSENx = 1)

PI[3:0] (I/O) (CSENx = 0) PI [3 :0 ] (I/O)(6) CS[3:0] (O)(6)

1. Digi tal I/O pin functi on provided by port replacement unit .

2. Writing PCDPA = 1 has an undefined pin operation for D[3 1:16] and EB[3:2] in single-chip mode.

3. This pin functions as the reset configurat ion override enable (RCON ) during reset.

4. Writing PEPAx = 1 has an undefined pin opera tion fo r port E pins in single-chip mode.

5. Writing PEPAx = 1 has an undefined pin operation for these port E pins in si ngle-chip and master modes.

6. CSENx has no effect on selecting CS[3:0] pin function in single-chip or emulation modes.

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Ports Module

Interrupts

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MOTOROLA Ports Module 2 83

12.5.2 Port Digital I/O Timing

Input data on all pins configured as digital I/O is synchronized to the

rising edge of CLKOUT. See Figure 12-8.

Figure 12-8. Digital Input Timing

Data written to PORTx of any pin configured as a digital output is

immediately driven to its respective pin. See Figure 12-9.

Figure 12-9. Digital Output Timing

12.6 Interrupts

The ports module does not generate interr upt requests.

CLKOUT

PIN DATA

INPUT

CLKOUT

OUTPUT DATA

OU T PUT PIN

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Ports Module

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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0  Advance Information
MOTOROLA Edge Port Module (EPOR T)  285
Advance Info rmation — MMC2114, MMC2113, and MMC2112
Section 13. Edge Port Module (EPORT)
13.1  Contents
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285
13.3 Low-Power Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . .286
13.3.1 Wait and Doze Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .286
13.3.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287
13.4 Interrupt/General-Purpose I/O Pin Descriptions. . . . . . . . . . .287
13.5 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .287
13.5.1 Memory Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287
13.5.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288
13.5.2.1 EPORT Pin Assignment Register . . . . . . . . . . . . . . . . .288
13.5.2.2 EPORT Data Direction Register. . . . . . . . . . . . . . . . . . .290
13.5.2.3 Edge Port Interrupt Enable Register . . . . . . . . . . . . . . .291
13.5.2.4 Edge Port Data Register . . . . . . . . . . . . . . . . . . . . . . . .292
13.5.2.5 Edge Port Pin Data Register . . . . . . . . . . . . . . . . . . . . .292
13.5.2.6 Edge Port Flag Register. . . . . . . . . . . . . . . . . . . . . . . . .293
13.2  Introduction
The edge port module (EPORT) has eight external interrupt pins. Each 
pin can be configured individually as a low level-sensitive interrupt pin, 
an edge-detecting interr upt pin (rising edge, falling edge, or both), or a 
general-purpose input/output (I/O) pin. See Figure 13-1.
    
  
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286 Edge Port Module (EPORT) MO TOROLA

Edge Port Module (EPORT)

Figure 13-1. EPORT Block Diagram

13.3 Low-Power Mode Operation

This subsection describes the operation of the EPORT module in

low-power modes.

13.3.1 Wait and Doze Modes

In wait and doze modes, the EPORT module continues to operate

normally and may be configured to exit the low-power modes by

generating an interrupt request on either a selected edge or a low level

on an external pin.

IPBUS

SYNCHRONIZER

EPDR[n]

EPFR[n]

EPPAR[ 2n, 2n + 1]

EPIER[n]

EDGE DE TECT

STOP

LOGIC

EPPDR[n]

D1 QD0

D1 Q

MODE

EPDDR[n]

TO INTERRUPT

CONTROLLER

INTx PIN

RISING EDGE

OF CLOCK

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Edge Port Module (EPORT)

Interrupt/General-Purpose I/O Pin Descriptions

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MOTOROLA Edge Port Module (EPOR T) 287

13.3.2 Stop Mode

In stop mode, there are no clocks available to perform the edge-detect

functi on. Only the level -detect l ogic is active (if configured ) to allo w any

low level on the external interrupt pin to generate an interrupt (if enabled)

to exit stop mode.

NOTE: The input pin synchronizer is bypassed for the level-detect logic since no

clocks are available.

13.4 Inter rup t/ Gen er al -P u rpo se I/O Pi n Desc ri ptio ns

All pins default to general-purpose input pins at reset. The pin value is

synchronized to the rising edge of CLKOUT when read from the EPORT

Pin Data Register (EP PDR). The values used in the edge/level detect

logic are also synchronized to the rising edge of CLKOUT. These pins

use Schmitt triggered input buffers which have built in hysteresis

designed to de crease the prob ability of gene rating false edge- triggered

interrupts for slow rising and falling input signals.

13.5 Memory Map and Register s

This subsection describes the memory map and register structure.

13.5.1 Memory Map

Refer to Table 13-1 for a description of the EP ORT memory map. The

EPORT has a base address of 0x00c6_0000.

Table 13-1. Edge Port Module Memory Map

Address Bits 15–8Bits 7–0 Access(1)

0x00c6_0000 EPORT Pin Assignment Register (EPPA R) S

0x00c6_0002 EPORT Data Direction Register (EPDDR) EPORT Interrupt Enable Register (EPIER) S

0x00c6_0004 EPORT Data Register (EPDR) EPORT Pin Data Register (EPPDR) S/U

0x00c6_0006 EPORT Flag Register (EPFR) Reserved(2) S/U

1. S = CPU supervi sor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor

only addresses have no effect and result in a cycl e termination transfer error.

2. Writ ing to reserved address locations has no effect, and reading returns 0s.

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288 Edge Port Module (EPORT) MO TOROLA

Edge Port Module (EPORT)

13.5.2 Registers

The EPORT programming model consists of these registers:

•The EPORT Pin Assignment Register (EPPAR) controls the

function of each pin individually.

•The EPORT Data Direction Register (EPDDR) controls the

direction of each one of the pins individually.

•The EPORT Interrupt Enable Register (EPIER) enables interrupt

requests for each pin individually.

•The E PORT D ata Reg ister (E PD R) holds th e data to be dr i ven to

the pins.

•The E PORT Pin Dat a Registe r (EPPDR) reflects the current sta te

of the pins.

•The EPORT Flag Register (EPFR) individually latches EPORT

edge events.

13.5.2.1 EPORT Pin Assignment Register

Address: 0x00c6_0000 and 0x00c6_0001

Bit 15 14 13 12 11 10 9 Bit 8

Read: EPPA7 EPPA6 EPPA5 EPPA4

Write:

Reset:00000000

Bit 76 54321Bit 0

Read: EPPA3 EPPA2 EPPA1 EPPA0

Write:

Reset:00000000

Figure 13-2. EPORT Pin Assignment Register (EPPAR)

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Edge Port Module (EPORT)

Mem ory Map and Registers

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MOTOROLA Edge Port Module (EPOR T) 289

EPPA[7:0] — EPORT Pin Assignment Select Fi elds

The read/write EPPAx fields configure EPORT pins for level detection

and rising and/or falling edge detection as Table 13-2 shows.

Pins configured as level-sensitive are inverted so that a logic 0 on the

external pin represents a valid interrupt request. Level-sensitive

interrupt inputs are not latched. To guarantee that a level-sensitive

interrupt request is acknowledged, the interrupt source must keep the

signal asserted until acknowledged by software. Level sensitivity

must be selected to bring the device out of stop mode with an INTx

interrupt.

Pins configured as edge-triggered are latched and need not remain

asserted for i nter rupt generati on. A p i n con figure d fo r e dge detecti o n

is monitored regardless of its configuration as input or output.

Interrupt requests generated in the EPORT module can be masked

by the interrupt controller module. EPPAR functionality is

independent of the selected pin direction.

Reset clears the EPPAx fields.

Table 13-2. EPPAx Field Settings

EPPAx Pin Con f ig ur a t ion

00 Pin INTx level-sensitive

01 Pin INTx rising edge triggered

10 Pin INTx falling edge triggered

11 Pin INTx both falling edge and rising edge triggered

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290 Edge Port Module (EPORT) MO TOROLA

Edge Port Module (EPORT)

13.5.2.2 EPORT Data Direction Register

EPDD[7:0] — Edge Port Data Direction Bits

Setting any bit in the E PDDR configur es th e cor responding pin as a n

output. Clearing any bit in EPDDR configures the corresponding pin

as an input. Pin direction is independent of the level/edge detection

configuration. Reset clears EPDD[7:0].

To use an EPORT pin as an external interrupt request source, its

corresponding bit in EPDDR must be clear. Software can generate

interrupt requests by programming the EPORT Data Register when

the EPDDR selects output.

1 = Corresponding EPORT pin configured as output

0 = Corresponding EPORT pin configured as input

Address: 0x00c6_0002

Bit 76 54321Bit 0

Read: EPDD7 EPDD6 EPDD5 EPDD4 EPDD3 EPDD2 EPDD1 EPDD0

Write:

Reset:00000000

Figure 13-3. EPORT Data Direction Register (EPDDR)

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Edge Port Module (EPORT)

Mem ory Map and Registers

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MOTOROLA Edge Port Module (EPOR T) 291

13.5.2.3 Edge Port Interrupt Enable Register

EPIE[7:0] — Edge Port Interrupt Enable Bits

The read/write EPIE[7:0] bits enable EPORT interrupt requests. If a

bit in EPIER is set, EPORT generates an interrupt request when:

•The corresponding bit in the EPORT Flag Register (EPFR) is

set or later becomes set, or

•The corr espond i ng pin le vel is l ow an d th e p i n is configured for

leve l-sensitive oper ati on

Clearing a bit in EP IER negates any interrupt request from the

corresponding EPORT pin. Reset clears EPIE[7:0].

1 = Interrupt requests from corresponding EPORT pin enabled

0 = Interrupt requests from corresponding EPORT pin disabled

Address: 0x00c6_0003

Bit 76 54321Bit 0

Read: EPIE7 EPIE6 EPIE5 EPIE4 EPIE3 EPIE2 EPIE1 EPIE0

Write:

Reset:00000000

Figure 13-4. EPORT Port Interrupt Enable Register (EPIER)

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292 Edge Port Module (EPORT) MO TOROLA

Edge Port Module (EPORT)

13.5.2.4 Edge Port Data Register

EPD[7 :0] — Edge Port Data Bits

Data written to E PDR is stored in an inte rnal register; if any pin of the

port is configured as an output, the bit stored for that pin is driven onto

the pi n. Reading E DPR re turn s the data stor ed in the reg is ter. Reset

sets EPD[7:0].

13.5.2.5 Edge Port P in Data Register

EPPD[7:0] — Edge Port Pin Data Bits

The read-only EPPDR reflects the current state of the EPORT pins.

Writing to EPPDR has no effect, and the write cycle terminates

normally. Reset does not affect EPPDR.

Address: 0x00c6_0004

Bit 76 54321Bit 0

Read: EPD7 EPD6 EPD5 EPD4 EPD3 EPD2 EPD1 EPD0

Write:

Reset:11111111

Figure 13-5. EP ORT Port Data Register (EPDR)

Address: 0x00c6_0005

Bit 7654321Bit 0

Read: EPPD7 EPPD6 EPPD5 EPPD4 EPPD3 EPPD2 EPPD1 EPPD0

Write:

Reset:PPPPPPPP

= Writes have no effect and the access terminates without a transf er error exception.

P = Current pin state

Figure 13-6. EPORT Port Pin Data Register (EPPDR)

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Edge Port Module (EPORT)

Mem ory Map and Registers

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MOTOROLA Edge Port Module (EPOR T) 293

13.5.2.6 Edge Port Flag Register

EPF[7:0] — Edge Port Flag Bits

When an EPORT pin is configured for edge triggering, its

corresponding read/write bit in EPFR indicates that the selected edge

has been detected. Reset clears EPF[7:0].

1 = Selected edge for INTx pin has been detected.

0 = Selected edge for INTx pin has not been detected.

Bits in thi s register are s et when the selected edg e is detecte d on the

corresponding pin. A bit remains set until cleared by writing a 1 to it.

Writing 0 has no effect. If a pin is configured as level-sensitive

(EPPARx = 00), pin transitions do not affect this register.

Address: 0x00c6_0006

Bit 76 54321Bit 0

Read: EPF7 EPF6 EPF5 EPF4 EPF3 EPF2 EPF1 EPF0

Write:

Reset:00000000

Figure 13-7. EPORT Port Flag Register (EPFR)

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294 Edge Port Module (EPORT) MO TOROLA

Edge Port Module (EPORT)

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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0  Advance Information
MOTO ROLA Watchdog Timer Module  2 95
Advance Info rmation — MMC2114, MMC2113, and MMC2112
Section 14. Watc hdog Time r Modu le
14.1  Contents
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
14.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
14.3.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
14.3.2 Doze Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
14.3.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
14.3.4 Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
14.4 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
14.5 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
14.6 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .298
14.6.1 Memory Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
14.6.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
14.6.2.1 Watchdog Control Register . . . . . . . . . . . . . . . . . . . . . .299
14.6.2.2 Watchdog Modulus Register . . . . . . . . . . . . . . . . . . . . .301
14.6.2.3 Watchdog Count Register . . . . . . . . . . . . . . . . . . . . . . .302
14.6.2.4 Watchdog Service Register . . . . . . . . . . . . . . . . . . . . . .303
14.2  Introduction
The w a tchdog  time r i s  a 16 -bit timer  used  to  help so ftw are  re cover  from  
runaway code. The watchdog timer has a free-running down-counter 
(watchdog counter) that generates a reset on underflow. To prevent a 
reset, soft w are must per i odically restart the countd ow n by serv icing the 
watchdog.
    
  
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296 Watchdog T ime r Module MOTOROLA

Wa tchdog Timer Module

14.3 Modes of Operation

This subsection describes the operation of the watchdog timer in

low-power modes and debug mode of operation.

14.3.1 Wait Mode

In wait mode with the WAIT bit set in the Watchdog Control Register

(WCR) , watch dog ti mer op eratio n sto ps. I n w ait mod e wi th the WAI T b it

clear, the watchdog timer continues to operate normally.

14.3.2 Doze Mode

In doze mode with the DOZE bit set in WCR, watchdog timer module

operation stops. In doze mode with the DOZE bit clear, the watchdog

timer continues to operate normally.

14.3.3 Stop Mode

The wat chdog operation st ops in stop m ode. Wh en stop mod e is exited,

the watchdog operation continues operation from the state it was in prior

to entering stop mode.

14.3.4 Debug Mode

In debug mode with the DBG bit set in WCR, watchdog timer module

operation stops. In debug mode with the DBG bit clear, the watchdog

timer continues to operate normally. When debug mode is exited,

watchdog timer operation continues from the state it was in before

entering debug mode, but any updates made in debug mode remain.

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Watchdog Timer Module

Block Diagram

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MOTO ROLA Watchdog Timer Module 297

14.4 Blo ck Diag r am

Figu re 14-1. Watchdog Timer Block Diagram

14.5 Signals

The watchdog timer module has no off-chip signals.

16-BIT WMR

16-BIT WATCHDOG COUNTER

COUNT = 0

SYSTEM DIVIDE BY RESET

CLOCK

IPBUS

4096

16-BIT WCN T R 16-BIT WS R

IPBUS

LOAD COUNTER

WAIT

DOZE

DBG

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298 Watchdog T ime r Module MOTOROLA

Wa tchdog Timer Module

14.6 Memory Map and Register s

This subsection describes the memory map and registers for the

watchdog timer. The watchdog timer has a base address of

0x00c7_0000.

14.6.1 Memory Map

Refer to Table 14-1 for an overview of the watchdog memory map.

14.6.2 Registers

The watchdog timer programming model consists of these registers:

•The Watchdog Control Register (WCR) configures watchdog timer

operation. See 14.6.2.1 Watchdog Contr ol Register.

•The Watchdog Modulus Register (WMR) determines the timer

modulus reload value. See 14.6.2.2 W at chd og Modulus

•The Watchd og Count Register (WCNTR) pro vides visibility to the

watchdog counter value. See 14.6.2.3 Watchdog Count

•The Watchdog Service Register (WSR) requires a service

sequence to prevent reset. See 14.6.2.4 Watchdog Service

Table 14-1. Watchd og Timer Modu le Memory Map

Address Bits 15–8Bits 7–0 Access(1)

1. S = CPU super visor mode access only. S/U = CPU supervisor or user mode access. Use r

mode accesses to super visor on ly addres ses have no effect and res ult in a cycle t ermina-

ti on tra n s fe r err o r.

0x00c7_0 000 Watchdog Control Register (WCR) S

0x00c7_0 002 Wat c hdog Mo dulus Register (WMR) S

0x00c7_0004 Watchdog Count Register (WCNTR) S/U

0x00c7_0006 Wat chdog Service Register (WSR) S/U

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MOTO ROLA Watchdog Timer Module 299

14.6.2.1 Watchdog Control Register

The 16-bit read/write Watchdog Control Register (WCR) configures

watchdog timer operation.

WAIT — Wait Mode B it

The read-always, write-once WAIT bit controls the function of the

watchdog timer in wait mode. Once written, the W AIT bit is not

affected by further writes except in debug mode. Reset sets WAIT.

1 = Watchdog timer stopped in wait mode

0 = Watchdog timer not affected in wait mode

DOZE — Doze Mode Bit

The read-always, write-once DOZE bit controls the function of the

watchdog timer in doze mode. Once written, the DOZE bit is not

affected by further writes except in debug mode. Reset sets DOZE.

1 = Watchdog timer stopped in doze mode

0 = Watchdog timer not affected in doze mode

Address: 0x00c7_0000 and 0x00c7_0001

Bit 15 14 13 12 11 10 9 B it 8

Write:

Reset:00000000

Bit 7654321Bit 0

WAIT DOZE DBG EN

Write:

Reset:00001111

= Writes have no effect and the access terminates without a transf er error exception.

Figure 14-2. Watchdog Control Register (WCR)

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300 Watchdog T ime r Module MOTOROLA

Wa tchdog Timer Module

DBG — Debug Mode Bit

The read-always, write-once DBG bit controls the function of the

watchdog timer in debug mode. Once written, the DBG bit is not

affected by further writes except in debug mode.

During debug mode, watchdog timer registers can be written and read

normally. When debug mode is exited, timer operation continues from

the state it was in before entering debug mode, but any updates made

in debug mode remain. If a write-once register is written for the first

tim e in de bug m ode, t he re gi ster is st i ll wr itable w he n deb ug mo de is

exited.

1 = Watchdog timer stopped in debug mode

0 = Watchdog timer not affected in debug mode

NOTE: Changing the DBG bit from 1 to 0 during debug mode starts the

watchdog timer. Changing the DBG bit from 0 to 1 during debug mode

stops the w atchdog timer.

EN — Watchdog Enable Bit

The read-always, write-once EN bit enables the watchdog timer.

Once written, the EN bit is not affected by further writes except in

debug mode. When the watchdog timer is disabled, the watchdog

counter and prescaler counter are held in a stopped state.

1 = Wat chdog timer enabled

0 = Wat chdog timer disabled

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MOTO ROLA Watchdog Timer Module 301

14.6.2.2 Watchdog Modulus Register

WM[15:0] — Watchdog Modulus Fiel d

The read-always, write-once WM[15:0] field contains the modulus

that is reloaded into the watchdog counter by a service sequence.

Once written, the WM[15:0] field is not affected by further writes

except in debug mode. Writing to WMR immediately loads the new

modulus value into the watchdog counter. The ne w value is also used

at the next and all subsequent reloads. Reading WMR returns the

value in the modulus register.

Reset initializes the WM[15:0] field to 0xFFFF.

NOTE: The prescaler counter is reset anytime a new value is loaded into the

watchdog counter and also during reset.

Address: 0x00c7_0002 and 0x00c7_0003

Bit 15 14 13 12 11 10 9 Bit 8

Read: WM15 WM14 WM13 WM12 WM11 WM10 WM9 WM8

Write:

Reset:11111111

Bit 76 54321Bit 0

Read: WM7 WM6 WM5 WM4 WM3 WM2 WM1 WM0

Write:

Reset:11111111

Figu re 14-3. Watchdog Modulus Register (WMR)

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302 Watchdog T ime r Module MOTOROLA

Wa tchdog Timer Module

14.6.2.3 Watchdog Count Register

WC[15:0] — Watchdog Count Field

The read-only WC[15:0] field reflects the current value in the

watch dog counte r. Reading t he 16-bi t WCNTR with two 8-bit rea ds is

not guar anteed to retu rn a coheren t value. Writi ng to WCNTR has no

effect, and write cycles are ter minated normally.

Address: 0x00c7_0004 and 0x00c7_0005

Bit 15 14 13 12 11 10 9 B it 8

Read: WC15 WC14 WC13 WC12 WC11 WC10 WC9 WC8

Write:

Reset:11111111

Bit 7654321Bit 0

Read: WC7 WC6 WC5 WC4 WC3 WC2 WC1 WC0

Write:

Reset:11111111

= Writes have no effect and the access terminates without a transf er error exception.

Figure 14-4. Watch dog Count Reg ister (WCNTR)

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MOTO ROLA Watchdog Timer Module 303

14.6.2.4 Watchdog Service Register

When the watchdog timer is enabled, writing 0x5555 and then 0xAAAA

to the Watchdog Service Register (WSR) before the watchdog counter

times o ut prevents a reset. If WSR is not serviced before the timeout, the

watch dog timer sends a signa l to the reset control ler module which sets

the WDR bit and asserts a system reset.

Both writes must occur in the order listed before the timeout, but any

number of instructions can be executed between the two writes.

However, writing any value other than 0x5555 or 0xAAAA to WSR resets

the servicing sequence, requiring both values to be written to keep the

watchdog timer from causing a reset.

Address: 0x00c7_0006 and 0x00c7_0007

Bit 15 14 13 12 11 10 9 Bit 8

Read: WS15 WS14 WS13 WS12 WS11 WS10 WS9 WS8

Write:

Reset:00000000

Bit 76 54321Bit 0

Read: WS7 WS6 WS5 WS4 WS3 WS2 WS1 WS0

Write:

Reset:00000000

Figure 14-5. Watchdog Service Register (WSR)

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304 Watchdog T ime r Module MOTOROLA

Wa tchdog Timer Module

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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0  Advance Information
MOTOROLA Programmable Interrupt Timer Modules (PIT1 and PIT2)  305
Advance Info rmation — MMC2114, MMC2113, and MMC2112
Section 15. Programmable Interrupt Timer Modules
(PIT1 and PIT2)
15.1  Contents
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
15.3 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
15.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
15.4.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
15.4.2 Doze Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
15.4.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
15.4.4 Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
15.5 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
15.6 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .308
15.6.1 Memory Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
15.6.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
15.6.2.1 PIT Control and Status Register . . . . . . . . . . . . . . . . . .309
15.6.2.2 PIT Modulus Register  . . . . . . . . . . . . . . . . . . . . . . . . . .312
15.6.2.3 PIT Count Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
15.7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
15.7.1 Set-and-Forget Timer Operation . . . . . . . . . . . . . . . . . . . .314
15.7.2 Free-Running Timer Operation  . . . . . . . . . . . . . . . . . . . . .315
15.7.3 Timeout Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . .315
15.8 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316
    
  
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306 Progra mmable Interrupt Timer Modules (PIT1 and PIT2) MOTOR OLA

Pr ogrammable Interrup t Timer Modules (PIT1 and PIT2)

15.2 Introduction

The programmable interrupt timer (PIT) is a 16-bit timer that provides

precise interrupts at regular intervals with minimal processor

intervention. The timer can either count down from the value written in

the modulus latch, or it can be a free-running down-counter.

This device has two programmable interrupt timers. PIT1 has a base

address located at 0x00c8_0000. PIT2 base address is 0x00c9_0000.

15.3 Blo ck Diag r am

Figure 15-1. PIT Block Diagram

16-BIT PMR

16-BIT PIT COUNTER

CO UNT = 0

SYSTEM

CLOCK

IPBUS

16-BIT PCNTR

IPBUS

EN OVW

PDOZE

PDBG

PRESCALER

PRE[3:0] RLD

PIF

PIE

LOAD

COUNTER

TO INTERRUPT

CONTROLLER

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Program m able Interrupt Timer Modules (PIT1 and PIT2)

Modes of Op eration

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MOTOROLA Programmable Interrupt Timer Modules (PIT1 and PIT2) 307

15.4 Modes of Operation

This subsection describes the three low-power modes and the debug

mode.

15.4.1 Wait Mode

In wait mod e, the PIT modu le conti nues to operate nor mally and can be

configured to exit the low-power mode by generating an interrupt

request.

15.4.2 Doze Mode

In doze mode with the PDOZE bit set in the PIT Control and Status

PDOZE bit clear, doze mod e doe s not affect PIT op erat ion. W hen d oze

mode is exited, PIT operation continues from the state it was in before

entering doze mode.

15.4.3 Stop Mode

In stop mode, the system clock is absent, and PIT module operation

stops.

15.4.4 Debug Mode

In debug mode with the PD BG bit set in PCSR, PIT module operation

stops. In debug mode with the PDBG bit clear, debug mode does not

affect PIT operation. When debug mode is exited, PIT operation

continues from the state it was in before entering debug mode, but any

updates made in debug mode remain.

15.5 Signals

The PIT module has no off-chip signals.

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308 Progra mmable Interrupt Timer Modules (PIT1 and PIT2) MOTOR OLA

Pr ogrammable Interrup t Timer Modules (PIT1 and PIT2)

15.6 Memory Map and Register s

This subsection describes the memory map and register structure for

PIT1 and PIT2.

15.6.1 Memory Map

Refer to Table 15-1 for a description of the memo ry map.

This device has two programmable interrupt timers. PIT1 has a base

address located at 0x00c8_0000. PIT2 base address is 0x00c9_0000.

15.6.2 Registers

The PIT programming model consists of these registers:

•The PIT Control and Status Register (PCSR) configures the

timer’s operation. See 15.6.2.1 PIT Control and Status Register.

•The PIT Modulus Register (PMR) determines the timer modulus

reload value. See 15.6.2.2 PIT Modulus Register.

•The PIT Count Register (PCNTR) provides visibility to the counter

value. See 15.6.2.3 P IT Count Register.

Table 15-1. Programmable Interrupt Timer Modules Memory Map

PIT1

Address PIT2

Address Bits 15–8Bits 7–0 Access(1)

0x00c8_0000 0x00c9_0000 PIT Control and Status Register (PCSR) S

0x00c8_0002 0x00c9_0002 PIT Modulu s Register (PMR) S

0x00c8_0004 0x00c9_0004 PIT Count Registe r (PCNTR) S/U

0x00c8_0006 0x00c9_0006 Unimplemented(2) —

1. S = CPU supervi sor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor

only addresses have no effect and result in a cycl e termination transfer error.

2. Accesses to unimplem ented address locations have no eff ect and result in a cycle terminat ion tr ansfer error.

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MOTOROLA Programmable Interrupt Timer Modules (PIT1 and PIT2) 309

15.6.2.1 PIT Control and Status Register

PRE[3:0] — Prescaler Bits

The read/write PRE[3:0] bits select the system clock divisor to

generate the PIT clock as Table 15-2 shows.

To accurately predict the timing of the next count, change the

PRE[3:0] bits only when the enable bit (EN) is clear. Changing the

PRE[ 3:0] re sets the pr escaler counter . System reset and the loadi ng

of a new value into the counter also reset the prescaler counter.

Setting the EN bit and writing to PRE[3:0] can be done in this same

write cycle. Clearing the EN bit stops the prescaler counter.

PDOZE — Doze Mode Bit

The read/write PDOZE bit controls the function of the PIT in doze

mode. Reset clears PDOZE.

1 = PIT function stopped in doze mode

0 = PIT function not affected in doze mode

When doze mode is exited, timer operation continues from the state

it was in before entering doze mode.

Address: PIT1 — 0x00c8_0000 and 0x00c8_0001

PIT2 — 0x00c9_0000 and 0x00c9_0001

Bit 15 14 13 12 11 10 9 B it 8

PRE3 PRE2 PRE1 PRE0

Write:

Reset:00000000

Bit 7654321Bit 0

Read: 0 PDOZE PDBG OVW PIE PIF RLD EN

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transf er error exception.

Figu re 15-2. PIT Control and Status Register (PCSR)

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310 Progra mmable Interrupt Timer Modules (PIT1 and PIT2) MOTOR OLA

Pr ogrammable Interrup t Timer Modules (PIT1 and PIT2)

PDBG — Debug Mode Bit

The read/write PDBG bit controls the function of the PIT in debug

mode. Reset clears PDBG.

1 = PIT function stopped in debug mode

0 = PIT function not affected in debug mode

During debug mode, register read and write accesses function

normally. When debug mode is exited, timer operation continues from

the state it was in before entering debug mode, but any updates made

in debug mode remain.

NOTE: Changing the PDBG bit from 1 to 0 during debug mode starts the PIT

timer. Likewise, changing the PDBG bit from 0 to 1 during debug mode

stops the PIT timer.

Table 15-2. Prescaler Select Encoding

PRE[3:0] System Clock Divisor

0000 1

0001 2

0010 4

0011 8

0100 16

0101 32

0110 64

0111 128

1000 256

1001 512

1010 1,024

1011 2,048

1100 4,096

1101 8,192

1110 16,384

1111 32,768

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Mem ory Map and Registers

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MOTOROLA Programmable Interrupt Timer Modules (PIT1 and PIT2) 311

OVW — Overwrite Bit

The read/write OVW bit enables wr iting to PMR to immediately

overwrite the value in the PIT counter.

1 = Writing PMR immediately replaces value in PIT counter.

0 = Valu e in PMR replaces value in PIT counter when count

reaches 0x0000.

PIE — PIT Interrupt Enable Bit

The read/write PIE bit enables the PIF flag to generate interrupt

requests.

1 = PIF interrupt requests enabled

0 = PIF interrupt requests disabled

PIF — PIT Interrupt Flag

The rea d/wri te PIF fl ag is set when the PIT counter reache s 0x0000.

Clear PIF by wr iting a 1 to it or by writing to PMR. Writing 0 has no

effect. Reset clears PIF.

1 = PIT count has reached 0x0000.

0 = PIT count has not reached 0x0000.

RLD — Rel oad Bit

The read/write RLD bit enables loading the value of PMR into the PIT

counter when the count reaches 0x0000.

1 = Counter reloaded from PMR on count of 0x0000

0 = Counter rolls over to 0xFFFF on count of 0x0000

EN — PIT Enable Bi t

The read/write EN bit enables PIT operation. When the PIT is

disabled, the counter and prescaler are held in a stopped state.

1 = PIT enabled

0 = PIT disabled

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312 Progra mmable Interrupt Timer Modules (PIT1 and PIT2) MOTOR OLA

Pr ogrammable Interrup t Timer Modules (PIT1 and PIT2)

15.6.2.2 PIT Modulus Register

The 16-bit read/write PIT Modulus Register (PMR) contains the timer

modul us value for loading i nto the PIT counter when the count reach es

0x0000 and the RLD bit is set.

When the OVW bit is set, PMR is transparent, and the value written to

PMR is imme diatel y load ed into the PIT counte r. Th e presca ler coun ter

is reset anytime a new value is loaded into the PIT counter and also

duri ng r eset. Re ading th e P MR ret urns th e val ue wr itten i n t he mo dulus

latch. Reset initializes PMR to 0xFFFF.

Address: PIT1 — 0x00c8_0002 and 0x00c8_0003

PIT2 — 0x00c9_0002 and 0x00c9_0003

Bit 15 14 13 12 11 10 9 Bit 8

Read: PM15 PM14 PM13 PM12 PM11 PM10 PM9 PM8

Write:

Reset:11111111

Bit 76 54321Bit 0

Read: PM7PM6PM5PM4PM3PM2PM1PM0

Write:

Reset:11111111

Figure 15-3. PIT Modulus Register (PMR)

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Mem ory Map and Registers

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MOTOROLA Programmable Interrupt Timer Modules (PIT1 and PIT2) 313

15.6.2.3 PIT Count Register

The 16-bit, read-only PIT Control Register (PCNTR) contains the

counter value. Reading the 16-bit counter with two 8-bit reads is not

guaranteed to be coherent. Writing to PCNTR has no effect, and write

cycles are terminated normally.

Address: PIT1 — 0x00c8_0004 and 0x00c8_0005

PIT2 — 0x00c9_0004 and 0x00c9_0005

Bit 15 14 13 12 11 10 9 B it 8

Read: PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8

Write:

Reset:11111111

Bit 7654321Bit 0

Read: PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

Write:

Reset:11111111

= Writes have no effect and the access terminates without a transf er error exception.

Figure 15-4. PIT Count Register (PCNTR)

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314 Progra mmable Interrupt Timer Modules (PIT1 and PIT2) MOTOR OLA

Pr ogrammable Interrup t Timer Modules (PIT1 and PIT2)

15 .7 Fun cti on al Descr iptio n

This subsection describes the PIT functional operation.

15.7.1 Set-and-Forget Timer Operation

This mode of operation is selected when the RLD bit in the PCSR

When the PIT counter reaches a count of 0x0000, the PIF flag is set in

PCSR. The value in the modulus latch is loaded into the counter, and the

counter begins decrementing toward 0x0000. If the PIE bit is set in

PCSR, the PIF flag issues an interrupt request to the CPU.

When the OVW bit is set in PCSR, the counter can be directl y initialized

by writing to PMR without having to wait for the count to reach 0x0000.

Figure 15-5. Counter Reloading from the Modulus Latch

0x0002 0x0001 0x0000 0x0005

0x0005

PIT CLOC K

COUNTER

MODULUS

PIF

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Functional Description

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MOTOROLA Programmable Interrupt Timer Modules (PIT1 and PIT2) 315

15.7.2 Free-Running Timer Operation

This mode of operation is selected when the RLD bit in PCSR is clear.

In this mode, the counter rolls over from 0x0000 to 0xFFFF without

reloading from the modulus latch and continues to decrement.

When the counter reaches a count of 0x0000, the PIF flag is set in

PCSR. If the PIE bit is set in PCSR, the PIF flag issues an interrupt

request to the CPU.

When the OVW bit is set in PCSR, the counter can be directl y initialized

by writing to PMR without having to wait for the count to reach 0x0000.

Figu re 15-6. Counter in Free-Runnin g Mode

15.7.3 Timeout Sp ecifications

The 1 6-bit PI T counter and pre scaler suppo rts differe nt tim eout perio ds.

The pre scaler divide s the system clock as sel ected by the PRE[3:0] bits

in PCSR. The PM[15:0] bits in PMR select the timeout period.

timeout period = PRE[3:0] × (PM[15:0] + 1) clocks

0x0002 0x0001 0x0000 0xFFFF

0x0005

PIT CLOC K

COUNTER

MODULUS

PIF

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316 Progra mmable Interrupt Timer Modules (PIT1 and PIT2) MOTOR OLA

Pr ogrammable Interrup t Timer Modules (PIT1 and PIT2)

15.8 Inter rup t Op eration

Table 15-3 lists the interrupt requests generated by the PIT.

The PIF flag is set when the PIT counter reaches 0x0000. The PIE bit

enabl es the PIF flag to ge nera te in terr upt requ ests. Cle ar PIF b y writi ng

a 1 to it or by writing to the PMR.

Table 15-3. PIT Interrupt Requests

Interrupt Requ est F lag E na ble Bit

Timeout PIF PIE

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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0  Advance Information
MOTOROLA Timer Modules (TIM1 and TIM2)  317
Advance Info rmation — MMC2114, MMC2113, and MMC2112
Section 16. Timer Modules (TIM1 and TIM2)
1  Contents
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319
4 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320
5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
5.1 Supervisor and User Modes. . . . . . . . . . . . . . . . . . . . . . . .321
5.2 Run Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
5.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
5.4 Wait, Doze, and Debug Modes  . . . . . . . . . . . . . . . . . . . . .321
5.5 Test Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
6 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
6.1 ICOC[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
6.2 ICOC3  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
7 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .323
7.1 Timer Input Capture/Output Compare Select Register  . . .324
7.2 Timer Compare Force Register . . . . . . . . . . . . . . . . . . . . .325
7.3 Timer Output Compar e 3 Mask Register . . . . . . . . . . . . . .326
7.4 Timer Output Compar e 3 Data Register. . . . . . . . . . . . . . .327
7.5 Timer Counter Registers  . . . . . . . . . . . . . . . . . . . . . . . . . .328
7.6 Timer System Control Register 1. . . . . . . . . . . . . . . . . . . .329
7.7 Timer To ggle-On-Overflow Register  . . . . . . . . . . . . . . . . .330
7.8 Timer Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . .331
7.9 Timer Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . .332
7.10 Timer Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . .333
7.11 Timer System Control Register 2. . . . . . . . . . . . . . . . . . . .334
7.12 Timer F lag Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
7.13 Timer F lag Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
7.14 Timer Channel Registers  . . . . . . . . . . . . . . . . . . . . . . . . . .338
    
  
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Timer Modules (TIM1 and TIM2) MOTOROLA
Timer Modules (TIM1 a nd TIM2)
7.15 Pulse Accumulator Control Register  . . . . . . . . . . . . . . . . .339
7.16 Pulse Accumulator Flag Register. . . . . . . . . . . . . . . . . . . .341
7.17 Pulse Accumulator Counter Registers . . . . . . . . . . . . . . . .342
7.18 Timer Port Data Register . . . . . . . . . . . . . . . . . . . . . . . . . .343
7.19 Timer Port Data Direction Register  . . . . . . . . . . . . . . . . . .344
7.20 Timer T e st Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
8.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
8.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
8.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346
8.4 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347
8.4.1 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .347
8.4.2 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . .348
8.5 General-Purpose I/O Ports. . . . . . . . . . . . . . . . . . . . . . . . .349
9 Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351
10 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351
10.1 Timer Channel Interrupts (CxF) . . . . . . . . . . . . . . . . . . . . .351
10.2 Pulse Accumulator Overflow (PAOVF). . . . . . . . . . . . . . . .352
10.3 Pulse Accumulator Input (PAIF). . . . . . . . . . . . . . . . . . . . .352
10.4 Timer Overflow (TOF)  . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
    
  
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Timer Modules (TIM1 and TIM2)

Introduction

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MOTO ROLA T imer Modul es (TIM1 and TIM2) 319

16.2 Introduction

The MMC2114, MMC2113 and MM C2112 have two 4-channel timer

modules (TIM1 and TIM2). Each consists of a 16-bit programmable

counter driven by a 7-stage programmable prescale r. Each of the four

timer channels can be configured for input capture or output compare.

Additionally, one of the channels, channel 3, can be configured as a

pulse accumulator.

A timer overflow function allows softwar e to exten d the timin g capability

of the syst em b eyond the 1 6-bit rang e of t he cou nter. The input captur e

and output compare functions allow simultaneous input waveform

measurements and output waveform generation. The input capture

function can capture the time of a selected transitio n edge. The output

compare function can generate output waveforms and timer software

delays. The 16-bit pulse accumulator can operate as a simple event

counter or a gated time accumulator. The pulse accumulator shares

timer channel 3 when in event mode.

16.3 Features

Features of the timer include:

•Four 16-bit input capture/output compare channels

•16-bit architecture

•Programmable prescaler

•Pulse widths variab le from microseconds to seconds

•Single 16-bit pulse accumulator

•Toggle-on-overflow feature for pulse-width modulator (PWM)

generation

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320 Timer Modules (TIM1 and TIM2) MOTOROLA

Timer Modules (TIM1 a nd TIM2)

16.4 Blo ck Diag r am

Figure 16-1. Timer Block Diagram

PRESCALER

CHANNEL 0

PT0

16- BIT COUNTE R

SYSTEM

LOGIC

PR[2:0]

DIVIDE-BY-64 MODULE CLOCK

TIMC0H:TIMC0L

EDGE

DETECT

TIMPACNTH:TIMPACNTL

PAOVF PEDGE

PAOVI

PAMOD

PAE

16-BIT COMPARATOR

TIMCNTH:TIMCNTL

16-BIT LATCH

CHANNEL 1

TIMC1H:TIMC1L

16-BIT COMPARATOR

16-BIT LATCH

16- BIT COUNTE R

INTERRUPT

LOGIC

TOF

TOI

C0F

C1F

EDGE

DETECT

PT1

LOGIC

EDGE

DETECT

CxF

CHANNEL 2

CHANNEL3

TIMC3H:TIMC3L

16-BIT COMPARATOR

16-BIT LATCH

C3F PT3

LOGIC

EDGE

DETECT

IOS0

IOS1

IOS3

OM:OL0

TOV0

OM:OL1

TOV1

OM:OL3

TOV3

EDG1A

EDG1B

EDG3A

EDG3B

EDG0A

EDG0B

TCRE

CHANNEL 3 OUTPUT COMPARE

PAIF

CLEA R CO UNTER

PAIF

PAI

INTERRUPT

LOGIC

CxI

INTERRUPT

REQUEST

INTERRUPT

REQUEST

PAOVF

CH. 3 COMPA RE

CH.3 CAP TURE

CH. 1 CAPTURE

MUX

CLK[1:0]

PACLK

PACLK/256

PACLK/65536

PACLK

PACLK/256

PACLK/65536

CLOCK

CH. 1 COMPARE

CH. 0 COMPARE

CH. 0 CAPTURE

PA INPUT

MUX

ICOC0

ICOC1

ICOC3

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Timer Modules (TIM1 and TIM2)

Modes of Op eration

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MOTO ROLA T imer Modul es (TIM1 and TIM2) 321

16.5 Modes of Operation

This subsection describes the supervisor and user modes, the five

low-power options, and test mode.

16.5.1 Supervisor and User Modes

The SO bit in the Chip-Select Control Register determines whether the

processor is operating in user mode or supervisor mode. Accessing

supervisor address locations while no t in supervisor mode causes the

timer to assert a transfer error. See Figure 21-2. Chip Select Control

Regi ster 0 (CSCR0).

16.5.2 Run Mode

Clearing the TIMEN bit in the Timer System Control Register 1

(TIMSCR1) or the PAE bit in the Pulse Accumulator Control Register

(TIMPACTL) reduces power consumption in run mode. Timer registers

are still accessible, but all timer functions are disabled. See Figure 16-8.

Timer System Control Register (TIMSCR1) and Figur e 16- 19. Pulse

Accumulator Control Register (TIMPACTL).

16.5.3 Stop Mode

If the central processor unit (CPU) enters stop mode, timer operation

stops. Upon exiting stop mode, the timer resumes operation unless stop

mode was exited by reset.

16.5.4 Wait, Doze, and Debug Modes

The timer is unaffected by these low-power modes.

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16.5.5 Test Mode

A high signal on the TEST pin puts the pro cessor in test mode or special

mode. The timer behaves as in user mode, except that timer test

registers are accessible.

16.6 Signal Description

Table 16-1 provides an overvi ew of the signal properties.

16.6.1 ICOC[2:0]

The ICOC[2:0] pins are for channel 2–0 input capture and output

compare functions. These pins are available for general-purpose

input/output (I/O) when not configured fo r timer functions.

16.6.2 ICOC3

The ICOC3 pin is for channel 3 input capture and output compare

functions or for the pulse accumulator input. This pin is available for

general-purpose I/O when not configured for timer functions.

Table 16-1. Signal Properties

Name(1)

1. x is timer designation 1 or 2

TIMPORT

ICOCx0 PORTT 0 Timer x ch annel 0 IC/OC pin Pin state Active

ICOCx1 PORTT 1 Timer x ch annel 1 IC/OC pin Pin state Active

ICOCx2 PORTT 2 Timer x ch annel 2 IC/OC pin Pin state Active

ICOCx3 PORTT3 T imer x channel 3 IC/OC or PA pin Pin state Active

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Timer Modules (TIM1 and TIM2)

Mem ory Map and Registers

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MOTO ROLA T imer Modul es (TIM1 and TIM2) 323

16.7 Memory Map and Register s

See Table 16-2 for a memory map of the two timer modules. Timer 1 has

a base address of 0x00ce_0000. Timer 2 has a base address of

0x00cf_0000.

NOTE: Reading reserved or unimplemented locations returns 0s. Writing to

reserved or unimpl emented locations has no effect.

Table 16-2. Timer Modu les Memory Map

Address Bits 7–0 Access(1)

TIM1 TIM2

0x00 ce_0000 0x00c f_0000 Timer IC/OC Select Register (TIMIOS) S

0x00ce_0001 0x00cf_0001 Ti mer Compare Force Register (TIMCFORC) S

0x00ce_0002 0x00cf_0002 T imer Output Compare 3 Mask Register (TIMOC3M) S

0x00 ce_0003 0x00cf_0003 Timer Output Compare 3 Data Register (TIMOC 3D) S

0x00 ce_0004 0x00cf_00 04 Tim er Counter Register High (TIMCNTH) S

0x00 ce_0005 0x00c f_0005 Timer Counter Register Low (TIMCNTL) S

0x00ce_0006 0x00cf_0006 T imer System Control Register 1 (TIMSCR1) S

0x00ce_0007 0x00cf_0007 Reserved(2)

0x00 ce_0008 0x00cf_0008 Timer Toggle-on-Overflow Regist er (TMTOV) S

0x00ce_0009 0x00cf_0009 T i mer Control Register 1 (TIMCTL1) S

0x00ce_000a 0x00cf_000a Reserved(2)

0x00ce_000b 0x00cf_000b T i mer Control Register 2 (TIMCTL2) S

0x00ce_000c 0x00cf_000c Timer Interrupt Enable Register (TIMIE) S

0x00ce_000d 0x00cf_000d T imer System Control Register 2 (TIMSCR2) S

0x00ce_000e 0x00cf_000e T i mer Flag Register 1 (TIMFLG1) S

0x00ce_000f 0x00cf_000f T i mer Flag Register 2 (TIMFLG2) S

0x00 ce_0010 0x00c f_0010 Ti mer Chann el 0 Register High (TIMC0H) S

0x00ce_00 11 0x00cf _0011 Ti me r Channel 0 Register Low (TIMC0L) S

0x00 ce_0012 0x00c f_0012 Ti mer Chann el 1 Register High (TIMC1H) S

0x00 ce_0013 0x00cf_0013 Ti me r Chan nel 1 Register Low (TIMC1L) S

0x00 ce_0014 0x00c f_0014 Ti mer Chann el 2 Register High (TIMC2H) S

0x00 ce_0015 0x00cf_0015 Ti me r Chan nel 2 Register Low (TIMC2L) S

0x00 ce_0016 0x00c f_0016 Ti mer Chann el 3 Register High (TIMC3H) S

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324 Timer Modules (TIM1 and TIM2) MOTOROLA

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16.7.1 Timer Input Captur e/Outpu t Compare Select Register

Read : Anytime; always read $00

Write: Anytime

IOS[3:0] — I/O Select Bits

The IOS[3:0] bits enable input capture or output compare operation

for the corresponding timer channels.

1 = Output compa re enabled

0 = Input capture enabled

0x00 ce_0017 0x00cf_0017 Ti me r Chan nel 3 Register Low (TIMC3L) S

0x00 ce_0018 0x00c f_0018 Pulse Accumulator Control Register (TIMPACT L) S

0x00 ce_0019 0x00cf_0019 Pulse A ccu mulato r Flag Register (TIMPAFLG) S

0x00ce_001a 0x00cf_001a Pulse Accumulator Counter Register High (TIMPACNTH) S

0x00 ce_001b 0x00c f_001b Pulse Accum ulator Counter Register Low (TIMPACNT L) S

0x00ce_001c 0x00cf_001c Reserved(2)

0x00 ce_001d 0x0 0cf_00 1d Timer Port Data Register (TIMPORT) S

0x00ce_001e 0x0 0cf_001e Time r Port Data Direction R egister (TIMDDR) S

0x00ce_0 01f 0x00cf_001 f Timer Te st Register (TIMTST) S

1. S = CPU supervisor mode access only.

2. Writ es have no effect, reads re turn 0s, and the access terminates wit hout a transfer error exception.

Table 16-2. Timer Modules Memory Map (Continued)

Address Bits 7–0 Access(1)

TIM1 TIM2

Address: TIM1 — 0x00ce_0000

TIM2 — 0x00cf_0000

Bit 7654321Bit 0

IOS3 IOS2 IOS1 IOS0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transf er error exception.

Figure 16- 2. Timer Input Capture/ Outp ut C ompare

Select Register (TIMIOS)

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Mem ory Map and Registers

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MOTO ROLA T imer Modul es (TIM1 and TIM2) 325

16.7.2 Timer Compare Force Register

Read: Anytime

Write: Anytime

FOC[3:0] — Force Output Compare Bits

Setting an FOC bit causes an immediate output compare on the

corresponding channel. Forcing an output compare does not set the

output compare flag.

1 = Force output compare

0 = No effect

NOTE: A successful channel 3 output compare overrides any channel 2:0

compares. For each OC3M bit that is set, the output compare action

reflects the corresponding OC3D bit.

Address: TIM1 — 0x00ce_0001

TIM2 — 0x00cf_0001

Bit 7654321Bit 0

Write: FOC3 FOC2 FOC1 FOC0

Reset:00000000

= Writes have no effect and the access terminates without a transf er error exception.

Figure 16-3. Timer Compare Force Register (TIMCFORC)

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16.7.3 Timer Output Compare 3 Mask Register

Read: Anytime

Write: Anytime

OC3M[3:0] — Output Compare 3 Mask B its

Setting an OC3M bit configures the corresponding TIMPORT pin to

be an output. OC3Mx makes the timer port pin an output regardless

of the da ta directio n bit when th e pin i s configu red for output compare

(IOSx = 1). The OC3Mx bits do not change the state of the TIMDDR

bits.

1 = Corresponding TIMPORT pin configured as output

0 = No effect

Address: TIM1 — 0x00ce_0002

TIM2 — 0x00cf_0002

Bit 7654321Bit 0

OC3M3 OC3M2 OC3M1 OC3M0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transf er error exception.

Figure 16-4. Timer Output Compare 3 Mask Register (TIMOC3M)

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Timer Modules (TIM1 and TIM2)

Mem ory Map and Registers

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MOTO ROLA T imer Modul es (TIM1 and TIM2) 327

16.7.4 Timer Output Compar e 3 Data Register

Read: Anytime

Write: Anytime

OC3D[3:0] — Output Compare 3 Data Bits

When a successful channel 3 output compare occurs, these bits

transfer to the Ti me r Port D at a Register i f the cor resp onding OC3Mx

bits are set.

NOTE: A successful channel 3 output compare overrides any channel 2:0

compares. For each OC3M bit that is set, the output compare action

reflects the corresponding OC3D bit.

Address: TIM1 — 0x00ce_0003

TIM2 — 0x00cf_0003

Bit 7654321Bit 0

OC3D3 OC3D2 OC3D1 OC3D0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transf er error exception.

Figure 16-5. Timer Output Compare 3 Data Register (TIMOC3D)

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Timer Modules (TIM1 a nd TIM2)

16.7.5 Timer Coun ter Registe rs

Read: Anytime

Write: Only in test (special) mode; has no effect in normal modes

To ensure coherent reading of the timer counter, such that a timer

rollover does not occur between two back-to-back 8-bit reads, it is

recommended that only half-word (16-bit) accesses be used.

A write to TIMCNT may have an extra cycle on the first count because

the write is not synchronized with the prescaler clock. The write occurs

at least one cycle before the synchronization of the prescaler clock.

Address: TIM1 — 0x00ce_0004

TIM2 — 0x00cf_0004

Bit 7654321Bit 0

Read: Bit 15 14 13 12 11 10 9 Bi t 8

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transf er error exception.

Figure 16-6. Timer Counter Register High (TIMCNTH)

Address: TIM1 — 0x00ce_0005

TIM2 — 0x00cf_0005

Bit 7654321Bit 0

Read: Bit 7 654321Bit 0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transf er error exception.

Figure 16-7. Timer Counter Register Low (TIMCNTL)

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Timer Modules (TIM1 and TIM2)

Mem ory Map and Registers

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MOTO ROLA T imer Modul es (TIM1 and TIM2) 329

16.7.6 Timer System Control Register 1

Read: Anytime

Write: Anytime

TIMEN — T i mer Enable Bit

TIMEN enables the timer. When the timer is disabled, only the

registers are accessible. Clearing TIMEN reduces power

consumption.

1 = Timer enabled

0 = Timer and timer counter disabled

TFFCA — Timer Fast Flag Clear All Bit

TFF CA enables fas t clear ing of t he m ai n timer inte rru pt fl a g regi ster s

(TIMFLG1 and TIMFLG2) and the PA Flag Register (TIMPAFLG).

TFFCA eliminates the software overhead of a separate clear

sequence.

When TFFCA is set:

•An input capt ure read or a write to an outpu t compar e channe l

clears the corresponding channel flag, CxF.

•Any access of the timer count registers (TIMCNTH/L) clears the

TOF flag.

•Any access of the PA counter registers (TIMPACNT) clears

both the PAOVF and PAIF flags in TIMPAFLG.

Writing logic 1s to the flags clears them only when TFFCA is clear.

1 = Fast flag clearing

0 = Normal flag clearing

Address: TIM1 — 0x00ce_0006

TIM2 — 0x00cf_0006

Bit 7654321Bit 0

Read: TIMEN 00

TFFCA 0000

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transf er error exception.

Figure 16-8. Timer System Control Register (TIMSCR1)

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330 Timer Modules (TIM1 and TIM2) MOTOROLA

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Figure 16-9. Fast C lear Flag Logic

16.7.7 Timer Toggle-On -Ove rf low Regist er

Read: Anytime

Write: Anytime

TOV[3:0]— Toggle- On-Overflow Bits

TOV[3:0] toggles the output compare pin on overflow. This feature

only takes effect when in output compare mode. When set, it takes

precedence over forced output compare but not channel 3 override

events.

1 = Toggle output compare pin on overflow feature enabled

0 = Toggle output compare pin on overflow feature disabled

CLEAR

WRIT E TIM Cx RE GI STE RS

READ TI M Cx RE GI STE RS

TFFCA

DATA BIT x

WRITE TIMFLG1 R EGI ST ER

CxF

CxF FLAG

Address: TIM1 — 0x00ce_0008

TIM2 — 0x00cf_0008

Bit 7654321Bit 0

TOV3 TOV2 TOV1 TOV0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transf er error exception.

Figure 16-10. Timer Toggl e-O n-Overflow Regist er (TIMTO V)

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Mem ory Map and Registers

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MOTO ROLA T imer Modul es (TIM1 and TIM2) 331

16.7.8 Timer Control Register 1

Read: Anytime

Write: Anytime

OMx/OLx — Output Mode/Output Level Bits

These bit pairs sele ct the output action to be taken as a result of a

successful output compare. When either OMx or OLx is set and the

IOSx bit is set, the pin is an output regardless of the state of the

corresponding DDR bit.

Channel 3 shares a pin with the pulse accumulator input pin. To use

the PAI i nput, clear both the OM3 and OL3 bits an d clear the OC3M3

bit in the Output Compare 3 Mask Register.

Address: TIM1 — 0x00ce_0009

TIM2 — 0x00cf_0009

Bit 7654321Bit 0

Read: OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0

Write:

Reset:00000000

Figure 16-11. Timer Control Register 1 (TIMCTL1)

Table 16-3. Output Compare Action Selection

OMx:OLx Action on Output Compare

00 Timer disconnected from outp ut pin logic

01 Toggle OCx output line

10 Clear OCx output line

11 Set OCx line

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332 Timer Modules (TIM1 and TIM2) MOTOROLA

Timer Modules (TIM1 a nd TIM2)

16.7.9 Timer Control Register 2

Read: Anytime

Write: Anytime

EDGx[B:A] — Input Capture Edge C ontrol Bits

These eight bit pairs configure the input capture edge detector

circuits.

Address: TIM1 — 0x00ce_000b

TIM2 — 0x00cf_000b

Bit 7654321Bit 0

Read: EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG10

Write:

Reset:00000000

Figure 16-12. Timer Control Register 2 (TIMCTL2)

Table 16-4. Input Capture Edge Selection

EDGx[B:A] Edge Selection

00 Input capture disabled

01 Input capture on rising edges only

10 Input capture on falling edges only

11 Input capture on any edge (rising or falling)

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16.7.10 Timer Interrupt Enable Register

Read: Anytime

Write: Anytime

C[3:0]I — Channel Interrupt Enabl e Bits

C[3:0]I enable the C[3:0]F flags in Timer Flag Register 1 to generate

interrupt requests.

1 = Corresponding channel interrupt requests enabled

0 = Corresponding channel interrupt requests disabled

Address: TIM1 — 0x00ce_000c

TIM2 — 0x00cf_000c

Bit 7654321Bit 0

C3I C2I C1I C0I

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transf er error exception.

Figure 16-13. Timer Interrupt Enable Register (TIMIE)

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16.7.11 Timer System Control Register 2

Read: Anytime

Write: Anytime

TOI — Timer Overflo w Interrupt Enable Bit

TOI enables timer overflow interrupt requests.

1 = Overflow interrupt requests enabled

0 = Overflow interrupt requests disabled

PUPT — Timer Pullup Enable Bit

PUPT enables pullup resistors on the timer ports when the ports are

configured a s inputs.

1 = Pullup resistors enabled

0 = Pullup resistors disabled

RDPT — Time r Drive Reduction Bit

RDPT reduces the output driver size.

1 = Output drive reduction enabled

0 = Output drive reduction disabled

TCRE — Timer Counter Reset Enable Bit

TCRE enables a counter reset after a channel 3 compare.

1 = Counter reset enabled

0 = Counter reset disabled

NOTE: W hen the time r ch annel 3 r egister s cont ain $ 0000 and TC RE i s se t, th e

timer counter registers remain at $0000 all the time.

Address: TIM1 — 0x00ce_000d

TIM2 — 0x00cf_000d

Bit 7654321Bit 0

Read: TOI 0PUPT RDPT TCRE PR2 PR1 PR0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transf er error exception.

Figure 16-14. Timer System Control Register 2 (TIMSCR2)

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When the timer channel 3 registers contain $FFFF and TCRE is set,

TOF never gets set even though the timer counter registers go from

$FFFF to $0000.

PR[2:0] — Prescaler Bits

These bits select the prescaler divisor for the timer counter.

NOTE: The newly selected prescaled clock does not take effect until the next

synchronized edge of the prescaled clock when the clock count

transit ions to $0000.)

Table 16-5. Prescaler Selection

PR[2:0] Prescaler Divisor

000 1

001 2

010 4

011 8

100 16

101 32

110 64

111 128

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336 Timer Modules (TIM1 and TIM2) MOTOROLA

Timer Modules (TIM1 a nd TIM2)

16.7.12 Timer Flag Register 1

Read: Anytime

Write: Anytime; writing 1 clears flag; writing 0 has no effect

C[3:0]F — Channe l Flags

A channe l flag is set when an input captur e or outpu t compar e event

occurs. Clear a channel flag by writing a 1 to the flag.

NOTE: When the fast flag clear all bit, TFFCA, is set, an input capture read or

an outpu t compare write cle ars the corr espond ing chan nel fl ag. TFF CA

is in timer System Control Register 1 (TIMSCR1).

When a channel flag is set, it does not inhibit subsequent output

compares or input captures.

Address: TIM1 — 0x00ce_000e

TIM2 — 0x00cf_000e

Bit 7654321Bit 0

C3F C2F C1F C0F

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transf er error exception.

Figure 16-15. Timer Flag Register 1 (TIMFLG1)

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16.7.13 Timer Flag Register 2

Read: Anytime

Write: Anytime; writing 1 clears flag; writing 0 has no effect

TOF — Timer Overflow Flag

TOF i s set when th e ti mer counter rol ls over from $F FF F to $0 000. If

the TOI bit in TIMSCR2 is also set, TOF generates an interrupt

request. Clear TOF by writing a 1 to it.

1 = Timer overflow

0 = No timer overflow

NOTE: When the timer channel 3 registers contain $FFFF and TCRE is set,

TOF never gets set even though the timer counter registers go from

$FFFF to $0000.

When the fast flag clear all bit, TFFCA, is set, any access to the timer

counter register s clears Timer Flag Register 2. The TFFCA bit is in timer

System Control Register 1 (TIMSCR1).

When TOF is set, it does not inhibit subsequent overflow events.

Address: TIM1 — 0x00ce_000f

TIM2 — 0x00cf_000f

Bit 7654321Bit 0

Read: TOF 0000000

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transf er error exception.

Figure 16-16. Timer Flag Register 2 (TIMFLG2)

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16.7.14 Timer Channel Registers

Read: Anytime

Write: Output compare channel, anytime; input capture channel, no

effect

When a channel is configured for input capture (IOSx = 0) , the timer

channel registers latch the value of the free-running counter when a

defined transition occurs on the corresponding input capture pin.

When a channel is configured for output compare (IOSx = 1), the timer

channel registers contai n the output compare value.

To ensure coherent reading of the timer counter, such that a timer

rollover does not occur between back-to-back 8-bit reads, it is

recommended that only half-word (16-bit) accesses be used.

Address: TIMC0H — 0x00ce_0010/0x00cf_0010

TIMC1H — 0x00ce_0012/0x00cf_0012

TIMC2H — 0x00ce_0014/0x00cf_0014

TIMC3H — 0x00ce_0016/0x00cf_0016

Bit 7654321Bit 0

Read: Bit 15 14 13 12 11 10 9 Bi t 8

Write:

Reset:00000000

Figure 16-17. Timer Channel [0:3] Register High (TIMCxH)

Address: TIMC0L — 0x00ce_0011/0x00cf_0011

TIMC1L — 0x00ce_0013/0x00cf_0013

TIMC2L — 0x00ce_0015/0x00cf_0015

TIMC3L — 0x00ce_0017/0x00cf_0017

Bit 7654321Bit 0

Read: Bit 7654321Bit 0

Write:

Reset:00000000

Figure 16-18. Timer Channel [0:3] Register Low (TIMCxL)

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16.7.15 Pulse Accumu lator Control Register

Read: Anytime

Write: Anytime

PAE — Pulse Accumulator Enable Bit

PAE enables the pulse accumulator.

1 = Pulse accumu l ator enable d

0 = Pulse accumu l ator disabled

NOTE: T he p ul se accu mulato r ca n ope rate i n eve nt m ode e ven whe n the ti me r

enable bit, TIMEN, is clear.

PAMOD — Pu lse Accumulator Mode Bit

PAMOD selects event counter mode or gated time accumulation

mode.

1 = Gated time accumulation mode

0 = Event counter mode

PEDGE — Pulse Accumulator Edge Bit

PEDG E sel ects falling or rising ed ges on th e PAI pin to increme nt the

counter.

In event counter mode (PAMOD = 0):

1 = Rising PAI edge increments counter

0 = Falling PAI edge increments counter

Address: TIM1 — 0x00ce_0018

TIM2 — 0x00cf_0018

Bit 7654321Bit 0

Read: 0 PAE PAMOD PEDGE CLK1 CLK0 PAOVI PAI

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transf er error exception.

Figure 16-19. Pulse Accumulator Control Register (TIMPACTL)

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In gated time accumulation mode (PAMOD = 1):

1 = Low PAI input enables divide-by-64 clock to pulse accumulator

and trailing rising edge on PAI sets PAIF flag.

0 = High PAI input enables divide-by-64 clock to pulse accumulator

and trailing falling edge on PAI sets PAIF flag.

NOTE: The timer prescaler generates the divide-by-64 clock. If the timer is not

active, there is no divide-by-64 clock.

To operate in gated time accumulation mode:

1. Apply logic 0 to RESET pin.

2. Initialize registers for pulse accumulator mode test.

3. Apply appropriate level to PAI pin.

4. Enable timer.

CLK[1:0] — Clock Se lect Bits

CLK[1:0 ] select the timer counter i np ut clock as sho wn in T able 16-6.

PAOVI — Pulse Accumulator Overflow Interrupt Enable Bit

PAOVI enables the PAOVF flag to generate interrupt requests.

1 = PAOVF interrupt requests enabled

0 = PAOVF interrupt requests disabled

PAI — Pulse Accumulator Input Interrupt Enable Bi t

PAI enables the PAIF flag to generate interrupt requests.

1 = PAIF interrupt requests enabled

0 = PAIF interrupt requests disabled

Table 1 6-6. Clock Sel ectio n

CLK[1:0] Timer Counter Clock(1)

1. Changi ng the CLKx bi ts caus es an immediat e ch ange in t he ti mer co unter c lock i nput.

00 Timer presca l er c lock(2)

2. When PAE = 0, the ti me r prescaler cloc k is al ways the ti mer counter clock.

01 PACLK

10 PACLK/256

11 PACLK/65536

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16.7.16 Pulse Accumulator Flag Register

Read: Anytime

Write: Anytime; writing 1 clears the flag; writing 0 has no effect

PAOVF — Pulse Accumulator Overflow Flag

PAOVF is set when the 16-bit pulse accumulator rolls over from

$FFFF to $0000. If the PAOVI bit in TIMPACTL is also set, PAOVF

generates an interrupt request. Clear PAOVF by writing a 1 to it.

1 = Pulse accumu l ator overflo w

0 = No pulse accumulator overflow

PAIF — Pulse Accumulator Input Flag

PAIF is set when the selected edge is detected at the PAI pin. In event

counter mode, th e event edge sets PAIF . In gated time accum ulation

mode, the trailing edge of the gate signal at the PAI pin sets PAIF. If

the PAI bit in TIMPACTL is also set, PAIF generates an interrupt

request. Clear PAIF by writing a 1 to it.

1 = Active PAI input

0 = No active PAI input

NOTE: W hen the fast flag clear all enab le bit, TFFCA, is set, any access to the

pulse accumulator counter registers clears all the flags in TIMPAFLG.

Address: TIM1 — 0x00ce_0019

TIM2 — 0x00cf_0019

Bit 7654321Bit 0

PAOVF PAIF

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transf er error exception.

Figure 16-20. Pulse Accumulator Flag Register (TIMPAF LG)

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Timer Modules (TIM1 a nd TIM2)

16.7.17 Pulse Accumulator Counter Registers

Read: Anytime

Write: Anytime

These r egisters conta in the number of active input edges o n the PAI pin

since the last reset.

NOTE: Re ading the pulse accumulator counter registers immediately after an

active edge on the PAI pin may miss the last count since the input first

has to be synchronized with the bus clock.

To ensure coherent reading of the PA counter, such that the counter

does not increment between back-to-back 8-bit reads, it is

recommended that only half-word (16-bit) accesses be used.

Address: TIM1 — 0x00ce_001a

TIM2 — 0x00cf_001a

Bit 7654321Bit 0

Read: Bit 15 14 13 12 11 10 9 Bi t 8

Write:

Reset:00000000

Figure 16-21. Pulse Accumulator Co unter Register High

(TIMPACNTH)

Address: TIM1 — 0x00ce_001b

TIM2 — 0x00cf_001b

Bit 7654321Bit 0

Read: Bit 7654321Bit 0

Write:

Reset:00000000

Figure 16-22. Pulse Accumulator Counter Register Low

(TIMPACNTL)

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16.7.18 Timer Port Data Register

Read: An ytime; read pin state when corresponding TIMDDR bit is 0;

read pin driver state when corresponding TIMDDR bit is 1

Write: Anytime

PORTT[3:0] — Timer Port Input Capture/Output Compare Data Bits

Data written to TIMPORT is buffered and drives the pins only when

they are configured as general-purpose outputs.

Reading an inp ut (DDR bit = 0) reads the pin state ; reading an ou tput

(DDR bit = 1) reads the latch.

Writin g to a p in configu red a s a timer outp ut doe s not cha nge th e pi n

state.

Address: TIM1 — 0x00ce_001d

TIM2 — 0x00cf_001d

Bit 7654321Bit 0

PORTT3 PORTT2 PORTT1 PORTT0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transf er error exception.

Figure 16-23. Timer Port Data Register (TIMPORT)

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16.7.19 Timer Port Data Direction Register

Read: Anytime

Write: Anytime

DDRT[3:0] — TIMPORT Data Direction Bits

These bits contr ol the port logic of TIM PORT. Reset clears the Ti mer

Port Data Direction Register, configuring all timer port pins as inputs.

1 = Corresponding pin configured as output

0 = Corresponding pin configured as input

Address: TIM1 — 0x00ce_001e

TIM2 — 0x00cf_001e

Bit 7654321Bit 0

DDRT3 DDRT2 DDRT1 DDRT0

Write:

Reset:00000000

Timer function: IC/OC3 IC/OC2 IC/OC1 IC/OC0

Pulse accumulator function: P AI

= Writes have no effect and the access terminates without a transf er error exception.

Figure 16-24. Timer Port Data Direction Register (TIMDDR)

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MOTO ROLA T imer Modul es (TIM1 and TIM2) 345

16.7.20 Timer Test Register

The Timer Test Register (TIMTST) is only for factory testing. When not

in test mode, TIMTST is read-only.

16 .8 Fun cti on al Descr iptio n

The timer module i s a 16-bit, 4-channel timer with input capture and

output compare functions and a pulse accumulator.

16.8.1 Prescaler

The pre scaler di vide s the mod ule cl ock by 1, 2, 4, 8, 16 , 32, 64, or 128.

The PR[2:0] bits in TIMSCR2 select the prescaler divisor.

16.8.2 Input Capture

Clearing an I/O select bit, IOSx, configures channel x as an input capture

channel. The input capture function captures the time at which an

external event occurs. When an active edge occurs on the pin of an input

capture channel, the timer transfers the value in the timer counter into

the timer channel registers, TIMCxH and TIMCxL.

The minimum pul se wi dth for the i np ut captu re inp ut i s grea ter th an two

module clocks.

Address: TIM1 — 0x00ce_001f

TIM2 — 0x00cf_001f

Bit 7654321Bit 0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transf er error exception.

Figure 16-25. Timer Test Register (TIMTST)

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The inpu t capture func tion doe s not force data direction . The Time r Port

Data Direction Register controls the data direction of an input capture

pin. Pin conditions such as rising or falling edges can trigger an input

capture only on a pin configured as an input.

An inp ut capture on channel x sets the CxF flag . The C xI bit enables t he

CxF flag to generate interrupt requests.

16.8.3 Output Compar e

Setting an I/O select bit, IOSx, configures channel x as an output

compar e channel. The output compar e functi on can ge nerate a periodic

pul se wi th a pro gram mab le polar i ty, dura tion, an d freq uency. W he n the

timer counter reaches the value in the channel registers of an output

compar e channel , the timer can set, clear , or toggle the chan nel pin. An

output co mpar e on channel x sets th e CxF fla g. Th e C xI bit e nabl es the

CxF flag to generate interrupt requests.

The output mode and level bits, OMx and OLx, select, set, clear, or

toggl e o n ou tput compa re. Cleari ng bot h OM x and OLx disconn ects th e

pin from the output logic.

Setting a force output compare bit, FOCx, causes an output compare on

channel x. A forced output compare does not set the channel flag.

A successful output compare on channel 3 overrides output compares

on al l other ou tput com pare channe ls. A channel 3 outpu t compa re can

cause bits in the Output Compare 3 Data Register to transfer to the

Timer Port Data Register, depending on the Output Compare 3 Mask

Output Compare 3 Data Register. The timer counter reset enable bit,

TCR E, enabl es chann el 3 output co mpares to reset the timer counte r. A

channel 3 output compare can reset the timer counter even if the

OC3/PAI pin is being used as the pulse accumulator input.

An output compare overrides the data direction bit of the output compare

pin but does not change the state of the data direction bit.

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Writin g to the ti m er p ort bit of an ou tput co mpar e pi n does not a ffect t he

pin state. The value written is stored in an internal latch. When the pin

becomes available for general-purpose output, the last value written to

the bit appears at the pin.

16.8.4 Pulse Accumulator

The pulse accumulator (PA) is a 16-bit counter that can operate in two

modes:

1. Ev ent counte r mode — Counts edges of selected polarity on the

pulse accumulator input pin, PAI

2. Gated time accumulation mode — Counts pulses from a

divide-by-64 clock

The PA mode bit, PAMOD, selects the mode of operation.

The minimum pulse width for the PAI input is greater than two module

clocks.

16.8.4.1 Event Counter Mode

Clearing the PAMOD bit configures the PA for event counter operation.

An active edge on the PAI pin increments the PA. The PA edge bit,

PEDGE, selects falling edges or rising edges to increment the PA.

An active edge on the PAI pin sets the PA input flag, PAIF. The PA input

interrupt enable bit, PAI, enables the PAIF flag to generate interrupt

requests.

NOTE: The PAI input and timer channel 3 use the same pin. To use the PAI

input, disconnect it from the output logic by clearing the channel 3 output

mode and output level bits, OM3 and OL3. Also clear the channel 3

output compare 3 mask bit, OC3M3.

The PA counter registers, TIMP ACNTH/L, reflect the number of active

inpu t edges on the PA I pin since the last reset.

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The PA overfl ow flag, PAOVF, is se t when the PA ro lls over fr om $FFFF

to $0000. The PA overflow interrupt enable bit, PAOVI, enables the

PAOVF flag to generate interrupt requests.

NOTE: T he PA can operate in event coun ter mode ev en when the timer enabl e

bit, TIMEN, is clear.

16.8.4.2 Gated Time Accumulation Mode

Setting the PAMOD bit configures the PA for gated time accumulation

operat ion. An active l evel on the PAI pin enabl es a divide- by-64 cl ock to

dri ve the PA. Th e PA edge bit, PEDGE, sel ects low levels or high leve ls

to enabl e the divide-by-64 clock.

The trailing edge of the active level at the PAI pin sets the PA input flag,

PAIF. The PA input interrupt enable bit, PAI, enables the PAIF flag to

generate interrupt requests.

NOTE: The PAI input and timer channel 3 use the same pin. To use the PAI

input, disconnect it from the output logic by clearing the channel 3 output

mode and output level bits, OM3 and OL3. Also clear the channel 3

output compare mask bit, OC3M3.

The PA counter registers, TIMP ACNTH/L reflect the number of pulses

from the divide-by-64 clock since the last reset.

NOTE: The timer prescaler generates the divide-by-64 clock. If the timer is not

active, there is no divide-by-64 clock.

Figu re 16- 26. Ch ann el 3 Out pu t Co mp are/ Pulse Accum u lato r Log ic

PAD

OM3

OL3

CHANNEL 3 OUTPUT COMPARE

PULSE

ACCUMULATOR

OC3M3

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16.8.5 General-Purpose I/O Ports

An I/O pin used by the timer defaults to general-purpose I/O unless an

internal function which uses that pin is enabled.

The timer pins can be configured for either an input capture function or

an output compare function. The IOSx bits in the Timer IC/OC Select

compare pins.

The T imer P ort Data Di re ction R eg ister co ntro ls the data direction of an

inp ut cap ture pin. Ext erna l pin c onditi on s trigg er i nput captur es o n inpu t

capture pins configured as inputs.

To confi gure a pin for input capture:

1. Clear the pin’s IOS bit in TIMIOS.

2. Clear the pin’s DDR bit in TIMDDR.

3. Write to TIMCTL2 to select the input edge to detect.

TIMDDR does not affect the data direction of an output compare pin. The

output compare function ov errid es th e Data Dire ction R egister but doe s

not affect the state of the Data Direction Register.

To confi gure a pin for output compare:

1. Set the pin’s IOS bit in TIMIOS.

2. Write the output compare value to TIMCxH/L.

3. Clear the pin’s DDR bit in TIMDDR.

4. Write to the OMx/OLx bits in TIMCTL1 to select the output action.

Table 16-7 shows how various timer settings affect pin functionality.

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Timer Modules (TI M1 and TIM2)

Ta ble 16-7. Timer Se ttings and Pin Function s

TIMEN DDR(1) TIMIOS EDGx

[B:A] OMx/

OLx(2) OC3Mx(3) Pin

Data

Direction

Driven

by Pin

Function Comments

X(4) X X X In Ext. Digital input Timer disabled by TIMEN = 0

0 1 X X X X Out Data reg. Digital output Timer disabled by TIMEN = 0

100 (IC)

0 (IC

disabled) X 0 In Ext. Digital input Input cap tur e disabled by EDGx setti ng

1 1 0 0 X 0 Out Data reg. Digit al out put Input capture disabled by EDGx setti ng

1 0 0 <> 0 X 0 In Ext. IC and

digi tal in put Normal settings for input capture

1 1 0 <> 0 X 0 Out Data reg. Digital output Input capture of data driven to output pin by CPU

1 0 0 <> 0 X 1 In Ext. IC and

digi tal in put OC 3M setting has no effect because IOS = 0

1 1 0 <> 0 X 1 Out Data reg. Digital output OC3M setting has no effect because IOS = 0;

input capture of data dr iven to output pin by CPU

101 (OC)

X(3) 0(5) 0 In Ext. Digital input Output compare ta kes place but does not affect

the pin because of the OMx/OLx setting

1 1 1 X 0 0 Out Data reg. Digital output Output compare takes place but does not af fect

the pin because of the OMx/OLx setting

1 0 1 X <> 0 0 Out OC action O utput compare Pin readable only if DDR = 0 (5)

1 1 1 X <> 0 0 Out OC action O utput compare Pin driven by OC action(5)

101 X X 1 Out OC

action/

OC3Dx

Output compare

(ch 3) Pin readable only if DDR = 0(6)

111 X X 1 Out OC

action/

OC3Dx

Output

compare/

OC3Dx

(ch 3)

Pin driven by channel OC action and OC3Dx via

channel 3 OC(6)

1. When DDR set the pin as input (0), reading the data register will retur n the st ate of the pin. Whe n DDR set the pin as output (1), reading the data

register will ret urn the content of the data lat ch. Pin cond itions such as ri sing or falling edges can trigger an input capture on a pin configured as an

input.

2. OM x/OL x bit pairs select the output acti on to be taken as a result of a successful output compare. When either OMx or OLx is set and the IOSx bit is

set, the pin is an output rega rdl ess of the stat e of the correspondi ng DDR bit .

3. Sett ing an OC3M bit configures th e corresponding TIMPO R T pin to be output. OC3Mx mak es the ti me r port pin an output reg ardless of the data

direction bit when the pi n is configured for output compare (IOSx = 1). The OC3Mx bits do not change the sta te of the TIMDDR bi ts.

4. X = Don’t car e

5. An output compare overri des the data direction bit of the output compare pin but does not change th e state of the data dir ection bit. Enabling output

compar e disables data register drive of the pin.

6. A successf ul output compare on channel 3 causes an output value determined by OC3Dx value to temporarily override the output compare pin state

of any ot her outp ut compa re channel .The next OC acti on for the speci fic channel wi ll stil l be outpu t to the pi n. A channel 3 o utput compa re can cause

bits in the output compare 3 data regi ster to transfe r to t he ti m er port data regis ter , depending on the output compare 3 mask register.

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Timer Modules (TIM1 and TIM2)

Reset

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MOTO ROLA T imer Modul es (TIM1 and TIM2) 351

16.9 Reset

Reset initializes the timer registers to a known startup state a s described

in 16.7 Memory Map and Registers.

16.10 Interrupts

Table 16-8 lists the interrupt requests generated by the timer.

16.10.1 Timer Channel Interrupts (CxF)

A channel flag is set when an input capture or output compare event

occurs. Clear a channel flag by writing a 1 to the flag.

NOTE: When the fast flag clear all bit, TFFCA, is set, an input capture read or

an outpu t compare write cle ars the corr espond ing chan nel fl ag. TFF CA

is in Timer System Control Register 1 (TIMSCR1).

When a channel flag is set, it does not inhibit subsequent output

compares or input captures

Table 16-8. Timer Interrupt Requests

Interrupt Requ est Flag En able Bit

Channel 3 IC/OC C3F C3I

Channel 2 IC/OC C2F C2I

Channel 1 IC/OC C1F C1I

Channel 0 IC/OC C0F C0I

PA overflow PA OVF PA OV I

PA input PAIF PAI

T i mer overflow TOF TOI

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Timer Modules (TIM1 a nd TIM2)

16.10.2 Pulse Accumulator Overflow (PAOVF)

PA OVF is set when the 16- bit pul se accu mulato r rol ls over from $FFF F

to $0000. If the PAOVI bit in TIMPACTL is also set, P AOVF generates

an interrupt request. Clear PAOVF by writing a 1 to this flag.

NOTE: W hen the fast flag clear all enab le bit, TFFCA, is set, any access to the

pulse accumulator counter registers clears all the flags in TIMPAFLG.

16.10.3 Pulse Accumu lator Input (PAIF)

PAIF is set when the selected edge is detected at the PAI pin. In event

counter mode, the event edge sets PAIF. In gated time accumulation

mode, the tr ailing edge of the gate signal at the P AI pin sets P AIF. If the

PAI bit in TIMPACTL is al so set, PAIF generates an interrupt request.

Clear PAIF by writing a 1 to this flag.

NOTE: W hen the fast flag clear all enab le bit, TFFCA, is set, any access to the

pulse accumulator counter registers clears all the flags in TIMPAFLG.

16.10.4 Timer Overflow (TOF)

TOF is set wh en the ti mer counter rol ls over from $F FFF to $0000. If the

TOI bit in TIMSCR2 is also set, TOF generates an interrupt request.

Clear TOF by writing a 1 to this flag.

NOTE: When the timer channel 3 registers contain $FFFF and TCRE is set,

TOF never gets set even though the timer counter registers go from

$FFFF to $0000.

When the fast flag clear all bit, TFFCA, is set, any access to the timer

counter registers clears Timer Flag Register 2. The TFFCA bit is in Timer

System Control Register 1 (TIMSCR1).

When TOF is set, it does not inhibit future overflow events.

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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0  Advance Information
MOTOROLA Serial Communications Interface Modules (SCI1 and SCI2)  353
Advance Info rmation — MMC2114, MMC2113, and MMC2112
Section 17. Serial Comm unications Interface Modules
(SCI1 and SCI2)
1  Contents
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
4 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356
5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
5.1 Doze Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
6 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
6.1 RXD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
6.2 TXD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
7 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .358
7.1 SCI Baud Rate Register s . . . . . . . . . . . . . . . . . . . . . . . . . .360
7.2 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .361
7.3 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
7.4 SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .366
7.5 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .369
7.6 SCI Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .370
7.7 SCI Pullup and Reduced Drive Register . . . . . . . . . . . . . .371
7.8 SCI Port Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .372
7.9 SCI Data Direction Register. . . . . . . . . . . . . . . . . . . . . . . .373
8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
9 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
10 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
11 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376
11.1 Frame Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377
11.2 Transmitting a Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . .378
    
  
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354 Serial Communications Interface Modules (SCI1 and SCI2) MOTOROLA
Serial Communications Interface Modules (SCI1 and SCI2)
17.11.3 Break Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380
17.11.4 Idle Frames  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380
17.12 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381
17.12.1 Frame Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381
17.12.2 Receiving a Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381
17.12.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382
17.12.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387
17.12.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387
17.12.5.1 Slow Data T o lerance . . . . . . . . . . . . . . . . . . . . . . . . . . .388
17.12.5.2  Fast Data T o lerance . . . . . . . . . . . . . . . . . . . . . . . . . . .389
17.12.6 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .390
17.12.6.1 Idle Input Line Wakeup (WAKE = 0) . . . . . . . . . . . . . . .390
17.12.6.2 Address Mark Wakeup (WAKE = 1). . . . . . . . . . . . . . . .391
17.13 Single-Wire Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392
17.14 Loop Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
17.15 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394
17.16 Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395
17.17 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395
17.17.1 Transmit Data Register E mpty. . . . . . . . . . . . . . . . . . . . . .395
17.17.2 Transmission Complete . . . . . . . . . . . . . . . . . . . . . . . . . . .395
17.17.3 Receive Data Register Full. . . . . . . . . . . . . . . . . . . . . . . . .396
17.17.4 Idle Receiver Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396
17.17.5 Overrun  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396
17.2  Introduction
The serial communicati ons interface (SCI) allows asynchronous serial 
commun ic ations wi th  periph eral d evi ces an d othe r micr ocont rol ler  units 
(MCU).
The MMC2114, MMC2113, and MM C2112 have two identical SCI 
modules, each with its own control registers and input/output (I/O) pins.
In the text that follows, SCI register names are denoted generically. 
Thus, SCIPORT refers interchangeably to SCI1PORT and SCI2PORT, 
the port data registers for SCI1 and SCI2, respectively.
    
  
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Serial Communications Interface Modules (SCI1 and SCI2)

Features

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MOTOROLA Serial Communications Interface Modules (SCI1 and SCI2) 355

17.3 Features

Features of each SCI module include:

•Full- duplex operation

•Standard mark/space non-return-to- zero (NRZ) format

•13-bit baud rate selection

•Programmable 8-bit or 9-bit data format

•Separately enabled transmitter and receiver

•Separate receiver and transmitter central processor unit (CPU)

interrupt requests

•Programmable transmitter output polarity

•Two receiver wakeup methods:

–Idle line wakeup

–Address mark wakeup

•Interrupt-driven operation with eight flags:

–Transmitter empty

–Transmission complete

–Receiver full

–Idle receiver input

–Receiver overrun

–Noise error

–Framing error

–Parity error

•Receiver framing error detection

•Hardwa re parity checking

•1/16 bit-time noise detection

•General-purpose, I/O capability

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Serial Communications Interface Modules (SCI1 and SCI2)

17.4 Blo ck Diag r am

Figure 17-1. SCI Block Diagram

SCI DAT A

RECEIVE

SHIFT REGIST ER

SCI DAT A

TRANSMIT

SHIFT REGIST ER

BAUD RATE

GENERATOR

SCBR[12:0]

RXD

TXD

RECEIVE

AND WAKEUP

DATA FORMA T

CONTROL

RDRF

IDLE

TIE

TCIE

RAF

CLOCK

IDLE

ILIE

RIE

RDRF/OR

TDRE

INTERRUPT

REQUEST

SBK

LOOPS

RSRC

TRANSMIT

CONTROL

LOOPS

RWU

RSRC

ILT

WAKE

÷16

TDRE

IPBUS

SYSTEM

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Serial Communications Interface Modules (SCI1 and SCI2)

Modes of Op eration

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MOTOROLA Serial Communications Interface Modules (SCI1 and SCI2) 357

17.5 Modes of Operation

SCI operation is identical in run, special, and emulation modes. The SCI

has two low-power modes, doze and stop.

NOTE: Run mode is the normal mode of operation and the WAIT instruction

does not affect SCI operation.

17.5.1 Doze Mode

When the S CIDOZ bit in the SCI Pullup and Redu ced Drive (SCIPURD)

SCI in a low-power state. The DOZE instruction does not affect S CI

mode entry and resumes when an internal or external interrupt request

brings the CPU out of doze mode. Exiting doze mode by reset aborts any

transmission or reception in progress and resets the SCI. See 17.7.7

SCI Pullup and Reduced Drive Register.

When the SCIDOZ bit is clear, execution of the DOZE instruction has no

effect on the SCI. Normal mod ule operation continues, allowing any SCI

interrupt to bring the CPU out of doze mode.

17.5.2 Stop Mode

The STOP instruction stops the SCI clock and puts the SCI in a

low-power state. The STOP instruction does not affect SCI register

states. Any transmission or reception in progress halts at stop mode

entry and resumes when an external interrupt request brings the CPU

out of stop mode. Exiting stop mod e by reset abor ts any transm ission o r

reception in progress and resets the SCI.

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17.6 Signal Description

Table 17-1 gives an overview of the signals which are described here.

17.6.1 RXD

RXD is the SCI receiver pin. RXD is available for general-purpose I/O

when it is not configured for receiver operation.

17.6.2 TXD

TXD is the SCI transmit ter pin. TXD is av ailable for ge neral-purpose I/O

when it is not configured for transmitter operation.

17.7 Memory Map and Register s

Table 17-1 shows the SCI memory map.

NOTE: Re ading unimplemented addresses (0x00cc_000b through

0x00cc_000f) return s 0s. Writing to unimplemented addresses has no

effect. Accessing u nimplemente d addre sses does not gene rate an error

response.

Table 17-1. Signal Properties

Name Function Port Reset

State Default

Pullup

State

RX D R eceive da ta pin SC IPORT0 0 Disa bled

TXD Transmit data pin SCIPORT1 0 Disabled

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Serial Communications Interface Modules (SCI1 and SCI2)

Mem ory Map and Registers

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MOTOROLA Serial Communications Interface Modules (SCI1 and SCI2) 359

Table 17-2. Serial Communications Interface Module Memory Map(1)

Address Bits 7–0 Access(2)

SCI1 SCI2

0x00cc_00 00 0x00cd_0000 SCI Ba ud Register High (SCIBDH) S/U

0x00cc_0001 0x0 0cd_0001 SCI Baud Register Low (SCIBDL) S/U

0x00cc_0002 0x00cd_0002 SCI Control Register 1 (SCICR1) S/U

0x00cc_0003 0x00cd_0003 SCI Control Register 2 (SCICR2) S/U

0x00cc_0004 0x0 0cd_0004 S CI Status Regist er 1 (SCISR1) S/U

0x00cc_0005 0x0 0cd_0005 S CI Status Regist er 2 (SCISR2) S/U

0x00cc_0006 0x00cd_0006 SCI Data Register High (SCIDRH) S/U

0x00cc_0007 0x00cd_0007 SCI Data Register Low (SCIDRL) S/U

0x00cc_0008 0x00cd_0008 SCI Pullu p and Reduced Drive Regist er (SCIPURD) S/U

0x00cc_0009 0x00cd_0009 SCI Port Data Register (SCIPORT) S/U

0x00cc_000a 0x00cd_000a SCI Data Direction Regist er (SCIDDR) S/U

0x00cc_000b

0x00cc_000f

0x00cd_000b

0x00cd_000f Reserved(3) S/U

1. Each modul e is assi gned 64 Kbytes of addres s space, al l of which may not be decode d. Acce sses ou tside of the spe cifi ed

modu le mem ory map generate a bus error exception.

2. S/U = CPU supervisor or user mode access. User mod e accesses to sup ervisor only addresses have no effect and result

in a cycl e termination transfe r err or.

3. Wit hin the spe cifi ed module m emory map, acces sing res erv ed address es does no t generat e a b us error e xcepti on. Reads

of reserved addresses return 0s and writes have no effect.

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17.7.1 SCI Baud Rate Registers

Read: Anytime

Write: Anytime

SBR[12:8], SBR[7:0] — SCI Baud Rate Bits

These read/write bits control the SCI baud rate:

where:

1 ≤ SBR[12:0] ≤ 8191

NOTE: The baud rate generator is disabled until the TE bit or the RE bit in

SCICR2 is set for the first time after reset. The baud rate generator is

disabled when SBR[12:0] = 0.

Writing to SCIBDH has no effect without also writing to SCIBDL. Writing

to SCIBDH puts the data in a temporary location until data is written to

SCIBDL.

Address: SCI1 — 0x00cc_0000

SCI2 — 0x00cd_0000

Bit 7654321Bit 0

Read: 0 0 0 SBR12 SBR11 SBR10 SBR9 SBR8

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transf er error exception.

Figure 17-2. SCI Baud Rate Register High (SCIBDH)

Address: SCI1 — 0x00cc_0001

SCI2 — 0x00cd_0001

Bit 7654321Bit 0

Read: SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0

Write:

Reset:00000100

Figure 17-3. SCI Baud Rate Register Low (SCIBDL)

SCI baud rate = fsys

16 x SBR[12:0]

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Serial Communications Interface Modules (SCI1 and SCI2)

Mem ory Map and Registers

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MOTOROLA Serial Communications Interface Modules (SCI1 and SCI2) 361

17.7.2 SCI Control Regist er 1

Read: Anytime

Write: Anytime

LOOPS — Loop Select Bit

This read/write control bit switches the SCI between normal mode

and loop mode. Reset clears LOOPS.

1 = Loop mode SCI operation

0 = Normal mode SCI operation

The S CI operate s normall y (LOOP S = 0 , RSRC = X) when th e output

of its transmitter is connected to the TXD pin, and the input of its

receiver is connected to the RXD pin.

In l oop mode (LOOP S =1, RSRC = 0) , the in put to the SC I receiver is

internally disconnected from the RXD pin logic and instead connected

to the outp ut of th e SCI transm itter. The be havior of TXD is gover ned

by the DDRSC1 bit in SCIDDR. If DDRSC1 = 1, the TXD pin is driven

with the output of the SCI transmitter. If DDRSC1 = 0, the TXD pin

idles high. See 17.14 Loop Operation for additional information.

For either loop mode or single-wire mode to function, both the SCI

receiver and transmitter must be enabled by setting the RE and TE

bits in SCIxCR2.

NOTE: The RXD pin becomes general-purpose I/O when LOOPS = 1,

regar dless of the state of the RSRC bit. DDRSC0 in S CIDDR is the da ta

direction bit for the RXD pin.

Table 17-3 shows how the LOOPS, RSRC, and DDRSC0 bits affect

SCI operation and the configuration of the RXD and TXD pins.

Address: SCI1 — 0x00cc_0002

SCI2 — 0x00cd_0002

Bit 76 54321Bit 0

Read: LOOPS WOMS RSRC M WAKE ILT PE PT

Write:

Reset:00000000

Figure 17-4. SCI Control Register 1 (SCICR1)

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WOMS — Wired-OR Mode Select Bit

This read/write bit configures the TXD and RXD pins for open-drain

operation. This allows all of the TXD pins to be tied together in a

multiple-transmitter system. WOMS also affects the TXD and RXD

pins when they are general-purpose outputs. External pullup resistors

are necessary on open-drain outputs. Reset clears WOMS.

1 = TXD and RXD pins open-drain when outputs

0 = TXD and RXD pins CMOS drive when outputs

RSRC — Receiver Source Bit

This read/write bit selects the internal feedback path to the receiver

input when LOOPS = 1. Reset clears RSRC.

1 = Receiver input tied to TXD pin when LOOPS = 1

0 = Receiver input tied to transmitter output when LOOPS = 1

M — Data Format Mode Bit

This read/write bit selects 11-bit or 10-bit frames. Reset clears M.

1 = Frames have 1 start bit, 9 data bits, and 1 stop bit.

0 = Frames have 1 start bit, 8 data bits, and 1 stop bit.

Ta ble 17-3 . SCI Normal, Lo op, and Single-W ire Mode Pin Configu ration s

LOOPS

RSRC

SCI

Mode Receiver

Input RXD

Function

DDRSC0

Transmitter

Output TXD

Function

0 X Norm al Tied to RX D input buffer Rec eive pin X Tied to TXD output driver Transm it pin

0 Loop Tied t o transm itter output General-

purpose

I/O

0 Tied to receiver input only None (idles high)

1Tied to receiver input

and TXD output driver T ransmit pin

1 Single-wire Tied to TXD 0 No connection Receive pin

1 Tied to TXD out put driver Trans m it pin

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WAKE — Wakeup Bit

This read/write bit selects the condition that wakes up the SCI

receiver when it has been placed in a standby state by setting the

RWU bit in SCICR2. When WAKE is set, a logic 1 (address mark) in

the most significant bit position of a received data character wakes the

receiv er . An id le condition on the R XD pin does so when WAKE = 0.

Reset clears WAKE.

1 = Address mark receiver wakeup

0 = Idle line receiver wakeup

ILT — Idle Line Type Bit

This read/write bit d etermines w hen the re ceiver starts coun ting logic

1s as i dle char acter bits. T he countin g beg i ns eith er a fter the start bi t

or after the stop bit. If the count begi ns after the start bit, then a st ring

of logic 1s preceding the stop bit may cause false recognition of an

idle ch aract er. B eginn ing the co unt afte r the stop bit avoid s false i dle

character recognition, but requires properly synchronized

transmissions. Reset clears ILT.

1 = Idle frame bit count begins after stop bit.

0 = Idle frame bit count begins after start bit.

PE — Parity Enable Bit

This read/write bit enables the parity function. When enabled, the

pari ty function inser ts a pa ri ty b it in the most si gnifican t b it positio n o f

an SCI data word. Reset clears PE.

1 = Parity function enabled

0 = Parity function disabled

PT — Parity Type Bit

This re ad/write bit sel ect s even parity o r od d par ity. W ith ev en parity,

an even number of 1s clears the parity bit and an odd number of 1s

sets the parity bit. With odd parity, an odd number of 1s clears the

parity bit and an even number of 1s sets the parity bit. Reset clears

PT.

1 = Odd parity when PE = 1

0 = Even parity when PE = 1

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17.7.3 SCI Control Register 2

Read: Anytime

Write: Anytime

TIE — Transmitter Interrupt Enable Bit

This read/write bit allows the TDRE flag to generate interr upt

requests. Reset clears TIE.

1 = TDRE interrupt requests enabled

0 = TDRE interrupt requests disabled

TCIE — Transmission Co mplete Interrupt Enable Bit

This read/write bit allows the TC flag to generate interrupt requests.

Reset clears TCIE.

1 = TC interr upt requests enabled

0 = TC interrupt requests disabled

RIE — Receiver Inte rrupt Enable Bit

This read/write bit allows the RDRF and OR flags to generate interrupt

requests. Reset clears RIE.

1 = RDRF and OR interrupt requests enabled

0 = RDRF and OR interrupt requests disabled

ILIE — Idle Line Interrupt Enable Bit

This read/write bit allows the IDLE flag to generate interrupt requests.

Reset clears ILIE.

1 = IDLE interrupt requests enabled

0 = IDLE interrupt requests disabled

Address: SCI1 — 0x00cc_0003

SCI2 — 0x00cd_0003

Bit 76 54321Bit 0

Read: TIE TCIE RIE ILIE TE RE RWU SBK

Write:

Reset:00000000

Figure 17-5. SCI Control Register 2 (SCICR2)

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TE — Transmitte r Enable Bit

This read/write bit enables the transmitter and configures the TXD pin

as the transmitter output. Toggling TE queues an idle frame. Reset

clears TE.

1 = Transmitter enabled

0 = Transmitter disabled

RE — Receiver Enable Bit

This read/write bit enables the receiver. Reset clears RE.

1 = Receiver enabled

0 = Receiver disabled

NOTE: When LOOPS = 0 and TE = RE = 1, the RXD pin is an input and the

TXD pin is an output regardless of the state of the DDRSC1 (TXD) and

DDRSC0 (RXD) bits.

RWU — Receiver Wakeup Bit

This read/write bit puts the receiver in a standby state that inhibits

receiver interrupt requests. The WAKE bit determines whether an idle

inpu t or an address mark wakes up the receiver and clears RWU.

Reset clears RWU.

1 = Receiver asleep when RE = 1

0 = Receiver awake when RE = 1

SBK — Send Break Bit

Setting this read/write bit causes the SCI to send break frames of 10

(M = 0) or 11 (M =1) l ogic 0 s. T o sen d on e br eak f ram e, set S BK an d

then clear it before the break frame is finished transmitting. As long as

SBK is set, the transmitter continues to send break frames.

1 = Transmitter sends break frames.

0 = Transmitter does not send break frames.

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17.7.4 SCI Status Register 1

Read: Anytime

Write: Has no meaning or effect

TDRE — Transmit Data Register Empty Flag

The TD RE fl ag is se t w he n th e tr ansmit shift re gi ster rece ives a w ord

from the SCI Data Register . It signals that the SCIDRH and SCIDRL

are empty and can receive new data to transmit. If the TIE bit in the

SCICR2 is also set, TDRE generates an interrupt request. Clear

TDRE by reading SCISR1 and then writing to SCIDRL. Reset sets

TDRE.

1 = Transmit data register empty

0 = Transmit data register not empty

TC — Transmit Complete Flag

The TC flag is set when TDRE = 1 and no data, preamble, or break

frame i s being transmitted. It signals that no transmission is in

progress. If the TCIE bit is set in SCICR2, TC generates an interrupt

request. When TC is set, the TXD pin is idle (logic 1). TC is cleared

automatically when a data, preamble, or break frame is queued. Clear

TC by reading SCISR1 with TC set and then writing to SCIDRL. TC

cannot be cl eared while a trans mission is in progress. Reset sets TC.

1 = No transmission in progress

0 = Transmission in progress

Address: SCI1 — 0x00cc_0004

SCI2 — 0x00cd_0004

Bit 7654321Bit 0

Read: TDRE TC RDRF IDLE OR NF FE PF

Write:

Reset:11000000

= Writes have no effect and the access terminates without a transf er error exception.

Figure 17-6. SCI Status Register 1 (SCISR1)

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MOTOROLA Serial Communications Interface Modules (SCI1 and SCI2) 367

RDRF — Receive Data Register Full Flag

The RDRF flag is set when the data in the receive shift register is

transfer red to S CIDRH and SC IDRL. It signals tha t th e r eceived data

is available to the MCU. If the RIE bit is set in SCICR2, RDRF

generates an interrupt request. Clear RDRF by reading the SCISR1

and then reading SCIDRL. Reset clears RDRF.

1 = Received data available in SCIDRH and SCIDRL

0 = Received data not available in SCIDRH and SCIDRL

IDLE — Idle Line Flag

The IDLE flag is set when 10 (if M = 0) or 11 (if M = 1) consecutive

log ic 1s appear on the re ceiver i nput . If the ILIE bit in SCICR2 is set,

IDLE generates an interrupt request. Once IDLE is cleared, a valid

frame must again set the RDRF flag befor e an idle condition can set

the IDLE flag. Clear IDLE by reading SCISR1 and then reading

SCIDRL. Reset clears IDLE.

1 = Receiver idle

0 = Receiver active or idle since reset or idle since IDLE flag last

cleared

NOTE: When RWU of SCICR2 =1, an idle line condition does not set the IDLE

flag.

OR — Overrun Flag

The OR flag is set if data is not read from SCIDRL befo re the receive

shift register receives th e stop bit of the next fram e. This is a re ceiver

overrun condition. If the RIE bit in SCICR2 is set, OR generates an

interrupt request. The data in the shift register is lost, but the data

already in the SCIDRH and SCIDRL is not affected. Clear OR by

reading SCISR1 and then reading SCIDRL. Reset clears OR.

1 = Ov err un

0 = No overrun

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NF — Noise Flag

The NF flag is set when the SCI detects noise on the receiver input.

NF is set during the same cycle as the RDRF flag but does not get set

in the case of an overrun. Clear NF by reading SCISR1 and then

reading SCIDRL. Reset clears NF.

1 = Nois e

0 = No noise

FE — Framing Err or Fl ag

The F E flag is set whe n a logic 0 is accepte d as the stop bit. FE is set

during the same cycle as the RDRF flag but does not get set in the

case of an overrun. FE inhibits further data reception until it is cleared.

Clear FE by reading SCISR1 and then reading SCIDRL. Reset clears

FE.

1 = Fr aming error

0 = No framing error

PF — Parity Error Flag

The PF flag is set when PE = 1 and the parity of the received data

does not match its parity bit. Clear PF by reading SCISR1 and then

reading SCIDRL. Reset clears PF.

1 = Parity error

0 = No parity error

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MOTOROLA Serial Communications Interface Modules (SCI1 and SCI2) 369

17.7.5 SCI Status Register 2

Read: Anytime

Write: Has no meaning or effect

RAF — Receiver Active Flag

The RAF flag is set when the receiver detects a logic 0 during the RT1

time period of the start bit search. When the receiver detects an idle

character , it clears RAF. Reset clears RAF.

1 = Recepti on in progress

0 = No reception in progress

Address: SCI1 — 0x00cc_0005

SCI2 — 0x00cd_0005

Bit 7654321Bit 0

Read: 0000000RAF

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transf er error exception.

Figure 17-7. SCI Status Register 2 (SCISR2)

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17.7.6 SCI Data Registers

Read: Anytime

Write: Anytime; writing to R8 has no effect

R8 — Receive Bit 8

The R8 bit is the ninth received data bit when using the 9-bit data

format (M = 1). Reset clears R8.

T8 — Transmit Bit 8

The T8 bit is the ninth transmitted data bit when using the 9-bit data

format (M = 1). Reset clears T8.

R[7:0] — Receive Bits [7:0]

The R[7 :0] bits are receive bits [7 :0] when using the 9-bit o r 8-bit da ta

format. Reset clears R[7:0].

Address: SCI1 — 0x00cc_0006

SCI2 — 0x00cd_0006

Bit 7654321Bit 0

Read: R8 T8 000000

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transf er error exception.

Figure 17-8. SCI Data Register High (SCIDRH)

Address: SCI1 — 0x00cc_0007

SCI2 — 0x00cd_0007

Bit 7654321Bit 0

Read: R7 R6 R5 R4 R3 R2 R1 R0

Write: T7 T6 T5 T4 T3 T2 T1 T0

Reset:00000000

Figure 17-9. SCI Dat a Register Low (SCIDRL)

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MOTOROLA Serial Communications Interface Modules (SCI1 and SCI2) 371

T[7:0] — Transmit Bits [7:0]

The T[7:0] bits are transmit bits [7:0] when using the 9-bit or 8-bit data

format. Reset clears T[7:0].

NOTE: If the value of T8 is the same as in the previous transmission, T8 does

not have to be rewritten. The same value is transmitted until T8 is

rewritten.

When using the 8-bit data format, only SC IDRL needs to be accessed.

When using 8-bit write instructions to transmit 9-bit data, write first to

SCIDRH, then to SCIDRL.

17.7.7 SCI Pullup and Reduced Drive Register

Write: Anytime

SCISDOZ — SCI Stop in Doze Mode Bit

The SCISDOZ bit disables the SCI in doze mode.

1 = SCI disabled in doze mode

0 = SCI enabled in doze mode

RSVD[5:1] — Reserved

Writin g to these re ad/w rite bits upda tes th ei r va lues b ut h as no effe ct

on functionality.

RDPSCI — Reduced Drive Bit

This read/write bit controls the drive capability of TXD and RXD.

1 = Reduced TXD and RXD pin drive

0 = Full TXD and RXD pin drive

Address: SCI1 — 0x00cc_0008

SCI2 — 0x00cd_0008

Bit 7654321Bit 0

Read: SCISDOZ 0RSVD5 RDPSCI 00

RSVD1 PUPSCI

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transf er error exception.

Figure 17-10. SCI Pullup and Reduced Drive Register (SCIPURD)

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PUPSCI — Pullu p Enable Bit

This read/write bit e nables the pu l lups o n pins T X D an d RX D. If a pi n

is programmed as an output, the pullup is disabled.

1 = TXD and RXD pullups enabled

0 = TXD and RXD pullups disabled

17.7.8 SCI Port Data Register

Read: Anytime; when DDRSCx = 0, its pin is configured as an input, and

reading PORTSCx returns the pin level; when DDRSCx = 1, its pin is

configured as an output, and reading PORTSCx returns the pin driver

output level.

Write: Anytime; data stored in internal latch drives pin only if D DRSC

bit = 1

RSVD[7:2] — Reserved

Writin g to these re ad/w rite bits upda tes th ei r va lues b ut h as no effe ct

on functionality.

PORTSC[1:0] — SCIPORT Data Bits

These are the read/write data bits of the SCI port.

NOTE: Wr ites to SCIPORT do not change the pin state when the pin is

configured for SCI input.

To e nsure cor rect rea ding of t he S CI pi n va lues f rom S CIPORT, always

wait at least one cycle after writing to SCIDDR before reading SCIPORT.

Address: SCI1 — 0x00cc_0009

SCI2 — 0x00cd_0009

Bit 7654321Bit 0

Read: RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 PORTSC1 PORTSC0

Write:

Reset:00000000

Pin function: TXD RXD

Figure 17-11. SC I Port Data Register (SCIPORT)

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MOTOROLA Serial Communications Interface Modules (SCI1 and SCI2) 373

17.7.9 SCI Data Direction Register

Read: Anytime

Write: Anytime

RSVD[7:2] — Reserved

Writin g to these re ad/w rite bits upda tes th ei r va lues b ut h as no effe ct

on functionality.

DDRSC[1:0] — SCIPORT Da ta Direction Bits

These bits control the data direction of the SCIPORT pins. Reset

clears DDRSC[1:0].

1 = Corresponding pin configured as output

0 = Corresponding pin configured as input

NOTE: When LOOPS = 0 and TE = RE = 1, the RXD pin is an input and the

TXD pin is an output regardless of the state of the DDRSC1 (TXD) and

DDRSC0 (RXD) bits.

Address: SCI1 — 0x00cc_000a

SCI2 — 0x00cd_000a

Bit 76 54321Bit 0

Read: RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 DDRSC1 DDRSC0

Write:

Reset:00000000

Figure 17-12. SC I Data Dire ction Register (SCIDDR)

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17 .8 Fun cti on al Descr iptio n

The SCI allows full-duplex, asynchronous, non-return-to-zero (NRZ)

serial communication between the MCU and remote devices, including

other MCUs. The SCI transmitter and receiver operate independently,

alth ough they use the same bau d rate generator . The CPU m onitor s the

status of the SCI, writes the data to be transmitted, and processes

received data.

17.9 Data Format

The SCI uses the standard NRZ mark/space data format shown in

Fi gu re 17-1 3.

Each frame has a start bit, eight or nine data bits, and one or two stop

bits. Clearing the M bit in SCCR1 configures the SCI for 10-bit fra mes.

Setting the M bit configures the SCI for 11-bit frames.

When the SCI is conf igured for 9- bit data, th e ni nth dat a bit is the T8 bit

in SCI Data Register high (SCIDRH). It remains unchanged after

transmission and can be used repeatedly without rewriting it. A frame

with nine data bits has a total of 11 bits.

Figure 17-13. SCI Data Formats

10-BIT FRAME

START B IT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

BIT STOP

BIT

START

BIT

M = 0 in S CICR1

START B IT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

BIT STOP

BIT

START

BIT

11-BIT FRAME

M = 1 IN SC ICR1

BIT 8

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MOTOROLA Serial Communications Interface Modules (SCI1 and SCI2) 375

17.10 Baud Rate Generation

A 13-bit modulus counter in the baud rate generator derives the baud

rate for both the receiver and the transmitter. The value from 0 to 8191

written to S CIBDH and SCIBDL deter mines the system clock divisor.

The baud rate clock is synchronized with the bus clock and drives the

receiver. The baud rate clock divided by 16 drives the transmitter. The

receiver acquisition rate is 16 samples per bit time.

Baud rate generation is subject to two sources of error:

1. In teger division of the modu l e clock may n ot give the exact tar get

frequency.

2. Synchronization with the bus clock can cause phase shift.

Table 17-4. Example Baud Rates

(System Clock = 33 MHz)

SBR[12:0] Receiver Clock

(Hz) Transmitter Clock

(Hz) Target

Baud Rate Percent

Error

0x0012 1,833,333.3 114,583.3 115,200 0.54

0x0024 916,666.7 57,291.7 57,600 0.54

0x0036 611,111.1 38,194.4 38,400 0.54

0x003d 540,983.6 33,811.4 33,600 0.63

0x0048 458,333.3 28,645.8 28,800 0.54

0x006b 308,411.2 19,275.7 19,200 0.39

0x0008f 230,769.2 14,423.1 14,400 0.16

0x00d7 153,488.4 95,93.0 9,600 0.07

0x01ae 76,744.2 4,796.5 4,800 0.07

0x035b 38,416.8 2,401.0 2,400 0.04

0x06b7 19,197.2 1,199.8 1,200 0.01

0x0d6d 9,601.4 600.1 600 0.01

0x1adb 4,800.0 300.0 300 0

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17.11 Transmitter

Figure 17-14. Transmitter Block Diagram

H876543210L

11-BIT TRAN SM I T SHIFT REG ISTER

STOP

START

TDRE

TIE

TCIE

SBK

MSB

SCI DATA REGISTER

LOAD FROM SCIDR

SH IFT ENABL E

PREAMBLE (ALL 1s)

BREA K (ALL 0s)

TRANSM I TTER CO NTR OL

IPBUS

SBR[12:0]

÷ 16

TXD

TDRE

SYSTEM

LOOP

LOOPS

CLOCK

CONTROL RECEIVER

WOMS

FORC E P IN DIR EC TIO N

PIN BUF FE R

AND CONTROL

BAUD

DIVIDER

PARITY

GENERATION

INTERRUPT

REQUEST

INTERRUPT

REQUEST

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17.11.1 Frame Length

The transmitter can generate either 10-bit or 11-bit frames. In SCICR1,

the M bit selects frame length, and the PE bit enables the parity function.

One data bit may be an address mark or an extra stop bit. All frames

begin with a start bit and end with one or two stop bits. When transmitting

9-bit data, bit T8 in SCI Data Register high (SCIDRH) is the ninth bit

(bit 8).

Table 17-5. Example 10-Bit and 11-Bit Frames

M Bit Frame

Length Start

Bit Data

Bits Parity

Bit Address

Mark(1)

1. When implementing a multidrop network using the SCI, the address mark bit is used to

designate subse quent data frames as a networ k address and not device data.

Stop

Bit(s)

0 10 bit s

1 8 No No 1

1 7 No No 2

17No Yes 1

17Yes No 1

111 bits

1 9 No No 1

1 8 No No 2

18No Yes 1

18Yes No 1

17No Yes 2

17Yes No 2

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17.11.2 Transmitting a Frame

To begin an SCI transmission:

1. Configure the SCI:

a. Write a baud rate value to SCIBDH and SCIBDL.

b. Write to SCICR1 to:

i. Enable or disable loop mode and select the receiver

feedback path

ii. Select open-drain or wired-OR SCI outputs

iii. Select 10-bit or 11-bit frames

iv. Select the receiver wakeup condition: address mark or

idle line

v. Se lect idle line type

vi. Enable or disable the parity function and select odd or

even parity

c. Write to SCICR2 to:

i. Enab le or d isable TDRE, T C, RDRF, and IDLE interrupt

requests

ii. Enable the transmitter and queue a break frame

iii. Enable or disable the receiver

iv. Put the receiver in standby if required

2. Transmit a byte:

a. Clear the TDRE f lag by read ing SCISR1 and, if send ing 9-bit

data, write the ninth data bit to SCDRH.

b. Write the byte to be transmitted (or low-order 8 bits if sending

9-bit data) to SCIDRL.

3. Repeat step 2 for each subsequent transmission.

Writing the TE bit from 0 to 1 loads the transmit shift register with a

preamble of 10 (if M = 0) or 11 (if M = 1) logic 1s. When the preamble

shifts out, the SCI transfers the data from SCIDRH and SCIDRL to the

transmit shift register. The transmit shift register prefaces the data with

a 0 start bit and appends the data with a 1 stop bit and begins shifting

out the frame.

The SCI sets the TDRE flag every time it transfers data from SCIDRH

and SCIDRL to the transmit sh ift register. TDRE indicates t hat SCIDRH

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and SCIDR L can accept new data. If the TIE bit is set, TDR E generate s

an interrupt request.

NOTE: SCIDRH and SCIDRL transfer data to the transmit shift register and sets

TDRE 9/16ths of a bit time after the previous frame’s stop bit starts t o

shift out.

Hardware supports odd or even parity. When parity is enabled, the most

significant data bit is the parity bit.

When the tr ansmit sh if t registe r is not tr ansm itt ing a fr ame, t he TX D pin

goes to the idle condition, logic 1. Clearing the TE bit while the

transmitter is idle will return control of the TXD pin to the SCI data

direction (SCIDDR) and SCI port (SCIPORT) registers.

If the TE bit is cleared while a transmission is in progress (while TC = 0),

the frame in the transmit shift register continues to shift out. Then the

TXD pin re verts to bei n g a gener al-pur pose I/O pin even if there is data

pending in the SCI Data Register. To avoid accidentally cutting off a

message, always wait until TDRE is set after the last frame before

clearing TE.

To se para te messag es w ith pr eam bles with m inimum i dle li ne time, use

this sequence between messages:

1. Write the last byte of the first message to SCID RH and SCIDRL.

2. Wait until the TDRE flag is set, indicating the transfer of the last

frame to the transmit shift register .

3. Queue a preamble by clearing and then setting the TE bit.

4. Write the first byte o f the second message to SCIDRH and

SCIDRL.

When the SCI relinquishes the TXD pin, the SCIPORT and SCIDDR

registers control the TXD pin.

To force TXD high when turning off the transmitter, set bit 1 of the SCI

Port Register (SCIPORT) and bit 1 of the SCI Data Direction Register

(SCIDDR). The TXD pin goes high as soon as the SCI relinquishes

contro l of it. See 17.7.8 SCI Port Data Register and 17.7.9 SCI Data

Direction Register.

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17.11.3 Break Frames

Setting the SBK bit in SCICR2 loads the transmit shift register with a

break frame. A break frame contains all l ogic 0s and has no start, stop,

or parity bit. Break frame length depends on the M bit in the SCICR1

into the transmit shift register. After SBK is clear, the transmit shift

least one logic 1. The automatic logic 1 at the end of a break frame

guarantees the recognition of the next start bit.

The SCI recognizes a break frame when a start bit is followed by eight

or nine 0 data bits and a 0 where the stop bit should be. Receiving a

break frame has these effects on SCI registers:

•Sets the FE flag

•Sets the RDRF flag

•Clears the SCIDRH and SCIDRL

•May set the OR flag, NF flag, PE flag, or the RAF flag

17.11.4 Idle Frames

An idle frame contains all logic 1s and has no start, stop, or parity bit. Idle

frame length depends on the M bit in the SCICR1 register. The preamble

is a synchronizing idle frame that begins the first transmission after

writing the TE bit from 0 to 1.

If the TE bit i s cleare d duri n g a tran smission, th e TX D pi n beco mes idle

after completion of the transmission in progress. Clearing and then

set ting th e T E bi t duri ng a tra nsmission queues an i dle f rame to be se nt

after the frame currently being transmitted.

NOTE: When queueing an idle frame, return the TE bit to logic 1 before the stop

bit of the current frame shifts out to the TXD pin. Setting TE after the stop

bit appears on TXD causes data previously wr itten to SCIDRH and

SCIDRL to be lost. Toggle TE to queue an idle frame, while the TDRE

flag is set, immediately before writing new data to SCIDRH and SCIDRL.

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17.12 Receiver

Figure 17-15. SCI Receiver Block Diagram

17.12.1 Frame Length

The receiver can handle either 8-bit or 9-bit data. The state of the M bit

in SCICR1 selects frame length. Wh en receiving 9-bit data, bit R8 in

SCIDRH is the ninth bit (bit 8).

17.12.2 Receiving a Frame

When the SCI receives a frame, the receive shift register shifts the frame

in from the RXD pin.

ALL 1s

WAKE

ILT

H876543210L

11-BIT RECEIVE SHIFT REGISTER

STOP

START

DATA

WAKEUP

PARITY

CHECKING

MSB

SCI DA TA REG IS T ER

RIE

ILIE

RDRF

IPBUS

RXD

SYSTEM

IDLE

RDRF/OR

SBR[12:0]

BAUD DIVIDER

LOOP

LOOPS

RSRC

FROM TXD OR

TRANSMITTER

CLOCK

IDLE

RAF

RECOVERY

CONTROL

LOGIC

RWU

INTERRUPT

REQUEST

INTERRUPT

REQUEST

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After an entire frame shifts into the receive shift register, the data portion

of the frame transfers to SCIDRH and SCIDRL. The RDRF flag is set,

indicating that the received data can be read. If the RIE bit is also set,

RDRF generates an interrupt re quest.

17.12.3 Data Sampling

The r eceiver sam ples t he RX D pin at the R T clock rate. The RT clock is

an in tern al signal with a fr equen cy 16 ti mes th e baud rate. To adju st for

baud rate mismatch, the RT clock resynchronizes:

•After every start bit

•After the r eceiver detects a data b it chang e from l ogic 1 to logic 0

(after the majority of data bit samples at RT8, RT9, and RT10

returns a valid logic 1 and the majority of the next RT 8, RT9, and

RT10 samples returns a valid logic 0)

To locate the start bit, data recovery logic does an asynchronous search

for a 0 preceded by three 1s. When the falling edge of a possible start bit

occurs, the RT clock begins to count to 16.

Figure 17-16. Receiver Data Sampling

RESET RT CLOCK

RT1

RT2

RT3

RT4

RT5

RT8

RT7

RT6

RT11

RT10

RT9

RT15

RT14

RT13

RT12

RT16

RT1

RT2

RT3

RT4

SAMPLES

RT CLOCK

RT CLOCK COUNT

START BI T

RXD

START BI T

QUALIFICATION START BIT DATA

SAMPLING

111111110000000

LSB

VERIFICATION

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To verify the start bit and to detect noise, data recovery logic takes

samples at RT3, RT5, and RT7.

If start bit verification is not successful, the RT clock is reset and a new

search for a start bit begins.

To determine the value of a data bit and to detect noise, recovery logic

takes samples at RT8, RT9, and RT10.

NOTE: The RT8, RT9, and RT10 data samples do not affect start bit verification.

If any or all of th e RT 8, RT 9, an d RT 10 sa mples are l ogic 1s foll owing a

successful start bit verification, the NF flag is set and the receiver

interprets the bit as a start bit (logic 0).

Table 17-6. Start Bit Verification

R T3, RT5, and RT7 Samples Start Bit Verification No i se Flag

000 Yes 0

001 Yes 1

010 Yes 1

011 No 0

100 Yes 1

101 No 0

110 No 0

111 No 0

Table 17-7. Data Bit Recovery

RT8, RT9, and RT10 Samples Data Bit Determination Noise Flag

000 0 0

001 0 1

010 0 1

011 1 1

100 0 1

101 1 1

110 1 1

111 1 0

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The RT8, RT9, and RT10 samples also verify stop bits.

In Figure 17-17, the verification samples RT3 and RT5 determine that

the fi rst low dete c ted wa s noise and n ot th e beg i nning of a st art b i t. The

RT clock is reset and the start bit search begins again. The NF flag is not

set because the noise occurred before the start bit was verified.

Figure 17-17. Start Bit Search Example 1

Table 17-8. Stop Bit Recovery

RT8, RT9, and RT10 Sampl es Framing Error F lag Noise Flag

000 1 0

001 1 1

010 1 1

011 0 1

100 1 1

101 0 1

110 0 1

111 0 0

RESET RT CLOCK

RT1

RT2

RT3

RT4

RT5

RT1

RT2

RT3

RT4

RT7

RT6

RT5

RT10

RT9

RT8

RT14

RT13

RT12

RT11

RT15

RT16

RT1

RT2

RT3

SAMPLES

RT CLOCK

RT CLOCK COUNT

START BIT

RXD

110111100000

LSB

0 0

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In Figure 17-18, noise is perceived as the beginning of a start bit

although the RT3 sample is high. The RT3 sample sets the noise flag.

Although the perceived bit time is misaligned, the RT8, RT9, and RT10

data samples are within the bit time, and data recovery is successful.

Figure 17-18. Start Bit Search Example 2

In Fig ure 17-19 a lar ge burst of noise is perceive d as the beginni ng of a

start bit, although the RT5 sample is high. The RT5 sample sets the

noise flag. Although this is a worst-case misalignment of perceived bit

time, the data samples RT8, RT9, and RT10 are within the bit time and

data recovery is successful.

Figure 17-19. Start Bit Search Example 3

RESET RT CLOCK

RT1

RT2

RT3

RT4

RT5

RT6

RT7

RT8

RT11

RT10

RT9

RT14

RT13

RT12

RT2

RT1

RT16

RT15

RT3

RT4

RT5

RT6

RT7

SAMPLES

RT CLOCK

RT CLOCK COUNT

AC T UAL START BIT

RXD

1111110000

LSB

PER CEIVED STAR T BIT

RESET RT CLOCK

RT1

RT2

RT3

RT4

RT5

RT6

RT7

RT8

RT9

RT10

RT13

RT12

RT11

RT16

RT15

RT14

RT4

RT3

RT2

RT1

RT5

RT6

RT7

RT8

RT9

SAMPLES

RT CLOCK

RT CLOCK COUNT

ACTUAL START BIT

RXD

101110000

LSB

PERCEIVED ST ART BI T

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Fi gu re 17-2 0 shows the effect of noise early in the start bit time.

Althou gh this noise does not a ffect proper synchron ization with the s tart

bit time, it does set the noise flag.

Figure 17-20. Start Bit Search Example 4

Fi gu re 17-2 1 shows a burst of noise near the beginning of the start bit

that resets the RT clock. The sample after the reset is low but is not

preceded by three high samples that would qualify as a falling edge.

Depending on the timing of the start bit search and on the data, the frame

may be missed entirely or it may set the framing error flag.

Figure 17-21. Start Bit Search Example 5

RESET RT CL OC K

RT1

RT2

RT3

RT4

RT7

RT6

RT5

RT10

RT9

RT8

RT14

RT13

RT12

RT11

RT15

RT16

RT1

RT2

RT3

SAMPLES

RT CLOC K

RT CLOCK CO UNT

PER CEIVED AND ACTU AL STA RT BIT

RXD

11111001

LSB

11 1 1

RESET RT CL OC K

RT1

RT2

RT3

RT4

RT7

RT6

RT5

RT1

SAMPLES

RT CLOC K

RT CLOCK CO UNT

START BIT

RXD

11111010

LSB

11 1 1 1 0000000 0

NO START BIT FOUND

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In Figure 17-22 a noise burst m akes the major ity of data sample s RT8,

RT9, and RT10 hi gh. Th is sets the noise flag but does not rese t the RT

clock. In start bits only, the RT8, RT9, and RT10 data samples are

ignored.

Figure 17-22. Start Bit Search Example 6

17.12.4 Framing Errors

If the data recovery logic does not detect a 1 where the stop bit should

be in an incoming frame, it sets the FE flag in SCISR1. A break frame

also sets the FE flag because a break frame has no stop bit. The FE flag

is set at the same time that the RDRF flag is set.

17.12.5 Baud Rate Tolerance

A transmitting device may be operating at a baud rate below or above

the receiver baud rate. Accumulated bit time misalignment can cause

one of the RT8, RT 9, an d R T10 stop bi t d ata sampl es t o fall o utsi de t he

stop bit. A noise error occurs if the samples are not all the same value.

If more than one of the samples i s outside the stop bit, a framing error

occurs. In m ost applica tions, the baud rate to lerance i s much more than

the degree of misalignment that is likely to occur.

As the re ceiver samples an incoming frame, it resynchronizes the RT

clock on any valid falling edge within the frame. Resynchronization

within f ram es corr ects misa lig nmen ts betwee n tran smi tter bit time s and

receiver bit times.

RESET RT CL OC K

RT1

RT2

RT3

RT4

RT7

RT6

RT5

RT10

RT9

RT8

RT14

RT13

RT12

RT11

RT15

RT16

RT1

RT2

RT3

SAMPLES

RT CLOC K

RT CLOCK CO UNT

START BIT

RXD

11111000

LSB

11 1 1 0 110

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17.12.5.1 Slow Data Tolerance

Figure 17-23 shows how much a slow received frame can be misaligned

without causing a noise error or a framing error. The slow stop bit begins

at RT8 instead of RT1 but arrives in ti me for the stop bit data samples at

RT8, RT9, and RT10.

Figure 17-23. Slow Data

For 8-bit data, sampling of the stop bit takes the receiver:

9bittimes×16 RT cycles + 10 RT cycles = 154 RT cycles.

With the misaligned data shown in Figure 17 -23, the receiver counts

154 RT cycles at the point when the count of the transmitting device is:

9bittimes×16 RT cycles + 3 RT cycles = 147 RT cycles.

The maximum percent difference between the receiver count and the

transmitter count for slow 8-bit data with no errors is:

For 9-bit data, sampling of the stop bit takes the receiver:

10 bit times ×16 RT cycles + 10 RT cycles = 170 RT cycles.

With the misaligned data shown in Figure 17 -23, the receiver counts

170 RT cycles at the point when the count of the transmitting device is:

10 bit times ×16 RT cycles + 3 RT cycles = 163 RT cycles.

The maximum percent difference between the receiver count and the

transmitter count for slow 9-bit data with no errors is:

MSB STOP

RT1

RT2

RT3

RT4

RT5

RT6

RT7

RT8

RT9

RT10

RT11

RT12

RT13

RT14

RT15

RT16

DATA

SAMPLES

RECEIVER

RT CLOC K

154 147–

154

--------------------------100×4.54%=

170 163–

170

--------------------------100×4.12%=

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17.12.5.2 Fast Data Tolerance

Figure 17-24 shows how mu ch a fast rece ived fr ame can be mi saligned

without causing a noise error or a framing error. The fast stop bit ends at

RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10.

Figure 17-24. Fast Data

For 8-bit data, sampling of the stop bit takes the receiver:

9bittimes×16 RT cycles + 10 RT cycles = 154 RT cycles.

With the misaligned data shown in Figure 17 -24, the receiver counts

154 RT cycles at the point when the count of the transmitting device is:

10 bit times ×16 RT cycles = 160 RT cycles.

The maximum percent difference between the receiver count and the

transmitter count for fast 8-bit data with no errors is:

For 9-bit data, sampling of the stop bit takes the receiver:

10 bit times ×16 RT cycles + 10 RT cycles = 170 RT cycles.

With the misaligned data shown in Figure 17 -24, the receiver counts

170 RT cycles at the point when the count of the transmitting device is:

11 bit times ×16 RT cycles = 176 RT cycles.

The maximum percent difference between the receiver count and the

transmitter count for fast 9-bit data with no errors is:

IDLE OR NEXT FRAMESTOP

RT1

RT2

RT3

RT4

RT5

RT6

RT7

RT8

RT9

RT10

RT11

RT12

RT13

RT14

RT15

RT16

DATA

SAMPLES

RECEIVER

RT CLOCK

154 160–

154

--------------------------100×3.90%=

170 176–

170

--------------------------100×3.53%=

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17.12.6 Receiver Wakeup

So that the SCI can ignore transmissions intended only for other devices

in multiple-receiver systems, the receiver can be put into a standby

state. Setting the RWU bit in SCICR2 puts the receiver into a standby

state during which receiver interrupts are disabled.

The t ransmitting d evice can ad dress messag es to selected re ceivers by

including addressing information in the initial frame or frames of each

message.

The WAK E bit in SCICR1 deter mines how the SCI is brough t out of the

standby sta t e to proce ss an inco ming m essage . The W AKE bit ena bl es

either idle line wa keup or address mark wakeup.

17.12.6.1 Idle Input Line Wakeup (WAKE = 0)

When WAKE = 0, an idle condition on the RXD pin clears the RWU bit

and wakes up the receiver. The initial frame or frames of every message

contain addressing information. All receivers evaluate the addressing

info rmation, and rece ive rs for which the message is addr essed process

the frames that follow. Any re ceiver for which a message is not

addressed can set its RWU bit and return to the standby state. The RWU

bit remains set and the receiver remains on standby until another idle

frame appears on the RXD pin.

Idle line wakeup requires that messages be separated by at least one

idle frame and that no message contains idle frames.

The idle frame that wakes up the receiver does not set the IDLE flag or

the RDRF flag.

The ILT bit in SCICR1 de termines wheth er the receiv er begins cou nting

logic 1s as idle frame bits after the start bit or after the stop bit.

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17.12.6.2 Address Mark Wakeup (WAKE = 1)

When WAKE = 1, an address mark clears the RWU bit and wakes up the

receiv er. An addr ess mark is a 1 in the most sign ificant dat a bit posi tion.

The receiver interprets the data as address data. When using address

mark wakeup, the MSB of all non-address data must be 0. User code

must compare the address data to the receiver’s address and, if the

addresses match, the receiver processes the frames that follo w. If the

addresse s do not mat c h, user cod e must put the receive r back to sleep

by setting the RWU bit. The RWU bit remains set and the receiver

remains on standby until another address frame appears on the RXD

pin.

The address mark clears the RWU bit before the stop bit is received and

sets the RDRF flag.

Address mark wakeup allows messages to contain idle frames but

requires that the most significant byte (MSB) be reserved for address

data.

NOTE: With the WAKE bit clear, setting the RWU bit after the RXD pin has been

idle can cause the receiver to wake up immediately.

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17.13 Single-Wire Operation

Nor mally, the SCI use s t he TXD pin for transm itting and the R XD pin for

receiv ing ( LOOPS = 0, RS RC = X). In single-wire m ode, th e RXD pin is

disconnected from the SCI and is available as a general-purpose I/O pin.

The SCI uses the TXD pin for both receiving and transmitting.

In single-wire mode (LOOPS = 1, RXRC = 1), setting the data direction

bit for the TXD pin configures TXD as the output for transmitted data.

Clearing the data direction bit configures TXD as the input for received

data.

Figure 17-25. Single-Wir e Operation (LOOPS = 1, RSRC = 1)

Enable single-wire operation by setting the LOOPS bit and the RSRC bit

in SCICR1. Setting the LOOPS bit disables the path from the RXD pin to

the receiver. Setting the RSRC bit connects the receiver input to the

output of the TXD pin driver. Both the transmitter and receiver must be

enabled (TE = 1 and RE = 1).

The WOMS bit in the SCICR1 register configures the TXD pin for full

CMOS drive or for open-drain drive. WOM S controls the TXD pin in both

normal operation and in single-wire operation. When WOMS is set, the

DDR bit for the TXD pin does not ha ve to be cleared for transmitter to

receive data.

TXD SCIDDR

GENERAL-PURPOSE I/O

TRANSMITTER

WOMS

TXD

RECEIVER

TRANSMITTER

RECEIVER

RXD

TXD

RXD

BIT = 1

BIT = 0

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17.14 Loop Operation

In loop mode (LO OPS = 1 , RSRC = 0), the transmitter output goes to the

receiver input. The RXD pin is disconnected from the SCI and is

available as a general-purpose I/O pin.

Setting the DDR bit for the TXD pin connects the transmitter output to the

TXD pin. Clearing the data direction bit disconnects the transmitter

output from the TXD pin.

Figure 17-26. Loop Operation (LOOPS = 1, RSRC = 0)

Enab le l oop oper ation by sett ing the LOOPS bi t a nd cle aring the R SR C

bit in SCICR1. Setting the LOOPS bit disables the path from the RXD pin

to the receiver . Clearing the RSRC bit connects the tra nsmitter o utput to

the receiver input. Both the transmitter and receiver must be enabled

(TE = 1 and RE = 1).

The WOMS bi t in SC ICR1 confi gures t he TXD pi n for full CMOS drive or

for open-drain drive. WOMS controls the TXD pin during both normal

operation and loop operation.

TXD

WOMS

TXD SCIDDR

GENE RA L - P URP O SE I/O

TRANSMITTER

RECEIVER

TRANSMITTER

RECEIVER

WOMS

RXD

TXD

BIT = 1

BIT = 0

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17.15 I/O Ports

The SCIPORT register is associated with two pins:

•The TXD pin is connected to SCIPORT1.

•The RXD pin is connected to SCIPORT0.

The SCI Data Direction Register (SCIDDR) configures the pins as inputs

or outputs (see 17.7.9 SCI Data Direction Register). The SCI Pullup

and Reduced Drive Register (SCIPURD) controls pin drive capability

and enables or disables pullups (see 17.7.7 SCI Pullu p and Red uced

Drive Register). The WOMS bit in SCI Control Register 1 (SCICR1)

configures output ports as full CMOS drive outputs or as open-drain

outputs (see 17.7.2 SCI Control Register 1).

Table 17-9. SCI Port Control Summary

Pullup Enable Control Reduced Dri ve Control Wired- OR Mode Control

State Register Bit Reset

State

SCIPURD PUPSCI 0 SCIPURD RDPSCI 0 SCICR1 WOMS CMOS

drive

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17.16 Reset

Rese t initial izes t he S CI r egister s to a known startu p sta te as described

in 17.7 Memory Map and Registers.

17.17 Interrupts

Table 17-10 lists the five interrupt requests associated with each SCI

module.

17.17.1 Transmit Data Register Empty

The TDRE flag is set when the transmit shift register receives a byte from

the SCI Data Re gister. It signals that SCIDRH and SCIDRL are empty

and can receive new data to tra nsmit. If the TIE bit in SCICR2 is also set,

TDRE generates an interrupt request. Clear TDRE by reading SCISR1

and then writing to SCIDRL. Reset sets TDRE.

17.17.2 Transmission Complete

The TC flag is set when TDRE = 1 and no data, preamble, or break

frame is being transmitted. It signa ls that no tr ansmissio n is in progr ess.

If the TCIE bit is set in SCICR2, TC generates an interrupt request.

When TC is set, the TX D pin is idle (lo gic 1). T C is cleared a utomatically

whe n a data, pream ble, or bre ak frame is queue d. Clear TC by readi ng

SCIS R1 w ith TC set and th en writing to the SCIDR L register . TC cannot

be cleared while a transmission is in progress.

Table 17-10. SCI Interrupt Request Sources

Source Flag Enable Bit

Transmitter TDRE TIE

TC TCIE

Receiver

RDRF RIE

OR RIE

IDLE ILIE

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Serial Communications Interface Modules (SCI1 and SCI2)

17.17.3 Receive Data Register Full

The RDRF flag is set when the data in the receive shift register transfers

to S CID RH and SCIDRL. It signal s t hat t he r eceived data is a vailabl e t o

be read. If the RIE bit is set in SCICR2, RDRF generates an interrupt

request. Clear RDRF by reading SCISR1 and then reading SCIDRL.

17.17.4 Idle Receiver Input

The IDLE flag is set when 10 (if M = 0) or 11 (if M = 1) consecutive

logic 1s appear on the receiver input. This signals an idle condition on

the receiver input. If the ILIE bit in SCICR2 is set, IDLE generates an

interrupt request. Once IDLE is cleared, a valid frame must again set the

RDRF flag before an idle condition can set the IDLE flag. Clear IDLE by

reading SCISR1 with IDLE set and then reading SCIDRL.

17.17.5 Overrun

The OR flag is set if data is not read from SCIDRL before the receive

shift register receives the stop bit of the next frame. This signals a

receiver overrun condition. If the RIE bit in SCICR2 is set, OR generates

an interrupt request. The data in the shift register is lost, but the data

already in S CIDRH and SCIDRL is not affected. Clear OR by reading

SCISR1 and then reading SCIDRL.

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MOTOROLA Serial Peripheral Interface Mo dule (SPI)  397
Advance Info rmation — MMC2114, MMC2113, and MMC2112
Section 18. Serial Peripheral Interface Module (SPI)
1  Contents
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398
4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
5 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
6 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400
6.1 MISO (Master In/Slave Out). . . . . . . . . . . . . . . . . . . . . . . .400
6.2 MOSI (Master Out/Slave In). . . . . . . . . . . . . . . . . . . . . . . .400
6.3 SCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401
6.4 SS (Slave Select). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401
7 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .401
7.1 SPI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .402
7.2 SPI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .405
7.3 SPI Baud Rate Register. . . . . . . . . . . . . . . . . . . . . . . . . . .406
7.4 SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .408
7.5 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .409
7.6 SPI Pullup and Reduced Drive Re gister  . . . . . . . . . . . . . .410
7.7 SPI Port Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .411
7.8 SPI Port Data Direction Register . . . . . . . . . . . . . . . . . . . .412
8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .413
8.1 Master Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .414
8.2 Slave Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415
8.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . .416
8.3.1 Transfer Format When CPHA = 1 . . . . . . . . . . . . . . . . .416
8.3.2 Transfer Format When CPHA = 0 . . . . . . . . . . . . . . . . .417
8.4 SPI Baud Rate Generatio n. . . . . . . . . . . . . . . . . . . . . . . . .420
8.5 Slave-Select Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420
8.6 Bidirectional Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .421
    
  
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Serial Peripheral Interface Module (SPI)
18.8.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422
18.8.7.1 Write Collision Error. . . . . . . . . . . . . . . . . . . . . . . . . . . .422
18.8.7.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422
18.8.8 Low-Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . .423
18.8.8.1 Run Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .423
18.8.8.2 Doze Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .423
18.8.8.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .424
18.9 Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .424
18.10 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .424
18.10.1 Mode Fault (MODF) Flag . . . . . . . . . . . . . . . . . . . . . . . . . .424
18.10.2 SPI Interrupt Flag (SPIF) . . . . . . . . . . . . . . . . . . . . . . . . . .424
18.2  Introduction
The serial peripheral interface (SPI) module allows full-duplex, 
synchronous, serial communication between the microcontroller unit 
(MCU ) and periphera l  device s. S oftwar e ca n p oll  the  SPI  statu s flag s or  
SPI operation can be interrupt driven.
18.3  Features
Features include:
•Master mode and slave mode
•Wired-OR mode
•Slave-select output
•Mode fault error flag with central processor unit (CPU) interrupt 
capability
•Double-buffered operation
•Serial  clock with programmable polarity and phase
•Control of SPI operation during doze mode
•Reduced drive control for lower power consumption
    
  
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18.4 Modes of Operation

The SPI functions in these three modes:

1. Run mode — Run mode is the normal mode of operation.

2. Doze mode — Doze mode is a configurable low-power mode.

3. Stop mode — The SPI is inactive in stop mode.

18.5 Blo ck Diag r am

Figure 18-1. SPI Block Diagram

MSTR

SWOM

SSOE

LSBFE

SPISDOZ SPC0

SPIF

WCOL

MODF

256128643216842 DIVIDER

BAUD RATE SELECT

BAUD RATE GENERATO R

SHIFT REGISTER

SHIFT

SPIPORT

MISO

MOSI

SCK

CONTROL

CLOCK

CONTROL

SPI

CONTROL

SPR[2:0]SPPR[6:4] MSTR

CPOL

CPHA

MSTR

SPI DATA R EGI ST ER

SPIE

SPE

RDPSP

PUPSP

DDRSP[7:0]

IP INTERFACE

SPI

INTERRUPT

REQUEST

SPI CLOCK

MSB LSB

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Serial Peripheral Interface Module (SPI)

18.6 Signal Description

An overview of the signals is provided in Table 18-1.

18.6.1 MISO (Master In/Slave Out)

MISO is one of the two SPI data pins.

•In master mode, MISO is the data input.

•In sl ave mo de, M ISO i s the da ta ou tput an d is three-stated unti l a

master drives the SS input pin low.

•In bidirectional mode, a slave MISO pin is the SISO pin (slave

in/slave out).

•In a multiple-master system, all MISO pins are tied together.

18.6.2 MOSI (Master Out/Slave In)

MOSI is one of the two SPI data pins.

•In master mode, MOSI is the data output.

•In slave mode, MOSI is the data input.

•In bi directional mode , a master MOSI pi n is the M OMI pi n (master

out/master in).

•In a multiple-master system, all MOSI pins are tied together.

Table 18-1. Signal Properties

Name Port Function(1)

1. The SPI por ts (MI SO, MOSI, SCK, and SS) are gener al-pu rpose I /O p orts whe n the SPI is

disabled (SPE = 0).

Reset State

MISO SPIPORT0 Master data in/slave data out 0

MOSI SPIPORT1 Master data out/slave data in 0

SCK SPIPORT2 S erial clock 0

SS SPIPORT3 Slave select 0

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18.6.3 SCK (Serial Clock)

The SCK pin is the serial clock pin for synchronizing transmissions

between master and slave devices.

•In master mode, SCK is an output.

•In slave mode, SCK is an input.

•In a multiple-master system, all SCK pins are tied together.

18.6.4 SS (Slave Select)

In master mode, the SS pin can be:

•A mode-fault input

•A general-purpose input

•A general-purpose output

•A slave-select output

In slave mode, the SS pin is always a slave-select input.

18.7 Memory Map and Register s

Table 18-2 shows the SPI memory map.

NOTE: Reading reserved addresses (0x00cb_004 and 0x00cb_0009 through

0x00cb_000b) and unimplemented addresses (0x00cb_000c through

0x00cb_000f) returns 0s. Writing to unimplemented addresses has no

effect. Accessing u nimplemente d addre sses does not gene rate an error

response.

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18.7.1 SPI Control Register 1

Read: Anytime

Write: Anytime

SPIE — SPI Interrupt Enable Bit

The SPIE bit enabl es the SPIF and MODF fla gs to gener ate interrupt

requests. Reset clears SPIE.

1 = SPIF and MODF interrupt requests enabled

0 = SPIF and MODF interrupt requests disabled

Table 18-2. SPI Memory Map

Address Bits 7–0 Access(1)

1. S/U = CPU supervisor or user m ode access. User mode accesses to supervisor only ad-

dresses have no effe ct and resul t in a cycle termination transfer err or.

0x00cb_ 0000 SP I Control Register 1 (SPICR1) S/U

0x00cb_ 0001 SP I Control Register 2 (SPICR2) S/U

0x00cb_ 0002 S P I Baud Rate Register (SPIBR) S /U

0x00cb_ 0003 SPI Status Register (SPISR) S/U

0x00cb_0005 SPI Data Register (SPIDR) S/U

0x00cb_0006 SPI Pullup and Reduced Drive Register (SPIPURD) S/U

0x00cb_ 0007 SPI Port Data Register (SPIPORT) S/U

0x00cb_0008 SPI Port Data Direct ion Register (SPIDDR) S/U

Address: 0x00cb_0000

%LW%LW

Read: SPIE SPE SWOM MSTR CPOL CPHA SSOE LSBFE

Write:

Reset:00000100

Figure 18-2. SPI Control Regi ster 1 (SPICR1)

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SPE — SPI Sys tem Enable Bit

The SPE bit enabl e s the SPI and ded ica tes SP I p ort pins [3 :0] to SPI

functions. When SPE is clear, the SPI system is initialized but in a

low-power disabled state. Reset clears SPE.

1 = SPI enabled

0 = SPI disabled

SWOM — SPI Wired-OR Mode Bit

The SWOM bit configures the output buffers of SPI port pins [3:0] as

open-d rai n outp uts. SWOM control s SPI port pins [3:0] whet her they

are SPI outputs or general-purpose outputs. Reset clears SWOM.

1 = Output buffers of SPI port pins [3:0] open-drain

0 = Output buffers of SPI port pins [3:0] CMOS drive

MSTR — Master Bit

The MSTR bit selects SPI master mode or SPI slave mode opera tion.

Reset clears MSTR.

1 = Master mode

0 = Slave mode

CPOL — Clock Polarity Bit

The CPOL bit selects an inverted or non-inverted SPI clock. To

transmit data between SPI modules, the SPI modules must have

identical CPOL values. Reset clears CPOL.

1 = Active-low clock; SCK idles high

0 = Active-high clock; SCK idles low

CPHA — Clock Phase Bit

The CPHA bit delays the first edge of the SCK clock. Reset sets

CPHA.

1 = First SCK edge at start of transmission

0 = First SCK edge 1/2 cycle after start of transmission

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SSOE — Slave Select Output Enable Bit

The SSOE bit and the DDRSP 3 bit configure the SS pin as a

general-purpose input or a slave-select output. Reset clears SSOE.

NOTE: Setting the SSOE bit disables the mode fault detect function.

LSBFE — LSB-First Enable Bit

The LSBFE enables data to be transmitted LSB first. Reset clears

LSBFE.

1 = Data transmitted LSB first.

0 = Data transmitted MSB first

NOTE: In SPIDR, the MSB is always bit 7 regardless of the LSBFE bit.

Table 18-3. SS Pin I/O Configurations

DDRSP3 SSOE M aster M ode Slave Mode

0 0 Mode-fault input Slave-select input

0 1 General-purpose input Slave-select input

1 0 General-purpose output Slave-select input

1 1 Slave-select output Slave-select input

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18.7.2 SPI Control Register 2

Read: Anytime

Write: Anytime; writing to unimplemented bits has no effect

SPISDOZ — SPI Stop in Doze Bit

The S PIDOZ bit stops the SPI clocks when the CPU is in doze mode.

Reset clears S PISDOZ.

1 = SPI inactive in doze mode

0 = SPI active in doze mode

SPC0 — Seri al Pin Control Bit 0

The SPC0 bit enables the bidirectional pin configurations shown in

Table 18-4. Reset clears SPC0.

Address: 0x00cb_0001

Bit 7654321Bit 0

SPISDOZ SPC0

Write:

Reset:00000100

= Writes have no effect and the access terminates without a transf er error exception.

Figure 18-3. SPI Control Regi ster 2 (SPICR2)

Tab le 18-4. Bidirectional Pin Configurations

Pi n Mo de SPC0 MSTR MISO Pin(1) MOSI Pin(2) SCK Pin(3) SS Pin(4)

ANormal 0 0S lave data

output Slave data input SCK input Slave-select input

B1 Master data input Master data

output SCK output MODF/GP input (DDRSP3 = 0)

or GP output (DDRSP3 = 1)

CBidirectional 1 0 Slave dat a I/O GP(5) I/O SCK input Slav e-select inp ut

D1 GP I/O Master data I/O SCK output MODF/GP input (DDRSP3 = 0)

or GP output (DDRSP3 = 1)

1. Slav e output is enabled if SPIDDR bit 0 = 1, SS = 0, and MST R = 0 (A, C).

2. Master output is enabled if SPIDDR bit 1 = 1 and MSTR = 1 (B, D).

3. SCK output is enabl ed if SPIDDR bit 2 = 1 and MSTR = 1 (B, D).

4. SS output is enabled if SPIDDR bit 3 = 1, SPICR1 bit 1 (SSOE) = 1, and MSTR = 1 (B, D). MODF input is enabled if SPI

DDR bit 3 = 0 and SSOE = 0. GP input is enabled if SPI DDR bit 3 = 0 and SSOE = 1.

5. GP = General-purpose

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18.7.3 SPI Baud Rate Register

Read: Anytime

Write: Anytime; writing to unimplemented bits has no effect

SPPR[6:4] — SPI Baud Rate Preselection Bits

The SPP R[6:4] and SPR[2:0] bits select the SPI clock divisor as

shown in Table 18-5. Reset clears SPPR[6:4] and SPR[2:0], selecting

an SPI clock divisor of 2.

SPR[2 :0] — SPI Baud Rate Bits

The SPP R[6:4] and SPR[2:0] bits select the SPI clock divisor as

shown in Table 18-5. Reset clears SPPR[6:4] and SPR[2:0], selecting

an SPI clock divisor of 2.

NOTE: Writing to SPIBR during a transmission may cause spurious results.

Address: 0x00cb_0002

Bit 7654321Bit 0

Read: 0 SPPR6 SPPR5 SPPR4 0SPR2 SPR1 SPR0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transf er error exception.

Figure 18-4. SPI Baud Rate Register (SPIBR)

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Table 18-5. SPI Baud Rate Selection (33-MHz Modu le Clock)

SPPR[6:4] SPR[2:0] SPI Clock

Divisor Bau d Rate SPPR[6: 4 ] S PR [ 2 : 0 ] SPI Clo ck

Divisor Ba ud Rate

000 000 2 16.5 MHz 100 000 10 3.3 MHz

000 001 4 8.25 MHz 100 001 20 1.65 MHz

000 010 8 4.125 MH z 100 010 40 825 MHz

000 011 16 2.06 MHz 100 011 80 412.5 kHz

000 100 32 1.03 MHz 100 100 160 206.25 kHz

000 101 64 515.62 kHz 100 101 320 103.13 kHz

000 110 128 257.81 kHz 100 110 640 51.56 kHz

000 111 256 128.9 k Hz 100 111 1280 25.78 kHz

001 000 4 8.25 MHz 101 000 12 2.75 MHz

001 001 8 4.12 MHz 101 001 24 1.375 MHz

001 010 16 2.06 MHz 101 010 48 687.5 kHz

001 011 32 1.03 MHz 101 011 96 343.75 kHz

001 100 64 515.62 kHz 101 100 192 171.88 kHz

001 101 128 257.81 kHz 101 101 384 85.94 kHz

001 110 256 128.9 kHz 10 1 110 76 8 42.9 7 kHz

001 111 512 64.45 k Hz 101 111 1536 21.48 kHz

010 000 6 5.5 MHz 110 000 14 2.36 M H z

010 001 12 2.75 MHz 110 001 28 1.18 MHz

010 010 24 1.375 MH z 110 010 56 589.29 kHz

010 011 48 687.5 kHz 110 011 112 296. 64 kH z

010 100 96 343.75 kHz 110 100 224 147.32 kHz

010 101 192 171.88 kHz 110 101 448 73.66 kHz

010 110 384 85.94 kHz 110 110 896 36.83 kHz

010 111 768 42.97 k Hz 110 111 1792 18.42 kHz

011 000 8 4.13 MHz 111 000 16 2.06 MHz

011 001 16 2. 06 MHz 111 001 32 1.03 MHz

011 010 32 1. 03 MHz 111 010 64 515.63 kHz

011 011 64 515.63 kHz 111 011 128 257.81 kHz

011 100 128 257.81 kHz 111 100 256 128.91 kHz

011 101 256 128.91 kHz 111 101 512 64.45 kHz

011 110 512 64. 45 kH z 111 110 1024 32.23 kHz

011 111 1024 32.23 k Hz 111 111 2048 16.11 k Hz

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18.7.4 SPI Status Reg ister

Read: Anytime

Write: Has no meaning or effect

SPIF — SPI Interrupt Flag

The SPIF flag is set after the eighth SCK cycle in a transmission when

received data transfers from the shift register to SPIDR. If the SPIE bit

is also set, S PIF g enerates a n interru pt request . Once S PIF i s set, n o

new data can be transferred into SPIDR until SPIF is cleared. Clear

SPIF by reading SPISR with SPIF set and then accessing SPIDR.

Reset clears S PIF.

1 = New data available in SPIDR

0 = No new data availa ble in SPIDR

WCOL — Write Collision Flag

The WCOL flag is set when software writes to SPIDR during a

transmission . Clear WCOL by reading SPISR with WCOL set and

then accessing SPIDR. Reset clears WCOL.

1 = Write collision

0 = No write collision

MODF — Mode Fault Flag

The MODF flag is set when the SS pin of a master S PI is driven low

and the SS pin is configured as a mode-fault input. If the SPIE bit is

also set, MODF generates an interrupt request. A mode fault clears

the SPE, MSTR, and DDRSP[2:0] bits. Clear MODF by reading

SPISR with MODF set and then writing to SPICR1. Reset clears

MODF.

1 = Mode fault

0 = No mode fault

Address: 0x00cb_0003

Bit 7654321Bit 0

Read: SPIF WCOL 0 MODF 0000

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transf er error exception.

Figure 18-5. SPI Status Register (SPISR)

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18.7.5 SPI Data Register

Read: Anytime; normally read onl y after SPIF is set

Write: Anytime; see WCOL

SPIDR is both the input and output register for SP I data. Writing to

SPIDR while a transmission is in progress sets the WCOL flag and

disa bles the attempted write. Rea d SPID R after the S PIF fla g is set and

before the end of the next transmission. If the SPIF flag is not serviced

before a new byte enters the shift register, the new byte and any

successive b ytes a re lost. T he byte alre ady in the SPIDR remains there

until SPIF is serviced.

Address: 0x00cb_0005

Bit 76 54321Bit 0

Read: BIT 7654321BIT 0

Write:

Reset:00000000

Figure 18-6. SPI Data Register (SPIDR)

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18.7.6 SPI Pullup and Reduced Drive Register

Read: Anytime

Write: Anytime; writing to unimplemented bits has no effect

RSVD5 and RSVD1 — Reserved

Writin g to these re ad/w rite bits upda tes th ei r va lues b ut h as no effe ct

on functionality.

RDPSP — SPI Port Reduced Drive Co ntrol Bit

1 = Reduced drive capability on SPIPORT bits [7:4]

0 = Full drive enabled on SPIPORT bits [7:4]

PUPSP — SPI Port Pullup Enable Bit

1 = Pullup devices enabled for SPIPORT bits [3:0]

0 = Pullup devices disabled for SPIPORT bits [3:0]

Address: 0x00cb_0006

Bit 7654321Bit 0

Read: 0 0 RSVD5 RDPSP 00

RSVD1 PUPSP

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transf er error exception.

Figure 18-7. SPI Pullup and Reduced Drive Register (SPIPURD)

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Serial Peripheral Interface Module (SPI)

Mem ory Map and Registers

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 A dv ance I nforma tion

MOTOROLA Serial Peripheral Interface Mo dule (SPI) 411

18.7.7 SPI Port Data Register

Read: Anytime

Write: Anytime

RSVD[7:4] — Reserved

Writin g to these re ad/w rite bits upda tes th ei r va lues b ut h as no effe ct

on functionality.

PORTSP[3:0] — SPI Port Data Bits

Data written to SPIPORT drives pins only when they are configured

as general -pu rpose outputs.

Reading an input (DDRSP bit clear) returns the pin level; reading an

output (DDRS P bit set) returns the pin driver input level.

Writing to any of the PORTSP[3:0 ] pins does not change the pin state

when the pin is configured for SPI output.

SPIPORT I/O function depends upon the state of the SPE bit in

SPICR1 and the state the DDRSP bits in SPIDDR.

Address: 0x00cb_0007

Bit 7654321Bit 0

Read: RSVD7 RSVD6 RSVD5 RSVD4 PORTSP3 PORTSP2 PORTSP1 PORTSP0

Write:

Reset:00000000

Pin function: SS SCK MOSI/

MOMI MISO/

SISO

Figure 18-8. SPI Port Data Register (SPIPORT )

Table 18-6. SPI Port Summary

Pullup Enable Control Reduced Drive Control Wired-OR

Mode C on t rol

State Register Bit Reset

State

SPIPURD PUPSP 0 SPIPURD RDPS P[1: 0] Full drive SPICR1 SWOM Normal

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412 Serial Peripheral Interface Module (SPI) MO TOROLA

Serial Peripheral Interface Module (SPI)

18.7.8 SPI Port Data Direction Register

Read: Anytime

Write: Anytime

RSVD[7:4] — Reserved

Writin g to these re ad/w rite bits upda tes th ei r va lues b ut h as no effe ct

on functionality.

DDRSP[3:0] — Data Direction Bits

The DDRSP[3:0] bits control the data direction of SPIPORT pins.

Reset clears DDRSP[3:0].

1 = Corresponding pin configured as output

0 = Corresponding pin configured as input

In slave mode, DDRSP3 has no meaning or effect. In master mode,

the DDRSP3 and the SSOE bits determine whether SP I port pin 3 is

a mode-fault input, a general-purpose input, a general-purpose

output, or a slave-sele ct output.

NOTE: When the SPI is enabled (SPE = 1), the MISO, MOSI, and S CK pins:

•Are inputs if their SPI functions are input functions regardless of

the state of their DDRSP bits.

•Are outputs if their SPI functions are ou tput functions only if their

DDRSP bits are set.

Address: 0x00cb_0008

Bit 7654321Bit 0

Read: RSVD7 RSVD6 RSVD5 RSVD4 DDRSP3 DDRSP2 DDRSP1 DDRSP0

Write:

Reset:00000000

Pin function: SS SCK MOSI/

MOMI MISO/

SISO

Figure 18-9. SPI Port Data Direction Registe r (SPIDDR)

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Serial Peripheral Interface Module (SPI)

Functional Description

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 A dv ance I nforma tion

MOTOROLA Serial Peripheral Interface Mo dule (SPI) 413

18 .8 Fun cti on al Descr iptio n

The SPI module allows full -duplex, synchronous, serial communication

between the MCU and peripheral devices. Software can poll the SPI

status flags or SPI operation can be interrupt driven.

Setting the SPE bit in SPICR1 enables the SPI and dedicates four SPI

port pins to SPI functions:

•Slave select (SS)

•Serial clock (SCK)

•Master out/slave in (MOSI)

•Master in/slave out (MISO)

When the SPE bit is clear, the SS, SCK, MOSI, and MISO pins are

general-purpose I/O pins controlled by SPIDDR.

The 8-bit shift register in a master SPI is linked by the MOSI and MISO

pin s to t he 8- bit sh if t re gister in the sl ave. The linked shi ft r egister s for m

a di stribu ted 1 6-bit regi ste r. In an SPI tr ansmiss ion, th e S CK clo ck fro m

the master shifts the data in the 16-bit register eight bit positions, and the

master and slave exchange data. Data written to the master SPIDR

from the master SPIDR is the input data from the slave.

Figure 18-10. Full-Duplex Operation

SHIFT REGISTER

SHIFT REGI ST ER

BAUD RAT E

GENERATOR

MASTER SPI SLAVE SPI

VDD

MOSI MOSI

MISO MISO

SCK SCK

SS SS

SPIDRSPIDR

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414 Serial Peripheral Interface Module (SPI) MO TOROLA

Serial Peripheral Interface Module (SPI)

18.8.1 Master Mod e

Setting the MSTR bit in SPICR1 puts the SPI in master mode. Only a

master SPI can initiate a transmission. Writing to the master SPIDR

begi ns a tra nsmission . If the sh i ft regi ster is em pty, the byte t ransf ers t o

the shift register and begins shifting out on the MOSI pin under the

control of the master SCK clock. The SCK clock starts one-half SCK

cycle after writing to SPIDR.

The SPR[2:0] and SPPR[6:4] bits in SPIBR control the baud rate

generator and determ in e the speed of the shift registe r. The SCK pin is

the SP I clock output. Through the SCK pin, the baud rate generator of

the master controls the shift register of the slave.

The MS TR bit in SPICR1 and the SPC0 bit in SPICR2 control the

function of the data pins, MOSI and MISO.

The SS pin is normally an input that remains in the inactive high state.

Setting the DDRSP3 bit in SPIDDR configures SS as an output. The

DDRSP3 bit and the SSOE bit in SPICR1 can configure SS for

general-purpose I/O, mode fault detection, or slave selection.

See Table 18-3.

The S S output g oes l ow dur ing each transmi ssion an d is hi gh when the

SPI is in the idle state. Driving the master SS input low sets the MODF

flag in SPISR, indicating a mode fault. More than one master may be

trying to drive the MOSI and SCK lines simultaneously. A mode fault

clears the data direction bits of the MISO, MOSI (or MOMI), and SCK

pin s to make them inputs. A mode faul t also clears the SPE and MSTR

bits in SPICR1. If the SPIE bit is also set, the MODF flag generates an

interrupt request.

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Serial Peripheral Interface Module (SPI)

Functional Description

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 A dv ance I nforma tion

MOTOROLA Serial Peripheral Interface Mo dule (SPI) 415

18.8.2 Slave Mode

Clear ing t he M ST R bit in S PICR1 puts t he S P I in sla ve mode. The SCK

pin is the SPI clock input from the master, and the SS pin is the

slave-select input. For a transmission to occur, the SS pin must be driven

low and remain low until the transmission is complete.

The MS TR bit and the SPC0 bit in SPICR2 control the function of the

data pi ns, MOSI and MISO. The SS input also con trol s the M ISO pin. If

SS is low, the MSB i n the shift reg ister shi fts ou t on the MISO pin. If S S

is high, the MISO pin is in a high impedance state, and the slave ignores

the SCK input.

NOTE: When using peripherals with full-duplex capability, do not simultaneously

enable two receivers that drive the same MISO output line.

As long as only one slave drives the master input line, it is possible for

several slaves to receive the same tr ansmission simultaneously.

If the CPHA bit in SPICR1 is clear, odd-numbered edges on the SCK

input latch the data on the MOSI pin. Even-numbered edges shift the

data int o th e LS B po sit ion o f the SPI shift registe r a nd sh ift the MSB ou t

to the MISO pin.

If the CPHA bit is set, even -numbere d edges on the SCK input l atch the

data on the MOSI pin. Odd-numbered e dges shif t the dat a into the LS B

position of the SPI shift register and shift the MSB out to the MISO pin.

The transmission is complete after the eighth shift. The received data

transfers to SPIDR, setting the SPIF flag in SPISR.

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416 Serial Peripheral Interface Module (SPI) MO TOROLA

Serial Peripheral Interface Module (SPI)

18.8.3 Transmission Formats

The CP HA and CPOL bi ts in SPICR 1 select one of fo ur combinatio ns of

serial clock phase and polarity. Clock phase and polarity must be

ide ntical for the master SPI devic e and the communi cating slave device.

18.8.3.1 Transfer Format When CPHA = 1

Some peripherals require the first SCK edge to occur before the slave

MSB becomes available at its MISO pin. When the CPHA bit is set, the

master SPI waits for a synchronization delay of one-half SCK clock

cycle. Then it issues the first SCK edge at the beginning of the

transmissi o n. The first ed ge cause s the sl ave to transm it its MS B to the

MISO pin of t he master. The second edge and the following

even-numbered edges latch the data. The third edge and the following

odd-numbered edges shift the latched slave data into the master shift

After the 16th and final SCK edge:

•Data that was in the master S PIDR registe r is in the sl ave SPIDR.

Data that was in the slave SPIDR register is in the master SPIDR.

•The S CK clock sto ps and the SPIF fl ag in SPISR is set, ind icating

that the transm i ssion is com plete. If the S P IE bit i n SP CR1 is set,

SPIF generates an interrupt request.

Figure 18-11 shows the timi ng of a transmi ssion with the CPHA bit set.

The SS pin of the master must be either high or configured as a

general-purpose output not affecting the SP I.

When CP HA = 1, the slave SS line can remain low between bytes. This

format is good for systems with a single master and a single slave driving

the MISO data line.

Writing to SPIDR while a transmission is in progress sets the WCOL flag

to indicate a write collision and inhibits the write. WCOL does not

generate an interrupt request; the SPIF interrupt request comes at the

end of the transfer that was in progress at the time of the error.

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Serial Peripheral Interface Module (SPI)

Functional Description

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MOTOROLA Serial Peripheral Interface Mo dule (SPI) 417

Figure 18-11. SPI Clock Format 1 (CP HA = 1)

18.8.3.2 Transfer Format When CPHA = 0

In som e p eri phe rals, the sl ave MSB is available a t it s MISO p i n a s soon

as the slave is selected. When the CPHA bit is clear, the master SPI

delays its first SCK edge for half a SCK cycle after the transmission

starts. The first edge and all following odd-numbered edges latch the

slave data. Even- numb ered SCK edges sh ift slave data i nt o the ma ster

shift register and shift master data out on the master MOSI pin.

BEGIN TRANSMISSION END TRANSMISSION

SCK (CPO L = 0)

SAMP LE IN PU T

CHANGE OUTPUT

SS PIN OUTPUT

SCK (CPO L = 1)

MSB FIRST (LSBF E = 0):

L S B FIRST (LSB FE = 1) : MSB

LSB LSB

MSB

BIT 5

BIT 2

BIT 6

BIT 1 BIT 4

BIT 3 BIT 3

BIT 4 BIT 2

BIT 5 BIT 1

BIT 6

CHANGE OUTPUT

SLAVE SS PI N

MOSI PIN

MISO PIN

MASTER ONLY

MOSI/MISO

IF NEXT TRANSFER BEGINS HERE

FOR tT, tL, t l

MINIMUM 1/2 SCK

tItL

tL = Minimum leading time before the first SCK edge

tT = Minimum trailing time after the last SCK edge

tI = Minimum idling time between transmissions (minimum SS high time)

tL, tT, and tI ar e guaranteed for master mo de and re quired for slave mode.

Legend:

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418 Serial Peripheral Interface Module (SPI) MO TOROLA

Serial Peripheral Interface Module (SPI)

After the 16th and final SCK edge:

•Data that was in the master SPIDR is in the slave SPIDR. Data

that wa s in the slave SPIDR is in the master SPIDR.

•The S CK clock sto ps and the SPIF fl ag in SPISR is set, ind icating

that the transm i ssion is com plete. If the S P IE bit i n SP CR1 is set,

SPIF generates an interrupt request.

Figure 18-12 shows the timing of a transmission with the CPHA bit clear.

The SS pin of the master must be either high or configured as a

general-purpose output not affecting the SP I.

When CPHA = 0, the slave SS pin must be negated and reasserted

between bytes.

Figure 18-12. SPI Clock Format 0 (CP HA = 0)

BEGIN TR AN SM I SSI ON END TR AN SM I SSI ON

SCK (CPOL = 0)

SAMP LE IN PU T

CHAN GE OU TPUT

SS PIN OUTPUT

SCK (CPOL = 1)

MSB FI RS T (LSBFE = 0):

LSB FIRST (LSBF E = 1): MSB

LSB LSB

MSB

Bit 5

Bit 2

Bit 6

Bit 1 Bit 4

Bit 3

Bit 4 Bit 2

Bit 5 Bit 1

Bit 6

CHAN GE OU TPUT

SLAVE SS PIN

MOSI PIN

MISO PIN

MASTER ONLY

MOSI/MISO

IF NEXT TRANSFER BEGINS HERE

FOR tT, tL, tl

MINIMUM 1/2 SCK

tItL

tL = Mi nimum leading tim e befor e the first SCK edge

tT = Minimum trailing time after the last SCK edge

tI = Minimum idling time between transmissions (m inimum SS high ti me)

tL, tT, an d tI are guarante ed for master mode and required for slave mode.

Legend:

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Serial Peripheral Interface Module (SPI)

Functional Description

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 A dv ance I nforma tion

MOTOROLA Serial Peripheral Interface Mo dule (SPI) 419

NOTE: Clock skew between the master and slave can cause data to be lost

when:

•CPHA = 0, and,

•The baud rate is the SPI clock divided by two, and

•The master SCK frequency is half the slave SPI clock frequency,

and

•Software writes to the slave SPIDR just before the synchronized

SS signal goes low.

The synchronized SS signal is synchronized to the SPI clock. Figure

18-13 shows an example with the synchronized SS signal almost a full

SPI clock cycle late. While the synchronized SS of the slave is high,

writing is allowed even though the SS pin is already low. The write can

change the MISO pin while the master is sampling the MISO line. The

fir st bit of t he tr ansfe r m ay n ot be stab le w hen the ma ster samp les it, so

the byte sent to the master may be corrupted.

Figure 18-13. Transmission Error Due to Master/Slave Clock Skew

SCK (CPOL = 0)

SAMP LE I

CHA NG E O

SS PIN (I)

SPI CLOCK

SS SYNCHRONIZE D

MISO PIN

SPIDR W RIT E

TO SPI CLOC K

MOSI/MISO

MOSI PIN

MISO PIN

SCK (CPOL = 1)

THIS CYCLE

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420 Serial Peripheral Interface Module (SPI) MO TOROLA

Serial Peripheral Interface Module (SPI)

Also, if the sl ave gener ates a lat e write, i ts stat e machin e may no t have

time to reset, causing it to incorrectly receive a byte from the ma ster.

This error is most likely when the SCK frequency is half the slave SPI

clock frequency. At other baud rates, the SCK skew is no more than one

SPI clock, and there is more time between the synchronized SS signal

and the first SCK edge. For example, with a SCK frequency one-fourth

the slave S PI clock frequency, t here are t wo SPI clocks b etween the fall

of SS and the SCK edge.

As lon g as another late SPIDR write do es no t occur , th e fo llo wing byt es

to and from the slave are correctly transmitted.

18.8.4 SPI Baud Rate Generation

The baud rate generator divides the SPI clock to produce the SPI baud

clock. The SPPR[6:4] and SPR[2:0] bits in SPIBR select the SPI clock

divisor:

SPI clock divisor = (SPPR + 1) × 2(SPR+1)

where:

SPPR = the val ue written to bi ts SPPR[6:4]

SPR = the value written to bits SPR[2:0]

The baud rate generator is active only when the SPI is in master mode

and transm itting. Oth erwise, the divide r is inactive to redu ce IDD current.

18.8.5 Slave-Select Output

The slave-select output feature automatically drives the SS pin low

during transmission to select external devices and drives it high during

idle to deselect external devices. When S S output is selected, the SS

output pin is connected to the SS input pin of the external device.

In master mode only, s etting the SSOE bit in SPICR1 and the DDRSP[3]

bit in SPIDDR configures the SS pin as a slave-select output.

Setting the SSOE bit disables the mode fault feature.

NOTE: Be careful when using the slave- select output feature in a multimaster

system. The mode fault feature is not available for detecting system

errors between masters.

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Serial Peripheral Interface Module (SPI)

Functional Description

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MOTOROLA Serial Peripheral Interface Mo dule (SPI) 421

18.8.6 Bidirectional Mode

Setting the SPC0 bit in SPICR1 selects bidirectional mode (see

Table 18-7). The SPI uses only one data pin for the interface with

external device(s). The MSTR bit determines which pin to use. In master

mode, the MOSI pin is the master out/master in pin, MOMI. In slave

mode, t he MISO pin is the slave out/slave i n pin, S ISO. The MI SO pin in

master mode and M OSI pin i n slave mo de are gen eral-purp ose I/O pi ns.

The dir ection of e ach da ta I/O pin d epend s on its dat a direct io n reg ister

bit. A pin configured as an output is the output from the shift register. A

pin configured as an input is the input to the shift register, and data

coming out of the shift register is discarded.

The SCK pin is an output in master mode and an input in slave mode.

The SS pin can be an input or an output in master mode, and it is always

an input in slave mode.

In bidirectional mode, a mode fault does not clear DDRSP0, the data

direction bit for the SISO pin.



Table 18-7. Normal Mode and Bidirectional Mode

SPE = 1 Master Mode, M S TR = 1 Slave Mo de, MSTR = 0

Normal Mo de

SPC0 = 0

SWOM enables open drain output.SWOM enab les open drain out put.

Bidir e ct ional Mode

SPC0 = 1

SWOM enables open drain output.

SPI port pin 0 is general-purpos e I/O. SWOM enab les open drain output.

SPI port pin 1 is general-p urpose I/O.

SPI

MOSI

MISO

DDRSP1

SERIAL OUT

SERIAL IN

SPI

MOSI

MISO

SERIAL IN

SERIAL OUT

DDRSP0

SPI

MOMI

SPI PORT

DDRSP1

SERIAL OUT

SERIAL IN PIN 0

SPI

SISO

DDRSP0

SERIAL IN

SERIAL OUT

SPI PORT

PIN 1

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422 Serial Peripheral Interface Module (SPI) MO TOROLA

Serial Peripheral Interface Module (SPI)

18.8.7 Error Conditions

The SPI has two error conditions:

•Write collision error

•Mode fault error

18.8.7.1 Write Collision Error

The WCOL flag in SPIS R indicat es that a ser ial tra nsfer was in pr ogress

when the MCU tried to write new data to SPIDR. Valid write times are

listed below (see Fi gu re 18-1 1 and Figure 18-12 for definitions of tT

and tI):

•In master mode, a valid write is within tI (when SS is high).

•In slave phase 0, a valid write within tI (when SS is high).

•In slave phase 1, a valid write is within tT or tI (after the last SCK

edge and before SS goes low), excluding the first two SPI clocks

after the last SCK edge (the beginning of tT is an illegal write).

A write during any other time causes a WCOL error. The write is disabled

to avoid writing over the data being transmitted. WCOL does not

genera te an interrupt request because the WCOL flag can be read upon

completion of the transmission that was in progress at the time of the

error.

18.8.7.2 Mode Fault Error

If the SS input of a master S PI goes low, it indicates a system error in

which more than one master may be trying to drive the MOSI and SCK

lines simultaneously. This cond ition is not permitted in normal operation;

it sets the MODF flag in SPISR. If the SPIE bit in SPI CR1 is also set,

MODF generates an in terrupt request.

Configuring the SS pin as a general-purpose output or a slave-select

output disables the mode fault function.

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Serial Peripheral Interface Module (SPI)

Functional Description

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 A dv ance I nforma tion

MOTOROLA Serial Peripheral Interface Mo dule (SPI) 423

A mode fault clears the SPE and MSTR bits and the DDRSP bits of the

SCK, MISO, and MOSI (or MOMI) pins. This forces those pins to be

high-impedance inputs to avoid any conflict with another output driver.

If the mo de fault error occurs in bidirectional mode, the DDRSP bit of the

SISO pin is not affected, since it is a general-purpose I/O pin.

18.8.8 Low-Power Mode Options

This subsection describes the low-power mode options.

18.8.8.1 Run Mode

Clearing the SPE bit in SPICR1 puts the SPI in a disabled, low-power

state. SPI registers are accessible, but SPI clocks are disabled.

18.8.8.2 Doze Mode

SPI operation in doze m ode depen ds on the stat e of th e SPISDOZ bi t in

SPICR2.

•If SPISDOZ is clear, the SPI operates normally in doze mode.

•If SPISDOZ is set, the SPI clock stops, and the SPI enters a

low-power state in doze mode.

–Any master tra nsmission in progress stops at doze mode entry

and resumes at doze mode exit.

–Any slave transmission in progress continues if a master

continues to drive the slave SCK pin. The slave stays

synchronized to the master SCK clock.

NOTE: Although the slave shift register can receive MOSI data, it cannot

transfer data to SPIDR or set the S PIF flag in doze or stop mode. If the

slave enters doze mode in an idle state and exits doze mode in an idle

state, SPIF remains clear and no transfer to SPIDR occurs.

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424 Serial Peripheral Interface Module (SPI) MO TOROLA

Serial Peripheral Interface Module (SPI)

18.8.8.3 Stop Mode

SPI operation in stop mode i s the same as in doze mode w ith the

SPISDOZ bit set.

18.9 Reset

Rese t initial izes the SPI re gisters t o a know n startu p state as descr ibed

in 18 .7 Memory Map and Regist er s . A transmi ssion from a slave after

reset an d befo re w ritin g to the SPID R re gister i s eit her i nd eter minate or

the byte last received from the master before the reset. Reading the

SPIDR after reset returns 0s.

18.10 Interrupts

18.10.1 Mode Fault (MODF) Flag

MODF is set when the SS pin of a master SPI is driven low and the SS

pin is confi gured as a mode- fault inp ut. If the SPIE bit is also set, MODF

generates an interrupt request. A mode fault clears the SPE, MSTR, and

DDRSP[2:0] bits. Cl ear MODF by reading SPISR with MODF set and

then writing to SPICR1. Reset clears MODF.

18.10.2 SPI Interrupt Flag (SPIF)

SPIF is set after the eighth SCK cycle in a transmission when received

data tr ansfers fr om the sh ift register to SPIDR. If the SPIE bit is also set,

SPIF generates an interrupt request. Once SPIF is set, no new data can

be transferred into SPIDR until SPIF is cleared. Clear SPIF by reading

SPISR with SPIF set and then accessing SPIDR. Reset clears SPIF.

Table 18-8. SPI Interrupt Request Sources

Interrupt Request Flag Enable Bit

Mode fault MODF SPIE

Tr ansm iss ion com plete SPIF

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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0  Advance Information
MOTOROLA Queued A nalog-to-Digital Converter (QADC)  425
Advance Info rmation — MMC2114, MMC2113, and MMC2112
Section 19. Queued Analog-to-Digital Converter (QADC)
1  Contents
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .428
4 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .429
5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .430
5.1 Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .430
5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431
6 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431
6.1 Port QA Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . .432
6.1.1 Port QA Analog Input Pins. . . . . . . . . . . . . . . . . . . . . . .432
6.1.2 Port QA Digital Input/Output Pins  . . . . . . . . . . . . . . . . .433
6.2 Port QB Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . .433
6.2.1 Port QB Analog Input Pins. . . . . . . . . . . . . . . . . . . . . . .433
6.2.2 Port QB Digital Input Pins  . . . . . . . . . . . . . . . . . . . . . . .433
6.3 External Trigger Input Pins. . . . . . . . . . . . . . . . . . . . . . . . .434
6.4 Multiplexed Address Output Pins. . . . . . . . . . . . . . . . . . . .434
6.5 Multiplexed A n alog Input Pins . . . . . . . . . . . . . . . . . . . . . .435
6.6 Voltage Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . .435
6.7 Dedicated Analog Supply Pins. . . . . . . . . . . . . . . . . . . . . .435
6.8 Dedicated Digital I/O Port Supply Pin . . . . . . . . . . . . . . . . .435
7 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .436
8 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .437
8.1 QADC Module Configuration Register (QADCMCR) . . . . .437
8.2 QADC Test Register (QADCTEST) . . . . . . . . . . . . . . . . . .438
8.3 Port Data Registers (P ORTQA and PORTQB)  . . . . . . . . .438
8.4 Port QA and QB Data Direction Register 
(DDRQA and DDRQB) . . . . . . . . . . . . . . . . . . . . . . . . .440
    
  
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Qu eued Analog-to-Digital Converter (QADC) MOTOROLA
Queued Analog-to-Digital Converter (QADC)
8.5 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .442
8.5.1 QADC Control Register 0 (QACR0). . . . . . . . . . . . . . . .442
8.5.2 QADC Control Register 1 (QACR1). . . . . . . . . . . . . . . .445
8.5.3 QADC Control Register 2 (QACR2). . . . . . . . . . . . . . . .448
8.6 Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .453
8.6.1 QADC Status Register 0 (QASR0). . . . . . . . . . . . . . . . .453
8.6.2 QADC Status Register 1 (QASR1). . . . . . . . . . . . . . . . .462
8.7 Conversion Command Word Table (CCW) . . . . . . . . . . . .463
8.8 Result Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .468
8.8.1 Right-Justified Unsigned Result Re gister (RJURR). . . .468
8.8.2 Left-Justified Signed Result Register (LJSRR) . . . . . . .469
8.8.3 Left-Justified Unsigned Result Register (LJURR) . . . . .470
9 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .470
9.1 Result Coherency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .470
9.2 External Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .471
9.2.1 External Mul tiplexing Operation. . . . . . . . . . . . . . . . . . .471
9.2.2 Module Version Options. . . . . . . . . . . . . . . . . . . . . . . . .473
9.3 Analog Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .474
9.3.1 Analog-to-Digital Converter Operation. . . . . . . . . . . . . .474
9.3.2 Conversion Cycle Times . . . . . . . . . . . . . . . . . . . . . . . .475
9.3.3 Channel De code and Multiplexer. . . . . . . . . . . . . . . . . .476
9.3.4 Sample Buffer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .476
9.3.5 Digital-to-Analog Converter (DAC) Array. . . . . . . . . . . .476
9.3.6 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .477
9.3.7 Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .477
9.3.8 Successive Approximation Register. . . . . . . . . . . . . . . .477
9.3.9 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .477
10 Digital Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .478
10.1 Queue Priority Timing Examples . . . . . . . . . . . . . . . . . . . .478
10.1.1 Queue Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .478
10.1.2 Queue Priority Schemes . . . . . . . . . . . . . . . . . . . . . . . .481
10.2 Boundary Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .492
10.3 Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .493
10.4 Disabled Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .494
10.5 Reserved Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .494
10.6 Single-Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .494
10.6.1 Software-Initiated Single-Scan Mode. . . . . . . . . . . . . . .495
    
  
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Queued A nalog -to-Digital Conv erter (QADC)
Introduction
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 A dv ance I nforma tion 
MOTOROLA Queued A nalog-to-Digital Converter (QADC)  427
19.10.6.2 Externally Triggered Single-Scan Mode. . . . . . . . . . . . .496
19.10.6.3 Externally Gated Single-Scan Mode . . . . . . . . . . . . . . .497
19.10.6.4 Interval Timer Single-Scan Mode. . . . . . . . . . . . . . . . . .497
19.10.7 Continuous-Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . .499
19.10.7.1 Software-Initiated Continuous-Scan Mode. . . . . . . . . . .500
19.10.7.2 Externally Triggered Continuous-Scan Mode  . . . . . . . .501
19.10.7.3 Externally Gated Continuous-Scan Mode . . . . . . . . . . .501
19.10.7.4 Periodic Timer Continuous-Scan Mode . . . . . . . . . . . . .502
19.10.8 QADC Clock (QCLK) Generation. . . . . . . . . . . . . . . . . . . .503
19.10.9 Periodic/Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . .504
19.10.10 Conversion Command Word Table . . . . . . . . . . . . . . . . . .505
19.10.11 Result Word Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .509
19.11 Pin Connection Considerations  . . . . . . . . . . . . . . . . . . . . . . .509
19.11.1 Analog Reference Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . .509
19.11.2 Analog Power Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .510
19.11.3 Conversion Timing Schemes . . . . . . . . . . . . . . . . . . . . . . .512
19.11.4 Analog Supply Filtering and Grounding . . . . . . . . . . . . . . .515
19.11.5 Accommodating Positive/Negative Stress Conditions . . . .517
19.11.6 Analog Input Considerations . . . . . . . . . . . . . . . . . . . . . . .519
19.11.7 Analog Input Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .521
19.11.7.1 Settling Time for the External Circuit . . . . . . . . . . . . . . .522
19.11.7.2 Error Resulting from Leakage . . . . . . . . . . . . . . . . . . . .523
19.12 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .524
19.12.1 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .524
19.12.2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .525
19.2  Introduction
The queued analog-to-digital converter (QADC) is a 10-bit, unipolar, 
successive approximation converter. Up to eight analog input channels 
can be supported using internal multiplexing. A maximum of 18 input 
channels can be supported in the expanded, externally multiple xed 
mode. 
The QADC consists of an analog front-end and a digital control 
subsystem, which includes an IPbus interface block.
    
  
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428 Qu eued Analog-to-Digital Converter (QADC) MOTOROLA

Queued Analog-to-Digital Converter (QADC)

The analog section includes input pins, an analog multiplexer, and

sample and hold analog circuits. The analog conversion is performed by

the digital-to-analog converter (DAC) resistor-capacitor (RC) array and

a high-g ain compara tor.

The digi ta l control sect io n contain s queue contro l log ic to sequen ce the

conversion process and interrupt generation logic. Also included are the

periodic/interval ti mer, control and status registers, the conversion

command word (CCW) table, random-access memory (RAM), and the

result table RAM.

The bus interface unit (BIU) pr ovides access to registers that configure

the QADC , control the analog-to-digital converter and queue

mechanism, and present formatted conversion results.

19.3 Features

Features of the QADC module include:

•Internal sample and hold

•Up to eight analog input channels using internal multiplexing

•Up to four external analog multiplexers directly supported

•Up to 18 total input channels with internal and external

multiplexing

•Programmable input sample time for various source impedances

•Two conversion command word (CCW) queues with a total of 64

entrie s for setting conversion parameters of each A/D conversion

•Subqueues possible usi ng pause mechanism

•Queue complete and pause interrupts available on both queues

•Queue pointers indicating current location for each queue

•Automated queue modes initiated by:

–External edge trigger and gated trigger

–Periodic/interval timer, within QADC module (queues 1 and 2)

–Software command

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Queued A nalog -to-Digital Conv erter (QADC)

Block Diagram

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MOTOROLA Queued A nalog-to-Digital Converter (QADC) 429

•Single scan or continuous scan of queues

•64 result register s

•Output data readable in three formats:

–Right-justified unsigned

–Left-justified signed

–Left-justified unsigned

•Unused analog channels can be used as discrete input/output

pins.

19.4 Blo ck Diag r am

Figure 19-1. QADC Block Diagram

DIGITAL

EXTERNAL

REFERENCE

ANALOG POWER

64-ENTRY QUEUE

CONTROL

OF 10-B IT

CONVERSION

COMMA ND WO RDS

IPBUS

INTERFACE

10-BIT

ANALOG-TO-DIGITAL

CONVERTER

ANAL OG IN PU T MUX

AND DIGITAL

PIN FUNCTIONS

64-ENTR Y TABLE

OF 10-B IT

10-BIT TO 16-BIT

RESULT ALIGNMENT

(18 WITH EXTERN AL MUXI N G)

MUX ADDRESS

TRIGGERS INPUTS

INPUTS

(CCWs) RESULTS

8 ANALOG CHANNELS

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430 Qu eued Analog-to-Digital Converter (QADC) MOTOROLA

Queued Analog-to-Digital Converter (QADC)

19.5 Modes of Operation

This subsection describes the two modes of operation in which the

QADC does not perform conversions in a regular fashion:

•Debug mode

•Stop mode

19.5.1 Debug Mode

The QDBG bit in the Module Configuration Register (QADCMCR)

governs behavior of the QADC when the CPU ente rs backgro und debug

mode. When QDBG is clear, the QADC operates normally and is

unaffected by CPU background debug mode. See 19.8.1 QADC Module

Configuration Register (QADCMCR).

When QDBG is set and the CPU enters background debug mode, the

QADC finishes any conversion in progress and then freezes. This is

QADC debug mode. Depending on when debug mode is entered, the

three possible queue freeze scenarios are:

•When a queue is not executing, the QADC freezes immediately.

•When a queue is executing, the QADC completes the current

conversion and then freezes.

•If during the execution of the current conversion, the queue

operating mode for the active queue is changed, or a queue 2

abort occurs, the QADC freezes immediately.

When the QADC enters debug mode while a queue is active, the current

CCW lo cation of the queue pointer is saved.

Debug mode:

•Stops the analog clock

•Holds the periodic/in terval timer in reset

•Prevents external tr igger events from being captured

•Keeps all QADC registers and RAM accessible

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Queued A nalog -to-Digital Conv erter (QADC)

Signals

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MOTOROLA Queued A nalog-to-Digital Converter (QADC) 431

Although the QADC saves a pointer to the next CCW in the current

queue, software can force the QADC to execute a different CCW by

reconfigu ring the QA DC. W hen the QAD C exits deb ug m ode, it looks a t

the queu e operating modes, th e current queue pointer, and any pen ding

trigger events to decide which CCW to execute.

19.5.2 Stop Mode

The QADC enters a low-power idle state whene ver the QSTOP bit is set

or the CPU enters low-power stop mode.

QADC stop:

•Disable s the analog-to- digital converter, effect ively turning off the

analog circuit

•Aborts the conversion sequence in progress

•Makes the Data Direction Register (DDRQA), Port Data Registers

(PORTQA and PORTQB), Control Registers (QACR2, QACR1,

and QACR0) and the Status Registers (QASR1 and QASR0)

read-only. Only the Module Configuration Register (QADCMCR)

remains writable.

•Makes the RAM inaccessible, so that valid data cannot be read

from RAM (result word table and CCW) or written to RAM (result

word table and CCW)

•Resets QACR1, QACR2, QASR0, and QASR1

•Holds the QADC periodic/interval timer in reset

Because the bias currents to the analog circuit are turned off in stop

mode, the QADC requires some recovery time (tSR) to stabilize the

analog circuits.

19.6 Signals

The Q ADC uses the external pins shown in Figure 19-2. There are eight

channel/port pins that can support up to 18 channels when external

multiplexing is used (including intern al channels). All of the channel pins

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432 Qu eued Analog-to-Digital Converter (QADC) MOTOROLA

Queued Analog-to-Digital Converter (QADC)

also have some general-purpose input or input/output functionality. In

addition, there are also two analog reference pins and two analog

submodule power pins.

The QADC has external trigger inputs and multiplexer outputs that are

shared w ith some of the analog input pins.

19.6.1 Port QA Pin Functions

The fou r port QA pins can be used as a nalog inp uts or as a bidire ctional

4-bit digital input/output port.

19.6.1.1 Port QA Analog Input Pins

When used as analog inputs, the four port QA pins are referred to as

AN[56:55, 53:52]. Due to the digital output drivers associated with

port QA, the analog characteristics of port QA may be different from

those of port QB.

Figu re 19-2. QADC Input and Output Signals

AN52/MA0/PQA0

AN53/MA1/PQA1

AN55/ETRIG1/PQA3

AN56/ETRIG2/PQA4

AN0/ANW/PQB0

AN1/ANX/PQB1

AN2/ANY/PQB2

AN3/ANZ/PQB3

DIGITAL

ANALOG

VSSI

ANALOG PO WER AND GROUN D

INTE RNAL DIGIT AL POWE R

PORT QB

CONVERTER RESULTS

AND

CONTROL

ANALOG

MUX AND

PORT QB ANALOG INPUT S

EXTERNAL MUX INP UTS

DIGITAL INP UTS

POR T QA AN ALOG INPUTS

EXTERNAL TRIGGER INPUTS

EXTERNAL MUX ADDRESS OUTPUTS

VDDI

VSSA

VDDA

VRH

VRL

ANALOG REFERENCES

SHARE D WITH O THE R MO DUL E S

DIGIT A L I/ O

PORT LOGIC

PORT QA

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Queued A nalog -to-Digital Conv erter (QADC)

Signals

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MOTOROLA Queued A nalog-to-Digital Converter (QADC) 433

19.6.1.2 Port QA Digital Input/Output Pins

Port QA pins are referred to as PQA[4:3, 1:0] when used as a

bid irectiona l 4-bit digita l input/ou tput po rt. Th ese four pins may be used

for general-purpose digital input signals or digital output signals.

Port QA pins are conne cted to a digital in put synchro nizer dur ing read s

and may be used as general-purpose digital inputs when the applied

voltages meet high-voltage input (VIH) and low-voltage input (V IL)

requirements.

Each port QA pin is configured as an input or output by programming the

Port Data Direction Register (DDRQA). The digital input signal states are

read from the port QA Data Register (PORTQA) when DDRQA specifies

that the pins are inputs. The digital data in PORTQA is driven onto the

port QA pins when the corresponding bits in DDRQA specify output.

See 19.8 .4 Port QA and QB Data Direction Register (DDRQA and

DDRQB).

19.6.2 Port QB Pin Functions

The four port QB pins can be used as analog inputs or as a 4-bit digital

input-only port.

19.6.2.1 Port QB Analog Input Pins

When used as analog inputs, the four port QB pins are referred to as

AN[3:0] . Because port QB functi ons as an alog and dig ital input only, t he

analog characteristics may be different from those of port QA.

19.6.2.2 Port QB Digital Input Pins

Port QB pins are referred to as PQB[3:0] when used as a 4-bit digital

inp ut/output po rt. In add ition to functioning as analog i nput pins, th e port

QB pins are also connected to the input of a synchronizer during reads

and may be used as general-purpose digital inputs when the applied

voltages meet VIH and VIL requirements.

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Queued Analog-to-Digital Converter (QADC)

Each port QB pin is configured as an input or output by programming the

Port Data Direction Register (DDRQB). The digital input signal states are

read from the port QB Data Register (PORTQB) when DDRQB specifies

that the pins are inputs. The digital data in PORTQB is driven onto the

port QB pins when the corresponding bits in DDRQB specify output.

See 19.8 .4 Port QA and QB Data Direction Register (DDRQA and

DDRQB).

19.6.3 External Trigger Input Pins

The QADC has two external trigger pins, ETRIG2 and ETRIG1. Each

external trigger input is associated with one of the scan queues, queue

1 or queu e 2. The assignme nt of E TRIG[2:1] to a qu eue is mad e by the

TRG bit in QADC Control Register 0 (QACR0). When TRG = 0, ETRIG1

triggers queue 1 and ETRIG2 triggers queue 2. When TRG = 1, ETRIG1

triggers queue 2 and ETRIG2 triggers queue 1. See 19.8.5 Control

Registers.

19.6.4 Multiplexed Address Output Pins

In non-mult iplexed mode , the QA DC a nalog input pins ar e connected to

an internal multiplexer which routes the analog signals into the internal

A/D converter.

In externally multi plexed mode, the QADC allows automatic channel

selection through up to four external 4-to-1 multiplexer chips. The QADC

provides a 2-bit multiplexed address output to the external multiplexer

chips to allow selection of one of four inputs. The multiplexed address

output signals, MA1 and MA0, can be used as multiplexed address

output b its or as general-purpose I/O when externa l multiplexed mode is

not being used.

MA[1:0] are used as the address inputs for up to four 4-channel

multiplexer chips. Because the MA[1:0] pins are digital outputs in

multiplexed mo de, the state of thei r corre spond ing data direction bits in

DDRQA is ignored.

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Queued A nalog -to-Digital Conv erter (QADC)

Signals

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MOTOROLA Queued A nalog-to-Digital Converter (QADC) 435

19.6.5 Multiplexed Analog Input Pins

In external multiplexed mode, four of the port QB pins are redefined to

each represent four analog input channels. See Table 19-1.

19.6.6 Voltage Reference P ins

VRH an d VRL are the d edicated input pins for the high an d low re ference

voltages. Separating the reference inputs from the power supply pins

allows for additional external filtering, which increases reference voltage

precision and stability, and subsequen tly contributes to a higher degree

of conversion accuracy.

NOTE: VRH and VRL must be set to VDDA and VSSA potential, respectively.

19.6.7 Dedicated Analog Supply Pins

The V DDA and VSSA pins sup ply power to the an alog su bsystem s of t he

QADC module. Dedicated power is required to isolate the sensitive

analog circuitry from the normal levels of noise present on the digital

power supply.

19.6.8 Dedicated Digital I/O Port Supply Pin

VDDH provides 5-V power to the digital I/O functions of QADC port QA

and port QB. This allows those pins to tolerate 5 volts when configured

as inputs and drive 5 volts when configured as outputs.

Table 19-1. Multiplexed Analog Input Channels

Multiplexed

Analog Input Channels

ANw Even numbered channels from 0 to 6

ANx Odd numbered channels from 1 to 7

ANy E ven numb ered channels from 16 to 22

ANz Odd numbered channels from 17 to 23

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Queued Analog-to-Digital Converter (QADC)

19.7 Memory Map

The QADC occupies 1 Kbyte, or 512 half-word (16-bit) en tries, of

address space. Ten half-word registers are control, port, and status

registers, 64 half-word entries are the CCW table, and 64 half-word

entries are the result table which occupies 192 half-word address

locations because the result data is readable in three data alignment

formats. Table 19-2 is the QADC memory map.

Table 19-2. QADC Memory Map

Address MSB LSB Access(1)

0x00ca_0000 QADC Module Configuration Register (QADCMCR) S

0x00ca_0002 QADC Test Register (Q ADCTES T)(2) S

0x00ca_0004 Reserved(3) —

0x00ca_0006 Port QA Data Register (PORTQA) Port QB Data Register (PORT QB) S/U

0x00ca_0008 Port QA Data Direction Register

(DDRQA) Port QB Data Direction Register

(DDRQB) S/U

0x00ca_000a QADC Cont rol Register 0 (QACR0) S/U

0x00ca_000 c QADC Control Register 1 (QACR1) S/U

0x00ca_000e QADC Cont rol Register 2 (QACR2) S/U

0x00ca_0010 QA DC Status R egister 0 (QASR 0) S/U

0x00ca_0012 QA DC Status R egister 1 (QASR 1) S/U

0x00ca_0014–

0x00ca_01fe Reserved(3) —

0x00ca_0200–

0x00ca_027e Convers ion Comma nd Word Table (CCW) S/U

0x00ca_0280–

0x00ca_02fe Ri ght Justified, Unsigned Result Register (RJURR) S/ U

0x00ca_0300–

0x00ca_037e Left Justified, Signed Result Register (LJSRR) S/U

0x00ca_0380–

0x00ca_03fe Left Justified, Unsigned Result Register (LJURR) S/U

1. S = CPU supervi sor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor

only addresses have no effect and result in a cycl e termination transfer error.

2. Access results in the modul e generating an access terminat ion transfer error if not in test mode.

3. Read/writes have no effect and the a ccess terminates with a tran sfer error except ion.

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Queued A nalog -to-Digital Conv erter (QADC)

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MOTOROLA Queued A nalog-to-Digital Converter (QADC) 437

19.8 Register Descriptions

This subsection describes the QADC registers.

19.8.1 QADC Module Configuration Register (QADCMCR)

QADCMCR contains bits that control QADC debug and stop modes and

determines the privilege level required to access most registers.

QSTOP — Stop Enable Bit

1 = Force QADC to idle state.

0 = QA DC operates normally.

QDBG — Debug Enable Bit

1 = Finish any conversion in progress, then freeze in debug mode

0 = QA DC operates normally.

SUPV — Supervisor/Unrestricted Data Space Bit

1 = All QADC registers are accessible in supervisor mode only;

user mode accesses have no effect and result in a cycle

termination error.

0 = Only QADCMCR and QADCTEST require supervisor mode

access; access to all other QADC registers is unrestricted

Address: 0x00ca_0000 and 0x00ca_0001

Bit 15 14 13 12 11 10 9 B it 8

Read: QSTOP QDBG 000000

Write:

Reset:00000000

Bit 7654321Bit 0

Read: SUPV 0000000

Write:

Reset:10000000

= Writes have no effect and the access terminates without a transfer error exception.

Figure 19-3. QADC Module Configuration Register (QADCMCR)

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Queued Analog-to-Digital Converter (QADC)

19.8.2 QADC Test Register (QADCTEST)

QADCTE ST is used only duri ng fa ctory testing of th e MC U. Attempts to

access this register outside of factory test mode will result in access

privilege violation.

19.8.3 Port Data Registers (PORTQA and PORT QB)

QADC ports QA and QB are accessed through two 8-bit port data

registers (PORTQA and PORTQB).

Port QA pins are referred to as PQA[4:3, 1:0] when used as a

bidirectional, 4-bit, input/output port. Port QA can also be used for

analog inputs (AN[56:55, 53:52]), external trigger inputs (ETRIG[2:1]),

and external multiplexer address outputs (MA[1:0]).

Port QB pins are referred to as PQB[3:0] when used as a 4-bit, digital

input-only port. Port QB can also be used for non-multiplexed (AN[3:0])

and multiplexed (ANz, ANy, ANx, ANw) analog inputs.

PORTQA and PORTQB are not initialized by reset.

Address: 0x00ca_0002 and 0x00ca_0003

Bit 15 14 13 12 11 10 9 B it 8

Read: Access results in the module generating an access termination transfer error if not in test mode.

Write:

Bit 7654321Bit 0

Read: Access results in the module generating an access termination transfer error if not in test mode.

Write:

Figure 19-4. QADC Test Register (QADCTEST)

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MOTOROLA Queued A nalog-to-Digital Converter (QADC) 439

Read: Anytime

Write: Anytime except during stop mode

Address: 0x00ca_0006

Bit 7654321Bit 0

Read: 0 0 0 PQA4 PQA3 0PQA1 PQA0

Write:

Reset: 0 0 0 P P 0 P P

= Writes have no effect and the access terminates without a transfer error exception.

P = Current pin state if DDR is input; otherwise, undefined

Analog Channel:

Muxed Address Outputs:

External Trigger Inputs:

AN56

ETRIG2

AN55

ETRIG1

AN53

MA1 AN52

MA0

Figure 19-5. QADC Port QA Data Register (PORTQA)

Address: 0x00ca_0007

Bit 7654321Bit 0

Read: 0 0 0 0 PQB3 PQB2 PQB1 PQB0

Write:

Reset:0000PPPP

= Writes have no effect and the access terminates without a transfer error exception.

P = Current pin state if DDR is input; otherwise, undefined

Analog Channel:

Muxed Analog Input s: AN3

AN2 AN2

ANy AN1

ANx AN0

ANw

Figure 19-6. QADC Port QB Data Register (PORTQB)

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Queued Analog-to-Digital Converter (QADC)

19.8.4 Port QA and QB Data Direction Register (DDRQA and DDRQB)

The Port QA and QB Data Direction Register (DDRQA and DDRQB) are

associated with port QA and QB digital I/O pins. Setting a bit in these

registers configures the corresponding pin as an output. Clearing a bit in

these registers configures the corresponding pin as an input. During

QADC initialization, port QA and QB pins that will be used as direct or

multiplexed analog inputs must have their corresponding data direction

an outpu t i s selected for a nal og co nversio n, the vo ltage sa mpl ed is that

of the output digital driver as influenced by the load.

When the MUX (externally multiplexed) bit is set in QACR0, the data

direction register settings are ignored for the bits corresponding to

PQA[1:0], the two multiplexed address (MA[1:0]) output pins. The

MA[1:0] pins are forced to be digital outputs, regardless of their data

direction setting, and the multiplexed address outputs are driven. The

data re turn ed during a port data r egister rea d is the val ue of the M A[1 :0]

pins, regardless of their data direction setting.

Similarly, when the external trigger pins are assigned to port pins and

external trigger queue operating mode is selected, the data direction

setting for the corresponding pins, PQA3 and/or PQA4, is ignored. The

port pins are fo rced to be d i gital i np uts fo r ETRIG1 and/or E TRIG2. Th e

data retu rned during a port da ta register rea d is the value of ETRIG[2:1]

pins, regardless of their data direction setting.

NOTE: Use caution when mixing digital and analog inputs. They shou ld be

isolated as much as possible. Rise and fall times should be as large as

possible to minimize ac coupling effects.

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Queued A nalog -to-Digital Conv erter (QADC)

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MOTOROLA Queued A nalog-to-Digital Converter (QADC) 441

Read: Anytime

Write: Anytime except during stop mode

Address: 0x00ca_0008 and 0x00ca_0009

Bit 15 14 13 12 11 10 9 B it 8

Read: 0 0 0 DDQA4 DDQA3 0DDQA1 DDQA0

Write:

Reset:00000000

Bit 7654321Bit 0

Read: 0 0 0 0 DDQB3 DDQB2 DDQB1 DDQB0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfer error exception.

Figure 19-7. QADC Port QA Data Direction Register (DDR QA)

and Port QB Data Direction Register (DDRQB)

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Queued Analog-to-Digital Converter (QADC)

19.8.5 Control Registers

This subsection describes the QADC control registers.

19.8.5.1 QADC Control Register 0 (QACR0)

QADC Control Register 0 (QACR0) establishes the QADC sampling

clock (QCLK) with prescaler parameter fields and defines whether

external multiplexing is enabled. Typically, these bits are written once

when the QADC is initialized and not changed thereafter.

Read: Anytime

Write: Anytime except during stop mode

MUX — Externally Multiplexed Mode Bit

The MUX bit configures the QADC for operation in externally

multiplexed mode, which affects the interpretation of the channel

numbers and forces the MA[1:0] pins to be outputs.

1 = Externally multiplexed, up to 18 possible channels

0 = Internally multiplexed, up to 8 possible channels

Address: 0x00ca_000a and 0x00ca_000b

Bit 15 14 13 12 11 10 9 B it 8

Read: MUX 00

TRG 0000

Write:

Reset:00000000

Bit 7654321Bit 0

Read: 0 QPR6 QPR5 QPR4 QPR3 QPR2 QPR1 QPR0

Write:

Reset:00010011

= Writes have no effect and the access terminates without a transfer error exception.

Figure 19 -8. QADC Control Register 0 (QACR0)

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MOTOROLA Queued A nalog-to-Digital Converter (QADC) 443

TRG — Trigger Assignment Bit

The TRG bit determines the queue assignment of the ETRIG[2:1]

pins.

1 = ETRIG1 triggers queue 2; ETRIG2 triggers queue 1.

0 = ETRIG1 triggers queue 1; ETRIG2 triggers queue 2.

QPR[6:0] — Prescaler Clock Divider Bits

The read/write QPR[6:0] bits select the system clock divisor to

genera te the QADC cl ock as Table 19-3 shows. The resulting QADC

clock rate can be given as:

where:

1 <= QPR[6:0] <= 127.

If QPR[6:0] = 0, then the QPR register field value is read as a 1 and

the prescaler divisor is 2.

The prescaler should be selected so that the QADC clock rate is

within the required fQCLK range. See Table 23-8. QADC

Conversion Specifications (Operating ) .

fQCLK = fSYS

QPR[6: 0] + 1

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Queued Analog-to-Digital Converter (QADC)

Table 19-3. Prescaler fSYS Divide-by Values

QPR[6:0] fSYS

Divisor QPR[6:0] fSYS

Divisor

0000000 2 0100000 33 1000000 65 1100000 97

0000001 2 0100001 34 1000001 66 1100001 98

0000010 3 0100010 35 1000010 67 1100010 99

0000011 4 0100011 36 1000011 68 1100011 100

0000100 5 0100100 37 1000100 69 1100100 101

0000101 6 0100101 38 1000101 70 1100101 102

0000110 7 0100110 39 1000110 71 1100110 103

0000111 8 0100111 40 1000111 72 1100111 104

0001000 9 0101000 41 1001000 73 1101000 105

0001001 10 0101001 42 1001001 74 1101001 106

0001010 11 0101010 43 1001010 75 1101010 107

0001011 12 0101011 44 1001011 76 1101011 108

0001100 13 0101100 45 1001100 77 1101100 109

0001101 14 0101101 46 1001101 78 1101101 110

0001110 15 0101110 47 1001110 79 1101110 111

0001111 16 0101111 48 1001111 80 1101111 112

0010000 17 0110000 49 1010000 81 1110000 113

0010001 18 0110001 50 1010001 82 1110001 114

0010010 19 0110010 51 1010010 83 1110010 115

0010011 20 0110011 52 1010011 84 1110011 116

0010100 21 0110100 53 1010100 85 1110100 117

0010101 22 0110101 54 1010101 86 1110101 118

0010110 23 0110110 55 1010110 87 1110110 119

0010111 24 0110111 56 1010111 88 1110111 120

0011000 25 0111000 57 1011000 89 1111000 121

0011001 26 0111001 58 1011001 90 1111001 122

0011010 27 0111010 59 1011010 91 1111010 123

0011011 28 0111011 60 1011011 92 1111011 124

0011100 29 0111100 61 1011100 93 1111100 125

0011101 30 0111101 62 1011101 94 1111101 126

0011110 31 0111110 63 1011110 95 1111110 127

0011111 32 0111111 64 1011111 96 1111111 128

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Queued A nalog -to-Digital Conv erter (QADC)

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MOTOROLA Queued A nalog-to-Digital Converter (QADC) 445

19.8.5.2 QADC Control Register 1 (QACR1)

QADC Control Register 1 (QACR1) is the mode control register for

queue 1. This register governs queue operating mode and the use of

completion and/or pause interrupts. Typically, these bits are written once

when the QADC is initialized and not changed thereafter.

Stop mode resets this register ($0000).

Read: Anytime

Write: Anytime except during stop mode

CIE1 — Queue 1 Completion Interrupt Enable Bit

CIE1 enables an interrupt request upon completion of queue 1. The

interrupt request is initiated when the conversion is complete for the

last CCW in queue 1.

1 = Enable queue 1 completion interrupt.

0 = Disable queue 1 completion interr upt.

Address: 0x00ca_000c and 0x00ca_000d

Bit 15 14 13 12 11 10 9 B it 8

Read: CIE1 PIE1 0MQ112 MQ111 MQ110 MQ19 MQ18

Write: SSE1

Reset:00000000

Bit 7654321Bit 0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfer error exception.

Figure 19-9. QADC Control Register 1 (QACR1)

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PIE1 — Queue 1 Pause Interrupt Enable Bit

PIE1 enables an interrupt request when queue 1 enters the pause

state. The interrupt request is initiated when conversion is complete

for a CCW that has the pause bit set.

1 = Enable the queue 1 pause interrupt.

0 = Disable the queue 1 pause interrupt.

SSE1 — Queue 1 Single-Scan Enable Bit

SSE1 enables a single-scan of queue 1 after a trigger event occurs.

SSE1 m a y be set during the same write cycle that sets the MQ1 bits

for one of the single-scan queue operating modes. The single-scan

enable bit can be written to 1 or 0, but is always read as a 0, unless

the QADC is in test mode. The QADC clears SSE1 when the

single-scan is complete.

1 = Allow a trigger event to start queue 1 in a single-scan mode.

0 = Trigger events are ignored for queue 1 single-scan modes.

MQ1[12:8] — Queue 1 Operating Mode Field

The MQ1 field selects the operating mode for queue 1.

Table 19-4 shows the bits in the MQ1 field which enable different

queue 1 operating modes.

Table 19-4. Queue 1 Operat ing Modes

MQ1[12:8] Opera ting Mode

00000 Disa bled mode, conversions do not occur

00001 Software-triggered single-scan mod e (started wit h SSE1)

00010 External-trigger rising-edge single-scan mode

00011 External-trigger falling-edge single-scan mode

00100 Interval timer single-scan mode: time = QCLK period × 27

00101 Interval timer single-scan mode: time = QCLK period × 28

00110 Interval timer single-scan mode: time = QCLK period × 29

00111 Interval timer single-scan mode: time = QCLK period × 210

01000 Interval timer single-scan mode: time = QCLK period × 211

01001 Interval timer single-scan mode: time = QCLK period × 212

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01010 Interval timer single-scan mode: time = QCLK period × 213

01011 Interval timer single-scan mode: time = QCLK period × 214

01100 Interval timer single-scan mode: time = QCLK period × 215

01101 Interval timer single-scan mode: time = QCLK period × 216

01110 Interval timer single-scan mode: time = QCLK period × 217

01111 Externally gated single-scan mode (started with SSE1)

10000 Reserved m ode

10001 Software-triggered continuous-scan mode

10010 Exte rnal-trigger rising-edge continuou s-scan mo de

10011 External-trigger falling-edge continuous-scan mode

10100 Periodic timer continuous-scan mode: time = QCLK period × 27

10101 Periodic timer continuous-scan mode: time = QCLK period × 28

10110 Periodic timer continuous-scan mode: time = QCLK period × 29

10111 Periodic timer continuous-scan mode: time = QCLK period × 210

11000 Periodic timer continuous-scan mode: time = QCLK period × 211

11001 Periodic timer continuous-scan mode: time = QCLK period × 212

11010 Periodic timer continuous-scan mode: time = QCLK period × 213

11011 Periodic timer continuous-scan mode: time = QCLK period × 214

11100 Periodic timer continuous-scan mode: time = QCLK period × 215

11101 Periodic timer continuous-scan mode: time = QCLK period × 216

11110 Periodic timer continuous-scan mode: time = QCLK period × 217

11111 Externally gated continuous-scan mode

Table 19-4. Queue 1 Oper ating Modes (Continued)

MQ1[12:8] Opera ting Mode

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Queued Analog-to-Digital Converter (QADC)

19.8.5.3 QADC Control Register 2 (QACR2)

QADC Control Register 2 (QACR2) is the mode control register for

queue 2. This register governs queue operating mode and the use of

completion and/or pause interrupts. Typically, these bits are written once

when the QADC is initialized an d not changed thereafter.

Stop mode resets this register ($007f).

Read: Anytime

Write: Anytime except during stop mode

CIE2 — Queue 2 Completion Software Interrupt Enable Bit

CIE2 enables an interrupt request upon completion of queue 2. The

interrupt request is initiated when the conversion is complete for the

last CCW in queue 2.

1 = Enable queue 2 completion interrupts.

0 = Disable queue 2 completion interr upts.

Address: 0x00ca_000e and 0x00ca_000f

Bit 15 14 13 12 11 10 9 B it 8

Read: CIE2 PIE2 0MQ212 MQ211 MQ210 MQ29 MQ28

Write: SSE2

Reset:00000000

Bit 7654321Bit 0

Read: RESUME BQ26 BQ25 BQ24 BQ23 BQ22 BQ21 BQ20

Write:

Reset:01111111

Figure 19-10. QADC Control Register 2 (QACR2)

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PIE2 — Queue 2 Pause Software Interrupt Enable Bit

PIE2 enables an interrupt request when queue 2 enters the pause

state. The interrupt request is initiated when conversion is complete

for a CCW that has the pause bit set.

1 = Enable the queue 2 pause interrupt.

0 = Disable the queue 2 pause interrupt.

SSE2 — Queue 2 Single-Scan Enable Bit

SSE2 enables a single-scan of queue 2 after a trigger event occurs.

SSE2 m a y be set during the same write cycle that sets the MQ2 bits

for one of the single-scan queue operating modes. The single-scan

enable bit can be written to 1 or 0, but is always read as a 0, unless

the QADC is in test mode. The QADC clears SSE2 when the

single-scan is complete.

1 = Allow a trigger event to start queue 2 in a single-scan mode.

0 = Trigger events are ignored for queue 2 single-scan modes.

MQ2[12:8] — Queue 2 Operating Mode Field

The MQ2 field selects the operating mode for queue 2.

Table 19-5 shows the bits in the MQ2 field which enable different

queue 2 operating modes.

Table 19-5. Queue 2 Operat ing Modes

MQ2[12:8] Operating Modes

00000 Disabled mode, conversions do not occur

00001 Software triggered single-scan mode (started with SSE2)

00010 Externally triggered rising edge single-scan mode

000 11 Ext ernally tri ggered falling edge sin gle-s can mode

00100 I nt erval timer single-scan mode: time = QCLK period x 27

00101 I nt erval timer single-scan mode: time = QCLK period x 28

00110 Interval timer single-scan mode: time = QCLK period x 29

00111 I nterv al timer single-scan mode: time = QCLK period x 210

01000 I nt erval timer single-scan mode: time = QCLK period x 211

01001 I nt erval timer single-scan mode: time = QCLK period x 212

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01010 I nt erval timer single-scan mode: time = QCLK period x 213

01011 Interv al timer single-scan mode: time = QCLK period x 214

01100 Interval timer single-scan mode: time = QCLK period x 215

01101 Interval timer single-scan mode: time = QCLK period x 216

01110 I nterv al timer single-scan mode: time = QCLK period x 217

01111 Reserved mode

10000 Reserved mode

10001 Software triggered continuous-scan mode

10010 Externally tri ggered rising edge continuous-scan m ode

10011 Externally triggered falling edge continuous-scan mode

10100 P eri odic timer continuous -scan mode : time = QCLK period x 27

10101 P eri odic timer continuous -scan mode : time = QCLK period x 28

10110 Peri odic timer continuous-sc an mode : time = QCLK period x 29

10111 P eri odic timer continuous-s can mode : time = QCLK period x 210

11000 Peri odic timer continuous-sc an mode : time = QCLK period x 211

11001 Peri odic timer continuous-sc an mode : time = QCLK period x 212

11010 Peri odic timer continuous-sc an mode : time = QCLK period x 213

11011 Peri odic timer continuous -sc an mode : time = QCLK period x 214

11100 Peri odic timer continuous -sc an mode : time = QCLK period x 215

11101 Peri odic timer continuous -sc an mode : time = QCLK period x 216

11110 Peri odic timer continuous -scan mode : time = QCLK period x 217

11111 Reserved mode

Table 19-5. Queue 2 Operating Modes (Continued)

MQ2[12:8] Operating Modes

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RESUME — Queue 2 Resume Bit

RESUM E selects the resumptio n point for queu e 2 after its operation

is susp ende d due to a qu eue 1 tri gg er eve nt. If RE SUME is changed

during the execution of queue 2, the change is not recognized until a n

end-of-queue condi tio n is reached or the ope rati ng mode of queue 2

is changed.

The primary reason for selecting re-execution of the entire queue or

subqueu e i s to guar ante e tha t all sam pl es are t aken co nsecuti ve ly i n

one scan (coherency).

When subqueues are not used, queue 2 execution restarts after

suspension with the first CCW in queue 2. When a pause has

previously occurred in queue 2 execution, queue execution restarts

after suspensio n with the first CCW in the current subqueue.

A subqueue is considered to be a stand-alone sequence of

conversions. Once a pause flag has been set to report subqueue

completion, that subqueue is not repeated until all CCWs in queue 2

are executed.

An example of using the RESUME bit is when the frequency of

queue 1 trigger events prohibit queue 2 completion. If the rate of

queue 1 execution is too high, it is best for queue 2 execution to

conti nue with the C CW that w as being con verted when queue 2 was

suspended. This allows queue 2 to eventually complete execution.

1 = After suspension, begin execution with the aborted CCW in

queue 2.

0 = After suspension, begin execution with the first CCW of

queue 2 or the current subqueue of queue 2.

BQ2[6:0] — Beginning of Queue 2 Field

BQ2[6:0] denotes the CCW location where queue 2 begins. This

allows the len gth of queu e 1 an d qu eue 2 to var y. Th e B Q2 fiel d also

serves as an end-of-queue condition for queue 1.

The beg inning o f queue 2 is defined by program ming the BQ 2 field in

QACR2. BQ2 is usually set before or at the same time as the queue

operat ing mode for queue 2 is selecte d. If BQ2[6:0] ≥ 64, queue 2 has

no entries, the ent ire CCW table is dedicated to qu eue 1, and CCW63

is the end-of-queue 1. If BQ2[6:0] is 0, the entire CCW table is

dedicated to queu e 2. A special case occurs when an operating mode

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452 Qu eued Analog-to-Digital Converter (QADC) MOTOROLA

Queued Analog-to-Digital Converter (QADC)

is selected for queue 1 and a trigger event occurs for queue 1 with

BQ2 set to 0. Queue 1 execution starts momentarily, but is terminated

after CCW0 is read. No conversions occur.

The BQ2[6:0] pointer may be changed dynamically to alternate

between queue 2 scan sequences. A change in BQ2 after queue 2

has begun or when queue 2 has a trigger pending does not affect

queue 2 until it is started again. For example, two scan sequences

could be defined as follows: The first sequence starts at CCW10, with

a pause after CCW11 and an end of queue (EOQ) programmed in

CCW15; the second sequence starts at CCW16, with a pause after

CCW17 and an EOQ programmed in CCW39.

With BQ2[6:0] set to CCW10 and the continuous-scan mode

selected, queue execution begins. When the pause is encountered in

CCW11, an interrupt service routine can retarget BQ2[6:0] to CCW16.

When the end-of-queue is recognized in CCW15, an internal retrigger

event is generated and execution restarts at CCW16. When the

pause softw ar e interru pt occurs again , BQ2 can be changed b ack to

CCW10. Af ter the end-o f-qu eue is recogni zed in CCW39, an internal

retrigger event is created and execution now restarts at CCW10.

If BQ2[6 :0] is changed while que ue 1 is acti ve, th e effect o f BQ2[6:0]

as an end-of-queue indication for queue 1 is immediate. However,

beware of the risk of losing the end-of-queue 1 when changing

BQ2[6:0]. Using EOQ (channel 63) to end queue 1 is recommended.

NOTE: If BQ2[6:0] was assigned to the CCW that queue 1 is currently working

on, then that conversi on is completed before the change to BQ2[6:0]

takes effect.

Each time a C CW is read for queu e 1, the C CW locat ion i s compar ed

with the current value of the BQ2[6:0] pointer to detect a possible

end-of-queue condition. For example, if BQ2[6:0] is changed to

CCW3 while queue 1 is converting CCW2, queue 1 is terminated after

the conversion is completed. However, if BQ2[6:0] is changed to

CCW1 wh ile queue 1 is converting CCW2, the QADC would not

recognize a BQ2[6:0] end-of-queue condition until queue 1 execution

reached CCW1 again, presumably on the next pass through the

queue.

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19.8.6 Status Registers

This subsection describes the QADC status registers.

19.8.6.1 QADC Status Register 0 (QASR0)

QADC Status Register 0 (QASR0) contains information about the state

of each queue and the current A/D conversion.

Stop mode resets this register ($0000).

Read: Anytime

Write:

For f la g bits (C F1, PF1, C F 2, PF2 , TOR1, TO R2): W r itin g a 1 has no

effect, wr ite a 0 to clear.

For QS[9:6] and CWP: Writes have no effect.

CF1 — Queue 1 Completion Flag

CF1 indicates that a queue 1 scan has been completed. CF1 is set by

the QADC when the input channel sample requested by the last CCW

in queue 1 is converted, and the result is stored in the result table.

Address: 0x00ca_0010 and 0x00ca_0011

Bit 15 14 13 12 11 10 9 B it 8

Read: CF1 PF1 CF2 PF2 TOR1 TOR2 QS9 QS8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: QS7 QS6 CWP5 CWP4 CWP3 CWP2 CWP1 CWP0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfer error exception.

Figure 1 9-11. QADC Status Regist er 0 (QASR0)

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454 Qu eued Analog-to-Digital Converter (QADC) MOTOROLA

Queued Analog-to-Digital Converter (QADC)

The end-of-queue 1 is identified when execution is complete on the

CCW i n th e loca tion pri or t o th at pointed to by B Q2, when the current

CCW co ntai ns the end- of- queue cod e ( chann el 63 ) i n stead of a va lid

channel num ber, or when the cur rently com pleted CCW is in the last

location of the CCW RAM.

When CF1 is set and queue 1 completion interrupts are enabled

(CIE1 = 1), the QADC requests an interrupt. The interrupt request is

cleared when a 0 is written to the CF1 bit after it has been read as a

1. Once se t, CF1 can b e clear ed o nly by a rese t or by w riting a 0 to it.

CF1 is updated by the QADC regardless of whether the

corresponding interrupt is enabled. This allows polled recognition of

queue 1 scan completion.

PF1 — Queue 1 Pause Flag

PF1 indicates that a queue 1 scan has reached a pause. PF1 is set

by the QADC when the current queue 1 CCW has the pause bit set,

the selected input channel has been converted, and the result has

been stored in the result table.

Once PF1 is set, the queue enters the paused state and waits for a

trigger event to allow queue execution to continue. However, a

special case occurs when the CCW with the pause bit set is the last

CCW in a queue; queue execution is complete. The queue status

becomes idle, not paused, and both the pause and completion fl ags

are set.

Another special case occurs when queue 1 is operating in

software-initiated single-scan or continuous-scan mode and a CCW

pause bit is set. The QADC will set PF1 and will also automatically

generate a retrigger event that restarts execution after two QCLK

cycles. Pause mode is never entered.

When PF1 is set and interrupts are enabled (PIE1 = 1), the QADC

requests an interrupt. The interrupt request is cleared when a 0 is

written to PF1, after it has been read as a 1. Once set, PF1 can be

cleared only by reset or by writing a 0 to it.

In externally gated single-scan and continuous-scan mode, the

behavior of PF1 has been redefined. When the gate closes before the

end-of-queue 1 is reached, PF1 is set to indicate that an incomplete

scan has occurred. In single-scan mode, a resultant interrupt can be

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MOTOROLA Queued A nalog-to-Digital Converter (QADC) 455

used to determine if queue 1 should be enabled again. In either

externally gated mode, setting PF1 indicates that the results for

queue 1 have not been collected during one scan (coherently).

NOTE: If a set CCW pause bit is encountered in either externally gated mode,

the pause flag will not set, and execution continues without pausing. This

has allowed for the modified behavior of PF1 in the externally gated

modes.

PF1 is maintained by the QADC regardless of whether the

corresponding interrupt is enabled. PF1 may be polled to determine if

the QADC has reached a pause in scanning a queue.

1 = Queue 1 has reached a pause or gate closed before

end-of-queue in gated mode.

0 = Queue 1 has not reached a pause or gate has not closed before

end-of-queue in gated mode.

See Table 19-6 for a summary of CCW pause bit response in all scan

modes.

CF2 — Queue 2 Completion Flag

CF2 indicates that a queue 2 scan has been completed. CF2 is set by

the QADC when the input channel sample requested by the last CCW

in queue 2 is converted, and the result is stored in the result table.

The end-of-queue 2 is identified when the current CCW contains

an end-of-queue code (channel 63) instead of a valid channel number

Table 19-6. CCW Pause Bit Response

Scan Mode Qu eue Opera tion PF Asser ts?

Exte rnally triggered single-scan Pau ses Yes

Exte rnally triggered continuous-s can P au se s Yes

Interval timer tri gger single-scan Pauses Yes

Interval timer continuous-scan Pauses Yes

Softwa re-initiated single-scan Continues Yes

Softwa re-initiated continuous-s can Con tinues Yes

Extern ally gated single-scan Continues No

Extern ally gated continuous-s can Continues No

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Queued Analog-to-Digital Converter (QADC)

or when the currently completed CCW is in the last location of the

CCW RAM.

When CF2 is set and queue 2 completion interrupts are enabled

(CIE2 = 1), the QADC requests an interrupt. The interrupt request is

cleared when a 0 is written to the CF2 bit after it has been read as a

1. Once set, CF2 can b e clear ed o nly by a rese t or by writing a 0 to it.

CF2 is updated by the QADC regardless of whether the

corresponding interrupt is enabled. This allows polled recognition of

queue 2 scan completion.

PF2 — Queue 2 Pause Flag

PF2 indicates that a queue 2 scan has reached a pause. PF2 is set

by the QADC when the current queue 2 CCW has the pause bit set,

the selected input channel has been converted, and the result has

been stored in the result table.

Once PF2 is set, the queue enters the paused state and waits for a

trigger event to allow queue execution to continue. However, a

special case occurs when the CCW with the pause bit set is the last

CCW in a queue: Queue execution is complete. The queue status

becomes idle, not paused, and both the pause and completion fl ags

are set.

Another special case occurs when queue 2 is operating in

software-initiated single-scan or continuous-scan mode and a CCW

pause bit is set. The QADC will set PF2 and will also automatically

generate a retrigger event that restarts execution after two QCLK

cycles. Pause mode is never entered.

When PF2 is set and interrupts are enabled (PIE2 = 1), the QADC

requests an interrupt. The interrupt request is cleared when a 0 is

written to PF2, after it has been read as a 1. Once set, PF2 can be

cleared only by a reset or by writing a 0 to it.

PF2 is maintained by the QADC regardless of whether the

corresponding interrupt is enabled. PF2 may be polled to determine if

the QADC has reached a pause in scanning a queue.

1 = Queue 2 has reached a pause.

0 = Queue 2 has not reached a pause.

See Table 19-6 for a summary of pause response in all scan modes.

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TOR1 — Queue 1 Trigger Overrun Flag

TOR1 indicates that an unexpected trigger event has occurred for

queue 1. TOR1 can be set only while queue 1 is in the active state.

A tr igger event gener ated by a tr ansition on the exte rnal trigger pin o r

by the periodic/interval timer may be captured as a trigger overrun.

TOR1 cann ot be set whe n the software- initiated sin gle-scan mod e or

the software-initiated continuous-scan mode is selected.

TOR1 is set when a trigger event is received while a queue is

executing and before the scan has completed or paused. TOR1 has

no effect on queue execution.

After a trigger event has occurred for queue 1, and before the scan

has completed or paused, additional queue 1 trigger events are not

retained. Such trigger events are considered unexpected, and the

QADC sets the TOR1 error status bit. An unexpected trigger event

may denote a system over run situation.

In exte rnally gated con tinuous-scan mod e, the b ehavior of TOR1 ha s

been redefined. In the case when queu e 1 reaches an end -of- queue

condi tion for the secon d ti me du ring an open ga te, TO R 1 is s e t. This

is conside red an overru n condition . In this case CF1 has be en set for

the fi rst end-of- queue 1 condition and then TOR1 set s for the second

end-of-queue 1 condi tion . For TO R1 to se t, CF2 must not be clear ed

before the second end-of-queue 1.

Once set, TOR1 is cleared only by a reset or by writing a 0 to it.

1 = At least on e unexpected queue 1 t rigger even t has occurr ed or

queue 1 reaches an end-of-queue condition for the second

time in externally gated continuous scan.

0 = No unexpected queue 1 trigger events have occurred.

TOR2 — Queue 2 Trigger Overrun Flag

TOR2 indicates that an unexpected trigger event has occurred for

queue 2. TOR 2 can be set when queue 2 is in the active, su spended,

and trigger pending states.

The TOR2 trigger overrun can occur only when using an external

trigger mode or a periodic/interval timer mode. Trigger overruns

cannot occur when the software-initiated single-scan mode and the

software-initiated continuous-scan mode are selected.

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Queued Analog-to-Digital Converter (QADC)

TOR2 is set when a trigger event is received while queue 2 is

executing, suspended, or a trigger is pending. TOR2 has no effect on

queue execution. A trigger event that causes a trigger overrun is not

retained since it is considered unexpected. An unexpected trigger

event may be a system overrun situation.

Once set, TOR2 is cleared only by a reset or by writing a 0 to it.

1 = At least one unexpected queue 2 trigger event has occurred.

0 = No unexpected queue 2 trigger events have occurred.

QS[9:6] — Queue Status Field

The 4-bit read-only QS field indicates the current condition of queue 1

and queue 2. The five queue status conditions are:

–Idle

–Active

–Paused

–Suspended

–Trigger pending

The two most significant bits are associated primarily with queue 1,

and the remai ning two bits ar e associat ed with queue 2 . Because the

priority scheme between the two queues causes the status to be

interlinked, the status bits must be considered as one 4-bit field.

Table 19-7 shows the bits in the QS field and how they denote the

status of queue 1 and queue 2.

Table 19-7. Queue Status

QS[9:6] Queue 1/Queue 2 States

0000 Queue 1 idle , queue 2 idle

0001 Queue 1 idle , queue 2 paused

0010 Queue 1 idle , queue 2 active

0011 Queue 1 idle, queue 2 trigger pending

0100 Queue 1 paus ed, queue 2 idle

0101 Queue 1 paus ed, queue 2 paus ed

0110 Queue 1 paused, queue 2 active

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One or both queues may be in the idle state. When a queue is idle,

CCWs are not be in g executed for that que ue, the queu e is no t in the

pause state, and no trigger is pending.

The idl e state occurs when a queu e is disa bled, when a que ue is in a

reserved mode, or when a queue is in a valid queue operating mode

awaiting a trigger event to initiate queue execution.

A queue is in the active state when a valid queue operating mode is

selected, when the selected trigger even t has occurred, or when the

QADC is performing a conversion specified by a CCW from that

queue.

Only one queue can be active at a time. One or both queues can be

in the paused state. A queue is paused when the previous CCW

exec uted from that queue ha d the pause b it set. The QA DC does not

execute any CCWs from the paused queue until a trigger event

occurs. C onsequently, th e QADC can ser vice queue 2 while queue 1

is paused.

Only queue 2 can be in the suspended state. When a trigger event

occurs on queue 1 while queue 2 is executing, the curr ent queue 2

conv ersion is aborted . The queue 2 statu s is re ported as suspen ded.

Queue 2 transitions back to the active state when queue 1 becomes

idle or paused.

0111 Queue 1 paused, queue 2 trigger pending

1000 Queue 1 ac tive, queue 2 idle

1001 Queue 1 ac tive, queue 2 paused

1010 Queue 1 ac tive, queue 2 suspended

1011 Queue 1 active, queue 2 trigger pending

1100 Reserved

1101 Reserved

1110 Reserved

1111 Reserved

Table 19-7. Queue Status (Continued)

QS[9:6] Queue 1/Queue 2 States

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460 Qu eued Analog-to-Digital Converter (QADC) MOTOROLA

Queued Analog-to-Digital Converter (QADC)

A trigger pending state is required because both queues cannot be

active at the same time. The status of queue 2 is changed to trigger

pending when a trigger event occurs for queue 2 while queue 1 is

act ive. In th e opp osite case , w hen a trigg er eve nt occur s for queu e 1

while qu eue 2 is active, qu eue 2 is aborted and th e status is repo rted

as queue 1 active, queue 2 suspended. So due to the priority scheme,

only queue 2 can be in the trigger pending state.

Two transition cases cause the queue 2 status to be trigger pending

before queue 2 is shown to be in the active state. When queue 1 is

active and there is a trigger pending on queue 2, after queue 1

completes or pauses, queue 2 continues to be in the trigger pending

state for a few clock cycles. The fleeting status conditions are:

•Queue 1 idle with queue 2 trigger pending

•Queue 1 paused with queue 2 trigger pending

Fi gu re 19-1 2 displays the status conditions of the QS field as the

QADC goes through the transition from queue 1 active to queue 2

active.

The queue status field is affected by QADC stop mode. Because all

of the analog logic and control registers are reset, the queue status

field is reset to queue 1 idle, queue 2 idle.

During debug mode, the queue status field is not modified. The queue

status field retains the status it held prior to freezing. As a result, the

queue status can show queue 1 active, queue 2 idle, even though

neither queue is being executed during freeze.

CWP[5:0] — Command Word Pointer Field

The comm and word poi nter (CWP) den otes which CCW is executi ng

at present or was last completed. CWP is a read-only field with a valid

range of 0 to 63; write operations have no effect.

When a queue e nters the p aused state, CWP po ints to th e CCW with

the pause bit set. While in pause, the CWP value is maintained until

a trigger event occurs on either queue. Usually, the CWP is updated

a few clock cycles before th e queue status field show s that the queue

has become active. For example, a read of CWP may point to a CCW

in queue 2, while the queue status field shows queue 1 paused and

queue 2 trigger pending.

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Figure 19-12. Queue Status Transition

When the QAD C finishes a queue sca n, th e C WP poi nts to th e CCW

where the end-of-queue condition was detected. Therefore, when the

end-of-queue condition is a C CW with the EOQ code (channel 63),

the CWP points to the CCW containing the EOQ.

When the last CCW in a queue is the last CCW table location

(CCW63 ), and it does not contain the EOQ code, the end-of- queue is

detected when the following CCW is read, so the CWP points to word

CCW0.

Q1 IDLE/

Q2 ACTIVE

Q1 IDLE/

Q2 IDLE

Q1 ACTIVE/

Q2 IDLE

Q1 PAUSED /

Q2 IDLE

Q1 ACTIVE/

Q2 SUSPENDED

Q1 ACTIVE/

Q2 PAUSED

Q1 PAUSED/

Q2 ACTIVE

Q1 I D LE/

Q2 PAUSED

Q1 PAUSED/

Q2 PAUSED

Q1 ACTIVE/

Q2 TRIGGER

PENDING

Q1 PAUSED /

Q2 TRIGG ER

PENDING

(TEMPORARY)

Q2 C OMP LET E

DE L AYE D TRANS ITION

Q1 PAUSE BIT SET

Q2 TRIGGER EVENT

Q1 TRIGGER EVENT

Q1 PAUSE BIT SET

Q1 C OMP LETE

Q1 TRIGGER EVENT

Q1 COMPLETE

DEL AYED TRANSITION

Q1 TRIGGER EVEN T

Q1 C OMP LETE

Q1 PAUSE BI T SET

Q1 TRIGGER EVEN T

Q2 C OMP LETE

Q2 TRIGGER EVENT

Q2 PAU SE BI T SET

Q2 TRIGGER EVENT

Q1 TRIGGER EVENT

Q1 COMPLETE

Q1 TRIGGER EVEN T

Q1 PAUSE BIT SET

Q2 PAUSE BIT SET

Q2 TRIGGER EVENT

Q1 IDLE/

Q2 TRIGGER

PENDING

(TEMPORARY)

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462 Qu eued Analog-to-Digital Converter (QADC) MOTOROLA

Queued Analog-to-Digital Converter (QADC)

Finally, when queue 1 operati on is terminated after a CCW is read

that i s pointed to by BQ2, the CWP poin ts to the sam e CCW as BQ2.

During stop mode, CWP is reset to 0 because the control registers

and the ana log logic are reset. When debug mode is entered, CWP is

not changed; it points to the last executed CCW.

19.8.6.2 QADC Status Register 1 (QASR1)

Stop mode resets this register ($3f3f).

Read: Anytime

Write: Never

CWPQ1[5:0] — Queue 1 Command Word Pointer Field

CWPQ1[5:0] points to the last queue 1 CCW executed. This is a

read-only field with a valid range of 0 to 63; writes have no effect.

CWPQ1 always points to the last executed CCW in queue 1,

regardless of which queue is active.

In contrast to CWP, CPWQ1 is updated when a conversion result is

written. When the QADC finishes a conversion in queue 1, both the

result register is written and CWPQ1 is updated.

Address: 0x00ca_0012 and 0x00ca_0013

Bit 15 14 13 12 11 10 9 B it 8

Read: 0 0 CWPQ15 CWPQ14 CWPQ13 CWPQ12 CWPQ11 CWPQ10

Write:

Reset:00111111

Bit 7654321Bit 0

Read: 0 0 CWPQ25 CWPQ24 CWPQ23 CWPQ22 CWPQ21 CWPQ20

Write:

Reset:00111111

= Writes have no effect and the access terminates without a transfer error exception.

Figure 1 9-13. QADC Status Regist er 1 (QASR1)

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Finally, when queue 1 operati on is terminated after a CCW is read

that is pointed to by BQ2, CWP points to BQ2 while CWPQ1 poin ts to

the last queue 1 CCW.

During stop mode, CWPQ1 is reset to 63, because the control

registers and the analog logic are reset. When debug mode is

entered, CWPQ1 is not changed; it points to the last executed CCW

in queue 1.

CWPQ2[5:0] — Queue 2 Command Word Pointer Field

CWPQ2[5:0] points to the last queue 2 CCW executed. This is a

read-only field with a valid range of 0 to 63; writes have no effect.

CWPQ2 always points to the last executed CCW in queue 2,

regardless which queue is active.

In contrast to CWP, CPWQ2 is updated when a conversion result is

written. When the QADC finishes a conversion in queue 2, both the

result register is written and CWPQ2 is updated.

During stop mode, CWPQ2 is reset to 63 because the control

registers and the analog logic are reset. When debug mode is

entered, CWPQ2 is not changed; it points to the last executed CCW

in queue 2.

19.8.7 Conversion Command Word Table (CCW)

The conversion command word (CCW) table is 64 half-word (128 byte)

long RAM with 10 bits of each entry implemented. The CCW table is

written by the user and is not modified by the QADC. Each CCW

requests the conversion of one analog channel to a digital result. The

CCW specifies the analog channel number, the input sample time, and

whether the queue is to pause after the current CCW.

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Queued Analog-to-Digital Converter (QADC)

Read: Anytime except reads during stop mode are invalid

Write: Anytime except during stop mode

P — Pause Bit

The pause bit allows subqueues to be created within queue 1 and

queue 2. The QADC performs the conversion specified by the CCW

with the pause bit set and then the queue enters the pause state.

Another trigger event causes execution to continue from the pause to

the next CCW.

1 = Enter pause state after execution of current CCW.

0 = Do not enter pause state after execution of current CCW.

NOTE: The P bit does not cause the queue to pause in the software. Initiated

modes or externally gated modes.

BYP — Sample Amplif ier Bypass Bit

Setti ng BYP in a CCW enables the amplifier bypass mode for a

conversion and subsequently changes the timing. The initial sample

time is eliminated, reducing the potential conversion time by two

QCLKs. However, due to internal RC effects, a minimum final sample

time of four QCLKs must be allowed. When using this mode, the

Address: 0x00ca_0200 through 0x00ca_027e

Bit 15 14 13 12 11 10 9 B it 8

Read: 0 0 0000PBYP

Write:

Reset:000000UU

Bit 7654321Bit 0

Read: IST1 IST0 CHAN5 CHAN4 CHAN3 CHAN2 CHAN1 CHAN0

Write:

Reset:UUUUUUUU

= Writes have no effect and the access terminates without a transfer error exception.

U = Unaffected

Figure 19-14. Conversion Command Word Table (C CW)

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external circuit should be of low source impedance. Loading effects of

the external circuitry need to be considered because the benefits of

the sample amplifier are not present.

1 = Amplifier bypass mode enabled

0 = Amplifier bypass mode disabled

NOTE: BYP is maintained for software compatibility but has no functional

benefit on this version of the QADC.

IST[1:0] — Input Sample Time Field

The IST field specifies the length of the sample window. The input

sample time can be varied, under software control, to accommodate

various input channel source impedances. Longer sample times

permit more accurate A/D conversions of signals with higher source

impedances.

Table 19-8 shows the four selectable input sample times.

The programmable sample time can also be used to adjust queue

execution time or sampling rate by increasing the time interval

between conversions.

CHAN[5:0] — Channel Number Field

The CHAN field selects the input channel number. The CCW channel

field is programmed with the channel number corresponding to the

analog input pin to be sampled and converted. The analog input pin

channel nu mber assignm ents and the pin de fi nitions var y depen di ng

on whether the QADC multiplexed or non-multiplexed mode is used

by the application. As far as queue scanning operations are

concerned, there is no distinction between an internally or externally

mul tiplexed analog input.

Table 19-8. Input Sample Times

IST[1:0] Input Sample Time s

00 Inpu t sa mp le tim e = QCLK p e rio d × 2

01 Inpu t sa mp le tim e = QCLK p e rio d × 4

10 Inpu t sa mp le tim e = QCLK p e rio d × 8

11 Inpu t s a mp l e time = Q C LK pe r io d × 16

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Table 19-9 shows the channel number assignments for

non-m ul tiplexed mode. Table 19-10 shows the channel number

assignments for multiplexed mode.

Programming the channel field to channel 63 denotes the end of the

queue. Chan nels 60 t o 62 a re special intern al channels. When one of

the special channels is selected, the sampling amplifier is not used.

The value of VRL, VRH, or (VRH–VRL)/2 is converted directly.

Programming any input sample time other than two has no benefit for

the special internal channels except to lengthen the overall

conversion time.

Table 19-9. Non-Multiplexed Channel Assignments

and Pin Designations

Non - Mu l tiplex e d Inp ut Pins Channel Number(1)

in CCW CHAN Field

Port Pin Name Analog Pin Name Other

Functions Pin Type Bi nary Decimal

PQB0

PQB1

PQB2

PQB3

AN0

AN1

AN2

AN3

—

Input

000000

000001

000010

000011

PQA0

PQA1 AN52

AN53 —

—Input/output

Input/output 110100

110101 52

PQA3

PQA4 AN55

AN56 ETRIG1

ETRIG2 Input/output

Input/output 110111

111000 55

VRL

VRH

—

Low reference

High reference

—

(VRH–VRL)/2

Input

—

111100

111101

111110

——End-of-queue code —111111 63

1. All channels not li sted are reserved or unimplem ented and return undefined results.

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Queued A nalog -to-Digital Conv erter (QADC)

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Table 19-10. Multiplexed Channel Assignments

and Pin Designations

Multiplexed Input Pins Channel Number(1)

in CCW CHAN Field

Port Pin

Name Analog

Pin Name Other

Functions Pin Type Bi na ry Decimal

PQB0

PQB1

PQB2

PQB3

ANw

ANx

ANy

ANz

—

Input

000XX0

000XX1

010XX0

010XX1

0, 2, 4, 6

1, 3, 5, 7

16, 18, 20, 22

17, 19, 21, 23

PQA0

PQA1 —

—MA0

MA1 Output

Output 110100

110101 52

PQA3

PQA4 AN55

AN56 ETRIG1

ETRIG2 Input/output

Input/output 110111

111000 55

VRL

VRH

—

Low reference

High reference

—

(VRH–VRL)/2

Input

—

111100

111101

111110

——End-of-queue code —111111 63

1. All channels not li sted are reserved or unimplem ented and return undefined results.

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19.8.8 Result Registers

The result word table is a 64 half-word (128 byte) long by 10-bit wide

RAM. An entry is written by the QADC after completing an analog

conversion specified by the corresponding CCW table entry.

19.8.8.1 Right-Justified Unsigned Result Register (RJURR)

Read: Anytime except reads during stop mode are invalid

Write: Anytime except during stop mode

RESULT[9:0] — Result Field

The conversion result is unsigned, right-justified data.

Address: 0x00ca_0280 through 0x00ca_02f e

Bit 15 14 13 12 11 10 9 B it 8

Read: 0 0 0000 RESULT

Write:

Reset:000000

Bit 7654321Bit 0

Read: RESULT

Write:

Reset:

= Writes have no effect and the access terminates without a transfer error exception.

Figure 19-15. Right-Justified Unsigned Result Register (RJURR)

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19.8.8.2 Left-Justified Signed Result Register (LJSRR)

S — Sign Bit

The left justified, signed format corresponds to a half-scale, offset

binary, two’s complement data format. Conversion values

corresponding to 1/2 full scale, 0x0200, or higher are interpreted as

positive values and have a sign bit of 0. An unsigned, right justified

conv ersion of 0x0200 wou ld be represen ted as 0x0000 in this si gned

regi ster, w her e th e sign = 0 and t he r esult = 0. For an unsigned, rig ht

justified conversion of 0x3FF (full range or VRH), the signed

equivalent in this register would be 0x7FC0, sign = 0 and

resul t = 0x1FF. For an un si gned, right justifi ed con version of 0x 0000

(VRL), the signed equivalent in this register would be 0x8000, sign = 1

and result = 0x000, a two’s complement value representing –512.

RESULT[14:6] — Result Field

The conversion result is signed, left-justified data.

Address: 0x00ca_0300 through 0x00ca_037e

Bit 15 14 13 12 11 10 9 B it 8

Read: S RESULT

Write:

Reset:

Bit 7654321Bit 0

Read: RESULT 000000

Write:

Reset: 000000

= Writes have no effect and the access terminates without a transfer error exception.

Figure 19-16. Left-Justified Signed Result Register (LJSRR)

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19.8.8.3 Left-Justified Unsigned Result Register (LJURR)

RESULT[15:6] — Result Field

The conversion result is unsigned, left-justified data.

19 .9 Fun cti on al Descr iptio n

This subsection provides a functional description of the QADC.

19.9.1 Result Coherency

The QADC supports byte and half-word reads and writes across a 16-bit

data bus interface. All conversion results are stored in half-word

regi sters, and t he QADC does no t allow mo re than one result register to

be read at a time. For this reason, the QADC does not guarantee read

coherency.

Specifically, this means that while the QADC is operating, the data in the

resul t register s can change from on e read to the next. Simp ly init iating a

read of one result register will not prevent another from being updated

with a new conversion result.

Thus, to read any given number of result registers coherently, th e queue

or queues capable of modifying these registers must be inactive. This

can be guaranteed by system operating conditions (such as, known

completion of a software-initiated queue single-scan or no possibility of

an externally triggered/gated queue scan) or by simply disabling the

queues (writing MQ1 and/or MQ2 to 0).

Address: 0x00ca_0380 through 0x00ca_03f e

Bit 15 14 13 12 11 10 9 Bit 8

Read: RESULT

Write:

Reset: Bit 76 54321Bit 0

Read: RESULT 000000

Write:

Reset: 000000

= Writes have no effect and the access terminates without a transfer error exception.

Figure 19-17. Left-Justified Unsigned Result Register (LJURR)

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Queued A nalog -to-Digital Conv erter (QADC)

Functional Description

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MOTOROLA Queued A nalog-to-Digital Converter (QADC) 471

19.9.2 External Multip lexing

Exter nal mul tip lexer chi p s concentrate a n umbe r of an al og signa ls onto

a few QADC inputs. This is useful for applications that need to convert

more analog signals than the QADC converter can normally support.

External multiple xing also puts the multiplexed chip closer to the signal

source. This minimizes the number of analog signals that need to be

shielded due to the proximity of noisy high speed digital signals at the

micr ocontroller chip.

For example, four 4-input multiplexer chips can be put at the connector

where the analog signals first arrive on the printed circuit board. As a

result, only four analog signals need to be shielded from noise as they

approach the microcontroller chip, rather than having to protect 16

analog signals. However, external multiplexer chips may introduce

additional noise and errors if not properly utilized. Therefore, it is

necessary to maintain low “on” resistance (th e im peda nce of an analog

switch when active within a multip lexed chip) and insert a low pass filter

(R/C) on the input side of the multiplexed chip .

19.9.2.1 External Multiplexing Operation

The QADC can use from one to four external multiplexer chips to expand

the number of analog signals that may be converted. Up to 16 analog

channels can be converted through external multiplexer selection. The

externally multiplexed channels are automatically selected from the

channel field of the CCW, the same as internally multiplexed channels.

The QADC is configured for the externally multiplexed mode by setting

the MUX bit in Control Register 0 (QACR0).

Fi gu re 19-1 8 shows the maximum configuration of four external

multiplexer chips connected to the QADC. The external multiplexer chips

select one of four analog inputs and connect it to one analog output,

which becomes an input to the QADC. The QADC provides two

multi plexed addr ess signals — MA[1:0] — to select one of four inputs.

These inputs are connected to all four external multiplexer chips. The

analog output of the four multiplexer chips are each connected to

separate QADC inputs (ANw, ANx, ANy, and ANz) as shown in

Fi gu re 19-1 8.

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Figure 19-18. External Multiplexing Configuration

AN52/MA0/PQA0

AN53/MA1/PQA1

AN55/ETRIG1PQA3

AN56/ETRIG2/PQA4

AN0/ANW/PQB0

AN1/ANX/PQB1

AN2/ANY/PQB2

AN3/ANZ/PQB3

PORT QBPORT QA

AN0

AN2

AN4

AN6

AN1

AN3

AN5

AN7

AN16

AN18

AN20

AN22

AN17

AN19

AN21

AN23 MUX

MUX

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Functional Description

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MOTOROLA Queued A nalog-to-Digital Converter (QADC) 473

When externa lly mult iplexed mode is selected, the QA DC automat ical ly

drives the MA output signals from the channel number in each CCW.

The QADC also convert s the proper input chann el (ANw, ANx, ANy, and

ANz) by interpreting the CCW channel number. As a result, up to 16

externally multiplexed channels appear to the conversion queues as

directly connected signals. User software simply puts the channel

number of externally multiplexed channels into CCWs.

Fi gu re 19-1 8 shows that the two MA signals may also be analog input

pins. When external multiplexing is selected, none of the MA pins can be

used for analog or digital inputs. They become multiplexed address

outputs and are unaffected by DDRQA[1:0].

19.9.2.2 Module Version Options

The n umber o f availab le analog ch anne ls vari es, dep ending on whether

external multiplexing is used. A maximum of eight analog channels are

supported by the in ternal multiplexing circuitry of the converter.

Table 19-11 shows the total number of analog input channels supported

with 0 to 4 external multiplexer chips.

Table 19-11. Analog Input Channels

Number of Analog Input Channels Available

Directly Connected + External Mult ip lexed = Total Channels(1), (2)

1. The external trigger inp uts are not shared with two analog input pins.

2. Whe n external multi plexing is used, two input channels are configured as multiplexed ad-

dress outputs, and for each external multiplexer chip, one input channel is a mul tiplexed

analog input.

No External

Mux One External

Mux Two Exte rnal

Muxes Three External

Muxes Four External

Muxes

8 5 + 4 = 9 4 + 8 = 12 3 + 12 = 15 2 + 16 = 18

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19.9.3 Analog Subsystem

This section describes the QADC analog subsystem, which includes the

front-end analog multiplexer and analog-to-digital converter.

19.9.3.1 Analog-to-Digital Converter Operation

The analog subsy stem consists of the path from the input pins to the A/D

converter block. Signals from the queue control logic are fed to the

multiplexer and state machine. The end -of-conversion (EOC) signal a nd

the Successive Approximati on Register (SAR) reflect the result of the

conversion. Figure 19-19 shows a block diagram of the QADC analog

subsystem.

Figure 19-19. QADC Analog Subsystem Block Diagram

PQA4

PQA0

PQB3

PQB0

VDDA

VSSA

VRH

VRL

QCLK

START CONV

END OF CON V

RST

STOP

SAR[9:0]

10-BIT A/D CONVERTER INPUT

ANALOG

POWER

2IST

SAMPLE

COMPAR- SUCCESSIVE

ATOR

BI AS CIRCUIT

APPROXIMATION

BUFFER

CHAN[5:0]

10-BIT RC

DAC

CSAMP

CHAN. DECODE & MUX

16:1

SIGNALS FROM /TO QU EU E CO NTROL LOGIC

STATE MACHINE & LOGIC

POWER-

DOWN

INTERNAL

CHANNEL

DECODE

SAR TIMING

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Queued A nalog -to-Digital Conv erter (QADC)

Functional Description

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19.9.3.2 Conversion Cycle Times

Total conversion time is made up of initial sample time, final sample time,

and resolution time. Initial sample time refers to the time during which the

sele cted input channel i s coupled thro ugh the sample buffer amplif ier to

the sample capacitor. The sample buffer is used to quickly reproduce its

input signal on the sample capacitor and minimize charge sharing errors.

During the final sampling period the amplifier is bypassed, and the

multiplexer input charges the sample capacitor array directly for

improved accuracy. During the resolution period, the voltage in the

sample capacitor is converted to a digital value and stored in the SAR.

Initial sample time is fixed at two Q CLK cycles. Final sample time can be

2, 4, 8, or 16 QCLK cycles, depending on the value of the IST field in the

CCW. Resolution time is 10 QCLK cycles.

A conversion requires a minimum of 14 QCLK cycles (7 µs with a

2. 0-MHz QCLK ). If the maxim um final sample time peri od of 16 QCLKs

is selected, the total conversion time is 28 QCLKs or 14 µs (with a

2. 0-MHz QCLK) .

Figure 19-20. Conversion Timing

If the amplifier bypass mode is enabled for a conversion by setting the

amplifier bypass (BYP) field in the CCW, the timing changes to that

shown in Figure 19-21. See 19.8.7 Conversion Command Word

Table (CCW) for more information on the BYP field. The initial sample

time is eliminated, reducing the potential conversion time by two QCLKs.

When using the bypass mode, the external circuit should be of low

source impedance (typically less than 10 kΩ). Also, the loading effects

on the external circuitry of the QADC need to be considered, because

the benefits of the sample amplifier are not present.

SAM PLE TI M E SUC C ESSI VE APPROXIMAT I ON RESOLU TION SEQU EN CE

QCLK

BUFFER

SAMPLE

TIME:

2 CYCLES

FINAL

SAMPLE

TIME:

N CYCLE S

(2,4,8,16)

RESOLUTION

TIME:

10 CYCLE S

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NOTE: B ecau se o f inte rnal RC time constan ts, use of a tw o QCLK sa mple time

in bypass mode will cause serious er rors when operating the QADC at

high frequencies.

Figure 19-21. Bypass Mode Conversion Timing

19.9.3.3 Channel Decode and Multiplexer

The internal multiplexer selects one of the eight analog input pins for

conversion. The selected input is connected to the sample buffer

amplifier or to the sample capacitor. The multiplexer also includes

positive and negative stress protection circuitry, whi ch prevents

deselected channels from affecting the selected channel when current is

injected into the deselected channels.

19.9.3.4 Sample Buffer

The sample buffer is used to raise the effective input impedance of the

A/D converter, so that external factors (higher bandwidth or higher

impedance) are less critical to accuracy. The input voltage is buffered

onto the sample capacitor to reduce crosstalk between channels.

19.9.3.5 Digital-to-Analog Converter (DA C) Array

The digi tal-to-a nalog conv erter (DA C) array consists of bi nary-weig hted

capacitors and a resistor-divider chain. The reference voltages, VRH and

VRL, are used by the DAC to per form ratiome tric conversions. The DAC

also converts the following three internal channels:

• VRH — reference voltage high

• VRL — reference voltage low

•(VRH–VRL)/2 — reference voltage

SAMPLE TIME SUCCESSIVE APPROXIMATION RESOLUTION SEQUENCE

QCLK

SAMPLE

TIME:

N CYCLES

(2,4,8,16)

RESOLUTION

TIME:

10 CYCLE S

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The DAC array provides a mechanism for the successive approximation

A/D conversion.

Resolution begins with the most significant bit (MSB) and works down to

the least significant bit (LSB). The switching sequence is controlled by

the comparator and SAR logic. The sample capacitor samples and holds

the voltage to be converted.

19.9.3.6 Comparator

During the approximation process, the comparator senses whether the

digitally selected arrangement of the DAC array produces a voltage level

higher or lower than the sampled input. The comparator outpu t feeds

into the SAR which accum ulates the A /D conversion re sult sequ entially,

beginning with the MSB.

19.9.3.7 Bias

The bias circuit is controlled by the STOP signal to power-up and

power-down all the analog circuits.

19.9.3.8 Successive Approximation Register

The input of the SAR is connected to the comparator output. The SAR

sequentially receives the conversion value one bit at a time, starting with

the MSB. After accumulating the 10 bits of the conversion result, the

SAR data is transferred to the appropriate result location, where it may

be read by user software.

19.9.3.9 State Machine

The state machine generates all timing to perform an A/D conversion. An

internal start-conversion signal indicates to the A/D converter that the

desired channel has been sent to the MUX. IST[1:0] denotes the desired

sample time. BYP determines whether to bypass the sample amplifier.

Once the end of conversion has been reached a signal is sent to the

queue control logic indi cating that a resu lt is availab le for stor age in the

result RAM.

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19.10 Digital Control

The digital contr ol subsystem includes the contr ol logic to sequence the

conversion activity, the clock and periodic/interval timer, control and

status registers, the conversion command word table RAM, and the

result word table RAM.

The central element for control of QADC conversions is the 64-entry

conversion command word (CCW) table. Each CCW specifies the

conversion of one input channel. Depending on the application, one or

two queues can be established in the CCW table. A queue is a scan

sequence of one or more inpu t channel s. By using a pause m echanism,

subqueues can be created in the two queues. Ea ch queue can be

operated using one of several different scan modes. The scan modes for

queue 1 and queue 2 are programmed in control registers QACR1 and

QACR2. Once a queue has been started by a trigger event (any of the

ways to cause the QADC to begin executing the CCWs in a queue or

subqueu e), the QA DC performs a seque nce of conver si ons and places

the results in the result word table.

19.10.1 Queue Priority Timing Exam ples

This subsection describes the QADC priority scheme when trigger

events on two queues overlap or conflict.

19.10.1.1 Queue Pr iority

Queue 1 has priority over queue 2 execution. These cases show the

conditions under which queue 1 asserts its priority:

•When a queue is not active, a trigger event for queue 1 or queue

2 causes the corresponding queue execution to begin.

•When queue 1 is active and a trigger event occurs for queue 2,

queue 2 cannot begin execution until queue 1 reaches completion

or the paused state. The status register records the trigger event

by reporting the queue 2 status as trigger pending. Additional

trigger events for queue 2, which occur before execution can

begin, are flagged as trigger overruns.

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Digital Control

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•When queue 2 is active and a trigger event occurs for queue 1, the

curren t queue 2 conversio n is aborted. The sta tus register reports

the queu e 2 status as suspended . Any trigge r events occurring f or

queue 2 while it is suspended are flagged as trigger overruns.

Once queue 1 reach es the completion or the paused state, queue

2 begins executing again. The programming o f the RESUME bit in

QACR2 determines which CCW is executed i n queue 2.

•When simultaneous trigger events occur for queue 1 and queue 2,

queue 1 begins execution and the queue 2 status is changed to

trigger pendi ng.

•When subqueues are paused

The pause feature can be used to divide queue 1 and/or queue 2 into

multiple subqueues. A subqueue is defined by setting the pause bit in

the last CCW of the subqueue.

Figure 19-2 2 shows the CCW fo rmat and a n example of u sing pause to

create subqueues. Queue 1 is shown with four CCWs in each subqueue

and queue 2 has two CCWs in each subqueue.

The operating mode selected for queue 1 determines what type of

trigger event causes the execution of each of the subqueues within

queue 1. Simi larly, the operating mode for queu e 2 determines the type

of trigger event required to execute each of the subqueues within

queue 2.

For example, when the external trigger rising edge continuous-scan

mode is selected for queue 1, and there are six subqueues within

queue 1, a separate rising edge is required on the external trigger pin

after every pause to begin the execution of each subqueue (refer to

Fi gu re 19-2 2).

The choice of single-scan or continuous-scan applies to the full queue,

and is not applied to each subqueue. Once a subqueue is initiated, each

CCW is executed sequentially until the last CCW in the subqueue is

executed and the pause state is entered. Execution can only continue

with the next CCW, which is the beginning of the next subqueue. A

subqueue cannot be executed a second time before the overall queue

execution has been completed.

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Figure 19-22. QADC Queue Operation with Pause

Trigger events which occur during the execution of a subqueue are

ignored, except that the tri gger overrun flag is set. When a

continuous-scan mode is selected, a trigger event occurring after the

compl etion of the last subqueue (a fter the queu e compl etion flag is se t),

causes the execution to continue with the first subqueue, starting with

the first CCW in the queue.

When the QADC encounters a CCW with the pause bit set, the queue

enters the pa used state aft er completing the conve rsion specified in the

CCW with the pause bit. The pau se flag is set and a pause interrupt may

opti onally be req uested. The status of th e queue is show n to be p aused,

indicating completion of a subqueue. The QADC then waits for another

trigger event to again begin execution of the next subqueue.

BEGINNING OF QUEUE 1 00

CHANN EL SELECT,

SAMPL E, H OLD ,

A/D CONVERSION

CONVE RS IO N CO MMA ND RESU LT WOR D TABLE

PAUSE

WORD (CCW) TA BLE

0PAUSE

00 P

PAUSE

0PAUSE

END OF QU EU E 1

BEGINNING OF QUEUE 2

BQ2

PAUSE

END OF QU EU E 2

063 63

•

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Queued A nalog -to-Digital Conv erter (QADC)

Digital Control

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 A dv ance I nforma tion

MOTOROLA Queued A nalog-to-Digital Converter (QADC) 481

19.10.1.2 Queue Pr iority Schemes

Because there are two conversion command queues and only one A/D

conv erter, a pri ority scheme det ermines whic h conversion oc curs. Each

queue has a variety of trigger events that are intended to ini tiate

conversions, and they can occur asynchronously in relation to each

other and other conversions in progress. For example, a queue can be

idle awaiting a trigger event; a trigger event can have occurred, but the

first conversion has not started; a conversion can be in progress; a

pause co ndi tion can exi st awa iti ng a nother tri gger even t to continu e th e

queue; and so on.

The following paragraphs and figures outline the prioritizing criteria used

to determine which conversion occurs in each overlap situation.

NOTE: Each situation in Figure 19-23 through Figure 19-33 is labeled S1

through S19. In each diagram, time is shown increasing from left to right.

The executio n of qu eue 1 and queu e 2 (Q 1 and Q 2) is shown a s a string

of rectangles representing the execution time of each CCW in the queue.

In mo st of the situa tions, ther e are four CC Ws (label ed C1 t o C4) in both

queue 1 and queue 2. In some of the situations, CCW C2 is presumed

to have the pause bit set, to show the similarities of pause and

end-of-queue as terminations of queue execution.

Trigger events are described in Table 19-12.

When a trigger event causes a CCW execution in progress to be

aborted, the aborted conversion is shown as a ragged end of a

shortened CCW rectangle.

Table 19-12. Trigger Events

Trigger Events

T1 Events that trigger queue 1 execution (external trigger, software-initiated

single-scan enab le bit, or comple tion of the previous continuou s loop)

T2 Events that trigger queue 2 execution (external trigger, software-initiated

single-scan enab le bit, timer period/in terval expired, or completion of the

previous continuous loop)

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482 Qu eued Analog-to-Digital Converter (QADC) MOTOROLA

Queued Analog-to-Digital Converter (QADC)

The situation diagrams also show when key status bits are set.

Table 19-13 describes the status bits.

Below the qu eue execu tion flows are three sets of blocks that show the

status information that is made available to the user. The first two rows

of status blocks show the condition of each queue as:

•Idle

•Active

•Pause

•Suspended (queue 2 only)

•Trigger pending

The third row of status blocks shows the 4-bit QS status register field that

encodes the condition of the two queues. Two transition status cases,

QS = 001 1 and QS = 0111, ar e not shown be cause th ey exi st on ly very

briefly between stable status conditions.

The first three examples i n Figure 19- 23 through Figure 19- 25 (S 1, S2,

and S3) show what happens when a new trigger event is recognized

before the queue ha s com pl eted servicin g the previous tri gge r eve nt o n

the same queue.

In situation S 1 (Figu r e 19- 23) , one trigg er e vent is being recog ni zed o n

each queue while that queue is still working on the previously recognized

trigger event. The trigger overrun error status bit is set, and the

premature trigger event is otherwise ignored. A trigger event that occurs

before the servicing of the previous trigger event is through does not

distur b the queue execution in progress.

Table 19-13. Status Bits

Bit Function

CF flag Set when the end of the queue is reached

PF flag Set when a queue complet es execution up through a pause bit

Trigger overrun

error (TO R ) Set when a new trigger event occurs before the queue is finished

servicing the previous trigger event

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Queued A nalog -to-Digital Conv erter (QADC)

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MOTOROLA Queued A nalog-to-Digital Converter (QADC) 483

Figure 19-23. CCW Priority Situation 1

In situation S2 (Figure 19-24), more than one trigger event is recognized

before servicing of a previous trigger event is complete. The trigger

overrun bit is again set, but the additional trigger events are otherwise

ignored. After the queue is complete, the first newly detected trigger

event causes queue execution to begin again. When the trigger event

rate i s high, a new trigger event can be seen very soo n after com pletion

of the previou s que ue, l e aving li ttle time to r etri eve the previou s re sul ts.

Also, when trig ger events are occurring at a high rate for queue 1, the

lower priority queue 2 channels may not get serviced at all.

Figure 19-24. CCW Priority Situation 2

Q1:

Q2:

QS:

IDLE

IDLE ACTIVE IDLE

0000 1000 0000 0010 0000

TOR1

T1 T1

Q1: C1 C2 C3 C4

CF1 C1 C2 C3 C4

TOR2

T2 T2

Q2:

CF2

IDLE

ACTIVE

ACTIV E IDLE

Q1:

Q2:

QS:

IDLE ACTIVE

IDLE ACTIVE IDLE

1000 1000 0000 0010 0000

C1 C2 C3 C4

TOR2

T2 T2

Q2:

CF2

IDLE

C1 C2 C3 C4

CF1

C1 C2 C3 C4

TOR1

Q1:

CF1

TOR1

TOR2

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484 Qu eued Analog-to-Digital Converter (QADC) MOTOROLA

Queued Analog-to-Digital Converter (QADC)

Situati on S3 (F igure 19-25) shows that when the pause f eature i s used,

the trigger overrun error status bit is set the same way and that queue

execution continues unchanged.

Figure 19-25. CCW Priority Situation 3

The next two situations consider trigger events that occur for the lower

priority queue 2, while queue 1 is actively being serviced.

Situation S4 (Fi gu re 19-2 6) shows that a queue 2 trigger event is

recognized wh ile queue 1 is active is saved, and as soon as que ue 1 is

finished, queue 2 servicing begins.

Figure 19-26. CCW Priority Situation 4

PAUSE

Q1:

Q2:

QS:

IDLE ACTIVE

IDLE ACTIV E IDLE

1000 0110 0001 0010

ACTI VE

0000

IDLE

C1 C2

T1 T1

Q1:

TOR1 PF1

C1 C2

0000

Q2:

0100

TOR2 PF2

T2 T2

0101

C3 C4

T1 T1

TOR1 CF1

ACTIVE

PAUSE

1001

C3 C4

CF2

T2 T2

TOR2

Q1:

Q2:

QS:

IDLE

IDLE ACTIVE IDLE

0000 1000 0010

ACTIVE

0000

C1 C2 C3 C4

Q1:

CF1

Q2: C1 C2 C3 C4

CF2

IDLE

1011

TRIGGERED

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MOTOROLA Queued A nalog-to-Digital Converter (QADC) 485

Situation S5 (Fi gu re 19-2 7) shows that when multiple queue 2 trigger

events are detected while queue 1 is busy, the trigger overrun error bit

is set, but queue 1 execution is not disturbed. Situation S5 also shows

that the effect of queu e 2 tri gge r ev ents d uri ng queu e 1 executio n i s th e

same when the pause feature is used for either queue.

Figure 19-27. CCW Priority Situation 5

The remaining situ ations, S6 through S11, sh ow the impact of a queue 1

tri gger event occurr ing du ring queue 2 execution. B ecause que ue 1 has

hig her priority, the conve rsion taking place in queue 2 is abo rted so that

there i s no variabl e latency tim e in respondi ng to queu e 1 trigger ev ents.

In situation 6 (Figure 19-28), the conversion initiated by the second

CCW in queue 2 is aborted just before the conversion is complete, so

that queue 1 execution can begin. Queue 2 is considered suspended.

After queue 1 is finished, queue 2 starts over with the first CCW, when

the RESUME control bit is set to 0. Situation S7 (Figure 19-29) shows

that when pause operation is not used with queue 2, queue 2

suspension w orks the same way.

Q1:

Q2:

QS:

IDLE

IDLE IDLE

0000 1000 0010

ACTIV E

0000

C1 C2

Q1:

C1 C2

PF2

C3 C4

CF2

IDLE

1011

TRIG

Q2:

T2T2 PF1

PAUSE

ACTIV E PA U SE

TOR2

T2T2 CF1

TOR2

ACTIVE

TRIG

0110

ACTI VE

0101 1001 1011

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486 Qu eued Analog-to-Digital Converter (QADC) MOTOROLA

Queued Analog-to-Digital Converter (QADC)

Figure 19-28. CCW Priority Situation 6

Figure 19-29. CCW Priority Situation 7

IDLE

Q1:

Q2:

IDLE

0000 1000

ACTIV E

C1 C2

Q1:

C3 C4

IDLE

Q2:

PF1

PAUSE

ACTIV E

CF1

ACTIV E

SUSPE ND

0100

ACTIVE

0110 1010

C1 C2 C3 C4

CF2

0010 0000

RESUME = 0

PAUSE

Q1:

Q2:

QS:

IDLE ACTIVE

IDLE ACTIV E IDLE

0010 0110 1010 0010

ACTIV E

0000

IDLE

Q1:

PF1

C1 C2

0000 1010

ACTI VE

0110

Q2:

PF2

C3 C4

CF1

CF2

SUSPEND PAUSE SUSPEND

C1 C3

ACTIV E ACT

0101

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MOTOROLA Queued A nalog-to-Digital Converter (QADC) 487

Situatio ns S8 a nd S9 (Figure 19-30 and Figur e 19-31 ) r epeat the same

two situ ations with th e RESUME bit set t o a 1. When the RESUME bit is

set , followin g suspensio n, queue 2 resume s execution wi th the abo rted

CCW, not the first CCW, in the queue.

Figure 19-30. CCW Priority Situation 8

Figure 19-31. CCW Priority Situation 9

IDLE

Q1:

Q2:

QS:

IDLE

0000 1000 0010

ACTIVE

C1 C2

Q1:

C3 C4

IDLE

Q2:

PF1

PAUSE

ACTI VE

CF1

ACTI VE

SU SPEN D

0100

ACTI VE

0110 1010

C2 C3 C4

CF2

0000

RESUME=1

PAUSE

Q1:

Q2:

QS:

IDLE ACTIVE

IDLE ACT IDLE

0010 0110 1010 0010

ACTIV E

0000

IDLE

Q1:

PF1

C1 C2

0000 1010 0101

ACTI VE

PAUSE

0110

Q2:

PF2

C3 C4

CF1

CF2

SUSPEND ACT ACTIV E SUSPEND

C3C1 RESUME=1

C2 C4

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Situations S10 and S11 (Figure 19-32 and Figure 19-33) show that

whe n an additional trigger event is detected for queu e 2 wh ile the q ueue

is suspend ed, the t ri gge r ove rru n er ror bit is set, the same as i f qu eue 2

were being executed when a new trigger event occurs. Trigger overrun

on queue 2 thus allows the user to know that queue 1 is taking up so

much QADC time that queue 2 trigger events are being lost.

Figure 19-32. CCW Priority Situation 10

Figure 19-33. CCW Priority Situation 11

T1 T1

PAUSE

Q1:

Q2:

QS:

IDLE ACTIVE

IDLE A CTI VE IDLE

0010 0110 1010 0010

ACTIV E

0000

IDLE

Q1:

PF1

C1 C2

0000 1010 0101

ACTIVE

PAUSE

0110

Q2:

PF2

C1 C2

C3 C4

CF1

C3 C4

CF2

SUSPEND ACTI V E

ACT SUSPEND

TOR2

RESUME = 0

T1 T1

C3 C4

CF1

PAUSE

Q1:

Q2:

QS:

IDLE ACTIVE

IDLE ACT IDLE

0010 0110 1010 0010

ACTIV E

0000

IDLE

Q1:

PF1

C1 C2

0000 1010 0101

ACTIVE

PAUSE

0110

Q2:

SUSPEND AC T

ACTI VE SUSPEN D

TOR2

PF2

CF2

C2 C4 RESUME = 1

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Queued A nalog -to-Digital Conv erter (QADC)

Digital Control

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 A dv ance I nforma tion

MOTOROLA Queued A nalog-to-Digital Converter (QADC) 489

The previous situations co ver normal overl ap conditions that arise with

asynchron ous trigger events on the two queues. An additional conflict to

consider is that the freeze condition can arise while the QADC is actively

executing CCWs. The conventional use for the debug mode is for

software/hardware debugging. When the CPU enters background

debug mode, peripheral modules can cease operation. When freeze is

detected, the QADC completes the conversion in progress, unlike the

abort that occurs when queue 1 suspends queue 2. After the freeze

condition is removed, the QADC continues queue execution with the

next CCW in sequence.

Trigger events that occur during freeze are not captured. When a trigger

event is pending for queue 2 before freeze begins, that trigger event is

remembered when the freeze is passed. Similarly, when freeze occurs

while queue 2 is suspended, after freeze, queue 2 resumes execution as

soon as queue 1 is finished.

Situations 12 through 19 (Figure 19-34 to Figure 19-41) show examples

of all of the freeze situations.

Figure 19-34. CCW Freeze Situation 12

Figure 19-35. CCW Freeze Situation 13

C3 C4

CF1

C1 C2

Q1:

FREEZE

C1 C2

Q2:

CF2

C3 C4

FREEZE

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Figure 19-36. CCW Freeze Situation 14

Figure 19-37. CCW Freeze Situation 15

Figure 19-38. CCW Freeze Situation 16

C1 C2

Q1:

CF1

C3 C4

FREEZE

T1 T1

T2 T2

TRIG G ER S IGNO RE D

C1 C2

Q2:

CF2

C3 C4

FREEZE

T2 T2

T1 T1

TRIG G ER S IGNO RE D

C1 C2

Q1:

CF1

C3 C4

FREEZE

T1 T1

PF1

TRIG G E RS IGNO RED

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MOTOROLA Queued A nalog-to-Digital Converter (QADC) 491

Figure 19-39. CCW Freeze Situation 17

Figure 19-40. CCW Freeze Situation 18

Figure 19-41. CCW Freeze Situation 19

C1 C2

Q2:

CF2

C3 C4

FREEZE

T2 T2

PF2

TRIG G ER S IG NO RE D

C1 C2

Q1:

CF1

C3 C4

FREEZE

C1 C2

Q2: C3

CF2

TRIGGER CAP TUR ED , RESPONS E DEL AYED AFTER FREEZE

C1 C2

Q1:

CF1

FREEZ E

CF2

C1 C2

Q2: C3

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492 Qu eued Analog-to-Digital Converter (QADC) MOTOROLA

Queued Analog-to-Digital Converter (QADC)

19.10.2 Bo undary Conditions

The queue operation boundary conditions are:

•The first CCW in a queue speci fies ch annel 63, the end-o f-qu eue

(EOQ) code. The queue becomes active and the first CCW is

read. The end-of-queue is recognized, the completion flag is set,

and the queue becomes idle. A conversion is not performed.

•BQ2 (beginning of queue 2) is set at the end of the CCW table (63)

and a trigger event occurs on queue 2. The end-of-queue

condition is recognized, a conversion is performed, the completion

flag is set, and the queue becomes idle.

•BQ2 is set to C CW0 and a tr i gger event occur s on que ue 1. A fter

reading CCW0, the end-of-queue condition is recognized, the

completi on flag is set, and the qu eue b ecome s idl e. A conver sion

is not performed.

•BQ2 (beginning of queue 2) is set beyond the end of the CCW

table (64–127) and a trigger event occurs on queue 2. The

end-of-queue condition is recognized immediately, the completion

flag is set, and the queue becomes idle. A conversion is not

performed.

NOTE: Multiple end-of-queue conditions may be recognized simultaneously,

although there is no change in QADC behavior. For example, if BQ2 is

set to CCW0, CCW0 co ntains the EOQ code, and a tr igger eve nt occurs

on queue 1, the QADC reads CCW0 and detects both end-of-queue

conditions. The completion flag is set and queue 1 becomes idle.

Boundary conditions also exist for combinations of pause and

end-of-queue. One case is when a pause bit is in one CCW and an

end-of -que ue condition is in t he next CCW . The conversion sp ecified by

the CCW with the pause bit set completes normally. The pause flag is

set. However, because the end-of-queue condition is recognized, the

completion flag is also set and the queue status becomes idle, not

paused. Examples of this situation include:

•The pause bit is set in CCW5 and the channel 63 (EOQ) code is

in CCW6.

•The pause is in CCW63.

•During queue 1 operation, the pause bit is set in CCW20 and BQ2

points to CCW21.

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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 A dv ance I nforma tion

MOTOROLA Queued A nalog-to-Digital Converter (QADC) 493

Another pause and end-of-queue boundary condition occurs when the

pause and an end-of- queue condi tion occur in the same CC W. Both the

pause a nd end-of-queue conditions are recognized simultaneously. The

end-of-queue condition has precedence so a conversion is not

performed for the CCW and the pause flag is not set. The QADC sets the

completion flag and the queue status becomes idle. Examples of this

situation are:

•The pause bit is set in CCW10 and EOQ is programmed into

CCW10.

•During queue 1 operation, the pause bit set in CCW32, which is

also BQ2.

19.10.3 Scan Modes

The QADC queuing mechanism allows application software to utilize

different requirements for automati cally scanning input channels.

In single-scan mode, a single pass through a sequence of conversions

defined by a queue is performed. In continuous-scan mode, multiple

passes through a sequence of conversions de fined by a queue are

executed.

The possible modes are:

•Disabled mode and reserved mode

•Software-initiated single-scan mode

•Externally triggered single-scan mode

•Externally gated single-scan mode

•Interval timer single-scan mode

•Software-initiated continuous-scan mode

•Externally triggered continuous-scan mode

•Externally gated continuous-scan mode

•Periodic timer continuous-scan mode

The following paragraphs describe single-scan and continuous-scan

operations.

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19.10.4 Disabled Mode

When disabled mode is selected, the queue is not active. Trigger events

cannot initiate queue execution. When both queue 1 and queue 2 are

disabled, there is no possibility of encountering wait states when

accessi ng CCW table and result RA M. When bo th queues ar e disabl ed,

it is safe to change the QCLK prescaler values.

19.10.5 Reserved Mode

Rese rved mode is avai lab le for futur e m ode d efiniti ons. When r eser ved

mode is selected, the queue is not active. The behavior is the same as

disabled mode.

19.10.6 Single-Scan Modes

A single-scan queue operating mode is used to execute a single pass

through a sequence of conversions defined by a queue. By

programming the MQ1 field in QACR1 or the MQ2 field in QACR2, these

modes can be selected:

•Software-initiated single-scan mode

•Externally triggered single-scan mode

•Externally gated single-scan mode

•Interval timer single-scan mode

NOTE: Qu eue 2 canno t be programmed for extern all y gated single -scan mo de.

In all single-scan queue operating modes, queue execution is enabled

by writing the single-scan enable bit to a 1 in the queue’s control register.

The single-scan ena ble bits, SS E1 an d S SE2, are pro vid ed f or q ueue 1

and queue 2, respectively.

Until a queue’s single-scan enable bit is set, any trigger events for that

queue are ignored. The single-scan enable bit ma y be set to a 1 during

the same write cycle that selects the single-scan queue operating mode.

The single-scan enable bit can be written only to 1, but will always

read 0. Once set, writing the single-scan enable bit to 0 has no effect.

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MOTOROLA Queued A nalog-to-Digital Converter (QADC) 495

Only the QADC can clear the single-scan enable bit. The completion

flag, completion interrupt, or queue status is used to determine when the

queue has completed.

After the single- scan enabl e bit is set, a trigger even t cau ses th e QA DC

to begin execution with the first CCW in the queue. The single-scan

enable bit remains set until the queue is completed. After the queue

reaches completion, the QADC resets the single-scan enable bit to 0.

Writin g the sin gle-sca n ena bl e bit to a 1 or a 0 be fore the qu eue scan is

complete has no effect; however, if the queue operating mode is

changed, the new queue operating mode and the value of the

single-scan enable bit are recognized immediately. The conversion in

progress is aborted, and the new queue operating mode takes effect.

In software-initiated single-scan mode, writing a 1 to the single-scan

enable bit causes the QADC to generate a trigger event internally, and

queue execution begins immediately. In the other single-scan queue

operating modes, once the single-scan enable bit is written, the selected

trigger event must occur before the queue can start. The single-scan

enable bit allows the entire queue to be scanned once. A trigger overrun

is captured if a trigger event occurs during queue execution in an

edge-sensitive external trigger mode or a periodic/interval timer mode.

In the i nte rval ti mer si ng le-scan m ode, the next exp ir ation of the timer is

the trigger event for the queue. After queue execution is complete, the

queue status is shown as idle. The queue can be restarted by setting the

single-scan enable bit to 1. Queue execution begins with the first CCW

in the queue.

19.10.6.1 Software-Initiated Single-Scan Mode

Softwar e can ini tiate the ex ecuti on of a sca n seq uence for q ueue 1 or 2

by selecting software-initiated single-scan mode and writing the

single-scan enable bit in QACR1 or QACR2. A trigger event is generated

inte rnally and the Q ADC i m med iately be gi ns e xecution of the firs t CCW

in the queue. If a pause occurs, another trigger event is generated

internally, and then execution continues without pausing.

The QADC automatica lly performs the conversions in the queue until an

end-of -queue condition is encountered. The queue remains idle until the

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sing le-scan enab le bi t is agai n set. Whil e the t ime to inter nall y ge nera te

and act on a trigger event is very short, the queue status field can be

read as momentarily indicating that the queue is paused. The trigger

overrun flag is never set while in software-initiated single-scan mode.

The software-initiated single-scan mode is useful when:

•Complete control of queue execution is required

•There is a need to easily alternate between several queue

sequences

19.10.6.2 Externally Triggered Single-Scan Mode

The exter nall y trigger ed single- scan mod e is availab le on both queu e 1

and queu e 2. Both rising and falling edge triggered modes are available.

A scan must be enabled by setting the single-scan enable bit for the

queue.

The first external trigger edge causes the queue to be executed one

time. Each CCW is read and the indicated conversions are performed

until an end-of-queue condition is encountered. After the queue is

completed, the QADC clears the single-scan enable bit. The single-scan

enabl e bit can be w ritte n ag ain to al low anoth er scan of the qu eue to be

initiated by the next external trigger edge.

The externally tr iggered single-scan mode is useful when the input

trigger rate can exceed the queue execution rate. Analog samples can

be taken in sync with an external event, even though application

software does not require data taken from every edge. Externally

triggered single-scan mode can be enabl ed to get one set of data and,

at a later time, be enabled again for the next set of samples.

When a pause bit is encounte red during externally triggered single-scan

mode, another trigger event is required for queue execution to continue.

Software involvement is not required for queue execution to continue

from the paused state.

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Queued A nalog -to-Digital Conv erter (QADC)

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19.10.6.3 Externally Gated Single-Scan Mode

The QADC provides external gating for queue 1 only. When externally

gated single-scan mode is selected, the input level on the associated

ext erna l trigger pin enables and disab les queue exe cuti on. Th e polari ty

of the external gate signal is fixed so that only a high level opens the gate

and a low level closes the gate. Once the gate is open, each CCW is

read and the indicated conversions are performed until the gate is

closed . Queue scan must be enabled by setting the single-scan enable

bit for queue 1. If a pause is encountered, the pause flag does not s et,

and execution continues without pausing.

While the gate is open, queue 1 executes one time. Each CCW is read

and the indicated conversions are performed until an end-of-queue

condi tion is encounter ed. When queue 1 complete s, the QADC sets the

completion flag (CF1) and clears the single-scan enable bit. Set the

single-scan enable bit again to allow another scan of queue 1 to be

initiated during the next open gate.

If the ga te closes before queue 1 co mpletes execution, the current CCW

completes, execution of queue 1 stops, the single-scan enable bit is

cleared, and the PF1 bit is set. The CWPQ1 field can be read to

determine the last valid conversion in the queue. The single-scan enable

bit must be set again and the PF1 bit should be cleared before another

scan of queue 1 is initiated during the next open gate. The start of

queue 1 is always the first CCW in the CCW table.

Because the gate level is only sampled after each conversion during

queue execution, closing the gate for a period less than a conversion

time interval does not guarantee the closure will be captured.

19.10.6.4 Interval Timer Single-Scan Mode

Both queues can use the periodic/interval timer in a single-scan queue

operating mode. The timer interval can range from 27 to 217 QCLK

cycles in binary multiples. When the interval timer single-scan mode is

sele cted an d the s ingl e- scan en able b it i s set in QACR1 or QA CR2, the

timer begins counting. When the time interval elapses, an internal trigger

event is generated to start the queue and the QADC begins execution

with the first CCW.

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Queued Analog-to-Digital Converter (QADC)

The QADC automatical ly performs the conversions in the queue until a

pause or an end-of-queue condition is encountered. When a pause

occurs, queue execution stops until the timer in terval elapses again, and

queue execution continues. When queue execution reaches an

end-of-queue situation, the single-scan enable bit is cleared. Set the

single-scan enable bit again to allow another scan of the queue to be

initiated by the interval timer.

The interval timer generates a trigger event whenever the time interval

elapses. The trigger event may cause queue execution to continue

following a pause or may be considered a trigger overrun. Once queue

exec ution is compl ete d, the single-sca n enable bi t must be set aga in to

allow the timer to count again.

Normally, only one queue is enabled for interval timer single-scan mode,

and the timer will reset at the end-of-queue. However, if both queues are

enabled for either single-scan or continuous interval timer mode, the

end-of-queue cond ition will not reset the timer while the other queue is

active . In th is case , th e t imer will r eset when both qu eues have re ached

end-of-queue. See 19.10.9 Periodic/Interval Timer for a definition of

interval timer reset conditions.

The interval timer single-scan mode can be used in applications that

need coherent results. For example:

•When it is n ecessary that all sam ples ar e guar antee d to be taken

during the same scan of the analog pins

•When the interrupt rate in the periodic timer continuous-scan

mode would be too high

•In sensitive battery applications, where the interval timer

single-scan mode uses less power than the software-initiated

continuous-scan mode

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Queued A nalog -to-Digital Conv erter (QADC)

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19.10.7 Continuous-Scan Modes

A continuous-scan queue operating mode is used to execute multiple

passes through a sequence of conversions defined by a queue. By

programming the MQ1 field in QACR1 or the MQ2 field in QACR2, these

modes can be selected:

•Software-initiated continuous-scan mode

•Externally triggered continuous-scan mode

•Externally gated continuous-scan mode

•Periodic timer continuous-scan mode

NOTE: Queue 2 cannot be programmed for externally gated continuous-scan

mode.

When a queue is programmed for a continuous-scan mode, the

single-scan enable bit in the queue control register does not have any

meaning or effect. As soon as the queue operating mode is

programmed, the selected trigger event can initiate queue execution.

In the case of software-initiated continuous-scan mode, the trigger event

is generated internally and queue execution begins immediately. In the

other continuous-scan queue operating modes, the selected trigger

event must occur before the queue can start. A trigger overrun is

captured if a trigger event occurs during queue execution in the

externally triggered continuous-scan mode or the periodic timer

continuous-scan mode.

After queue execution is complete, the queue status is shown as idle.

Because the continuous-scan queue operating modes allow the entire

queue to be scanned multiple times, software involvement is not needed

for queue execution to continue from the idle state. The next trigger

event causes queue execution to begin again, starting with the first CCW

in the queue.

NOTE: In continuous-scan modes, all samples are guaranteed to be taken

during one pass through the queue (coherently), except when a queue 1

trigger event halts queue 2 execution. The time betwe en consecutive

conversions has been designed to be consistent. However, for queues

that end with a CCW containing the EOQ code (channel 63), the time

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500 Qu eued Analog-to-Digital Converter (QADC) MOTOROLA

Queued Analog-to-Digital Converter (QADC)

between the last queue conversion and the first queue conversion

requires one additional CCW fetch cycle. Continuous samples are not

coherent at this boundary.

In addition, the time from trigger to first conversion cannot be

guaranteed, because it is a function of clock synchronization,

programmable trigger events, queue priorities, and so on.

19.10.7.1 Software-Initiated Continuous-Scan Mode

When software-initiated continuous-scan mode is selected, the trigger

event is generated automa tically by the QADC. Queue execu tion begins

immediately. If a pause is encountered, another trigger event is

generated inte rnally, and execution continues without pausing. When

the end- of-queue is reach ed, another internal trigger e vent is ge nerated

and queue execution restarts at the beginning of the queue.

While the time to internally generate and act on a trigger event is very

short, the que ue status fi eld can be read as moment aril y indicati ng that

the queue is idle. The trigger overrun flag is never set while in

software-initiated continuous-scan mode.

The softwar e-i n itiated cont in uous- scan mod e keeps the result re gisters

updated more fre quen tl y than any of the other queue operatin g modes.

The resu lt table can alw ays be read to get the latest converte d value for

each channel . The channels scann ed are kept up to date by the QADC

without software involvement.

The software-initiated continuous-scan mode may be chosen for either

queue, but is normally used only with queue 2. When software-initiated

continuous-scan mode is chosen for queue 1, that queue operates

continuously and queue 2, being lower in priority, never gets executed.

The short interval of time between a queue 1 completion and the

subsequent trigger event is not sufficient to allow queue 2 execution to

begin.

The software-initiated continuous-scan mode is a useful choice with

queue 2 for conver ti ng ch annels that d o not need to be synchr onized to

anythi ng or for slo w-to-ch ange anal og channels. Interr upts are nor mally

not used with the software-initiated continuous-scan mode. Rather, the

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Queued A nalog -to-Digital Conv erter (QADC)

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MOTOROLA Queued A nalog-to-Digital Converter (QADC) 501

latest conversion results can be read from the result table at any time.

Once in itiated, software action is not needed to sustain conversions of

channel.

19.10.7.2 Externally Triggered Continuous-Scan Mode

The QADC provides external trigger pins for both queues. When

externally triggered continuous-scan mode is selected, a transition on

the associated external trigger pin initiates queue execution. The polarity

of the external trigger signal is programmable, so that a mode which

begins queue execution on the rising or falling edge can be selected.

Each CCW is read and the indicated conversions are performed until an

end-of-queue condition is encountered. When the next external trigger

edge is detected, queue exe cution begins again automatically. Software

involvement is not needed between trigger events.

When a pause bit is encountered in externally triggered continuous-scan

mode, another trigger event is required for queue execution to continue.

Software involvement is not needed for queue execution to continue

from the paused state.

Some applications need to synchronize the sampling of analog channels

to external events. There are cases when it is not possible to use

software initiation of the queue scan sequence, because interrupt

response times vary. Externally triggered continuous-scan mode is

useful in these cases.

19.10.7.3 Externally Gated Continuous-Scan Mode

The QADC provides external gating for queue 1 only. When externally

gated continuous-scan mode is selected, the input level on the

associated external trigger pin enables and disables queue execution.

The polarity of the external gate signal is fixed so that a high level opens

the gate and a low level closes the gate. Once the gate is open, each

CCW i s read a nd the indicate d conversi ons are performe d until the ga te

is closed. When the gate opens again, queue execution automatically

restarts at the beginning of the queue. Software involvement is not

needed between trigger events. If a pause in a CCW is encountered, the

pause flag does not set, and executio n continue s without pausing.

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Queued Analog-to-Digital Converter (QADC)

The purpose of externally gated continuous-scan mode is to

continuously collect digitized samples while the gate is open and to have

the m ost r ecent samp le s availab l e. It is up to the programmer to ensur e

that the gate is not opened so long that an end-of-queue is reached.

In the event that the queue completes before the gate closes, the CF1

flag will set, and the queue will roll over to the beginning and continue

conv ersion s unt il the gate closes. If th e ga te r emains open an d th e C F1

flag is not clear ed, whe n the qu eue com pletes a second time the TOR1

flag will set and the qu eue will roll-over again. The queue will continue to

execute until the gate closes or the mode is disabled.

If the g ate close s before q ueue 1 compl etes execution , the QADC st ops

and se ts the PF 1 b it to ind ica te an incomp lete queue . T he C WPQ1 field

can be read to determine the last valid conversion in the queue. If the

gate opens agai n, execution of queu e 1 re starts. The start of queue 1 is

always t he first CCW in the CCW tab le. The condition of the g ate is only

sampled after each conversion during queue execution, so closing the

gate fo r a period less than a conversion time interval does not guarantee

the closure will be captured.

19.10.7.4 Periodic Timer Continuous-Scan Mode

The QADC includes a dedicated periodic timer for initiating a scan

sequence on queue 1 and/or queue 2. A programmable timer i nterval

rangi ng fr om 27 to 217 times the QCLK pe riod in binary multi ples can be

selected. The QCLK period is prescaled down from the MCU clock.

When a periodic timer continuous-scan mode is selected, the timer

begins counting. After the programmed interval elapses, the timer

generated trigger event starts the appropriate queue. The QADC

automatically performs the conversions in the queue until an

end-of-queue condition or a pause is encountered. When a pause

occurs, the QADC waits for the periodic interval to expire again, then

continues with the queue. Once EOQ has been detected, the next trigger

event ca uses queue executi on to r estart with the first C CW in the que ue.

The periodic timer generates a trigger event whenever the time interval

elapses. The trigger event may cause queue execution to continue

following a pause or queue completion or may be considered a tr igger

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Queued A nalog -to-Digital Conv erter (QADC)

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overrun. As with all continuous-scan queue operating modes, software

act ion is not n eeded be tween trigge r events. Be cause b oth queu es may

be triggered by the periodic/interval timer, see 19.10.9 Periodic/Interval

Timer for a summary of periodic/interval timer reset conditions.

19.10.8 QADC Clock (QCLK) Generation

Fi gu re 19-4 2 is a block diagram of the clock subsystem. The QCLK

provides the timing for the A/D converter state machine which controls

the timing of the conversion. The QCLK is also the input to a 17-stage

binary divider which implements the periodic/interval timer. To retain the

specified analog conversion accuracy, the QCLK frequency (fQCLK)

must be within the tolerance specified in Table 23-8. QADC Conversion

Specifications (Operating).

Before using the QADC, the prescaler must be initialized with values that

put the QCLK within the specified range. Though most applications

initial ize the prescaler on ce and do not c hange it, write operati ons to th e

prescaler fields are permitted.

Figure 19-42. QADC Clock Subsystem Functions

ATD CONV E RTER

ST AT E MACHINE

272829210 211 212 213 214 215 216 217

PERIODIC TIMER/INTERVAL TIMER

SELECT

BINARY COUNTER

QUEUE 1 AND QUEUE 2 TIM ER

MODE RATE SELECTION

INPUT SAMPLE TIME

FROM CCW SAR

SAR CO NTRO L

PERIODIC/INTERVAL TRIGGER

EVENT FOR Q1 AN D Q2

PRESCALER

SYSTEM CLOCK

QPR[6:0]

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Queued Analog-to-Digital Converter (QADC)

CAUTION: A change in the prescaler value while a conversion is in progress is likely

to corr upt the result. Th erefo re, any presca le r wr ite op eration sho uld b e

done only when both queues ar e in the disabled modes.

To accommodate the wide range of the main MCU clock frequency,

QCLK is generated by a programmable prescale r which divides the

MCU system clock. To allow the A/D conversion time to be maximized

across the spectrum of system clock frequencies, the QADC prescaler

permits the QCLK frequency to be software selectable. The frequency of

QCLK is set with the QPR field in QACR0.

The MCU system clock frequency is the basis of QADC timing. The

QADC requires that the system clock frequency be at least twice the

QCLK frequency.

19.10.9 Periodic/Interval Time r

The QADC periodic/interval timer can be used to generate trigger events

at a programmable interval, initiating execution of queue 1 and/or

queue 2. The periodic/interval timer stays reset under these conditions:

•Both queue 1 and queue 2 are programmed to any mode which

does not use the periodic/interval timer.

•System reset is asserted.

•Stop mode is enabled.

•Debug mode is enabled.

NOTE: Interval timer single-scan mode does not start the periodic/interval timer

until the single-scan enable bit is set.

These conditions will cause a pulsed reset of the periodic/interval timer

during use:

•A queue 1 operating mode change to a mode which uses the

periodic/interval timer, even if queue 2 is already using the timer

•A queue 2 operating mode change to a mode which uses the

periodic/interval timer, provided queue 1 is not in a mode which

uses the periodic/interval timer

•Roll over of the timer

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During stop mode, the periodic/interval timer is held in reset. Because

stop mode cau ses QACR1 and QACR 2 to be reset to 0, a valid period ic

or interval timer mode must be written after leaving stop mode to release

the timer from reset.

When QADC debug mode is entered and a periodic or interval timer

mode is selected, the timer counter is reset after the conversion in

progr ess completes. W hen the periodic or in terval t imer mode has be en

enabl ed (the time r i s countin g), but a trigger even t ha s not been i ssued ,

debug mode takes effect immediately, and the timer is held in reset.

Removal of the QADC debug condition restarts the counter from the

beginning. Refer to 19.5.1 Debug Mode for more in form ation.

19.10.10 Conversion Command Word Table

The conversion command word (CCW) table is 64 half-word (128 byte)

long RAM with 10 bits of each entry implemented. The CCW table is

written by the user and is not modified by the QADC. Each CCW

requests the conversion of one analog channel to a digital result. The

CCW specifies the analog channel number, the input sample time, and

whether the queue is to pause after the current CCW. The 10

implemented bits of the CCW can be read and written. The remaining six

bits are unimp lement ed and re ad as 0s; write operations have no eff ect.

Each location in the CCW table corresponds to a location in the result

wor d table. When a conversi on is com pleted for a CCW entr y, the 10- bit

result is written in the corresponding re sult word entry.

The begi nnin g of que ue 1 i s th e fir st l ocat ion in the C CW tabl e. Th e fir st

loca tion of queue 2 is speci fied by the be ginning of queu e 2 pointer fiel d

(BQ2) in QACR2. To dedicate the entire CCW table to queue 1, place

queue 2 in disabled mode and write BQ2 to 64 or greater. To dedicate

the entire CCW table to queue 2, place queue 1 in disabled mode and

set BQ2 to the first location in the CCW table (CCW0).

Fi gu re 19-4 3 illustrates the operation of the queue stru cture.

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506 Qu eued Analog-to-Digital Converter (QADC) MOTOROLA

Queued Analog-to-Digital Converter (QADC)

Figure 19-43. QADC Conversion Queue Operation

To prepare the QADC for a scan sequence, write to the CCW table to

specify the desired channel conversions. The criteria for queue

execution is established by selecting the queue operating mode. The

queue operating mode determines what type of trigger event starts

queue execution. A trig ger event refe rs to any of th e ways that cause the

QADC to begin executing the CCWs in a queue or subqueue. An

external trigger is only one of the possible trigger events.

A scan sequence may be initiated by:

•A software command

•Expiration of the periodic/interval timer

•An external trigger signal

•An external gated signal (queue 1 only)

BEGINNI N G OF QUEUE 1 00

CHANN EL SELECT,

SAMPL E , HO LD ,

A /D CONVERSION

CONVE RS IO N CO MMA ND RESULT WORD TABLE

WORD (CCW) T ABLE

END OF QUEUE 1

BEGINNI N G OF QUEUE 2

END OF QUEUE 263 63

•

BYP

PIST CHAN

89 [7:6] [5:0]

P — PAUSE AF TER CONVER SI ON

UNTIL NEXT TRIGGER

BYP — BYP ASS BU FFER AMPLI F IER

IST — INPUT S AMPLE TIME

CHAN — CHANNEL NUMBE R AND

END-O F- Q UE UE CO DE

10-BIT CONVERSION COMMAND

WORD FORMA T

0RESULT

[9:0]

10-BIT RESU LT , READ ABLE IN

THREE 16-BIT FORM AT S

00000

15 14 13 12 11 10

RESULT 00000

RIGHT-JUST IFI ED, UNSIGNED RE SUL T

LEFT-JUSTIFIED, UNSIGNED RESULT

LEFT-JUSTIFIED, SIGNED RESULT

RESULT 0 0 0 0 0S

[5:0]

[15:6]

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Queued A nalog -to-Digital Conv erter (QADC)

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MOTOROLA Queued A nalog-to-Digital Converter (QADC) 507

The que ue can be scan ned i n single pass or cont inuous fash i on. When

a single-scan mode is selected, the scan must be engaged by setting the

single-scan enable bit. When a continuous-scan mode is selected, the

queue remains active in the selected queue operating mode after the

QADC completes each queue scan sequence.

During queue execution, the QADC reads each CCW from the active

queue and executes conversions in three stages:

•Initial sample

•Final sample

•Resolution

Duri ng ini tial sample, a buffer ed version of the selected input channel i s

connected to the sample capacitor at the input of the sample buffer

amplifier.

Dur ing the final sampl e pe riod, the sam ple bu ffer amplifier is bypa ssed,

and the multiplexer input charges the sample capacitor directly. Ea ch

CCW specifies a final input sample time of 2, 4, 8, or 16 QCLK cycles.

When an analog-to-digital conversion is complete, the result is written to

the corresponding location in the result word table. The QADC continues

to sequentially execute each CCW in the queue until the end of the

queue is detected or a pause bit is found in a CCW.

When the pause bit is set in the current CCW, the QADC stops execution

of the queue until a new trigger event occurs. The pause status flag bit

is set, and an interrupt may optionally be requested. After the trigger

event occurs, the paused state ends, and the QADC continues to

execute each CCW in the queue until another pause is encountered or

the end of the queue is detected.

An end-of-queue condition occurs when:

•The CC W cha nnel field i s pro gram med with 63 to specif y the e nd

of the queue.

•The end -of-queu e 1 is implied by the beginn ing of que ue 2, which

is specified by the BQ2 field in QACR2.

•The physical end of the queue RAM space defines the end of

either queue.

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Queued Analog-to-Digital Converter (QADC)

When any of the end-of-queue conditions is recognized, a queue

completion flag is set, and if enabled, an in terrupt is requested. These

situations prematurely terminate queue execution:

•Queue 1 is higher in priority than queue 2. When a trigger event

occurs on queue 1 during queue 2 execution, the execution of

queue 2 is suspended by aborting the execution of the CCW in

progress, and queue 1 execution begins. When queue 1 execution

is com plete, q ueue 2 conver sions re start wi th the fir st CCW en try

in queue 2 or the first CCW of the queue 2 subqueue being

executed when queue 2 was suspended. Alternately, conversions

can restart with the aborted queue 2 CCW entry. The RESUME bit

in QACR2 selects where queue 2 begins after suspension. By

choosing to re-execute all of the suspended queue 2 CCWs

(RESUME = 0), all of the samples are guaranteed to have been

taken during the same scan pass. However, a high trigger event

rate f or queue 1 can p revent com pletion of queue 2. If th is occur s,

execution of queue 2 can begin with the aborted CCW entry

(RESUME = 1).

•Any conversion in progress for a queue is aborted when that

queue’s operating mode is changed to disabled. Putting a queue

into the disabled mode does not power down the converter.

•Changing a queue’s operating mode to another valid mode aborts

any conversion in progress. The queue restarts at its beginning

once an appropriate trigger event occurs.

•For low-power operation, the stop bit can be set to prepare the

module for a loss of clocks. The QADC aborts any conversion in

progress when stop mode is entered.

•When the QADC de bug bit is set and the CP U enters ba ckground

debug mode, the QADC freezes at the end of the conversion in

progress. After leaving debug mode, the QADC resumes queue

execution beginning with the next CCW entry. Refer to 19.5.1

Debug Mode for more information.

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19.10.11 Result Word Table

The result word table is a 64 half-word (128 byte) long by 10-bit wide

RAM. An entry is written by the QADC after completing an analog

conversion specified by the corresponding CCW table entry. The result

wor d table can b e read or written , but in nor mal operat ion is on ly read to

obtain analog conversions from the QADC. Unimplemented bits read as

0s and writes have no effect.

NOTE: Although the result RAM can be written, some write operations, like bit

manipulation, may not operate as expected because the hardware

cannot access a true 16-bit value.

While ther e is only one result word tabl e, the half-wor d (16- bit) data can

be accessed in three different data formats:

•Right justified with 0s in the higher order unused bits

•Left justified with th e most significant bit inverted to form a sign bit,

and 0s in the unused lower order bits

•Left justified with 0s in the lower order unused bits

The left justified, signed format corresponds to a half-scale, offset binary,

two’s complement data format. The address used to read the result table

determines the data alignmen t format. All wri te operations to the result

word table are right justified.

19.11 Pin C onnection Considerations

The QADC requires accurate, noise-free input signals for proper

operation. This section discusses the design of external circuitry to

maximize QADC performance.

19.11.1 Analog Reference Pins

No A/D converter can be more accurate than its analog reference. Any

noise in the reference can result in at least that much error in a

conversion. The reference for the QADC, supplied by pins VRH and VRL,

should be low-pass filtered from its source to obtain a noise-free, clean

signal. In many cases, simple capacitive bypassing may suffice. In

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extreme cases, inductors or ferrite beads may be necessary if noise or

RF energy i s present. Series resistan ce is not advisable, becau se there

is an effective DC current required from the reference voltage by the

internal resistor string in the RC DAC array. External resistance may

introduce error in this architecture under certain conditions. Any series

devices in the filter network should contain a minimum amount of DC

resistance.

For accur ate conversion results, the analo g refer ence voltages must be

within the limits defined by VDDA and VSSA, as explained in this

subsection.

19.11.2 Analog Power Pins

The analog supply pins (VDDA and VSSA) define the l imits of the analog

reference voltages (VRH and VRL) and of the analog multiplexer inputs.

Fi gu re 19-4 4 is a diagram of the analog input circuitry.

Figure 19-44. Equivalent Analog Input Circuitry

Because the sample amplifier is powered by VDDA and VSSA, it can

accurate ly transfe r input signal le vels up to but not exceedin g VDDA and

down to but not below VSSA. If the input signal is outside of this range,

the output from the sample amplifier is clipped.

SAMPLE

AMP

16 CHANNELS TOTAL

VRL

VDDA VRH

S/H

RC DAC

COMPARATOR

VSSA

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In addi tio n, VRH an d V RL must be with in the rang e de fined b y VDDA and

VSSA. As long as VRH is less than or equal to VDDA, and VRL is greater

than or equal to VSSA, and the sample amplifier has accurately

transferred the input signal, resolution is ra tiometric within the limits

defined by VRL and VRH. If VRH is greater than VDDA, the sample

amplifier can never transfer a full-scale value. If VRL is less than VSSA,

the sample amplifier can never transfer a 0 value.

Figu re 19-45 sh ow s the re sults of ref eren c e volta ges o utside the range

defi ned by VDDA an d VSSA. At the top of the input signa l range , VDDA is

10 mV lower than VRH. This results in a maximum obtainable 10-bit

conversion value 0x03fe. At the bottom of the signal range, VSSA is

15 mV higher than VRL, resulting in a minimum obtainable 10-bit

conversion value of 0x0003.

Figure 19-45. Errors Resulting from Clipping

0 .020 5.100 5.110

3FA

3FB

3FC

3FD

3FE

3FF

.010 .030 5.120 5.130

10- B IT RES ULT (H E X ADE CIM A L )

INPUTS IN VOLTS (VRH = 5.120 V, VRL = 0 V)

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19.11.3 Conversion Timing Schemes

This section contains some conversion timing examples. Figure 19-46

shows the timing for basic conversions where it is assumed that:

•Q1 begins with CCW0 and ends with CCW3.

•CCW0 has pause bit set.

•CCW1 does not have pause bit set.

•External trigger rising edge for Q1

•CCW4 = BQ2 and Q2 is disabled.

•Q1 RES shows relative result register updates.

Recall that when QS = 0, both queues are disabled; when QS = 8,

queue 1 is active and queue 2 is idle; and when QS = 4; queue 1 is

paused and queue 2 is disabled.

Figure 19-46. External Positive Edge Trigger Mode Timing with Pause

LAST

CCW0 CCW1

CCW2CCW1

CONVERS ION TIME

TIME BETWEEN

QCLK

TRIG1

EOC

CWP

CWPQ1

Q1 RES

LAST

84 8

CCW0

TRIGGERS

= 14 QC LK S CONVERSION TIME

= 14 QC LK S

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A time separator is provided between the triggers and the end of

conversion (EOC). The relationship to QCLK displayed is not

guaranteed.

CWP Q1 and CWPQ2 typi cally lag CWP and only ma tch CWP when the

associated queue is inactive. Another way to view CWPQ1 and CWPQ2

is that these registers update when EOC triggers the write to the result

For the CCW with the pause bit set (CCW0), CWP does not increment

unti l trigger ed. Fo r the CC W with the pause bit clear (CC W1), the CW P

increments with the EOC.

The conversion results Q1 RESx show the result associated with CCWx,

such that R0 represents the result associated with CCW0.

Fi gu re 19-4 7 shows the timing for conversions in externally gated

single-scan with same assumptions in example 1 except:

•No pause bits set in any CCW

•Externally gated single scan mode for Q1

•Single scan enable bit (SSE1) is set.

When the gate closes and opens again, the conversions start with the

first CCW in Q1.

When the gate closes, the active conversion completes before the

queue goes idle.

When Q1 completes, both the CF1 bit sets and the SSE bit clears.

In this mode, the PF1 bit sets to reflect that a gate cl osing occurred

before the queue completed.

Fi gu re 19-4 8 shows the timing for conversions in externally gated

continuous scan mode with the same assumptions as in Figure 19-47.

At the en d of Q1,the completion f lag CF1 sets an d the queue rest arts. If

the queue starts a second time and completes, the trigger overrun flag

TOR1 sets.

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Figure 19-47. Gated Mode, Single Scan Timing

Figure 19-48. Gated Mode, Continuo us Scan Timing

08 0 8 0

CCW3CCW2CCW1CCW0LAST CCW0 CCW1

R3R2R1R0LAST R0 R1

TRIG 1 (GATE)

EOC

CWP

CWPQ1

Q1 RES

SSE

CF1

PF1

LAST CCW0 CCW1 CCW1CCW0 CCW2 CCW3

EOC

CWP

CSPQ1

Q1 RE S

CF1

CCW0CCW3CCW0CCW3CCW2CCW1CCW0LAST

LAST

CCW0 CCW1 CCW2 CCW3

LAST

R0 R1 R2 R3 R2

CCW2

QUEUE RESTART

TOR1

CCW3

TRIG 1 (GATE)

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19.11.4 Analog Supply Filtering and Grounding

Two im portant factors influencing performance in analog integrated

circ uits ar e supp ly filteri ng and grou nding. Gener al ly, digi ta l circui ts use

bypass capacitors on every VDD/VSS pin pair. This applies to analog

subsystems and submodules also. Equally important as bypassing is the

distribution of power and ground.

Analog supplies should be isolated from digital supplies as much as

possible. This necessity stems from the higher performance

requirements often associated with analog circuits. Therefore, deriving

an analog supply from a local digital supply is not recommended.

However, if for cost reasons digital and analog power are derived from a

common regulator, filtering of the analog power is recommended in

addition to the bypassing of the supplies already mentioned. For

example, an RC low pass filter could be used to isolate the digital and

analog supplies when generated by a common regulator. If multiple high

precision analog circuits are locally employed (for example, two A/D

converters), the analog supplies should be isolated from each other as

sharing supplies introduces the potential for interference between

analog circuits.

Grounding is the most important factor influencing analog circuit

performance in mixed signal systems (or in standalone analog systems).

Close attention must be paid not to introduce additional sources of noise

into the analog circuitry. Common sources of noise include ground

loops, inductive coupling, and combining digital and analog grounds

together inappropriately.

The problem of how and when to combine digital and analog grounds

arises from the large transients which the digital ground must handle. If

the digital ground is not able to handle the large transients, the

associ ated current can retu rn to ground throu gh the analog ground. It is

this excess current overflowing into the analog ground which causes

performance degradation by developing a differential voltage between

the true analog ground and the microcontroller’s ground pins. The end

resul t is that th e grou nd obse rved b y the ana lo g circuit i s no lon ger tr ue

ground and thus skews converter performance.

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Two similar approaches to improving or eliminating the problems

associated with grounding excess transient currents involve star-point

ground systems. One approach is to star-point the different grounds at

the power supply origin, thus keeping the ground isolated. Refer to

Fi gu re 19-4 9.

Another approach is to star-point the different grounds near the analog

ground pin on the microcontroller by using small traces for connecting

the non-analog grounds to the analog ground. The small traces are

meant only to accommodate dc differences, not ac transients.

NOTE: This star-point scheme still re quires adequate grounding for digital and

analog subsystems in addition to the star-point ground.

Figure 19-49. Star-Ground at the Point of Power Supply Origin

QADC

SSA

DDA

VDD

VSS

ANALOG POWER SUPPLY

+5 V

+5 V AGND

DIGITAL POWER SUPPLY

+5 V

PGND

PCB

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Other suggestions for PCB layout in which the QADC is employed

include:

•Analog ground must be low impedance to all analog ground points

in the circuit.

•Bypass capacitors should be as close to the power pins as

possible.

•The analog ground should be isolated from the digital ground. This

can be done by cutting a separate ground plane for the analog

ground.

•Non-minimum traces should be utilized for connecting bypass

capacitors and filters to their corresponding ground/power points.

•Minimum distance for trace runs when possible.

19.11.5 Accommodating Positive/Negative Stress Conditions

Positive or negative stress refers to conditions which exceed nominally

defined operating limits. Examples include applying a voltage exceeding

the normal limit on an input (for example, voltages outside of the

suggested supply/reference ranges) or causing currents into or out of

the pin which exceed normal limits. QADC specific considerations are

volta ges gr eater than VDDA or less than VSSA applied to an a nal og in put

which cause excessive curr ents into or out of the input. Refer to

Table 23-6. QADC Absolute Maximum Ratings and Table 23-7.

QADC Electrical Specifications (Operating) for more information on

exact magnitudes.

Either stress conditions can potentially disrupt conversion results on

neighboring inputs. Parasitic devices, associated with CMOS

processes, can cau se a n immedia te disrupti ve influ ence on neighb oring

pins. Common examples of parasitic devices are diodes to substrate and

bipolar devices with the base terminal tied to substrate (VSS/VSSA

ground). Under stress conditions, current injected on an adjacent pin can

cause errors on the selected channel by developing a voltage drop

across the selected channel’s impedances.

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Figure 19-50 show s an active pa rasitic bi pola r NPN tr ansistor when an

input pin is subjected to negative stress conditions. Figure 19-51 shows

positive stress conditions can activate a similar PNP transistor.

Figure 19-50. Input Pin Subjected to Negative Stress

Figure 19-51. Input Pin Subjected to Positive Stress

The cu rrent i nto the p in (IINJN or IINJP) unde r negati ve or p ositive stress is

determined by these equations:

Where:

VStress = Adjustable voltage source

VEB = Parasitic PNP emitter/base voltage

VBE = Pa rasitic NPN base/emitter voltage

RStress = Source impedance (10 kΩ resistor in Figure 19-50 and

Fi gu re 19-5 1 on stressed channel)

RSelected = Source impedance on channel selected for conver sion

RStress

RSelected

ADJACENT

10 kΩ

PIN UNDER

PARASITIC

IINJN

IIn

+STRESS

VStress

DEVICE

VIn

ANn

ANn+1

RStress

RSelected

ADJACENT

10 kΩ

PIN UN DER

PARASITIC

IINJP

IIn

+STRESS

VStress

DEVICE

VIn

VDDA

ANn

ANn+1

IINJN VStress VBE

–()–

RStress

-----------------------------------------------=

IINJP VStress VEB

–VDDA

–

RStress

---------------------------------------------------------------=

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The c urrent into (IIn) the neighboring pin is determined by the KN (curren t

coupl ing rat io) of the pa rasi tic bipol a r transi stor (KN ‹‹ 1) . The IIn can be

expressed by this equation:

IIn = – KN * IINJ

Where:

IINJ is either IINJN or IINJP.

A meth od for minimi zing the impact of str ess conditions on the QA DC is

to strategically allocate QADC inputs so that the lower accuracy inputs

are adjacent to the inputs most likely to see stress condition s.

Also, suitable source impedances should be selected to meet design

goals and minimize the effect of stress conditions.

19.11.6 Analog Input Considerations

The source impedance of the analog signal to be measured and any

intermediate filtering should be considered w hether external

mult iplexing i s u sed or not. F igu re 19-5 2 shows th e conne ction of e ight

typical analog signal sources to one QADC analog input pin through a

separate multiplexer chip. Also, an example of an analog signal source

connected directly to a QADC analog input channel is displayed.

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Figure 19-52. External Multiplexing of Analog Signal Sources

CPCSAMP

CIn = CP + CSAMP

RMUXOUT

RSource2

ANA LOG SIGNAL SOU R CE FILTERING AN D

INTERCONNECT TYPICAL MUX CHIP INTERCONNECT QADC

CFilter

CSource

RFilter2

CMUXIN

0.01 µF1

CMUXOUT

(MC54HC4051, MC74HC4051,

MC54H C4052, MC74HC4052,

MC54HC4053, ETC.)

RSource2

CFilter

CSource

RFilter2

CMUXIN

0.01 µF1

RSource2

CFilter

CSource

RFilter2

CMUXIN

0.01 µF1

RSource2

CFilter

CSource

RFilter2

CMUXIN

0.01 µF1

RSource2

CFilter

CSource

RFilter2

CMUXIN

0.01 µF1

RSource2

CFilter

CSource

RFilter2

CMUXIN

0.01 µF1

RSource2

CFilter

CSource

RFilter2

CMUXIN

0.01 µF1

RSource2

CFilter

CSource

RFilter2

CMUXIN

0.01 µF1

CFilter

RFilter2

0.01 µF1

1. Typical value

2. RFilter, typically 10 kΩ–20 kΩ

Notes:

RSource2

CSource

CPCB

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19.11.7 Analog In put Pins

Analog inputs should have low ac impedance at the pins. Low ac

impedance can be realized by placing a capacitor with good high

frequency characteristics at the input pin of the part. Ideally, that

capacitor should be as large as possible (within the practical range of

capacitors that still have good high-frequency char acteristics). This

capacitor has two effects:

•It helps attenuate any noise that may exist on the input.

•It sources charge during the sample period when the analog signal

source is a high-im pedance source.

Series resistance can be used with the capacitor on an input pin to

imp lemen t a simpl e RC fi lter. Th e m axi mum level of fi lte ring at th e i npu t

pins is application dependent and is based on the bandpass

characteristics required to accurately track the dynamic characteristics

of an inpu t. Simple RC filtering at the pin may be limited by the source

impedance of the tr ansduce r or ci rcuit supplyi ng the ana log sig nal t o be

measured. (See 19.11.7.2 Error Resulting from Leakage.) In some

cases, the si ze of the capacitor at the pin may be very small.

Fi gu re 19-5 3 is a simplified model of an input channel. Refer to this

model in the follow ing discussi on of the int eraction b etween the e xternal

circuitry and the circuitry inside the QADC.

Figure 19-53. Electrical Model of an A/D Input Pin

AMP

RFS3

CSAMP

VICP

SRC

INTERNAL CIRCUIT MODELEXTERN AL FILT ER

VSRC = Source voltage = Internal parasitic capacitance

CSAMP = Sample capacitor

= Filter i mp edance

= Filter capacitor = Internal volt age source duri ng sam ple and hold

SOURCE

RSRC

RSRC = Source impedance

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In Figure 19-53, RF, RSRC, and CF comprise the external filter circuit. CP

is the internal parasitic capacitor. CSamp is the capacitor array used to

sampl e a nd ho ld the input voltage. VI i s an intern al voltag e sou rce u sed

to provide charge to Csamp during sample phase.

The following paragraphs provide a simplified description of the

interaction between the QA DC and the user’s external circuitry. This

circuitry is assumed to be a simple RC low-pass filter passing a signal

from a source to the QADC input pin. These simplifying assu mptions are

made:

•The external capacitor is perfect (no leakage, no significant

dielectric absorption characteristics, etc.).

•All parasitic capacitance associated with the input pin is included

in the value of the external capacitor.

•Inductance is ignored.

•The "on" resistance of the internal switch es is 0 ohms and the "off"

resistance is infinite.

19.11.7.1 Settling Time for the External Circuit

The values for RSRC, RF, and CF in the user's external circuitry

determ ine t he length of time r equired to charge CF to the so urce voltag e

level (VSRC). A t time t = 0, VSRC changes in Figure 19-53 while S1 is

open, disconnecting the internal circuitry from the external circuitry.

Assume that the initial voltage across CF is 0. As CF charges, the voltage

across it is determined by the equation, where t is the total charge time:

As t appr oaches infinity, VCF will equal VSRC. ( This assumes no inte rnal

leakage.) With 10-bit resolution, 1/2 of a count is equal to 1/2048

full-scale value. Assuming worst case (VSRC = full scale), Table 19-14

shows the required time for CF to charge to within 1/2 of a count of the

actual source voltage during 10-bit conversions. Table 19-14 is based

on the RC network in Figure 19-53.

NOTE: The following times are completely independent of the A/D converter

architecture (assuming the QADC is not affecting the charging).

VCF = VSRC (1 –e–t/(RF + RSRC) CF)

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The external circuit described in Table 19-14 is a low-pass filter.

Measur ements of an AC component of the external si gnal m ust take th e

characteristics of this filter into account.

19.11.7.2 Error Resulting from Leakage

A series resistor limits th e current to a pin therefore, input leakage acting

through a large source impedance can degrade A/D accuracy. The

maximum input leakage current is specified in Table 23-7. QADC

Electrical Specifications (Operating) . Input leakage is greater at

hig her o pera ti ng temperatures . In the tempe ratu re ra nge fr om 1 25°C to

50°C, the leakage current is halved for every 8°C to 12°C reduction in

temperature.

Assuming VRH–VRL = 5.12 V , 1 count (with 10-bit resolution)

corresp onds to 5 mV of input voltag e. A typica l inpu t leakage of 200 nA

acting through 10 kΩ of external series resistance results in an error of

0.4 count (2.0 mV). If the source impedance is 100 kΩ and a typical

lea kage of 100 nA is presen t, an error of 2 count s (10 mV ) is in troduced.

In addi tion to internal junction l eakage, extern al le akage (for exampl e, if

external clamping diodes are used) and charge sharing effects with

internal capacitors also contribute to the total leakage current.

Table 19-15 illustrates the e ffe ct of different levels of total leakage on

accuracy for di ffere nt values of sou rce impe dance . The er ror is lis ted in

terms of 10-bit counts.

Table 19-14. External Circuit Sett ling Time to 1/2 LSB

Filter Capacitor (CF)S ou rce Resistanc e (RF + RSRC)

100 Ω1 kΩ10 kΩ100 kΩ

1 µF 760 µs 7.6 ms 76 ms 760 ms

0.1 µF76 µs 760 µs 7.6 ms 76 ms

0.01 µF7.6 µs76 µs 760 µs7.6 ms

0.001 µF 760 ns 7.6 µs 76 µs 760 µs

100 pF 76 ns 760 ns 7.6 µs 76 µs

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CAUTION: Leakage below 200 nA is obtainable only within a limited temperature

range.

19.12 Interrupts

The f our in terrupt lines ar e outputs of the mo dule a nd have no priority o r

arbitration within the module.

19.12.1 Interrupt Operation

QADC inputs can be monitored by polling or by using interrupts. When

interrupts are not needed, the completion flag and the pause flag for

each queue can be monitored in the Status Register (QASR0). In other

words, flag bits can be polled to determine when new results are

available.

Table 19-16 shows the status flag and in terrupt enable bits which

correspond to queue 1 and queue 2 activity.

Table 19-15. Error Resu lting from Input Leakage (IOff)

Source Impedance Leakage Value (10-Bit Conversio ns)

100 nA 200 nA 500 nA 1000 nA

1 kΩ——0.1 counts 0.2 counts

10 kΩ0.2 counts 0.4 cou nts 1 count s 2 count s

100 kΩ2 counts 4 count 10 counts 20 counts

Table 19-16. QADC Status Flags and Interrupt Sources

Queu e Queu e Activity Status

Flag Interrupt

Enable Bit

Queue 1 Result written for last CCW in queue 1 C F1 CI E1

Result written for a CCW with p aus e bit set in

queue 1 PF1 PIE1

Queue 2 Result written for last CCW in queue 2 C F2 CI E2

Result written for a CCW with p aus e bit set in

queue 2 PF2 PIE2

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If interrupts are enabled for an event, the QADC requests interrupt

service when the event occurs. Using interrupts does not require

continuously polling the status flags to see if an event has taken place;

however, status flags must be cleared after an interrupt is serviced, in

order to remove the interrupt request

In both polled and interrupt-driven operating modes, status flags must be

re-enabled after an event occurs. Flags are re-enabled by clearing the

appropriate QASR0 bits in a particular sequence. QASR0 must first be

read, th en 0s must be w ritten to the fla gs that are to be cleared . If a new

event occu rs bet ween the time that th e reg ister is read a nd the time t hat

it is written, the associated flag is not cleared.

19.12.2 Interrupt Sources

The QA DC incl udes f our so urces o f inter rupt r eque sts, each of which i s

separately enabled. Each time the result is written for the last conversion

command word (CCW) in a queue, the completion flag for the

corresponding queue is set, and when enabled, an interrupt is

requested. In the same way, each time the result is wr itten for a CCW

with the pause bit set, the queue pause flag is set, and when enabled,

an interrupt is requested. Refer to Table 19-16.

The pause and complete interrupts for queue 1 and queue 2 have

separate interrupt vector levels, so that each source can be separately

serviced.

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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0  Advance Information
MOTO ROLA External Bus Interface Module (EBI)  5 27
Advance Info rmation — MMC2114, MMC2113, and MMC2112
Section 20. Externa l Bus Interface Modul e (EBI)
1  Contents
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .528
3 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .529
3.1 Data Bus (D[31:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .530
3.2 Show Cycle Strobe (SHS) . . . . . . . . . . . . . . . . . . . . . . . . .530
3.3 Transfer Acknowledge (TA) . . . . . . . . . . . . . . . . . . . . . . . .530
3.4 Transfer Error Acknowledge (TEA) . . . . . . . . . . . . . . . . . .530
3.5 Emulation Mode Chip S e lects (CSE[1:0])  . . . . . . . . . . . . .530
3.6 Transfer Code (TC[2:0]). . . . . . . . . . . . . . . . . . . . . . . . . . .531
3.7 Read/Write (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .531
3.8 Address Bus (A[22:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . .531
3.9 Enable Byte (EB[3:0]). . . . . . . . . . . . . . . . . . . . . . . . . . . . .531
3.10 Chip Sele cts (CS[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . .531
3.11 Output Enable (OE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .531
3.12 Transfer Size (TSIZ[1:0]) . . . . . . . . . . . . . . . . . . . . . . . . . .532
3.13 Processor Status (PSTAT[3:0]) . . . . . . . . . . . . . . . . . . . . .532
4 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .532
5 Operand Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .532
6 Enable Byte Pins (EB[3:0]). . . . . . . . . . . . . . . . . . . . . . . . . . .534
7 Bus Master Cycl es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .534
7.1 Read Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .535
7.1.1 State 1 (X1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .536
7.1.2 Optional Wait States (X2W). . . . . . . . . . . . . . . . . . . . . .536
7.1.3 State 2 (X2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .536
7.2 Write Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .537
7.2.1 State 1 (X1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538
7.2.2 Optional Wait States (X2W). . . . . . . . . . . . . . . . . . . . . .538
7.2.3 State 2 (X2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538
    
  
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External Bus Interface Module (EBI)
20.8 Bus Exception Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .540
20.8.1 Transfer Error Termination. . . . . . . . . . . . . . . . . . . . . . . . .540
20.8.2 Transfer Abort Termination  . . . . . . . . . . . . . . . . . . . . . . . .540
20.9 Emulation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .540
20.9.1 Emulation Chip-Selects (CSE[1:0]) . . . . . . . . . . . . . . . . . .540
20.9.2 Internal Data Transfer Display (Show Cycles) . . . . . . . . . .541
20.9.3 Show Strobe (SHS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .542
20.9.4 Transfer Code (TC[2:0]). . . . . . . . . . . . . . . . . . . . . . . . . . .543
20.9.5 Processor Status (PSTAT). . . . . . . . . . . . . . . . . . . . . . . . .543
20.10 Bus Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .545
20.11 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .545
20.2  Introduction
The external bus interface (EBI) module is responsible for controlling the 
transfer of information between the internal M•CORE local bus and 
external address space. The external bus has 23 address lines and 32 
data lines.
In maste r mode  and emulatio n mo de, the EBI  functions as  a bus maste r 
and allows internal bus cycles to access external resources. In 
single-chip mode, the EBI is active, but the external data bus is not 
avai lable, and no exte rnal  data  or termin ation signal s are  transferred  to 
the internal bus.
The EBI supports data transfers to both 32-bit and 16-bit ports. 
Chip-select channels are programmed to define the port size for specific 
address ranges. When no chip-select is active during an external data 
transfer, the port size is defaults to 32 bits.
The EBI supports a variable length external bus cycle to accommodate 
the access speed of any device. During an external data transfer, the 
EBI drives the address pins, byte enable pins, output enable pins, size 
pins, and read/write pins. Wait states are inserted until the bus cycle is 
terminated by the assertion of the internal transfer acknowledge signal 
by a chip-select channel or by the assertion of the external TA or TEA 
pins. The minimum external bus cycle is one clock.
    
  
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External Bus Interface Module (EBI)

Sig nal Descriptions

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MOTO ROLA External Bus Interface Module (EBI) 529

The E BI may dr ive the address, si ze, and r ead/write pins dur ing inte rnal

data tra nsfer s if show cycles is enab led, but the out put en able and byte

enable pins are not asserted.

Only internal sources can terminate internal data transfers. Chip-select

channels, external TA assertion, and external TEA assertion cannot

terminate internal data transfers.

20.3 Signal Descriptions

Table 20-1 provides an overview of the signal properties which are

discussed in this subsection.

Table 20-1. Signal Properties

Name Port Function Pullup

D[ 3 1: 0 ] PA, PB, PC , PD Data bus —

SHS PE7 Show cycle strobe Acti ve

TA PE6 T rans fer acknowle dge Active

TEA P E 5 Tr ansfer error acknowledge Active

CSE[1:0] PE[4:3] Emulation chip selects Active

TC[2 :0] PE[2:0] Transfe r code A ctive

R/W PF7 Read/write Active

A[2 2 :0 ] PF[6:0], PG, PH Ad dr ess bus Ac ti ve

EB[ 3:0] PI[7:4] Enable byte Active

CS[3 :0] PI [3: 0] C h ip selec ts Activ e

OE —Out put ena ble —

TSIZ[1:0] —Transfer size —

PSTAT[3:0] —Processor status —

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External Bus Interface Module (EBI)

20.3.1 Data Bus (D[31:0] )

The three-state bidirectional data bus (D[31:0]) signals are the

general-purpose data path betwe en the micr ocontr oller uni t ( MCU) and

all other devices.

20.3.2 Show Cycle Strobe (SHS)

In master and emulation modes, show cycle strobe (SHS) is the strobe

for capturing address, controls, and data during show cycles. In master

mode this default functionality can be overridden to make the pin

function as digital I/O. See 12.4.2.6 Por t E Pin Assignment Register

and Table 12-3. Ports A–I Supported Pin Functions. In single-chip

mode, the SHS pin is configured as digital I/O (PE7) by default.

20.3.3 Transfer Acknowledge (TA)

The transfer acknowledge (TA) signal indicates that the external data

transfer is complete. During a read cycle, when the processor

recognizes TA, it latches the data and then terminates the bus cycle.

During a write cycle, when the pr ocessor recognizes TA, the bus cycle

is terminated. TA is an input in master and emulation modes. In

single-chip mode, the TA pin is configured as digital I/O (PE6) by default.

20.3.4 Transf er Error Acknowled ge (TE A)

The transfer error acknowledge (TEA) indicates an error condition exists

for the bus transfer. The bus cycle is terminated and the CPU begins

execution of the access error exception. TEA is an input in master and

emulation modes. In single-chip mode the TEA pin is configured a digital

I/O (PE5) by default.

20.3.5 Emulation Mode Chip Selects (CSE[1:0])

The emulation mode chip select (CSE[1:0]) output signals provide

information for development support. In single-chip mode and master

mode, th ese pins a re configure d as digital I/O (PE4 and PE3 ) by default.

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20.3.6 Transfer Code (TC[2:0])

The transfer code (TC[2:0]) output signals indicate the data transfer

code for the current bus cycle. S ee 20.9.4 Transfer Code (TC[2:0]) for

codes. In single -chip mode and ma ster mode , thes e pins ar e configure d

as digital I/O (PE2, PE1, PE0) by default.

20.3.7 Read/Write (R/W)

The read/write (R/W) output signal indicates the direction of the data

transfer on the bus. A logic 1 indica tes a read fr om a slave device and a

logic 0 indicates a write to a sl ave device.

20.3.8 Address Bus (A[22:0])

The address bus (A[22:0]) output signals provide the address for the

current bus transfer.

20.3.9 Enable Byte (EB[3:0])

The enable byte (EB[3:0]) output signals indicate which byte of data is

valid during external cycles.

20.3.10 Chip Selects (CS[3:0])

The chip select (CS[3:0]) output signals select external devices for

externa l bus transaction s.

20.3.11 Output Enable (OE)

The output enable (OE) signal indicates when an external device can

drive data during external read cycles.

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External Bus Interface Module (EBI)

20.3.12 Transfer Size (TS IZ[1: 0])

TSIZ[1:0] provides an indication of the M•CORE transfer size. See Table

20-2. This function is ena bled by def ault i n maste r mod e and emul ation

mode, and disabled by default in single-chip mode. Selection of this

function is through the Chip Configuration Register (see 4.7.3.1 Chip

Configuration Register). When this feature is disabled, these pins act

as pins INT7 and INT6 of the EPORT module.

20.3.13 Processor Status (PSTAT [3:0])

PSTAT[3:0] provides an indication of the M•CORE processor status.

See Table 20-6 for status indication codes. This function is enabled by

defaul t in emu lati on mo de, and disabl ed by de fault in master mode and

single-chip mode. Selection of this function is through the Chip

Con figura tion R egister . When thi s fe ature is disa bled, the se pins act as

pins INT5, INT4, INT3, and INT2 of the EPORT module.

20.4 Memory Map and Register s

The EBI is not memory-mapped and has no software-accessible

registers.

20.5 Oper an d Tr an sf er

The possible operand accesses for the internal M•CORE bus are:

•Byte

•Aligned upper half-word

•Aligned lower half-word

•Aligned word

No misaligned transfers are supported. The EBI controls the byte,

half-word, or word operand transfers between the M•CORE bus and a

16-bit or 32-bit port. “Port” refers to the width of the data path that an

external device uses during a data transfer. Each port is assigned to

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Operand Transf er

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particular bits of the data bus. A 16-bit port is assigned to pins D[31:16]

and a 32-bit port is assigned to pins D[31:0].

Table 20-2 shows each possible transfer size, alignment, and port width.

The data bytes shown in the table represent external data pins. This data

is multiplexed and driven to the external data bus as shown. The bytes

labeled with a dash are not required; the M•CORE will ignore them on

read transfers, and drive them with undefined data on write transfers.

In the case of a word (32-bit) access to a 16-bit port, the EBI runs two

external bus cycles to complete the transfer. During the first external bus

cycle, the A[1:0] pins are driven low, and the TSIZ[1:0] pins are driven to

indicate word size. During the second cycle, A1 is driven high to

Table 20-2. Data Tr ansfer Cases

Transfer

Size Port

Width

External Pins Data Bus Transfer

TSIZ1 TSIZ0 A1 A0

Byte

D[31:24] ———

32 D[31:24] ———

16 01 —D[23:16] ——

32 —D[23:16] ——

16 10 ——D[31:24] —

32 ——D[15:8] —

16 11 ———D[23:16]

32 ———D[7:0]

Half-word

D[31:24] D[23:16] ——

32 D[31:24] D[23:16] ——

16 10 ——D[31:24] D[23:16]

32 ——D[15:8] D[7:0]

Word 16(1)

1. T he EBI runs tw o cycl es for wor d acce sses to 16 -bi t por ts. The table shows t he data pl ace -

ment for both bus cycles.

0 0 D[31:24] D[23:16] ——

110——D[31:24] D[23:16]

32 0 0 0 D[31:24] D[23:16] D[15:8] D[7:0]

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534 External Bus Interface Module (EB I) MOTOROLA

External Bus Interface Module (EBI)

increment the e xternal address by two bytes, A0 is still d riven low, and

the TSIZ[1:0] pins are driven to indicate half-word size.

Dur ing any word-siz e transfer, the EBI alw ays drives the A[1:0 ] pins lo w

during a word transfer (except on the second cycle of a word to half-word

port transfer in which A1 is incremented).

20.6 Enable Byte Pins (EB[3:0])

The enable byte pins (EB[3:0]) are configurable as byte enables for re ad

and write cycles, or as write enables for write cycles only. The default

function is byte enable unless there is an active chip-select match with

the WE bit set. In all external cycles w hen one or more EB pins are

asserted , the enc oding correspon ds to the external data pi ns to be used

for the transfer as outlined in Table 20-3.

20.7 Bus Master Cycles

In this subsection, e ach EBI bus cycle type is defined in terms of actions

associated with a succession of internal states.

Read or write oper ations may require multiple bus cycles to complete

based on the oper and si ze and targ et port size. Refer to 20.5 Operand

Transfer for more information. In the discussion that follows, it is

assumed that only a single bus cycle is required for a transfer.

In the waveform diagrams (Figure 20-3 through Figure 20-6), data

transfers are related to clock cycles, independent of the clock frequency.

The external bus states are also noted.

Table 20-3. EB[3:0] Assertion Encoding

EB Pin External Data Pins

EB0 D[31:24]

EB1 D[23:16]

EB2 D[15:8]

EB3 D[7:0]

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20.7.1 Read Cycles

During a read cycle, the EBI receives data from an external memory or

peripheral device. During external read cycles, the OE pin is asserted

regar dless of operan d size. See Fi gure 20 -1. Also see F igure 20-3 and

Figure 20-4 for read cycle timing diag rams with and without wait states.

Figure 20-1. Read Cycle Flowchart

1. SET R/W TO READ.

2. DRIVE ADD RE SS ON A[22:0] .

3. DRIVE TSIZ[ 1: 0] PINS FOR OPER AN D SIZE.

4. ASSERT C S IF USED.

1. RECE IV E CS.

2. DECO DE ADD RE S S.

3. PUT DATA ON D[31:16] AND/OR D[15:0].

4. ASSERT TA IF NECESSARY FROM SLAVE DEVIC E.

1. RECEIVE DATA FRO M D[31:16 ] AND/OR D[15:0].

2. DRIVE DATA TO INTERNAL DATA BUS.

3. N EGAT E OE AND EB.

1. REMOVE DATA FROM D[31: 16] AND/OR D[15: 0].

2. NEGATE TA.

1. NEGATE EB AND CS IF USED.

PRESENT DATA

ADDRESS DEVI CE

ACQUIR E DA TA

T ERMINATE C YCL E

TERM INA TE CY CL E

5. ASSERT OE AND EB IF USED.

MMC 2114, MMC2113, AND MMC 2112 EXT ER N AL PER IP HE RAL

START N EXT CYCLE

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External Bus Interface Module (EBI)

20.7.1.1 State 1 (X1)

The EBI drives the address bus. R/W is driven high to indicate a read

cycle. The TSIZ[1:0] pins ar e driven to indicate the number of bytes in

the transfer. TC[2:0] pins are driven to indicate the type of access. CS

may be asserted to drive a device.

Later in state 1, OE is asserted. If the EB pins are not configured as write

enables for this cycle, one or more EB pins are also asserted, depending

on the size and position of the data to be transferr ed.

If eithe r the external TA pin o r in tern al chi p -select tra nsfer ackn owl edge

sign al is asserte d befor e the e nd of state 1, the EBI proce eds to sta t e 2.

20.7.1.2 Optional Wait States (X2W)

Wait states are inse rted until the slave assert s the TA pin or the intern al

chip-select transfer acknowledge signal is asserted. Wait states are

counted in full clocks.

20.7.1.3 State 2 (X2)

One-half clock later in state 2, the selected device puts its information on

D[31:16] and/or D[15:0]. One or both half-words of the external data bus

are driven to the in ternal data bus.

The address bus, R/W, CS, OE, EB, TC, and TSIZ pins remain valid

through state 2 to allow for static memory operation and signal skew.

The slave device asserts data until it detects the negation of OE, after

which it must remove its data within one-half state. Note that the data

bus may not become free until state 1.

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20.7.2 Write Cycles

On a write cycle, the EBI transfers data to an external memory or

peripheral device. See Figure 20-2 . Also see Figu re 20-3 and

Fi gure 20-4 for write cycle timing diagra ms with and without wait st ates.

Figure 20-2. Write Cycle Flowchart

1. DRI VE AD DRESS ON A[22:0].

2. DRI VE TS IZ[1 :0] PINS F OR OPER AN D SIZE .

3. ASSERT CS IF USED.

4. CLEAR R/W TO WRITE.

1. RECEIVE CS.

2. DECODE ADDR ESS.

3. RECEIVE DATA FROM D[31:16] AND/OR D[15:0].

4. ASSERT TA IF NECESSARY FROM SLAVE DEVICE.

1. NEGATE E B.

1. NEGATE TA.

1. NEGATE CS IF USED.

ACCEPT DATA

ADDRESS DEVICE

TERMINATE OUTPUT TRANSFER

TERM INA TE CY CL E

TERMINATE CY CLE

5. ASSERT E B ( ONE OR MORE DEPENDING ON DATA SIZE AND PO SITION.

6. DRI VE DA TA ON D[31: 16] AND/ OR D[15: 0].

2. REMOVE DATA FRO M D[3 1:1 6] AND/OR D[15:0] .

MMC2114, MMC2113, AND MMC2112 EXTERNAL PERIPHERAL

START NEXT CYCLE

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External Bus Interface Module (EBI)

20.7.2.1 State 1 (X1)

The EBI drives the address bus. The TSIZ[1:0] pins are driven to indicate

the number of bytes in the transfer. TC[2:0] pins are driven to indicate

the type of access. CS may be asserted to drive a device. OE is negated.

Later in state 1, R/W is driven low indicating a write cycle. One or more

EB pins are asser ted, dep ending on the size and posi tion of the data to

be transferred.

If eithe r the external TA pin o r in tern al chi p -select tra nsfer ackn owl edge

sign al is asserte d befor e the e nd of state 1, the EBI proce eds to sta t e 2.

20.7.2.2 Optional Wait States (X2W)

Wait states are inse rted until the slave assert s the TA pin or the intern al

chip-select transfer acknowledge signal is asserted. The EBI drives its

data on to data bus lines D[31:16] and/or D[15:0] on the first optional wait

state. Wait states are counted in full clocks.

20.7.2.3 State 2 (X2)

If the data was not already driven during optional wait states, the EBI

drives its data onto D[31:16] and/or D[15:0] in state 2.

EB is negated by the end of state 2. The address bus, data bus, R/W,

CS, TC[2: 0], and TSIZ[1:0 ] pi ns remain valid thro ugh stat e 2 to allow for

static memory operation and signal skew.

Fi gu re 20-3 and Figure 20-4 illustrate external bus master cycles with

and without wait states and show M•CORE bus activity.

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Figure 20-3. Master Mode — 1-Clock Read and Write Cycle

Figure 20-4. Master Mode — 2-Clock Read and Write Cycle

CLKOUT

R/W

A[22: 0 ], TS IZ[1:0]

D[31:0] D1 D2

TA, TEA

READ WRITE

EB[3:0]

X1 X2 X1 X2

EB[3:0] (EB SET

AS WRITE ENAB LE)

CLKOUT

R/W

A[ 2 2 :0 ], TSIZ[1:0 ]

D[31:0] D1 D2

TA, TEA

READ WRITE

EB[3:0] (EB SET

AS WRITE ENABLE)



X1 X2 X2W X2 X1 X2 X2 W X2

EB[3:0]

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20.8 Bus Exception Operation

20.8.1 Transfer Error Termination

Normal bus cycle ter mination re quire s the asser tion of th e T A pin o r th e

internal transfer acknowledge signal. Minimal bus exception support is

provided by transfer error cycle termination. Fo r transfer er ror cycle

termination, the external TEA pin or the internal transfer error

acknowledge signal is asserted. Transfer error cycle termination takes

precedence over normal cycle termination, provided TE A assertion

meets its timing constraints.

The internal bus monitor will assert the internal transfer erro r

acknowledge signal when TA r esponse tim e is too long, based upo n the

BMT[1:0] settings in the Chip Configuration Registers (CCR). See

4.7.3.1 Chip Configuration Register.

20.8.2 Transfer Abort Termination

External bus cycles which are aborted by the M•CORE, still have the

address, R/W, TC[2:0], TSIZ[1:0], CS (if used), OE (reads only), and

SHS (if used) driven to the external pins.

20.9 Emulation Support

20.9.1 Emulation Chip-Selects (CSE[1:0])

While i n emulatio n mode or m aster mode, speci al emulato r chip-selects

(CSE[1:0]) are driven externally to allow internal/external accesses to be

tracked by external hardware See Table 20-4.

In emulation mode, all port registers are mapped externally.

CSE[1:0] = 10 whenever any emulated port registers are addressed.

The lowe r bits of the address bus indicate the register accessed within

the block.

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Em ulation Support

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Accesses to the address space wh ich contains the registers for the

internal modules (except ports) are indicated by CSE[1:0] = 11.

Internal accesses, other than to the specific module control registers, are

indicated by CSE[1:0] = 01. It should be noted that at higher frequencies

writes to external memories emulating the internal memories may

require one clock for read accesses and two clocks for write accesses.

20.9.2 Internal Data Transfer Display (Show Cycles)

Internal data trans fers nor mally occur w ithou t showi ng the inter nal data

bus activity on the external data bus. For debugging purposes, however,

it may be desirable to have internal cycle data appear on the external

bus. These external bus cycles are referred to as show cycles and are

distinguished from normal exter n al cycles by the fact that OE and

EB[3:0] remain negated.

Regardless of whether show cycles are enabled, the EB I drives the

address bus, TC [2:0], TSIZ[ 1:0] and R/W signal s, indicating the intern al

cycle activity. When show cycles are disabled, D[31:0] remains in a high

impedance state. When show cycles are enabled, OE and EB[3:0]

remain negated while the internal data is presented on D[31:0] on the

first clock tick after the termination of the internal cycle.

Show cycles are always enabled in emulation mode. In master mode,

show cycles are disabled coming out of reset and must be enabled by

writing to the SHEN bit in the Chip Configuration Register (CCR).

Table 20-4. Emulation Mode Chip-Select Summary(1)

1. CSE[1:0] is valid only for the duration of v alid bus cycles or reset. Undefined otherwise.

CSE1 CSE0 Indication in Emula tion Mode

Internal access to any register space (excluding ports)

Reset state

(0x00c1_0000:0x00ff_ffff)

Internal access to ports register space

(0x00c0_0000:0x00c0_ffff)

Internal access not covered by CSE encoding = 11, 10

(0x0000_0000:0x00bf_ffff; 0x0100_0000:0x07ff_ffff)

Exte rn al acce ss

(0x8000_ 0000 to 0xffff_ffff)

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NOTE: The PEPA and PCDPA bits in the ports must also be set to 1 to obtain

full visibility. The waveforms shown in Figure 20-5 describe show

cycles.

20.9.3 Show Strobe (SHS)

The sho w strobe (S HS) pin pr ovides an indi cation to an e xterna l device

(emulator or logic analyzer) when to latch address, TC[2:0], TSIZ[1:0],

R/W, CSE, P STAT, and data from the external pins. In master and

emulation modes, show cycle strobe (SHS) is enabled coming out of

reset. In master mode this default functionality can be overridden to

make the pin function as digital I/O.

For any external cycle or show cycle, the SHS pin is driven low to

indica te valid addr ess, T C, T SIZ, R/W, C SE , and PST AT ar e pr esent at

the pins, and driven back high to indicate valid data. The SHS pin is

driven low and back high only once per external bus cycle. See

Fi gu re 20-5 and Figure 20-6.

Figure 20-5. Intern al (Show) Cycle Fo llowed by External 1-Clock Read

A2A1

SHOW DATA

INTERNAL CYCLE EXTERNAL READ

TA, TEA

EB[3:0]

CLKOUT

R/W

A {22 : 0 ], T S IZ[1:0 ]

D[31:0]

SHS

CSE[1:0] 00

D1 D2

X1 X2

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Em ulation Support

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Figure 20-6. Internal (Show) Cycle Fo llowed by External 1-Clock Write

20.9.4 Transfer Code (TC[2:0])

These signals are outputs from a master and inputs to a slave device.

They are enabled by default in emulation mode and can be enabled in

other modes by setting PEPA[2:0] of Port E Pin Assignment Register

(PEPAR). See 12.4.2.6 Port E Pin Assignment Register. These

sign als identify the processor state (su pervisor or user) and the address

space of the current bus cycle. T he space and state are defined in

Table 20-5.

20.9.5 Processor Status (PSTAT)

These sign als are outputs from the CPU and may be applied to external

pin s (I NT[5:2 ]). They ar e en abl ed by defau lt in emu lat ion mode an d can

be enab led in other m odes by setting PS TEN of CCR. See 4.7 .3.1 Chip

Configuration Register. The PSTAT pins indicate the internal state and

events occurring within the core, and may be monitored by a debug

block to condition events, and/or may be reflected off-chip as well.

Table 20-6 shows the definitions of the processor status encoding.

A2A1

SHOW DATA

INTERNAL CYCLE E XTERNAL WRITE

TA, TEA

EB[3:0]

CLKOUT

R/W

A{22:0], TSIZ[1:0]

D[31:0]

SHS

CSE[1:0] 00

D1 D2

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External Bus Interface Module (EBI)

Table 20-5. Transfer Code Definitions

TC[2] TC[1] TC[0] Transfer Type

000

User data access(1)

1. Except lrw a ccesses.

0 0 1 Reserved

010

User inst ruction access(2)

2. Except change of flow re lated instruc tion accesses , i ncludes lrw accesses.

011

User change of flow i ns truction access(3)

3. Change of flo w rel ated i nst ructi on ac cess for ta ken br anches , j umps, and l oopt ins truct ions

(includes tabl e accesses for jmpi, jsr i) .

100

Supervisor data access(1)

1 0 1 Supervisor exception vector access

110

Supervisor instruction access(2)

111

Supervisor change of flow instruction access(3)

Table 20-6. Processor Status Encoding

PST[3] PST[2] PST[1] PST[0] Internal Processor State

0 0 0 0 Execution stalled

0 0 0 1 Execution stalled

0 0 1 0 Exec ute exception

0011Reserved

0 1 0 0 Processo r in STOP, WAIT, or DO ZE state

0 1 0 1 Execution stalled

0 1 1 0 Proc esso r in debug mode

0111Reserved

1000

Launch instruction(1)

1. Except ldm, stm, ldq, stq, hardwar e acceler ator, lrw, change of f low, rte, or rfi instructions.

1 0 0 1 Launch ldm, stm, ldq, or stq

1 0 1 0 Launch hardware accelerator instruction

1 0 1 1 Launch lrw

1 1 0 0 Launch change of program flow instructi on

1 1 0 1 Launch rte or rfi

1110Reserved

1 1 1 1 Launch jmpi or jsri

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Bus Monitor

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20.10 Bus Monitor

The bus monitor can be set to detect excessively long bus access

termination re sponse times. Whenever an undecoded address is

accessed or a peripheral is inoperative, the access is not terminated and

the bus is potentially locked up while it waits for the required response.

The bus monitor monitors the cycle termination response time during a

bus cycle. If the cycle termination response time exceeds a programmed

count, the bus monitor asserts an internal bus error.

The bus monitor monitors the cycle termination response time (in system

clock cycles) by using a programmable maximum allowable response

period. There are four selectable response time periods for the bus

monitor, selectable among 8, 16, 32, and 64 system clock cycles. The

periods are selectable with the BMT[1:0] field in the chip configuration

module CCR (see 4.7.3.1 Chip C onfiguration Register). T he

programmability of the timeout allows for varying external peripheral

response times. The monitor is cleared and restarted on all bus

accesses. If the cycle is not term inated within the selected response

time, a timeout occurs and the bus monitor terminates the bus cycle.

The bus monitor can be configured with the BME bit in the chip

configuration module CCR to monitor only internal bus accesses or both

internal and external bus accesses. Also, the bus monitor can be

disabled during debug mode for both internal and external accesses.

Two external bus cycles are required for a single 32-bit access to a 16-bit

port. If the bus monitor is enabled to mo nitor external accesses, then the

bus monitor views the 32-bit access as two separate external bus cycles

and not as one internal bus cycle.

20.11 Interrupts

The EBI does not generate interrupt requests.

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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0  Advance Information
MOTOROLA Chip Select Module  547
Advance Info rmation — MMC2114, MMC2113, and MMC2112
Section 21. Ch ip Select Modu le
21.1  Contents
21.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .547
21.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .548
21.4 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .549
21.5 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .550
21.6 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .550
21.6.1 Memory Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .550
21.6.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .551
21.7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .556
21.8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .557
21.2  Introduction
The chip select module provides chip enable signals for external 
memory and peripheral devices. The chip selects can also be 
programmed to terminate bus cycles. Up to four asynchronous chip 
select signals are available.  
    
  
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21.3 Features

Features of the chip select module include:

•Reduced system complexity — No e xternal glue logi c req uired for

typical systems if chip selects are used.

•Four prog ram mable asynchr onous active-l o w chip selects

(CS[3:0]) — Chip select s can be indep ende ntly pr ogr amm ed with

various features.

•Con trol for extern al b oot device — CS0 can be enabled at reset to

select an external boot device.

•Fixed base addresses with 8-Mbyte block sizes

•Support for emulating inte rnal memory space — When the EMINT

bit is set in the Chip Configuration Register (CCR), CS1 matche s

only addresses in the internal memory space.

•Support for 16-bit and 32-bit external devices — The external port

size can be programmed to be 16 or 32 bits.

•Programmable write protection — Each chip sele ct address range

can be designated for read access only.

•Programmable access protection — Each chip select address

range can be designated for supervisor access only.

•Write-enable selection — The enable byte pins (EB[3:0]) can be

configured as byte enables (assert on both external read and write

accesses) or write enables (onl y assert on external write

accesses).

•Bus cycle termination — This option allows the chip select logic to

terminate the bus cycle.

•Programmable wait states — To interface with various devices, up

to seven wait states can be programmed before the access is

terminated.

•Programmable extra wait state for write accesses — One wait

state can be adde d to write accesses to allow writing to m emories

that require additional data setup time.

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Block Diagram

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21.4 Blo ck Diag r am

Fi gu re 21-1 shows a programmable asynchronous chip select. All

asynchron ous chi p selects have the same structure. A ll signals used to

generate chip select signals are taken from the internal bu s. Each chip

select has a chip select control register to individually program the chip

select characteristics.

All the chip selects share the same cycle termination generator. The

active chip select for a particular bus cycle determines the number of

wait states pro duced by the cycle termination generator before the cycle

is terminated.

Figure 21-1. Chip Select Block Diagram

DATA

M•CORE LOCAL BUS

ADDRESS

OPT ION CO MPARE

ACCESS

MATCH

CSx

TO CYCLE TERMINATION GENERATOR

CHIP SELECT PAD

CONT ROL REGISTERS

ADDRESS COMP ARE

ATTRIBUTES

CONTROL

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21.5 Signals

Table 21-1 provides an overvi ew of the signals described here.

CS[3:0] are chip-select outputs. CS[3:0] are available for

general-purpose input/output (I/O) when not configured for chip select

operation.

21.6 Memory Map and Register s

Table 21-2 shows the chip select memory map. The registers are

described in 21.6.2 Registers.

21.6.1 Memory Map

Table 21-1. Signal Properties

Na m e Func tion Rese t S t ate Pullup

CS0 Chip se le c t 0 pin 1 A c ti ve

CS1 Chip se le c t 1 pin 1 A c ti ve

CS2 Chip se le c t 2 pin 1 A c ti ve

CS3 Chip se le c t 3 pin 1 A c ti ve

Tab le 21-2. Chip Select Memory Ma p

Address Bits 31–16 Bits 15–0 Access(1), (2)

0x00c2_0000 C SCR0 — Chip Select

Control Register 0 CSCR1 — C hip S e lec t

Control Register 1 S

0x00c2_0004 C SCR2 — Chip Select

Control Register 2 CSCR3 — C hip S e lec t

Control Register 3 S

1. User mode accesses to superv isor-only addr ess locations have no eff ect and resul t in a cycl e termination tran sfer error.

2. S = CPU supervisor mode access only.

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Mem ory Map and Registers

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21.6.2 Registers

The chip programming model consists of four Chip Select Control

Registers (CSCR0–CSCR3), one for each chip select (CS[3:0]).

CSCR0–CSCR3 are read/write always and define the conditions for

asserting the chip select signals.

All the chip select control registers are the same except for the reset

states of the C SEN a nd PS bits i n CS CR0 a nd t he C SE N bit in CSC R1.

This allows CS0 to be enab led at r eset wi th e ither a 16-bit or 32 -bit po rt

size for selecting an external boot device and allows CS1 to be used to

emul ate intern al memory.

Address: 0x00c2_0000 and 0x00c2_0001

Bit 15 14 13 12 11 10 9 B it 8

Read: SO RO PS WWS WE WS2 WS1 WS0

Write:

Reset:00See note11111

Bit 7654321Bit 0

TAEN CSEN

Write:

Reset:0000001See note

= Writes have no effect and t he access ter m inates without a transfer er ro r except ion.

Note: Reset state determined during reset configuration.

Figure 21-2. Chip Select Control Register 0 (CSCR0)

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Address: 0x00c2_0002 and 0x00c2_0003

Bit 15 14 13 12 11 10 9 B it 8

Read: SO RO PS WWS WE WS2 WS1 WS0

Write:

Reset:00111111

Bit 7654321Bit 0

TAEN CSEN

Write:

Reset:0000001See note

= Writes have no effect and t he access ter m inates without a transfer er ro r except ion.

Note: Reset state determined during reset configuration.

Figure 21-3. Chip Select Control Register 1 (CSCR1)

Address: 0x00c2_0004 and 0x00c2_0005

Bit 15 14 13 12 11 10 9 B it 8

Read: SO RO PS WWS WE WS2 WS1 WS0

Write:

Reset:00111111

Bit 7654321Bit 0

TAEN CSEN

Write:

Reset:00000010

= Writes have no effect and t he access ter m inates without a transfer er ro r except ion.

Figure 21-4. Chip Select Control Register 2 (CSCR2)

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Mem ory Map and Registers

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SO — Supervisor-Only Bit

The SO bit restricts user mode access to the address range defined

by the corresponding chip select. If the SO bit is 1, only supervisor

mode acce ss is perm itted. If the S O bit is 0, both sup ervisor and u ser

level accesses are perm itted.

When an access is made to a memory space assigned to the chip

select, the chip select logic compares the SO bit with bit 2 of the

internal tr ansfer code, which indicates whether the access is at the

supervisor or user level. If the chip select logic detects a protection

violation, the access is ignored.

1 = Only supervisor mod e accesses allowed; user mode acce sses

ignored by chip select logic

0 = Supervisor and user mode accesses allowed

RO — Read-Only Bit

The RO bit restricts write accesses to the address range defined by

the corresponding chip sele ct. If the RO bit is 1, only read access is

permitted. If the RO bit is 0, both read and write accesses are

permitted.

When an access is made to a memory space assigned to the chip

select, the chip select logic compares the RO bit with the internal

Address: 0x00c2_00006 and 0x00c2_0007

Bit 15 14 13 12 11 10 9 B it 8

Read: SO RO PS WWS WE WS2 WS1 WS0

Write:

Reset:00111111

Bit 7654321Bit 0

TAEN CSEN

Write:

Reset:00000010

= Writes have no effect and t he access ter m inates without a transfer er ro r except ion.

Figure 21-5. Chip Select Control Register 3 (CSCR3)

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read/write signal, which indicates whether the access is a read

(read/write = 1) or a write (read/write = 0). If the chip select logic

detects a violation (RO = 1 with read/write = 0), the access is ignored.

1 = Only read accesses allowed; write accesses ignored by the

chip select logic

0 = Read and write accesses allowed

PS — Port Size Bit

The PS bit defines the width of the external data port supported by the

chip select as either 16-bit or 32-bit. When a chip select is

progr amm ed as a 16 -bi t p ort, the extern al devi ce must be co nnecte d

to D[ 31:16 ]. For 32- bit accesses t o 16- bit por ts, the e xterna l mem ory

interface initiates two bus cycles and multiplexes data as needed to

complete the data transfer.

1 = 32 bit port

0 = 16 bit port

WWS — Write Wait State Bit

The WWS bit determines if an additional wait state is required for write

cycles. WWS does not affect read cycles.

1 = One additional wait state added for write cycles

0 = No additional wait state added for write cycles

WE — Write Enable Bit

The WE bit defines when the enable byte output pins (EB[3:0]) are

asserted . When WE is 0, EB[3:0] are configu red as byte enab les and

assert for both exter nal rea d and exter nal w rite acce sses. When W E

is 1, EB[3:0] are configured as write enables and assert only for

externa l write accesses.

1 = EB[3:0] configured as write enables

0 = EB[3:0] configured as byte enables

NOTE: T he WE bit has no effect on the EB[3:0] pin function if the chip select is

not a ctive. If th e ch ip se lect is not active , th e E B[3:0] pi n function is byte

enable by default.

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WS[2:0] — Wait States Field

The W S fie ld determine s t he number of w ait states for the chip sel ect

logic to insert before asserting the internal cycle termination signal.

One wait state is equ al to one system clock cycle. If WS is con figured

for zero wait states, then the internal cycle termination signal is

asserted in the clock cycle following the start of the cycle access,

resulting in one-clock transfers. A WS configured for one wait state

means that the inter nal cycle termina tion signal is asserted two clo ck

cycles after the start of the cycle access.

Since the internal cycle termination signal is asserted internally after

the programmed number of wa it states, software can adjust the bus

timing to accommodate the access speed of the e xternal device. With

up to seven possible wait states, even slow devices can be interfaced

with the MCU.

TAEN — Transfer Acknowledge Enable Bit

The TAEN bit deter mines whether the internal cycle termination

signal is asserted by the chip select logic when a ccesses occur to the

address range defined by th e corresponding chip select. When TAEN

is 0, an external device is responsible for asserting the external TA pin

to terminate the bus access. When TAEN is 1, the chip select logic

asserts the internal cycle te rmination signal after a time determined

by the pr ogramme d number of wait sta tes. When TAEN is 1 , external

Table 21-3. Chip Select Wait States Encoding

WS[2:0]

Number of Wait States

WWS = 0 WWS = 1

Read Access Write Access Read Access Wri te Access

0000001

0011112

0102223

0113334

1004445

1015556

1106667

1117778

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logic can still terminate the access before the internal cycle

termination signal is asserted by asserting the external TA pin.

1 = Internal cycle termination signal asserted by chip select logic

0 = Internal cycle termination signal asserted by external logic

CSEN — Chip Select Enable Bit

The CSEN bit enables the chip select logic. When the chip select

function is disabled, the CSx signal is negated high.

1 = Chip select function enabled

0 = Chip select function disabled

21 .7 Fun cti on al Descr iptio n

Each chip se le ct can provide a chip ena ble signal for an exter nal device

and assert the internal bus cycle termination signal.

Setting the CSEN bit in CSCR enables the chip select to provide an

external chip enable signal.

Setting both the CS EN and TAEN bits in CSCR ena bl es the chip select

to generate the internal bus cycle termination signal.

Both the chip select pin assertion a nd the bus cycle termination fun ction

depend on an initial address/option match for activation. During the

matching process, the fixed base address of each chip select is

compared to the corresponding address for the bus cycle to determine

whe ther an ad dress m atch h as occur red . This m atch is f urthe r qu alif ied

by compar ing the int ernal read/wr ite indication and access type wi th the

programmed values in CSCR of each chip select. When the address and

option information match the current cycle, the chip select is activated. If

no chip select m atches the bus cycle inf ormation for the cur rent access,

the chip select logic does not respond in any way.

Only one chip select can be active for a given bus cycle. The

configuration of the active chip sel ect, determined by the wait state

(WS/WWS) fie ld, the port size (PS) field, and the write enable (WE) field,

is used for the access.

NOTE: WWS and WS are valid only if the TAEN bit is 1 for the active chip select.

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Chip Select Module

Interrupts

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MOTO ROLA Chi p Select Module 5 57

When no chip select pin is available, the active chip select can still

terminate the bus cycle. If both the CSEN and TAEN bits are 1 and the

address/ options match the chip select configuration, then the chip select

logic asserts the internal termination signal; the bus cycle terminates

after the programmed number of wait states. If the external TA or TEA

pin is asserted before the chip select logic asserts the internal cycle

termination signal, then the bus cycle is terminated early.

If internal address bit 31 is 0, then the access is internal. If internal

address bit 31 is 1, then the access is external.

NOTE: Chip select logic does not decode internal address bits A[30:25].

21.8 Interrupts

The chip select module does not generate interrupt requests.

Table 21-4. Chip Select Address Range Encoding

Chip Select Block Size Address Range Address Bits Compared

(A[31:23])(1)

1. The chip selects do not decode A[30:25]. Thus, the total 32-Mbyte block size is repeat-

ed/mirrored in external memory space.

CS0 8 MB 0x8000_ 0000–0x807f_ffff 1xxx_xxx0_0

CS1 8 MB 0x8080_0000–0x80ff_ffff 1xxx_xxx0_1(2)

2. If the EMINT bit in the chi p confi guration modul e CCR is set, the n CS1 matches only inter-

nal acce sses to the 8-MB block st arting at address 0 to support emulati on of int ernal mem-

ory. Thus, A[31:23] match 0xxx_xxx0_0.

CS2 8 MB 0x8100_ 0000–0x817f_ffff 1xxx_xxx1_0

CS3 8 MB 0x8180_0000–0x81ff_ffff 1xxx_xxx1_1

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558 Chip Select Module MOTOROLA

Chip Selec t Module

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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0  Advance Information
MOTOROLA JTAG  Test Access Port and OnCE  559
Advance Info rmation — MMC2114, MMC2113, and MMC2112
Section 22. JTAG Test Access Port and OnCE
1  Contents
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .561
3 Top-Level Test Access Port (TAP). . . . . . . . . . . . . . . . . . . . .563
3.1 Test Clock (TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .564
3.2 Test Mode Select (TMS)  . . . . . . . . . . . . . . . . . . . . . . . . . .564
3.3 Test Data Input (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .564
3.4 Test Data Output (TDO). . . . . . . . . . . . . . . . . . . . . . . . . . .564
3.5 Test Reset (TRST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .564
3.6 Debug Event (DE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .564
4 Top-Level TAP Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . .566
5 Instruction Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .567
5.1 EXTEST Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .567
5.2 IDCODE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .568
5.3 SAMPLE/PRELOAD Instruction. . . . . . . . . . . . . . . . . . . . .569
5.4 ENABLE_MCU_ONCE Instruction. . . . . . . . . . . . . . . . . . .569
5.5 HIGHZ Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570
5.6 CLAMP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570
5.7 BYPASS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570
6 IDCODE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .571
7 Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .572
8 Boundary Scan Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .572
9 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .572
10 Non-Scan Chain Operation. . . . . . . . . . . . . . . . . . . . . . . . . . .573
11 Boundary Scan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .573
12 Low-Level TAP (OnCE) Module . . . . . . . . . . . . . . . . . . . . . . .579
13 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .581
13.1 Debug Serial Input (TDI)  . . . . . . . . . . . . . . . . . . . . . . . . . .581
13.2 Debug Serial Clock (TCLK) . . . . . . . . . . . . . . . . . . . . . . . .581
13.3 Debug Serial Output (TDO) . . . . . . . . . . . . . . . . . . . . . . . .581
    
  
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JTAG Test Access Port and OnCE
13.4 Debug Mode Select (TMS). . . . . . . . . . . . . . . . . . . . . . . . .582
13.5 Test Reset (TRST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .582
13.6 Debug Event (DE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .582
14 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .582
14.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .583
14.2 OnCE Controller and Serial Interface. . . . . . . . . . . . . . . . .584
14.3 OnCE Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . .585
14.3 . 1 Interna l Debug Request Input (IDR)  . . . . . . . . . . . . . . .585
14.3.2 CPU Debug Request (DBGRQ). . . . . . . . . . . . . . . . . . .586
14.3.3 CPU Debug Acknowledge (DBGACK). . . . . . . . . . . . . .586
14.3.4 CPU Breakpoint Request (BRKRQ). . . . . . . . . . . . . . . .586
14.3.5 CPU A ddress, Attributes (ADDR, ATTR). . . . . . . . . . . .587
14.3.6 CPU Status (PSTAT). . . . . . . . . . . . . . . . . . . . . . . . . . .587
14.3.7 OnCE Debug Output (DEBUG) . . . . . . . . . . . . . . . . . . .587
14.4 OnCE Controller Registers. . . . . . . . . . . . . . . . . . . . . . . . .587
14.4.1 OnCE Command Register . . . . . . . . . . . . . . . . . . . . . . .588
14.4.2 OnCE Control Register  . . . . . . . . . . . . . . . . . . . . . . . . .590
14.4.3 OnCE Status Register . . . . . . . . . . . . . . . . . . . . . . . . . .594
14.5 OnCE Decoder (ODEC). . . . . . . . . . . . . . . . . . . . . . . . . . .596
14.6 Memory Breakpoint Logic. . . . . . . . . . . . . . . . . . . . . . . . . .596
14.6.1 Memory Address Latch (MAL) . . . . . . . . . . . . . . . . . . . .597
14.6.2 Breakpoint Address Base Registers  . . . . . . . . . . . . . . .597
14.7 Breakpoint Address Mask Registers . . . . . . . . . . . . . . . . .597
14.7.1 Breakpoint Address Comparators . . . . . . . . . . . . . . . . .598
14.7.2 Memory Breakpoint Counters  . . . . . . . . . . . . . . . . . . . .598
14.8 OnCE Tr ace Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .598
14.8.1 OnCE Trace Counter. . . . . . . . . . . . . . . . . . . . . . . . . . .599
14.8.2 Trace Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .600
14.9 Methods of Entering Debug Mode . . . . . . . . . . . . . . . . . . .600
14.9.1 Debug Request During RESET . . . . . . . . . . . . . . . . . . .600
14.9.2 Debug Request During Normal Activity . . . . . . . . . . . . .601
14.9.3 Debug Request During Stop, Doze, or Wait Mode  . . . .601
14.9.4 Software Request During Normal Activity . . . . . . . . . . .601
14.10 Enabling OnCE Trace Mode  . . . . . . . . . . . . . . . . . . . . . . .601
14.11 Enabling OnCE Memo ry Breakpoints. . . . . . . . . . . . . . . . .602
14.12 Pipeline Information and Write-Back Bus Register  . . . . . .602
14.12.1 Program Counter Register. . . . . . . . . . . . . . . . . . . . . . .603
14.12.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .603
    
  
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JTAG Test Acce ss Port and OnCE
Introduction
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MOTOROLA JTAG  Test Access Port and OnCE  561
22.14.12.3 Control State Register . . . . . . . . . . . . . . . . . . . . . . . . . .603
22.14.12.4 Writeback Bus Register . . . . . . . . . . . . . . . . . . . . . . . . .605
22.14.12.5 Processor Status Register . . . . . . . . . . . . . . . . . . . . . . .605
22.14.13 Instruction Address FIFO Buffer (PC FIFO). . . . . . . . . . . .606
22.14.14 Reserved Test Control Registers. . . . . . . . . . . . . . . . . . . .607
22.14.15 Serial Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .607
22.14.16 OnCE Commands  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .608
22.14.17 Target Site Debug System Requirements . . . . . . . . . . . . .608
22.14.18 Interface Connector for JTAG/OnCE Serial Port . . . . . . . .608
22.2  Introduction
The MMC2114, MMC2113, and MM C2112 have two JTAG (Joint Test 
Action Group) TAP (test access port) controllers:
1. A top-level controlle r that allows access to the Boundary S can 
(external pins) Register, IDCODE Register, and Bypass Register
2. A low-level OnCE ( on-chip emulation) controller that allows 
access to the central processor unit (CPU) and debugger-related 
registers
At power-up, only the top-level TAP controller will be visible.  If desired, 
a user can then enable the low-level OnCE controller which will in turn 
disable the top-level TAP controller. The top- level T AP controller will 
remai n disa bled unti l eith er pow er  is remove d and re appli ed  or until the 
test reset signal, TRST, is asserted (logic 0).
The OnCE TAP controller can be enabled in either of two ways:
1. With the top-level TAP controller in its test-logic-reset state:
a. Deassert TRST, test reset (logic1)
b. Assert DE, the debug event (logic 0) for two TCLK, test  clock, 
cycles
2. Shift the ENABLE_MCU_ONCE instruction, 0x3, into the top-level 
TAP controller’s Instruction Register (IR) and pass through the 
TAP controller state update-IR.
Refer to Figure 22-1.
    
  
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562 JTAG Test Access Port and OnCE MOTO ROLA

JTAG Test Access Port and OnCE

Figure 22-1. Top-Level Tap Module and Low-Level (OnCE) TAP Module

TOP-LEVEL

TAP

CONTROLLER

TAP

INSTRUCTION

IDCODE

(SHIFT)

MUX

LOW-LEVEL TDO

BOUNDARY

SCAN

(SHIFT)

MSB

199

LSB

TDO

BYPASS

1 BIT

LOW-LEVEL

TAP (OnCE)

DE TCLK TMS TRS T

MSB

LSB

MUX

OnCE

TAP

CONTROLLER

OnCE CMD

INSTRUCTION

OnCE

DATA

REGISTERS

MUX

TDI

MODULE MODULE

MSB

LSB

IR[3:0] = 0 x 3?

ENABLE_MCU_ONCE

CMD SELECT

IF YES, T HE N B,

SELECT LOW-LEVEL

(OnCE) TDO;

IF NO, THAN A,

SELECT

TOP-LEV EL TDO

TOP-LEVEL TDO

TDO

SELECT

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JTAG Test Acce ss Port and OnCE

Top-Le ve l Test Acce ss Po rt (T AP)

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MOTOROLA JTAG Test Access Port and OnCE 563

22.3 Top-Level Test Access Port (TAP)

These devices provide a dedicated user-accessible test access port

(TAP) that is fully compatible with the IEEE 1149.1 Standard Test

Access Port and Boundary-Scan Architecture. Problems associated with

testing high-density circuit boards have led to development of this

proposed standard under the sponsorship of the Test Te chnology

Committee of IEEE and the Joint Test Action Group (JTAG). The

implementation supports circuit-board test strategies based on this

standard.

The top -level TAP consists o f five dedica ted signal pi ns, a 16-state TA P

controller, an instruction register, and three data registers, a boundary

scan register for mon itoring and contr oll ing t he d evi ce’s externa l pins, a

device identification register, and a 1-bit bypass (do nothing) register.

The top-level TAP provides the ability to:

1. Perform boundary scan (external pin) drive and monitor

operations to test circuitry external to these devices

2. Disable the output pins

3. Read the IDCODE Device Identification Register

CAUTION: Certain precautions must be observed to ensure that the top-level

TAP module does not interfere w ith non-test operation. See

22.10 Non-Scan Chain Operation for details.

The top-level TAP module includes a TAP controller, a 4-bit instruction

boundary scan register, and a 32-bit IDCODE register). The top-level tap

controller and the low-level (OnCE) TAP controller share the external

signals described here.

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JTAG Test Access Port and OnCE

22.3.1 Test Clock (TCLK)

TCLK is a test clock input to synchronize the test logic. TCLK is

independent of the processor clock. It includes an internal pu llup

resistor.

22.3.2 Test Mode Select (TMS)

TMS is a test mode select input (with an internal pullup resistor) that is

sampled on the rising edge of TCLK to sequence the TAP controller’s

state machine.

22.3.3 Test Data Input (T DI)

TDI is a serial test data input (with an internal pullup resistor) that is

sampled on the rising edge of TCLK.

22.3.4 Test Data Output (TDO)

TDO is a three-state test data output that is actively driven in the shift-IR

and shift-DR controller states. TDO changes on the falling edge of

TCLK.

22.3.5 Test Reset (TRST)

TRST is an active low asynchronous reset with an internal pullup resistor

that forces the TAP controller into the test-logic-reset state.

22.3.6 Debug Event (DE)

This is a bidirectional, active-low signal.

As an output, this signal will be asserted for three system clocks,

synchrono us to the rising CLK OUT ed ge, to acknowled ge tha t the CPU

has entered debu g m ode a s a resul t of a debu g r equest or a br eakpo i nt

condition.

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JTAG Test Acce ss Port and OnCE

Top-Le ve l Test Acce ss Po rt (T AP)

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MOTOROLA JTAG Test Access Port and OnCE 565

As an input, this signal provides multiple functions such as:

•The main function is a means of entering debug mode from an

ext ernal command control ler. This signal, when asserte d, caus es

the C PU to fin ish the curr ent in structio n bein g exe cuted, save the

instruction pipeline information, enter debug mode, and wait for

commands to be entered from the serial debug inpu t line. This

input must be asserted for at least three system clocks, sampled

with the rising CLKOUT edge. This function is ignored during

reset. While the processor is in debug mode, this signal is still

sampled but has no effect until debug mode is exited.

•Another input function is to enable OnCE. This is an alternate

method to the ENABLE_MCU_ONCE JTAG command to enable

the OnCE logic to be accessible via the JTAG interfa ce. This input

signal must be asserted low (while in t he test-logic-reset state with

POR/TRST not asserted) for at least two TCLK rising edges. Once

enabled, the OnCE will remain enabled until the next POR or

TRST resets.

•Another input function is as a wake-up event from a low -power

mode of operation. Asynchronously asserting this signal will cause

the clock controller to restart. This signal must be held asserted

unti l th e M•CORE receives thr ee valid rising edges on th e system

clock. Then the processor will exit the low-power mode and go into

debug mode.

NOTE: If used to en ter debug mode , DE must be neg ated before the pr ocessor

exits debu g mo de to pre vent a still low sign al fro m being u nintent ionally

recognized as another debug request. Also, asserting this signal to enter

debug mode may prevent external logic from seeing the processor

output a cknowledgment since the external pullup may not be able to pull

the signal negated before the handshake is asserted. Finally, if using this

signal to enable OnCE outside of reset it may be seen as a request to

enter debug mode.

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JTAG Test Access Port and OnCE

22.4 Top-Level TAP Controller

The top-level TAP controller is responsible for interpreting the sequence

of logical values on the TMS signal. It is a synchronous state machine

that controls the operation of the JTAG logic. The machine’s states are

shown in Figure 22-2. The value shown adjacent to each arc represents

the value of the TMS signal sampled on the rising edge of the TCLK

signal.

The top-level TAP controller can be asynchronously reset to the test-

logic-reset state by asserting TRS T, test reset. A s Figure 22-2 shows,

holding TMS high (to logic 1) while clocking TCLK through at least five

rising edges will also cause the state machine to enter its test-logic-reset

state.



Figure 22-2. Top-Level TAP Controller State Machine

TEST-LOGIC-

RESET

RUN-TEST/IDLE SELECT-DR_SCAN

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

EXIT2-DR

UPDATE-DR

SELECT-IR_SCAN

CAPTURE-IR

SHIFT-IR

EXIT1-IR

PAUSE-IR

EXIT2-IR

UPDATE-IR

111

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Instruction Shift Register

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22.5 Instruction Shift Register

The top- level TAP m odule uses a 4-bit Instru ction Shift Regi ster with no

parity. This register tr ansfers its value to a parallel hold register and

applies an i nstruction on the falling edge of TC LK when the TAP state

machine is in the update-IR state. To load the instructions into the shift

porti on of the reg ister, pl ace the serial data on the TDI pin prior to each

rising edge of TCLK. The MSB of the instruction shift register is the bit

closest to the TDI pin and the LSB is the bit closest to the TDO pin.

Table 22-1 lists the instructions supported along with their opcodes,

IR3–IR0. The last three instructions in the table are reserved for

manufacturing purposes only.

Unused opcodes are currently decoded to perform the BYPASS

operation, but Motorola reserves the right to change their decodings in

the future.

22.5.1 EXTEST Instruction

The external test instruction (EXTEST) selects the Boundary Scan

pins configured as outputs to the preloaded fixed values (with the

SAMP LE/PRE LOAD instructio n) and hel d in the bou ndar y-scan up date

registers. The EXTEST instruction can also configure the direction of

bidirectional pins and establish high-impedance states on some pins.

EXTEST also asserts internal reset for the system logic to force a

predictable internal state while performing external boundary scan

operations.

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22.5.2 IDC ODE Instruct ion

The IDCODE instruction selects the 32-bit IDCODE Register for

connection as a shift path between the TDI pin and the TDO pin. This

instruction allows interrogation of the device to determine its version

number and other part identification data. The IDCODE Register has

been implemented in accordance with the IEEE 1149.1 standard so that

the least significant bit of the shift register stage is set to logic 1 on the

rising edge of TCLK following entry into the capture-DR state. Therefore,

the first bit to be shifted out after selecting the IDCODE Register is

Table 22-1. JTAG Instructions

Instruction IR3–IR0 I ns t r uc tion S um m ary

EXTEST 0000 Selects the Boundary Scan Register while

applying fixed values to output pins and

asserting functional reset

IDCODE 0001 Selects the IDCODE Register for shift

SAMPLE/PRELOAD 0010 Selects the Boundary Scan Register for

shifting, sampling, and preloading without

disturbing functional operation

ENABLE_MCU_ONCE 0011 Instruction to enable the M•CORE TAP

controller

HIGHZ 1001 Selects the Bypass Register while

three-stating all output pins and asserting

functional reset

CLAMP 1100 Selects bypass while applying fixed values to

output pins and asserting functional reset

BYPASS 1111 Selects the Bypass Register for data

operations

Reserved

0100

0110

0101(1)

1000

1. To ex it this instruction, the TRST pin must be asserted or power- on reset.

Instruction for chip manufacturing purpo ses

only

Reserved 0111

1101–1110

1010–1011 Decoded to select the Bypass Register(2)

2. Motorola reserves the right to change the decoding of the unused opcodes in the futur e.

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MOTOROLA JTAG Test Access Port and OnCE 569

always a logic 1. The remaining 31 bits are also set to fixed values on

the rising edge of TCLK following entry into the capture-DR state.

IDCODE is the default instruction placed into the Instruction Shift

IDCODE (data) register will be selected automatically.

22.5.3 SAMPLE/PRELOAD Instruction

The SAMPLE/PRELOAD instruction provides two separate functions.

First, it obtains a sam ple of the syste m da ta and contr ol signa ls prese nt

at the input pins and just prior to the boundary scan cell at the output

pins. This sampling occurs on the rising edge of TCLK in the capture-DR

state w hen an instruction encodi ng of hex 2 is residen t in the Instructi on

Shift Register. The user can observe this sampled data by shifting it

through the Boundary Scan Register to the output TDO by using the

shift-DR state. Both the data capture and the shift operation are

transparent to system operation.

NOTE: The user is responsible for providing some form of external

synchronization to achieve meaningful results because there is no

internal synchronization between TCLK and the system clock.

The second function of the SAMPLE/PRELOAD instruction is to initialize

the Boundary Scan Register update cells before selecting EXTEST or

CLAMP. This is achieved by ignoring the data being shifted out of the

TDO pin while shifting in initialization data. The update-DR state in

conjunction with the falling edge of TCLK can then transfer this data to

the update cells. This data will be applied to the external output pins

when EXTEST or CLAMP instruction is applied.

22.5.4 ENABLE_MCU_ONCE Instruction

The ENABLE_MCU_ONCE is a public instruction to enable the

M•CORE OnCE TAP controller. When the OnCE TAP controller is

enabled, the top-level TAP controller connects the internal OnCE TDO

to the pin TDO and remains in the run-test/idle state . It will remain in this

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stat e until TRST is a sserted. Whi le the OnCE TAP contr oller is enabled,

the top-level JTAG remains transparent.

22.5.5 HIGHZ Instructio n

The HIGHZ instruction is provided as a manufacturer’s optional public

instruction to prevent having to backdrive the output pins during

circuit-board testing. When HIGHZ is invoked, all output drivers,

including the 2-state drivers, are turned off (for example, high

impedance). The instruction selects the Bypass Register. HIGHZ also

asserts internal reset for the system logic to force a predictable internal

state.

22.5.6 CLAMP Instruction

The CLAMP instruction selects the Bypass Register and asserts internal

reset while simultaneously forcing all output pins and bidirectional pins

confi gure d as out puts to th e fixed va lu es that a re prel oad ed and held in

the Boundary Scan Update Register. This instruction enhances test

efficiency by reducing the overall shift path to a single bit (the Bypass

Boundary Scan Register.

22.5.7 BYPASS Instruction

The BYPASS instruction selects the single-bit Bypass Register, creating

a single -bit shift regi ster path from the TDI pin t o the Bypass Re gister to

the TDO pin. This instruction enhances test efficiency by reducing the

overall shift path when a device other than the processor becomes the

device under test on a board design with multiple chips on the overall

IEEE 1149.1 standard defined boundary scan chain. The Bypass

standard so that the shift register state is set to logic 0 on the rising edge

of TCLK following entry into the capture-DR state. Therefore, the first bit

to be shifted out after selectin g the Bypass Register is always a logic 0

(to di fferent iate a part that suppo rts an IDCOD E regi ster from a part th at

supports only the Bypass Register).

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JTAG Test Acce ss Port and OnCE

IDCODE Register

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22.6 IDCODE Register

An IEEE 1149.1 standard compliant JTAG Identification Register

(IDCODE) has been included on these devices.

Bits 31–28 — Version Number (Part Revision Number)

This is equivalent to the lower four bits of the PRN of the chip

iden tification register located in the chip configuration module.

Bits 27–22 — D esign Center

Indicates the Motorola Microcontroller Division

Bits 21–12 — Device Number (Part Identification Number)

Bits 19-12 are equivalent to the P IN of the chip identification register

located in the chip configuration module.

Bits 11–1 — JEDEC ID

Indicates the reduced JEDEC ID for Motorola. JEDEC refers to the

Joint Electron Device Engineering Council. Refer to JEDEC

publication 106-A and chapter 11 of the IEEE 1149.1 standard for

further information on this field.

Bit 0

Differentiates this register as the JTAG IDCODE Register (as

opposed to the Bypass Register), according to the IEEE 1149.1

standard

Bit 31 30 29 28 27 26 25 Bit 24

00000101

Bit 23 22 21 20 19 18 17 Bit 16

11000001

Bit 15 14 13 12 11 10 9 Bit 8

01110000

Bit 7654321Bit 0

00011101

Figure 22-3. IDCODE Register Bit Specification

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22.7 Bypass Register

An IEEE 1149.1 standard-compliant Bypass Register is included. This

Bypass Register to TDO when the BYPASS instruction is selected.

22.8 Boundary Scan Register

An IEEE 1149.1 standard-compliant Boundary Scan Register is

included. The Boundary Scan Register is connected between TDI and

TDO when the EXTEST or SAMPLE/PRELOAD instructions are

sele cted. Thi s r egister capt ures signal p in data on the inp ut pi n s, for ces

fixed values on the output signal pins, and selects the direction and drive

characteristics (a logic value or high impedance) of the bidirection al and

three-state signal pins.

22.9 Restrictions

The test logic is implemented using static logic design, and TCLK can be

stopped i n either a high or low state without loss of data. The system

logic, however, operates on a different system clock which is not

synchroni ze d to T CLK i nter nally. A ny mixed ope rati on r equirin g th e use

of the IEEE 1149.1 standard test logic, in conjunction with system

functional logic that uses both clocks, must have coordination and

synchronization of these clocks done externally.

The control afforded by the output enable signals using the boundary

scan register and the EXTEST instruction re quires a comp atible

circuit-board test environment to avoid device-destructive

configurations. The user must avoid situations in which the output

drivers are enabled into actively driven networks.

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Non-Scan Chain Op eration

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These devices feature a low-power stop mode. The interaction of the

scan chain interface with low-power stop mode is:

1. The TAP controller must be in the test-logic-reset state to either

enter or remain in the low-power stop mode. Leaving the

test-logic-reset state negates the ability to achieve low- power, bu t

does not otherwise affect device functionality.

2. The TCLK input is not blocked in low-power stop mode. To

consume minimal power, the TCLK input should be externally

connected to VDD.

3. The TMS, TDI, TRST pins include on-chip pullup resistors. In

low-power stop mode, these three pins should remain either

unconnected or connected to VDD to achieve minimal power

consumption.

22.10 Non-Scan Chain Operation

Keeping the TAP controller in the test-logic-reset state will ensure that

the scan chain test logic is kept transparent to the system logic. It is

recommended that TMS, TDI, TCLK, and TRS T be pulled up. TRST

could be connected to ground. However, since there is a pullup on

TRST, some amount of current will result. JTAG will be initialized to the

test-l ogic-reset state o n power- up w ithout T RST asserted low due to the

JTAG power-on-reset internal input. The low-level TAP module in the

M•CORE also has the power-on-reset input.

22.11 Boundary Scan

The Boundary Scan Register contains 200 bits. This register can be

connected between TDI and TDO when EXTEST or

SAMPLE/PRELOAD instructions are selected. This register is used for

capturing signal pin data on the input pins, forcing fixed values on the

output signal pins, and selecting the direction and drive characteristics

(a logic value or high impedance) of the bidirectional and three-state

signal pins.

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This IEEE 1149.1 standard-compliant Boundary Scan Register contains

bits for bonded-out and non-bonded signals excluding JTAG signals,

analog signals, power supplies, compliance enable pins, and clock

signals.To maintain JTAG compliance, TEST should be held to logic 0

and D E shoul d be held to logic 1. T hese non- scanned pin s are shown in

Table 22-2.

Table 22-2. List of Pins Not Scanned in JTAG Mode

Pin Name Pin Type

EXTAL Clock/analog

XTAL Clock/analog

VDDSYN Supply

VSSSYN Supply

PQA4–PQA3 and PQA1–PQA0 Analog

PQB3–PQB0 Analog

VRH Supply

VRL Supply

VDDA Supply

VSSA Supply

VDDH Supply

TRST JTAG

TCLK JTAG

TMS JTAG

TDI JTAG

TDO JTAG

DE JTAG com pliance enab le

TEST JTA G com pliance enab le

Vpp Supply

VDDF Supply

VSSF Supply

VSTBY Supply

VDD Supply

VSS Supply

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Bound ary Scan

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Table 22-3 defines the Boundary Scan Register.

•The first column shows bit numbers assigned to each of the

defined as bit 0.

•The second column lists the logical state bit for each pin

alte rnately wi th the read/ wri te direction con trol bit f or that pi n. The

logic state bits are non-inverting with respect to their associated

pins, so that a 1 logical state bit equates to a logical high voltage

on its corresponding pin. A direction control bit value of 1 causes

a pin ’s logi cal state to be expr essed by its logic state bi t, a read of

a pin. A direction control bit value of 0 causes a pin’s logical

voltage to follow the state of its logical state bit, a write to a pin.

Table 22-3. Boundary Scan Register Definition (Sheet 1 of 4)

(Note: Shaded regions indicate optional pins)

Bit Log ical State and Direction

Control Bits for Each Pin Bit Logical State and Direction

Control Bits for Ea ch Pin

0 D 31 logical state 17 A18 direction co ntrol

1 D31 directi on control 18 A19 logical state

2A12 logical state 19 A19 direction co ntrol

3 A12 direction control 20 RSTOUT logic a l sta t e

4A13 logical state 21 RSTOUT direction control

5 A13 direction control 22 A20 logical state

6A14 logical state 23 A20 direction co ntrol

7 A14 dir ection control 24 RESET logi ca l state

8A15 logical state 25 RESET direction control

9 A15 direction control 26 A21 logical state

10 A16 logical state 27 A21 direction co ntrol

11 A16 direction control 28 A 22 logical state

12 A17 logical state 29 A22 direction co ntrol

13 A17 direction control 30 TEA logical state

14 CLKO UT logical state 31 TEA direction control

15 CLKO UT direction control 32 EB0 logical state

16 A18 logical state 33 EB0 direction control

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34 EB1 logi cal state 64 CS2 logical state

35 EB1 direction control 65 CS2 direction control

36 TA logical state 66 INT4 logica l state

37 TA direction control 67 INT4 direction control

38 EB2 logi cal state 68 CS3 logical state

39 EB2 direction control 69 CS3 direction control

40 SHS logical state 70 TC0 logical state

41 SHS direction control 71 TC0 direction control

42 EB3 logi cal state 72 INT3 logical state

43 EB3 direction control 73 IN T3 direction control

44 OE logical state 74 TC1 logical state

45 OE direction control 75 TC1 direction control

46 SS logical state 76 INT2 logi cal state

47 SS direction control 77 INT2 direction control

48 S CK logical state 78 INT1 logi cal state

49 S CK direction control 79 INT1 direction control

50 MISO logical state 80 INT0 logica l state

51 MISO direction control 81 INT0 direct ion control

52 MOSI logical state 82 RXD1 logical state

53 MOSI direction control 83 RXD1 direction control

54 INT7 logical state 84 TXD1 log ical state

55 INT7 direction control 85 TXD1 direction control

56 INT6 logical state 86 RXD2 logical state

57 INT6 direction control 87 RXD2 direction control

58 CS0 logic a l sta t e 88 TC2 logical state

59 CS0 direction control 89 TC2 direction control

60 CS1 logic a l sta t e 90 TX D 2 lo gic a l state

61 CS1 direction control 91 TXD2 direction cont rol

62 INT5 logical state 92 CSE0 logical state

63 INT5 direction control 93 CSE0 direction control

Table 22-3. Boundary Scan Register Definition (Sheet 2 of 4)

(Note: Shaded regions indicate optional pins)

Bit Log ical State and Direction

Control Bits for Each Pin Bit Logical State and Direction

Control Bits for Ea ch Pin

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Bound ary Scan

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94 I COC1_0 logical state 124 D2 logi cal state

95 I COC1_0 direction control 125 D2 direction control

96 CSE1 logi cal state 126 D3 logi cal state

97 CSE1 direct ion control 127 D3 direction control

98 R/W logical state 128 D4 logi cal state

99 R/W direction control 129 D4 direction control

100 ICO C1_1 logical state 130 D5 logi cal state

101 ICO C1_1 direction co ntrol 131 D5 direction control

102 ICO C1_2 logical state 132 D6 logi cal state

103 ICO C1_2 direction co ntrol 133 D6 direction control

104 ICO C1_3 logical state 134 D7 logi cal state

105 ICO C1_3 direction co ntrol 135 D7 direction control

106 ICO C2_0 logical state 136 D8 logi cal state

107 ICO C2_0 direction co ntrol 137 D8 direction control

108 ICO C2_1 logical state 138 D9 logi cal state

109 ICO C2_1 direction co ntrol 139 D9 direction control

110 I CO C2_2 logical state 140 D10 logi cal state

111 ICOC2_2 direction control 141 D10 direct ion cont rol

112 I CO C2_3 logical state 142 D11 logi cal state

113 I CO C2_3 direction co ntrol 143 D11 direct ion control

114 D0 logical state 144 D12 logic al state

115 D0 direction control 145 D12 direction control

116 A0 log ical state 146 D13 logical state

117 A0 direction control 147 D13 direction control

118 A1 log ical state 148 D14 logical state

119 A1 direction control 149 D14 direction control

120 D1 logical state 150 A3 logical state

121 D1 direction control 151 A3 direction control

122 A2 logic a l sta t e 152 A4 logica l stat e

123 A2 direction control 153 A4 direction control

Table 22-3. Boundary Scan Register Definition (Sheet 3 of 4)

(Note: Shaded regions indicate optional pins)

Bit Log ical State and Direction

Control Bits for Each Pin Bit Logical State and Direction

Control Bits for Ea ch Pin

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154 D15 logical state 177 A8 direction control

155 D15 direction control 178 A9 logical state

156 A5 logical state 179 A9 direction control

157 A5 direction control 180 D23 logi cal state

158 D16 logical state 181 D23 direction control

159 D16 direction control 182 A 10 logical state

160 A6 log ical state 183 A10 direction control

161 A6 direction control 184 D24 logi cal state

162 A7 log ical state 185 D24 direction control

163 A7 direction control 186 D25 logi cal state

164 D17 logical state 187 D25 direction control

165 D17 direction control 188 A 11 logical state

166 D18 logical state 189 A11 direction control

167 D18 direction control 190 D26 logical state

168 D19 logical state 191 D16 direction control

169 D19 direction control 192 D27 logical state

170 D20 logical state 193 D27 direction control

171 D20 direction control 194 D28 logical state

172 D21 logical state 195 D28 direction control

173 D21 direction control 196 D29 logical state

174 D22 logical state 197 D29 direction control

175 D22 direction control 198 D30 logical state

176 A8 log ical state 199 D30 direction control

Table 22-3. Boundary Scan Register Definition (Sheet 4 of 4)

(Note: Shaded regions indicate optional pins)

Bit Log ical State and Direction

Control Bits for Each Pin Bit Logical State and Direction

Control Bits for Ea ch Pin

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JTAG Test Acce ss Port and OnCE

Low-Level TAP (OnCE) Modul e

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22.12 Low-Level TAP (OnC E) Module

The low-level TAP (OnCE, on -chip emulation) circuitry provides a

simple, inexpensive debugging interface that allows external access to

the processor’s internal registers and to memory/peripherals. OnCE

capabilities are controlled through a serial interface, mapped onto a

JTAG test access port (TAP) protocol.

Refer to Figure 22-4 for a block diagram of the OnCE.

NOTE: The interface to the OnCE controller and its resources is based on the

TAP defined for JTA G in the IEEE 1149.1 standard.

Figure 22-4. OnCE Block Diagram

Fi gu re 22-5 shows the OnCE (low-level TAP module) data registers.

PIPELINE

INFORMATION

OnCE

CONTROLLER

AND SERIAL

BREAKPOINT

REGISTERS

AND

FIF O

BREAKPOINT

AND TRAC E

INTERFACE

LOGIC

COMPARATORS

TCLK

TDI

TMS

TDO

TRST

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

Figure 22-5. Low-Level (OnCE) Tap Module Data Registers (DRs)

CTL

PSR

WBBR

SQC

IDRE

TME

FRZC

RCB

BCB

RCA

BCA

TDO

LSB 0

LSB

LSB 0

LSB

LSB 0

LSB

LSB 0

LSB

1 BIT

1 BI T

MSB

31 MSB

MSB

127

112

111

MEMORY

BKPT

COUNTER A

(SHIFT)

MBCA

PROGRAM

COUNTER

FIFO A N D

INCREMENT

COUNTER

(SHIFT)

PC FI FO

MSB

BKPT

ADDRESS

BASE

(SHIFT)

BABB

BKPT

ADDRESS

MASK

(SHIFT)

BAMB

(SHIFT)

OSR

(SHIFT)

BYPASS

(SHIFT)

OTC (SHIFT)

MBCB

(SHIFT)

BABA

(SHIFT)

BAMA

(SHIFT)

OCR

(SHIFT)

CPUSCR

BYPASS

PASS-

BYPASS

PASS- OnCE

STATUS

TRACE

COUNTER MEMORY

BKPT

COUNTER

BKPT

ADDRESS

BASE

BKPT

ADDRESS

MASK

CPU

SCAN

CHAIN

OnCE

CONTROL

THROUGH,

BYPASS

THROUGH

LSB

MSB

TDI

MUX

OCMR,

0x3

0x4

0x5 0x6 0x7

0x8 0x9 0xa

0xb

0xc

0xd

0xe 0x1f

RS[4:0] =

RS4–RS0 FROM

ONCE CMD (I NS TR UCTION) RE G ISTER, OCMR

IN FIG URE 22-1 (TEST DATA IN)

(TE ST D ATA OUT)

DETAILED VIEW OF OnCE DATA REGISTERS BLOCK FOUND IN FIGURE 22-1

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JTAG Test Acce ss Port and OnCE

Sig nal Descriptions

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MOTOROLA JTAG Test Access Port and OnCE 581

22.13 Signal Descriptions

The OnCE pin interface is used to transfer OnCE instructions and data

to the OnCE control block. Depending on the particular resource being

accessed, the CPU may need to be placed in debug mode. For

resources outside of the CPU block and contained in the OnCE block,

the processor is not disturbed and may continue execution. If a

processor resource is required, the OnCE controller may assert an

internal debug request (DBGRQ) to the CPU. This causes the CPU to

finish the instruction being executed, save the instruction pipeline

information, enter debug mode, and wait for further commands.

NOTE: Asserting DBGRQ causes the de vice to exit stop, doze, or wait mode

and to enter debug mode.

22.13.1 Debug Serial Input (TDI)

Data and commands are provided to the OnCE controller through the

TDI pin. Data is latched on the rising edge of the TCLK serial clock. Data

is shifted into the OnCE serial port least significant bit (LSB) first.

22.13.2 Debug Serial Clock (TCLK)

The TCLK pin supplies the serial clock to the OnCE control block. The

serial clock provides pulses required to shift data and commands into

and out of the OnCE serial port. (Data is clocked into the OnCE on the

rising edge and is clocked out of the OnCE serial port on the falling

edge.) The debug serial clock frequency must be no greater than

50 percent of the processor clock frequency.

22.13.3 Debug Serial Output (TDO)

Serial data is read from the OnCE block through the TDO pin. Data is

always sh ifted out the OnC E serial po rt LSB first. Data i s clocked out of

the OnCE serial port o n the falling edge of TCLK. TDO is three-statea ble

and is actively driven in the shift-IR and shift-DR control ler states. TDO

changes on the falling edge of TCLK.

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22.13.4 Debug Mode Select (TMS)

The TM S input is used to cycle through states in the OnCE debug

controller. Toggling the TMS pin while clocking with TCLK controls the

transitions through the TAP state controller.

22.13.5 Test Reset (TRST)

The TRST input is used to reset the OnCE controller externally by

placing the OnCE control logic in a test logic reset state. OnCE operation

is disabled in the reset controller and reserved states.

22.13.6 Debug Event (DE)

The D E pin is a bidi rection al open dr ai n pin. A s an inpu t, D E provides a

fast means of entering debug mode from an external command

controller. As an output, this pin provides a fast means of acknowledging

debug mode entry to an external command controller.

The assertion of this pin by a command controller causes the CPU to

finish the current instruction being executed, save the instruction

pipeline information, enter debug mode, and wait for commands to be

entere d from the T DI line. If DE was used to ent er debug mode, then DE

must be negated after the OnCE responds with an acknowledgment and

before sending the first OnCE command.

The assertion of this pin by the CPU acknowledges that it has entered

debug mode and is waiting for commands to be entered from the TDI

line.

22.14 Functional D escription

The on-chip emulation (OnCE) circuitry provides a simple, inexpensive

debugging interface that allows external access to the processor’s

internal registers and to memory/peripherals. OnCE capabilities are

controlled through a serial interface, mapped onto a JTAG test access

port (TAP) protocol. Figure 22-6 shows the components of the OnCE

circuitry.

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Functional Description

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MOTOROLA JTAG Test Access Port and OnCE 583

22.14.1 Operation

An instruction is scanned into the OnCE module through the serial

interface and then decoded. Data may then be scanned in and used to

update a register or resource on a write to the resource, or data

associated with a resource may be scanned out for a read of the

resource.

For accesses to the CPU internal state, the OnCE controller requests the

CPU to enter debug mode via the CPU DBGRQ input. Once the CPU

enters debug mode, as indicated by the OnCE Status Register (OSR),

the processor state may be accessed through the CPU Scan Register.

Figure 22-6. OnCE Controller

CAPTURE — DR

SHIFT — DR

EXIT1 — DR

PAUSE — DR

EXIT2 — DR

UPDATE — DR

SEL ECT — IR

SCAN

CAPTURE — IR

SHIFT — IR

EXIT1 — IR

PAUSE — IR

EXIT2 — IR

UPDATE — IR

SELECT DR-

SCAN

RUN-TEST/IDLE

TEST-LOGIC-RESET

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The OnCE controll er is implem ente d as a 16-state fini te stat e machine,

with a one-to-one correspondence to the states defined for the JTAG

TAP controller.

CPU registers and the contents of memory locations are accessed by

scanning instructions and data into and out of the CPU scan chain.

Requ ired data is accessed by executing the scanned instructions.

Memory locations may be read by scanning in a load instruction to the

CPU that references the desired memory location, executing the load

instruction, and then scanning out the result of the load. Other resources

are accessed in a similar manner.

Resources contained in the OnCE module that do not require the CPU

to be halted for access may be controlled while the CPU is executing and

do not interfere with normal processor execution. Accesses to certain

resources, such as the PC FIFO and the count registers, while not part

of the CPU , may requir e the CP U to be stopped to al low access to avoid

synchronization hazards. If it is known that the CPU clock is enabled and

running no slower than the TCLK input, there is sufficient

synchronization performed to allow reads but not writes of these specific

resources. Debug firmware may ensure that it is safe to access these

resources by reading the OSR to determine the state of the CPU prior to

access. All other cases require the CPU to be in the debug state for

deterministic operation.

22.14.2 OnCE Controller and Serial Interface

Fi gu re 22-7 is a block diagram of the OnC E controller and serial

interface.

The OnCE Command Register (OCMR) acts as th e Instruction R egister

(IR) for the TAP contro ller. All other OnCE resources are treated as data

registers (DR) by the TAP controller. The Command Register is loaded

by seri ally shifting in com mands durin g the TAP contr oller shift- IR state,

and is loaded during the update-IR state. The OCMR selects a OnCE

resour ce to be accessed as a DR during the TAP con troller capture- DR,

shift-DR and update-DR states.

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Functional Description

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MOTOROLA JTAG Test Access Port and OnCE 585

Figure 22-7. On CE Controller and Serial Interface

22.14.3 OnCE Interface Signals

Fi gu re 22-8 shows the interface signals for the OnCE controller.

The following paragraphs describe the OnCE interface signals to other

internal blocks associated with the OnCE controller. These signals are

not available externally, and descriptions are provided to improve

understanding of OnCE operation.

22.14.3.1 Internal Debug Request Input (IDR)

The internal debug request input is a hardware signal which is used in

some implementations to force an immediate debug request to the CPU.

If present and enab le d, it functions i n an identical manner to the contro l

function provided by the DR control bit in the OCR. This input is

maskable by a control bit in the OCR.

OnCE CO MMAND REG IS TE R

OnCE STATUS

AND CONTROL

REGISTERS

ISBKPT

ISTRACE

ISDR

OnCE

DECODER OnC E TAP

CONTROLLER

TDI

TCLK

TDO

TMS

READ CPU

CONTROL/

STATUS

WRITE

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Figure 22-8. OnCE Interface Diagram

22.14.3.2 CPU Debug Request (DBGRQ)

The D BGR Q sig nal is a sserted by the OnCE contr ol logic to requ est the

CPU to enter the debug state. It may be asserted for a number of

different conditions. Assertion of this signal causes the CPU to finish the

current instruction being executed, save the instruction pipeline

information, enter debug mode, and wait for further commands.

Asserting DBGRQ causes the de vice to exit stop, doze, or wait mode.

22.14.3.3 CPU Debug Acknowledge (DBGACK)

The CPU asserts the DBGACK signal upon entering the debug state.

This signal is part of the handshake mechanism between the OnCE

control logic and the CPU.

22.14.3.4 CPU Breakpoint Request (BRKRQ)

The BRKRQ signal is asserted by the OnCE contro l logic to signal that

a breakpoint condition has occurred for the curr ent CPU bus access.

TCK

TDI

TMS

TDO

TRST

OnCE

CONTROLLER

AND

SERIAL

INTERFACE

BREAKPOINT

REGISTERS

AND

COMPARATORS

FIFO

PIPELINE

INFORMATION

BREAKPOINT

AND

TRACE LOGIC

DEBUG

IDR

DBGACK

DBGRQ

BRKRQ

ADDR

ATTR

PSTAT

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22.14.3.5 CPU Address, Attributes (ADDR, ATTR)

The CPU add ress and attri bute inform ation may be us ed in the memory

breakpoint logic to qualify memory breakpoints with access address and

cycle type information.

22.14.3.6 CPU Status (PSTAT)

The trace logic uses the PSTAT signals to qualify trace count

decrements with specific CPU activity.

22.14.3.7 OnCE Debug Output (DEBUG)

The DEBUG signal is used to indicate to on-chip resource s that a debug

session is in progress. Peripherals and other units may use this signal to

modify normal operation for the duration of a debug session. This may

involve the CPU executing a sequence of instructions sole ly for the

purpose of visibility/system control. These instructions are not part of the

normal instruction stream that the CPU would have executed had it not

been placed in debug mode.

This signal is asser ted the f irst tim e the CP U enter s the deb ug state an d

remains asserted until the CPU is released by a write to the OnCE

Command Register with the GO and EX bits set, and a register specified

as either no register selected or the CPUSCR. This signal remains

asserted even though the CPU may enter and exit the debug state for

each instruction executed under control of the OnCE controller.

22.14.4 OnCE Cont roller Registers

This sectio n describes the OnCE controller registers:

•OnCE Command Register (OCMR)

•OnCE Control Register (OCR)

•OnCE Status Register (OSR)

All OnCE registers are addressed by means of the RS field in the OCMR,

as shown in Table 22-4.

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22.14.4.1 OnCE Command Register

The OnCE Command Register (OCMR) is an 8-bit shift register that

receives its serial data fro m the TDI pin. This register corresponds to the

JTAG IR and is loaded when the update-IR TAP controller state is

entered. It holds the 8-bit commands shifted in during the shift-IR

controller state to be used as input for the OnCE decoder. The OCMR

contains fields for controlling access to a OnCE re source, as well as

controlling single-step operation, and exit from OnCE mode.

Although the OCMR is updated during the update-IR TA P controlle r

state, the corresponding resource is accessed in the DR scan sequence

of the TAP controller, and as such, the update-DR state must be

transitioned through in order for an access to occur. In addition, the

update-DR state must also be transitioned through in order for the

single-step and/or exit functionality to be performed, even though the

command appears to have no data resource requirement associated

with it.

R/W — Read/Write Bit

1 = Read the data in the register specified by the RS field.

0 = Write the data associated with the command into the register

specified by the RS field.

GO — Go Bit

When the GO bit is set, the device executes the instruction in the IR

leaves debug mode, executes the instruction, and if the EX bit is

cleared, returns to debug mode immediately after executing the

instruction. The processor resumes normal operation if the EX bit is

set. The GO command is executed only if the operation is a read/write

to eithe r the CPUSCR or to “no re gister selected .” Otherwise, the GO

Bit 7654321Bit 0

R/W G EX RS4 RS3 RS2 RS1 RS0

Figure 22-9. OnCE Command Register (OCMR)

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bit has no effect. The processor leaves debug mode after the TAP

controller update-DR state is entered.

1 = Execute instruction in IR

0 = Inactive (no action taken)

EX — Exit Bit

When the EX bit is set, the processor leaves debug mode and

resumes normal operation until another debug request is generated.

The exit command is executed only if the GO bit is set and the

operation is a read/write to the CPUSCR or a read/write to “no register

selected.” Otherwise, the EX bit has no effect. The processor exits

debug mode after the TAP controller update-DR state is entered.

1 = Leave debug mode

0 = Remain in debug mode

RS4–RS0 — Register Select Field

The RS field defines the source for the read operation or the

destination for the write operation. Table 22-4 shows OnCE register

addresses. Table 22-4. OnCE Register Addressing

RS4–RS0 Regi ster Selected

00000 Reserved

00001 Reserved

00010 Reserved

00011 OTC — OnCE trace counter

00100 MBCA — m em ory breakpoint counter A

00101 MBCB — m em ory breakpoint counter B

00110 PC FIFO — program co unter FIFO and increme nt counter

00111 BABA — Breakpoint Address Base Register A

01000 BABB — Breakpoint Address Base Register B

01001 BAMA — Breakp oint Address Mask Register A

01010 BAMB — Breakp oint Address Mask Register B

01011 CP U S CR — CPU Scan Chain Register

01100 Bypass — no register selected

01101 OCR — OnCE Control Register

01110 OSR — OnC E Status Register

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22.14.4.2 OnCE Control Register

The 32 -bit O nCE Contro l R egister (OCR) selects the even ts that put t he

device in debug mode and enables or disables sections of the OnCE

logic.

01111 Reserved (factory test control register — do not acc ess )

10000 Reserved (MEM_B IST — do not access)

10001–10110 Reserved (bypass, do not access)

10111 Reserved (LSRL, do not access)

11000–11110 Reserved (bypass, do not access)

11111 Bypass

Table 22-4. OnCE Register Addr essing (Continued)

RS4–RS0 Regi ster Selected

Bit 31 30 29 28 27 26 25 Bit 24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 Bit 16

SQC1 SQC0

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 B it 8

Read: DR IDRE TME FRZC RCB BCB4 BCB3 BCB2

Write:

Reset:00000000

Bit 7654321Bit 0

Read: BCB1 BCB0 RCA BCA4 BCA3 BCA2 BCA1 BCA0

Write:

Reset:00000000

= Unim plemented or reserved

Figure 22-10. OnCE Control Register (OCR)

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SQC1 and SQC0 — Sequential Control Field

The S QC fie ld al lows memor y breakpoint B and tra ce occurrences to

be suspended until a qualifying event occurs. Test logic reset clears

the SQC field. See Table 22-5.

DR — Debug Re quest Bit

DR requests the CPU to enter debug mode unconditionally. The PM

bits in the OnCE Status Register indicate that the CPU is in debug

mode. Once the CPU enters debug mode, it returns there even with

a write to the OCMR with GO and EX set until the DR bit is cleared.

Test logic re set clears the DR bit.

Table 22-5. Sequent ial Control Field Settings

SQC1

and SQC0 Meaning

00 Disable sequential control operation. Memory breakpoints and trace

operati on are unaffected by this field.

Suspend norm al trace counter operat ion until a breakpoint condition

occurs for memory breakpoint B. In this mode, memory breakpoint B

occurrences no longer cause breakpoint requests to be generated.

Instead, trace counter comparisons are suspended until the first

mem ory breakpoint B occurrence. After the first mem ory breakp oint

B occurrence, trace counter control is released to perform normally,

assum ing TME is set. This allows a sequence of breakpoint

conditions to be specified prior to trace counting.

Qualify memory breakpoint B matches with a breakpoint occurrence

for memory breakpoint A. In this mode, memory breakpoint A

occurrences no longer cause breakpoint requests to be generated.

Instead, memory breakpoint B comparisons are suspended until the

first memory breakpoint A occurrence. After the first memory

breakpo int A occurrence, memory breakpoint B is enabled to

perform normally. This allows a sequence of breakp oint conditions

to be specified.

Combin e the 01 and 10 qualifications. In this mode, no breakpoint

requests are generated, and trace count operat ion is enabled once

a memo ry breakpoint B occurrence follows a memory breakpoint A

occurrence if TME is set.

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IDRE — Internal Debug Request Enable Bit

The internal debug request (IDR) inpu t to the OnCE control log ic ma y

not be used in all implementations. In some implementations, the IDR

control input may be connected and used as an additional hardware

debug request. Test logic reset clears the IDRE bit.

1 = IDR input enabled

0 = IDR input disabled

TME — Trace Mode Enable Bit

TME enables trace operation. Test logic reset clears the TME bit.

Trace operation is also affected by the SQC field.

1 = Trace operation enabled

0 = Trace operation disabled

FRZC — Freeze Control Bit

This control bit is used in conjunction with memory breakpoint B

registers to select between asserting a breakpoint condition when a

memory breakpoint B occurs or freezing the PC FIFO from further

updates when memory breakpoint B occurs while allowing the CPU to

continue execution. The PC FIFO remains frozen until the FRZO bit

in the OSR is cleared.

1 = Memory breakpoi nt B occurrence freezes PC FIFO and does

not assert breakpoint condition.

0 = M emory breakpoi nt B occurr ence asserts b reakpoint cond ition.

RCB and RCA — Memory Breakpoint B and A Range Control Bits

RCB and RDA condition enabled memo ry breakpoint occurrences

happen when memory breakpoint matches are either within or outside

the range defined by memory base address and mask.

1 = Condition breakpoint on access outside of range

0 = Condition breakpoint on access within range

BCB4–BCB0 and BCA4–BCA0 — Memory Breakp oint B and A Contro l

Fields

The BCB and BCA field s enable mem ory breakpoi nts and qualify the

access attributes to select whether the breakpoint matches are

recognized for read, write, or in struction fetch (program space)

accesses. Test logic reset clears BCB4–BCB0 and BCA4–BCA0.

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Table 22-6. Memory Breakpoint Co ntrol Field Settings

BCB4–BCB0

BCA4–BCA0 Description

00000 B reakpoin t disable d

00001 Qualify match with any access

00010 Qu alify match with any instruction access

00011 Qualify match with any data access

00100 Qu alify match with any change of flow instruc t ion access

00101 Qualify match with any data write

00110 Qualify match with any data read

00111 Reserved

01XXX Reserved

10000 Reserved

10001 Qualify match with any user access

10010 Qualify match with any user instruction access

10011 Qualify match with any user data access

10100 Qualify match with any user change of flow access

10101 Qualify match with any user data write

10110 Qualify match with any user data read

10111 Reserved

11000 Reserved

11001 Qualify match with any supervisor access

11010 Qualify match with any supervisor instruction access

11011 Qualify match with any supervisor data access

11100 Qualify match with any supervisor change of flow access

11101 Qualify match with any supervisor data write

11110 Qualify match with any supervisor data read

11111 Reserved

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22.14.4.3 OnCE Status Register

The 16-bit OnCE Status Register (OSR) indicates the reason(s) that

debug mode was entered and the current operating mode of the CPU.

HDRO — Hardware Debug Request Occurrence Flag

HDRO is set when the p roces sor en ters de bug m ode a s a resu lt of a

hardw are deb ug request fr om the IDR signal or the DE pin. T his bit is

clea red on test log ic reset o r when debug mode i s exited with th e GO

and EX bits set.

DRO — Debug Request Occurrence Flag

DRO is set when the processor enters debug mode and the debug

request (DR) control bit in the OnCE Control Register is set. This bit

is cleared on test logic reset or when debug mode is exited with the

GO and EX bits set.

MBO — Memory Breakpoint Occurrence Flag

MBO is set when a memory breakpoint request has been issued to

the CPU via the BRKRQ input and the CPU enters debug mode. In

some situations involving breakpoint requests on instruction

prefetch es, the CPU may discard the r equest alon g with the prefetch .

In this case, this bit may become set due to the CPU entering debug

mode for another reason. This bit is cleared on test logic reset or

when debug mode is exited with the GO and EX bits set.

Bit 15 14 13 12 11 10 9 B it 8

Read: 0 0 0000HDRODRO

Write:

Reset: 0 0

Bit 7654321Bit 0

Read: MBO SWO TO FRZO SQB SQA PM1 PM0

Write:

Reset:00000000

= Unim plemented or reserved

Figure 22-11. OnCE Status Register (OSR)

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SWO — Software Debug Occurrence Flag

SWO bit is set when the processor enters debug mode of operation

as a result of the execution of the BKPT instruction. This bit is cleared

on test l ogic reset or whe n debug mode is exited w ith the GO and E X

bits set.

TO — Trace Count Occurrence Flag

TO is set when the trace counter reaches zero with the trace mode

enabled and the CPU enters debug mode. This bit is cleared on test

logic reset or when debug mode is exited with the GO and EX bits set.

FRZO — FIFO Freeze Occurrence Flag

FRZO is set when a FIFO freeze occurs. This bit is cleared on test

logic reset or when debug mode is exited with the GO and EX bits set.

SQB — Sequential Breakpoint B Arm Occurrence Flag

SQB is set when sequential operation is enabled and a memory

breakpoint B event has occurred to enable tr ace counter operation.

This bit is cleared on test logic reset or when debug mode is exited

with the GO and EX bits set.

SQA — Sequential Breakpoint A Arm Occurrence Flag

SQA is set when sequential operation is enabled and a memory

breakpoint A event has occurred to enable memory breakpoint B

operation. Thi s bit is clear ed on test log i c reset or whe n deb ug mo de

is exited with the GO and EX bits set.

PM1 and PM0 — Processor Mode Field

These fl ags reflect the processor operating mode. They allow

coordina tion of the OnCE con troller wi th the CPU f or synchroniza tion.

Table 22-7. Processor Mode Field Settings

PM1

and PM0 Meaning

00 Processo r in normal mode

01 Processo r in stop, doze, or wait mode

10 Processor in debug mode

11 Reserved

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22.14.5 OnCE Decoder (ODEC)

The ODEC receives as input the 8-bit command from the OCMR and

status signals from the processor. The ODEC generates all the strobes

required for reading and writing the selected OnCE registers.

22.14.6 Memory Breakpoint Logic

Memory breakpoints can be set for a particular memory location or on

accesses within an address range. The breakpoint logic contains an

inpu t latch for addresses, registers that store the base address and

address mask, comparators, attribute qualifiers, and a breakpoint

counter. Figure 22-12 illustrates the basic functionality of the OnCE

memory breakpoint logic. This logic is duplicated to provide two

independent breakpoint resources.

Figure 22-12. OnCE Memory Breakpoin t Logic

ADDRESS COMPARATOR

DEC

ADDRESS MASK RE GI STE R X

BREAKPOINT COUNTER

MEMORY

BREAKPOINT

QUALIFICATION

MATCH

BC[4:0], RCx

BREAKPOINT

MATCH

OCCURRED

ISBKPTx

COUNT = 0

DSO DSI

DSCK

ADDR[31:0] ATTR

MEMORY ADDRES S LATCH

ADDRESS BAS E REG IS TER X

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Address comparators can be used to determine where a program may

be getting lost or when data is being written to areas which should not

be wr itten. They are also useful in halting a program at a specific point

to ex amine or change register s or mem ory. Using ad dress comparators

to set breakpoints enables the user to set breakpo ints in RAM or ROM

in any operating mode. Memory accesses are monitored according to

the contents of the OCR.

The address comparator generat es a match signal when the address on

the bus matches the address stored in the Breakpoint Address Base

the Breakpoint Address Mask Register. The address match signal and

the access attributes are further qualified with the RCx4–RCx0 and

BCx4–BCx0 control bits. This qualification is used to decrement the

breakpoint counter conditionally if its contents are non-zero. If the

contents are zero, the counter is not decremented and the breakpoint

event occurs (ISBKPTx asserted).

22.14.6.1 Memory Address Latch (MAL)

The MA L is a 32-bit register that latches the address bus on every

access.

22.14.6.2 Breakpoint Address Base Registers

The 32- bit Breakpo int Add ress Base Registers (B ABA and BABB) store

memory breakpoint base addresses. BABA and B ABB can be read or

writ ten thro ugh the OnCE seria l inte rface . Befo re enab ling brea kpoi nts,

the external command controller should load these registers.

22.14.7 Breakpoint Addr ess Mask Registers

The 32-bit Breakpoint Address Mask Registers (BAMA and BAMB)

registers store memory breakpoint base address masks. BAMA and

BA MB can be rea d or writte n through the OnCE ser ial int erface . Bef ore

enabling breakpoints, the external command controller should load

these registers.

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22.14.7.1 Breakpoint Address Comparators

The breakpoint address comparators are not externally accessible. Each

compares the memory address stored in MAL with the contents of BABx,

as masked by BAMx, an d signal s the contro l lo gic when a m atch occurs.

22.14.7.2 Memory Breakpoint Counters

The 16-bit Memory Breakpoint Counter Registers (MBCA and MBCB)

are l oade d with a val ue eq ual to the n umbe r of times, minus one, that a

memory access event should occur before a memory breakpoint is

declared. The memory access event is specified by the RCx4–RCx0 and

BCx4–BCx0 bits in the OCR and by the Memory Base and Mask

Registers. On each occurrence of the memory access event, the

breakpoint counter, i f currently non-zero, is decremented. When the

counter has reached the value of zero and a new occurrence takes

place, the ISBKPTx signal is asserted and causes the CPU’s BRKRQ

input to be asserted. The MBCx can be read or written through the OnCE

serial interface.

Anytime the breakpoint registers are changed, or a different breakpoint

event is selected in the OCR, the breakpoint counter must be written

af terward. Th is assures that the OnCE breakp oint logic is re set and that

no previous events will a ffect the new breakpoint event selected.

22.14.8 OnCE Trace Logic

The OnCE trace logic allows the user to execute instructions in single or

multiple steps before the device returns to debug mode and awaits

OnCE commands from the debug serial port. The OnCE trace logic is

independent of the M•CORE trace facility, which is controlled through

the trace mode bits in the M•CORE Processor Status Register. The

OnCE trace logic block diagram is shown in Figure 22-13.

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22.14.8.1 OnCE Tr ace Counter

The OnC E Trace Coun ter Reg ister (OTC ) is a 16-bi t counter that al lows

more than one instruction to be executed in real time before the device

returns to debug mode. This feature helps the software developer debug

sections of code that are time-critical. The trace counter also enables the

user to count the number of instructions executed in a code segment.

Figure 22-13. OnCE Trace Logic Block Diagram

The OTC Register can be read, written, or cleared through the OnCE

serial interface. If N instructions are to be executed before entering

debug mod e, the trace counter sho uld be loaded with N –1. N must not

equal zero unless the sequential breakpoint control capability is be ing

used. In this case a value of zer o (indicating a single instruction) is

allowed.

A hardware reset clears the OTC.

DEC

OnCE TRACE COUNTER

COUNT = 0

ISTRACE

DSO

DSI

DSCK

END

INSTRUCTION

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22.14.8.2 Trace Operation

To initiate trace mode operation:

1. Load the OTC Register with a value. This value must be non-zero,

unless sequential breakpoint control operation is enabled in the

OCR Register. In this case, a value of zero (indicating a single

instruction) is allowed.

2. Initialize the program counter and Instruction Register in the

CPUSCR with values corresponding to the start location of the

instruction(s) to be executed real-time.

3. Set the T ME bit in the OCR.

4. Release the processor from debug mode by executing the

approp riate co mmand issued b y the external command contro ller.

When debug mode is exited, the counter is decremented after each

execution of an instruction. Interrupts can be serviced, and all

instructions executed (including interrupt services) will decrement the

trace counter.

When the trace counter decrements to zero, the OnCE control logi c

requests that the processor re-enter debug mode, and the trace

occurrence bit TO in the OSR is set to indicate that debug mode has

been requested as a result of the trace count function. The trace counter

allows a minimum of two instructions to be specified for execution prior

to entering trace (specified by a count value of one), unless sequential

breakpo int control oper ation is e nabled in the O CR. In this case, a value

of zero (indicating a single instruction) is allowed.

22.14.9 Methods of Entering Debug Mode

The PM status field in the OS R indicates that the CPU has entered

debug mode. The following paragraphs discuss conditions that invoke

debug mode.

22.14.9.1 Debug Request During RESET

When the DR bit in the OCR is set, assertion of RESET causes the

devi ce to en ter debu g m ode. In this ca se th e d evi ce m ay fetch the rese t

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vector and the first instruction of the reset exception handler but does not

execute an instruction before entering debug mode.

22.14.9.2 Debug Request During Normal Activity

Setting the DR bit in the OCR during normal device activity causes the

device to finish the execution of the current instruction and then enter

debug mode. Note that in this case the device completes the execution

of the current instruction and stops after the newly fetched instruction

enters the CPU instructi on latch. T his process is the sam e for any newl y

fetched instruction, including instructions fetched by interrupt processing

or those that will be aborted by interrupt processing.

22.14.9.3 Debug Request During Stop, Doze, or Wait Mode

Setting the DR bit in the OCR when the device is in stop, doze, or wait

mode (for instance, after execution of a STOP, DOZE, or WAIT

instruction) causes the device to exit the low-power state and enter the

debug mo de. Note tha t in this case, the devi ce completes the executi on

of the STOP, DOZE, or WAIT instruction and halts after the next

instruction enters the instruction latch.

22.14.9.4 Software Request During Normal Activity

Executing the BKPT instruction when the FDB (force debug enable

mode) contr ol bit i n th e Contr ol S tate Reg ister i s se t causes the CP U to

enter debug mode after the instruction following the BKPT instruction

has entered the instruction latch.

22.14.10 Enabling OnCE Trace Mode

When the OnC E trace mo de mechani sm is enable d and the tr ace count

is greater than zero, the trace counter is decremented for each

instruction executed. Completing execution of an instruction when the

trace counter is zero causes the CPU to enter debug mode.

NOTE: Only instructions actually executed cause the trace counter to

decrement. An aborted instruction does not decrement the trace counter

and does not invo ke debug mode.

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22.14.11 Enabling OnCE Memory Breakpoints

When the OnCE memory breakpoint mechanism is enabled with a

breakpoint counter value of zero, the device enters debug mode after

completing the execution of the instruction that caused the memory

breakpoint to occur. In case of breakpoints on instruction fetches, the

breakpoint is acknowledged immediately after the execution of the

fetched instruction. In case of breakpoints on data memory addresses,

the breakpoint is acknowledged after the completion of the memory

access instruction.

22.14.12 Pipeline Infor mation and Write-Back Bus Register

A number of on-chip registers store the CPU pipeline status and are

configured in the CPU Scan Chain Register (CPUSCR) for access by the

OnCE controller. The CPUSCR is used to restore the pipeline and

resume normal device activity upon return from debug mode. The

CPUSCR also provides a mechanism for the emulator software to

access pr ocessor an d m emo ry co ntents. F igure 22- 14 shows th e b lock

diagram of the pipeline information registers contained in the CPUSCR.

Figure 22-14. CPU Scan Chain Register (CPUSCR)

CTL

WBBR

PSR

31 0

015

TDO

TDI

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22.14.12.1 Program Counter Register

The Program Counter Register (PC) is a 32-bit latch that stores the value

in the CPU program counter when the device enters debug mode. The

CPU PC is affected by operations performed during debug mode and

must be restored by the external command controller when the CPU

returns to normal mode.

22.14.12.2 Instruction Register

The Instruction Register (IR) provides a mechanism for controlling the

debug session. The IR al lows the debug control block to execute

selected instructions; the debug control module provides single-step

capability.

When scan-out begins, the IR contains the opcode of the next instruction

to be e x ecuted at th e time debu g mo de w as e nter ed. Thi s opco de m ust

be saved i n orde r to resu me nor mal execu ti on at the po int debug mode

was entered.

On scan-in, the IR can be filled with an opcode selected by debug control

software in preparation for exiting debug mode. Selecting appropriate

instructions allows a user to examine or change memory locations and

processor registers.

Once the debug session is complete and normal processing is to be

resumed, the IR can be loaded with the value originally scanned out.

22.14.12.3 Control State Register

The Control State Register (CTL) is used to set control values when

debug mode is exited. On scan-in, this register is used to control sp ecific

aspects of the CPU. Certain bits re flect internal processor status and

should be restored to their original values.

The CTL regi ster is a 16-b it latch that stores th e value of certai n internal

CPU state variables befor e debug mode is entered. This register is

affected by the operations performed during the debug session and

should be restored by the external command controller when returning

to normal mode. In addition to saved internal state variables, the bits are

used by emulation firmware to control the debug process.

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Rese rved bits represe nt the internal pr ocessor state. Restor e these bits

to their original value after a debug session is completed, for example,

when a OnCE command is issued with the GO and EX bits set and not

igno red. Set these bits to 1s while instructions are executed during a

debug session.

FFY — Feed Forward Y Operand Bit

This control bit is used to force the content of the WBBR to be used

as the Y operand value of the first instruction to be executed following

an update of the CPUSCR. This gives the debug firmware the

capability of updating processor register s by initializing the WBBR

with the desired value, setting the FFY bit, and executing a MOV

instruction to the desired register.

FDB — Force Debug Enable Mode Bit

Setting this control bit p laces t he proce ssor in debug enable mode. In

debug enable mode, execution of the BKPT instruction as well as

recogniti on of the BRKRQ i nput causes t he processor to enter debug

mode, as if the DBGRQ input had been asserted.

SZ1 and SZ0 — Prefetch Size Field

This control field is used to drive the CPU SIZ1 and SIZ0 outputs on

the first instruction pre-fetch caused by issuing a OnCE command

with the GO bit set and not ignored. It should be set to indicate a 16-bit

size, for example, 0b10. This field should be restored to its original

value after a debug session is completed, for example, when a OnCE

command is issued with the GO and EX bits set and not ignored.

Bit 15 14 13 12 11 10 9 B it 8

Read: RSVD RSVD RSVD RSVD RSVD RSVD RSVD FFY

Write:

Reset: 0

Bit 7654321Bit 0

Read: FDB SZ1 SZ0 TC2 TC1 TC0 RSVD RSVD

Write:

Reset:000000

Figure 22-15. Control State Register (CTL)

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TC — Prefetch Transfer Code

This control field is used to drive the CPU TC2–TC0 outputs on the

first instruction pre-fetch caused by issuing a OnCE command with

the GO bi t set and not ignored . It should typically be set to indicate a

supervisor instruction access, for example, 0b110. This field should

be restored to its original value after a debug session is completed,

for example, when a OnCE command is issued with the GO and EX

bits set and not ignored.

22.14.12.4 Writeback Bus Register

The Writeback Bus Register (WBBR) is a means of passing operand

information between the CPU and the external command controller.

Whenever the external command controller needs to read the contents

of a register or memory location, it forces the device to execute an

instruction that brings that information to WBBR.

For example, to read the content of processor register r0, a MOV r0,r0

instruction is executed, and the resul t value of the instruction is latched

into th e WB BR. The contents o f W BBR can then be de l ivered ser ial ly to

the external command controller.

To update a processor resource, this register is initialized with a data

value to be written, and a MOV instruction is executed which uses this

value as a write-ba ck data value. The FFY bit in the CTL Register forces

the value of the WBBR to be substituted for the normal source value of

a MOV instruction, thus allowing updates to processor registers to be

performed.

22.14.12.5 Processor Status Register

The Pr ocessor Status Register (PSR ) is a 32-bit latch used to read or

write the M•CORE Processor Status Register. Whenever the external

command controller needs to save or modify the contents of the

M•CORE Processor Status Register, the PSR is used. This register is

affected by the operations performed in debug mode and must be

restored by the external command controller when returning to normal

mode.

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22.14.13 Instruction Address FIFO Buffer (PC FIFO)

To ease debugging activity and keep track of program flow, a

first-in-first-out (FIFO) buffer stores the addresses of the last eight

instruction change-of-flow prefetches that were issued.

The FIFO is a circular buffer containing eight 32-bit registers and one

3-bit counter. All the registers have the same address, but any read

access to the FIFO address causes the counter to increment and point

to the next FIFO register. The registers are serially available to the

external command controller through the common FIFO address.

Fi gu re 22-1 6 shows the structure of the PC FIFO.

Figure 22-16. OnCE PC FIFO

PC FIF O REG ISTER 0

TDO

TCLK

INSTRUCTION FETCH ADDRESS

CIRCULAR

BUFFER

POINTER

PC FIF O REG ISTER 1

PC FIF O REG ISTER 2

PC FIF O REG ISTER 3

PC FIF O REG ISTER 4

PC FIF O REG ISTER 5

PC FIF O REG ISTER 6

PC FIF O REG ISTER 7

PC FIF O SHIF T REGI ST ER

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The FIFO is not affected by operations performed in debug mode,

except for incrementing the FIFO pointer when the FIFO is read. When

debug mode is entered, the FIFO counter points to the FIFO register

containing the address of the oldest of the eight change-of-flow

pre-fetches. The first FIFO read obtains the oldest address, and the

following FIFO reads re turn the other addresses from the oldest to the

newest, in order of execution.

To ensure FIFO coherence, a complete set of eight reads of the FIFO

must be performed. Each read increments the FIFO pointer, causing it

to point to the next location . After eight reads, the po inter points to the

same location as before the start of the read procedure.

The data in the FIFO is not affected by the read operations.

22.14.14 Reserved Test Control Registers

The reserved test control registers (MEM_BIST, FTCR, and LSRL) are

reserved for factory testing.

CAUTION: To prevent dam a ge to the device or system, do not access these

registers during normal operation.

22.14.15 Serial Protocol

The serial protocol permits an efficient means of communication

between the OnCE external command controller and the MCU. B efore

starting any debugging activity, the external command controller must

wait for an acknowledgment that the device has entered debug mode.

The external command controller communicates with the device by

sending 8-bit commands to the OnCE Command Register and 1 6 to 128

bits of data to one of the other OnCE registers. Both commands and data

are sent or received LSB first. After sending a command, the external

command controller must wait for the processor to acknowledge

execution of certain commands before it can properly access another

OnCE Register.

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22.14.16 OnCE Commands

The OnCE commands can be classified as:

•Read commands (the device delivers the required data)

•Write comma nds (the device recei ve s data and writes the data in

one of the OnCE registers)

•Commands with no associated data transfers

22.14.17 Target Site Debug System Requirements

A typical debug environment consists of a target system in which the

MCU resides in the user-defined hardware.

The external command controller acts as the medium between the MCU

target system and a ho st computer. The external command controller

circuit acts as a serial debug port driver and host computer comm and

interpreter. The controller issues commands based on the host

computer inputs from a user interface program which communicates

with the user.

22.14.18 Interface Connector for JTAG/OnCE Serial Port

Fi gu re 22-1 7 shows the recommended connector pinout and interface

requirements for debug controllers that access the JTAG/OnCE port.

The connector has two rows o f seven pins with 0 .1-inch center-to-center

spacing between pins in each row and each column.

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Figure 22-17. Recomme nded Connector Interface to JTAG/OnCE Port

TDI

TDO

TCLK

GPIO/SI

TARGET_RESET

KEY (N o Connect)

GND

910

10 kΩ

TOP VIEW

11 12

13 14

TARGE T VDD

GPIO/SO

(0.1 INCH CENTER- TO-CENTER)

10 kΩ

TARGET VDD

TARGE T VDD

TRST 10 kΩ

TMS 10 kΩ

Note: GPIO/SI and GPIO/SO are not required for OnCE operation at this time.

These pins can be used for high-speed downloads with a recommended interface.

10 kΩ

WIRED OR WITH TA RG ET RESE T

CIRCUIT. THIS SIGNAL MUST BE

ABLE TO ASSERT/MON ITOR SYST EM

RESET.

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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0 Advance Inform ation

MOTOROLA Preliminary Electrical Specifi cations 611

Preliminary

Advance Inf o rmation — MMC2 114, MMC2113, and MMC2112

Section 23. Preliminary Electrical Specifications

23.1 Contents