Q0 Ay SC eS: RS WIC OCG oa. CGlil m@ DESCRIPTION The MB91106 is a standard single-chip microcontroller constructed around the 32-bit RISC CPU (FR* family) core with abundant I/O resources and bus control functions optimized for high-performance/high-speed CPU processing for embedded controller applications. To carry out hi-speed performance of CPU instructions, instruction/data ROM of 64 Kbytes and RAM of 2 Kbytes are embedded in the MB91106. The MB91101 is optimized for applications requiring high-performance CPU processing such as navigation systems, high-performance FAXs and printer controllers. *: FR Family stands for FUJITSU RISC controller. m@ FEATURES FR CPU * 32-bit RISC, load/store architecture, 5-stage pipeline * Operating clock frequency: Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz) * General purpose registers: 32 bits x 16 * 16-bit fixed length instructions (basic instructions), 1 instruction/1 cycle * Memory to memory transfer, bit processing, barrel shifter processing: Optimized for embedded applications * Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems supporting high level languages * Register interlock functions, efficient assembly language coding * Branch instructions with delay slots: Reduced overhead time in branch executions (Continued) m@ PACKAGE 100-pin Plastic LQFP 100-pin Plastic QFP (FPT-100P-M05) (FPT-100P-MO06)MB91106 Series (Continued) * Internal multiplier/supported at instruction level Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles * Interrupt (push PC and PS): 6 cycles, 16 priority levels External bus interface * Clock doublure: Maximum internal bus 50 MHz, maximum external bus 25 MHz operation * 25-bit address bus (32 Mbytes memory space} * 8/16-bit data bus * Basic external bus cycle: 2 clock cycles * Chip select outputs for setting down to a minimum memory block size of 64 Kbytes: 6 * Interface supported for various memory technologies DRAM interface (area 4 and 5) * Automatic wait cycle insertion: Flexible setting, from 0 to 7 for each area * Unused data/address pins can be configured us input/output ports * Little endian mode supported (Select 1 area from area 1 to 5) DRAM interface * 2 banks independent control (area 4 and 5) * Normal mode (double CAS DRAM)/high-speed page mode (single CAS DRAM)/Hyper DRAM * Basic bus cycle: Normally 5 cycles, 2-cycle access possible in high-speed page mode * Programmable waveform: Automatic 1-cycle wait insertion to RAS and CAS cycles * DRAM refresh CBR refresh (interval time configurable by 6-bit timer) Self-refresh mode * Supports 8/9/10/12-bit column address width * 2CAS/1WE, 2WE/1CAS selective DMA controller (DMAC) * 8 channels * Transfer incident/external pins/internal resource interrupt requests * Transfer sequence: Step transfer/block transfer/burst transfer/continuous transfer * Transfer data length: 8 bits/16 bits/32 bits selective * NMl/interrupt request enables temporary stop operation UART * 3 independent channels * Full-duplex double buffer * Data length: 7 bits to 9 bits (non-parity), 6 bits to 8 bits (parity) * Asynchronous (start-stop system), CLK-synchronized communication selective * Multi-orocessor mode * Internal 16-bit timer (U-TIMER) operating as a proprietary baud rate generator: Generates any given baud rate * Use external clock can be used as a transfer clock * Error detection: Parity, frame, overrunMB91106 Series (Continued) 10-bit A/D converter (successive approximation conversion type) 10-bit resolution, 4 channels * Successive approximation type: Conversion time of 5.6 us at 25 MHz * Internal sample and hold circuit * Conversion mode: Single conversion/scanning conversion/repeated conversion/stop conversion selective * Start: Software/external trigger/internal timer selective 16-bit reload timer * 3 channels * Internal clock: 2 clock cycle resolution, divide by 2/8/32 selective Other interval timers * 16-bit timer: 3 channels (U-TIMER) * PWM timer: 4 channels * Watchdog timer: 1 channel Bit search module First bit transition 1 or 0 from MSB can be detected in 1 cycle Interrupt controller * External interrupt input: Non-maskable interrupt (NMI), normal interrupt x 4 (INTO to INT3) * Internal interrupt incident: UART, DMA controller (DMAC), 10-bit A/D converter, 16-bit reload-timer, PWM timer, U-TIMER and delayed interrupt module * Priority levels of interrupts are programmable except for non-maskable interrupt (in 16 steps) Others * Reset cause: Power-on reset/software reset/external reset * Low-power consumption mode: Sleep mode/stop mode * Clock control Gear function: Operating clocks for CPU and peripherals are independently selective Gear clock can be selected from 1/1, 1/2, 1/4 and 1/8 (or 1/2, 1/4, 1/8 and 1/16) (However, operating frequency for peripherals is less than 25 MHz.) * Packages: LQFP-100 and QFP-100 CMOS technology (0.35 um) * Power supply voltage: 3.3V+0.3V m@ PRODUCT LINEUP Parameter Part number MB91106 MB91V106 Classification N(mask HOM products) __| (for evaluation and development) IROM size 63 Kbytes _ IRAM size _ 64 Kbytes CROM size 64 Kbytes _ CRAM size _ 64 Kbytes RAM size 2 Kbytes 5 Kbytes I$ Other Under trial manufacture Under developmentMB91106 Series m@ PIN ASSIGNMENT (Top view) 04d/0DYL/OIS L4d/FDYL/0OS ZAd/EWVddO/09S CAd/ZOUL/LIS PAd/EOHL/LOS Gd/WddO/ZIS 94d/evdd0/ZOS DlW/Z4d/0Vd00 Zad/LNova gad/oMovd gad/LOaYa vad/oosyd CAd/ZOS/ELNI ZAd/LOS/ELNI SSA LX Ox DA, Lod/-LNI OAd/OLNI Oad/OSVH Ladoso Zad/HOSO ead/OMa zdoa/rad/ISVH HUTTE 6871 A24/EOP0/P70 67 1 A23/P67 66[ 1 A22/P66 71[= +) AVss/AVRL 65[-] Vss 70[-1 AVRH 64[7 1 A21/P65 63[-1 A20/P64 62[- 1 A19/P63 61{[--1 A18/P62 60/71 A17/P61 591 1 A16/P60 58-1 A15/P57 57] A14/P56 56[-1 A13/P55 55[-1 A12/P54 54-71 A11/P53 53[-1] A10/P52 52,1 A09/P51 51/1 A08/P50 757] AN3 74(-_] AN2 73[7] AN1 727] ANO 69[-] AVcc OrTAMTMONDMOrAM TKHNMTMNONR ODMDrrrrrrrr rT rNNANNANA TUDO UU ou UUUUUUOL ag Be 5 jal aa Oo = 9 On x & oy t LO co ontanr a Oo fo} ao DIE OND Sr& eeeee azo Seen =rlt LM|FISAAFIS= Jk Cra> Col S HAE ss BRBRORS skp g8S8ao eae s DAE 8 BUBBBRS se s8osas fakes UUUUUUUUUUUUUUUUU UU Lvd/LO0V 9d/90V Std/SOV vrd/vov erd/eov evd/cov LPd/lOV 20, Ovd/00V Zd/Ld SSA, 9gd/0ed Gd/6cd ved/8ed d/Zed cd/9ed Ld/aed 0d/red Led/ed 9ed/ec Gd/led ved/0ed ed/610 ocd/81d bd/ZtC (FPT-100P-M05)MB91106 Series (Top view) (5 nN ae eefies =9 cebigni gent? manor ~TNOOq, pan Otonan aoWww OO SS Sr SQ OEGY Sah YLGGLLYZOKRELO ancr ASGmMMGOoOEALVSES AtEE Sor BEErreqOONOHO OrfZ22>x%xKx>22000O0OnHDHDH SanmnontH9ANromnmnontH8as HFADAMDADADADAIANAADDODDNDDOM OH CSOH/PB2 co 1 80 [4 SOO/TRG1/PF1 DW0/PB3 C2 79 FFG SIO/TRGO/PFO RAS1/PB4/EOP2 [] 3 78 FE AN3 CS1L/PB5/DREQ2E| 4 77 FE AN2 CS1H/PB6/DACK2 -] 5 76 FF ANI DW1/PB7 ee 75 FFG ANO Vec Cc] 7 74 [[7 AVss/AVRL CLK/PA6 Cy] 8 73 [7] AVRH CS5/PA5 Cy] 9 72 [] AVcc CS4/PA4 Cc] 10 71 [7 A24/EOPO/P70 CS3/PA3/EOP 1 Cy] 11 70 [_] A23/P67 CS2/PA2 Cy] 12 69 [_] A22/P66 CS1/PA1 Cy] 13 68 [_] Vss CSO0/PAO Cy] 14 67 [_] A21/P65 NMI Cy] 15 66 [_] A20/P64 Vec Cc] 16 65 [_ A19/P63 RST Cy] 17 64 [] A18/P62 Vss Cy] 18 63 [7] A17/P61 MDO Cy} 19 62 [_] A16/P60 MD1 Cc] 20 61 [7) A15/P57 MD2 LC} 21 60 [ A14/P56 RDY/P80 Cy 22 59 [7] A13/P55 BGRNT/P81 C=} 23 58 [7] A12/P54 BRQ/P82 [=] 24 57 [7 A11/P53 RD/P83 Cy} 25 56 [-_] A10/P52 WRO/P84 Cy} 26 55 [-] A09/P51 WR1/P85 C=} 27 54 [77] A08/P50 D16/P20 C=} 28 53 [= A07/P47 D17/P21 C=} 29 52 [77 A06/P46 D18/P22 CJ] 30 51 [-- A0d5/P45 HCTNMTNHOORODOATKH ANMTOORDAS OYOMONOMOMNMNMMMNMN TTT TTT tl AQAGKLASHHBSHS SY FYVX gqgoaaaqaaaaaananda ag goaaa HASTAAIHGRGAHAS, FS oHrAGHT TFTNNNANNNANNNNNNO DMO SG0CCOCSO anngoaongoeoOoooOosoO0a5e4 (FPT-100P-M06)MB91106 Series m@ PIN DESCRIPTION Pin no. . Circuit . Pin name Function LQFP*! | QFP*2 type 25 to 32 | 28 to 35 |D16 to D23 Cc Bit 16 to bit 23 of external data bus P20 to P27 Can be configured as general purpose I/O port when external data bus width is set to 8-bit or in single chip mode. 33 to 39, | 36 to 42, |D24 to D30, Cc Bit 24 to bit 31 of external data bus 41 44 D31 P30 to P36, Can be configured as general purpose I/O ports when not used P37 as address bus. 42, 45, AOO, E Bit 00 to bit 15 of external address bus 44 to 50, | 47 to 53, |A01 to A07, 51 to 58 | 54to 61 |A08 to A15 P40, Can be configured as general purpose I/O ports when not used P41 to P47, as address bus. P50 to P57 59 to 64, | 62 to 67, |A16 to A21, E Bit 16 to bit 23 of external address bus 66, 69, | A22, 67 70 A23 P60 to P67, Can be configured as general purpose I/O ports when not used P69, as address bus. P70 68 71 A24 E Bit 24 of external address bus EOPO Can be configured as DMAC EOP output (ch. 0) when DMAC EOP output is enabled. P70 Can be configured as general purpose I/O port when A24 and EOP0 are not used. 19 22 RDY Cc External ready input Inputs O when bus cycle is being executed and not completed. P80 Can be configured as general purpose I/O port when RDY is not used. 20 23 BGRNT E External bus release acknowledge output Outputs L level when external bus is released. P81 Can be configured as general purpose I/O port when BGRNT is not used. 21 24 BRQ Cc External bus release request input Inputs 1 when release of external bus is required. P82 Can be configured as general purpose I/O port when BRQ is not used. 22 25 |RD E _|Read strobe output pin for external bus P83 Can be configured as general purpose |/O port when RD is not used. "1: FPT-100P-M05 "2: FPT-100P-M06 (Continued)MB91106 Series Pin no. . Circuit . Pin name Function LQFP*! | QFP*2 type 23 26 P84 E Can be configured as general purpose |/O port when WRO is not used. WRO Write strobe output pin for external bus Relation between control signals and effective byte locations is as follows: 24 27 WR1 E 16-bit 8-bit Single chip bus width | bus width mode D31 to D24 WRO WRO (VO port enabled) woz (I/O port (I/O port D23 to D16 wrt enabled) enabled) Note: WR1 is Hi-Z during resetting. Attach an external pull-up resister when using at 16-bit bus width. P85 Can be configured as general purpose |/O port when WR is not used. 11 14 CSO E Chip select 0 output (L active) PAO Can be configured as general purpose I/O port when CSO is not used. 10 13 CSs1 E Chip select 1 output (L active) PA1 Can be configured as general purpose I/O port when CS1 is not used. 9 12 CS2 E Chip select 2 output (L active) PA2 Can be configured as a port when CS2 is not used. 8 11 CS3 E Chip select 3 output (L active) PA3 Can be configured as a port when CS3 and EOP1 are not used. EOP1 EOP output pin for DMAC (ch. 1) This function is available when EOP output for DMAC is enabled. 7 10 CS4 E Chip select 4 output (L active) PA4 Can be configured as general purpose I/O port when CS4 is not used. 6 9 CS5 E Chip select 5 output (L active) PA5 Can be configured as general purpose I/O port when CS5 is not used. 5 8 CLK E System clock output Outputs clock signal of external bus operating frequency. PA6 Can be configured as general purpose I/O port when CLK is not used. "1: FPT-100P-M05 "2: FPT-100P-M06 (Continued)MB91106 Series Pin no. . Circuit . Pin name Function LQFP*! QFP*2 type 96 99 RASO E RAS output for DRAM bank 0 PBO Can be configured as general purpose I/O port when RASO is not used. 97 100 CSOL E CASL output for DRAM bank 0 PB1 Can be configured as general purpose I/O port when CSOL is not used. 98 1 CSOH E CASH output for DRAM bank 0 PB2 Can be configured as general purpose I/O port when CSOH is not used. 99 2 Dwo E _| WE output for DRAM bank 0 (L active) PB3 Can be configured as general purpose I/O port when DW0 is not used. 100 3 RAS 1 E RAS output for DRAM bank 1 PB4 Can be configured as general purpose I/O port when RAS1 and EOP2 are not used. EOP2 DMAC EOP output (ch. 2) This function is available when DMAC EOP output is enabled. 1 4 CS1L E CASL output for DRAM bank 1 PB5 Can be configured as general purpose I/O port when CS1L and DREQ are not used. DREQ2 External transfer request input pin for DMA This pin is used for input when external trigger is selected to cause DMAC operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. 2 5 CS1H E CASH output for DRAM bank 1 PB6 Can be configured as general purpose I/O port when CS1H and DACK2 are not used. DACK2 External transfer request accept output pin for DMAC (ch. 2) This function is available when transfer request output for DMAC is enabled. 3 6 DW1 E | WE output for DRAM bank 1 (L active) PB7 Can be configured as general purpose I/O port when DW1 is not used. 16t0 18 | 19to21 |MDO to MD2 F Mode pins 0 to 2 MCU basic operation mode is set by these pins. Directly connect these pins with Vcc or Vss for use. 92 95 X0 A Clock (oscillator) input 91 94 x1 A Clock (oscillator) output 14 17 RST B External reset input 12 15 NMI G NMI (non-maskable interrupt pin) input (L active) *1: FPT-100P-M05 *2: FPT-100P-M06 (Continued)MB91106 Series Pin no. . Circuit . Pin name Function LQFP*! | QFP*2 type 95, 98, INTO, E External interrupt request input pins 94 97 INT1 These pins are used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from these pins unless such output is made intentionally. PEO, Can be configured as general purpose |/O ports when INTO PE1 and INT1 are not used. 89 92 INT2 E External interrupt request input pin This pin is used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. Sct Clock I/O pin for UART1 Clock output is available when clock output of UART1 is enabled. PE2 Can be configured as general purpose I/O port when INT2 and SC1 are not used. This function is available when UART1 clock output is disabled. 88 91 INT3 E External interrupt request input pin This pin is used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. $C2 UART2 clock I/O pin Clock output is available when UART2 clock output is enabled. PE3 Can be configured as general purpose I/O port when INT3 and SC2 are not used. This function is available when UART2 clock output is disabled. 87, 90, DREQO, E External transfer request input pins for DMA 86 89 DREQ1 These pins are used for input when external trigger is selected to cause DMAC operation, and it is necessary to disable output for other functions from these pins unless such output is made intentionally. PE4, Can be configured as general purpose I/O ports when DREQO PE5 and DREQ1 are not used. 85 88 DACKO E External transfer request acknowledge output pin for DMAC (ch. 0) This function is available when transfer request output for DMAC is enabled. PE6 Can be configured as general purpose I/O port when DACKO is not used. This function is available when transfer request acknowledge output for DMAC or DACKO output is disabled. "1: FPT-100P-M05 "2: FPT-100P-M06 (Continued)MB91106 Series Pin no. . Circuit . Pin name Function LQFP*! | QFP*2 type 84 87 DACK1 E External transfer request acknowledge output pin for DMAC (ch. 1) This function is available when transfer request output for DMAC is enabled. PE7 Can be configured as general purpose I/O port when DACK1 is not used. This function is available when transfer request output for DMAC or DACK1 output is disabled. 76 79 Sl0 E UARTO data input pin This pin is used for input during UARTO is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. TRGO PWM timer external trigger input pin (ch.0) This pin is used for input during PWM timer external trigger is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. PFO Can be configured as general purpose I/O port when SIO and TRGO are not used. 77 80 SOO E UARTO data output pin This function is available when UARTO data output is enabled. TRG1 PWM timer external trigger input pin This function is available when serial data output of PF1, UARTO are disabled. PF1 Can be configured as general purpose I/O port when SOO and TRG1 are not used. This function is available when serial data output of UARTO is disabled. 78 81 SCO E UARTO clock I/O pin Clock output is available when UARTO clock output is enabled. OCPA3 PWM timer output pin This function is available when PWM timer output is enabled. PF2 Can be configured as general purpose I/O port when SCO and OCPA3 are not used. This function is available when UARTO clock output is disabled. 79 82 Slit E UART1 data input pin This pin is used for input during UART1 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. TRG2 PWM timer external trigger input pin This pin is used for input during PWM timer external trigger is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. PF3 Can be configured as general purpose I/O port when SI1 and TRG2 are not used. *1: FPT-100P-M05 *2: FPT-100P-M06 10 (Continued)MB91106 Series Pin no. . Circuit . Pin name Function LQFP*! QFP*2 type 80 83 $01 E UART1 data output pin This function is available when UART1 data output is enabled. TRG3 PWM timer external trigger input pin This function is available when PF4, UART1 data outputs are disabled. PF4 Can be configured as general purpose I/O port when SO1 and TRG3 are not used. This function is available when UART1 data output is disabled. 81 84 $l2 E UART2 data input pin This pin is used for input during UART2 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. OCPA1 PWM timer output pin This function is available when PWM timer output is enabled. PF5 Can be configured as general purpose |/O port when Sl2 and OCPA2 are not used. 82 85 $02 E UART2 data output pin This function is available when UART2 data output is enabled. OCPA2 PWM timer output pin This function is available when PWM timer output is enabled. PF6 Can be configured as general purpose I/O port when SO2 and OCPA2 are not used. This function is available when UART2 data output is disabled. 83 86 OCPAO E PWM timer output pin This function is available when PWM timer output is enabled. PF7 Can be configured as a port when OCPAO and ATG are not used. This function is available when PWM timer output is disabled. ATG External trigger input pin for A/D converter This pin is used for input when external trigger is selected to cause A/D converter operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. 72 to 75 | 75to 78 | ANO to AN3 D Analog input pins of A/D converter This function is available when AIC register is set to specify analog input mode. 69 72 AVcc _ Power supply pin (Vcc) for A/D converter 70 73 AVRH _ Reference voltage input (high) for A/D converter Make sure to turn on and off this pin with potential of AVRH or more applied to Vcc. 71 74 AVss, _ Power supply pin (Vss) for A/D converter and reference voltage AVRL input pin (low) *1: FPT-100P-M05 *2: FPT-100P-M06 (Continued) 14MB91106 Series (Continued) Pin no. . Circuit . Pin name Function LQFP*! | QFP*2 type 4, 7, Vec _ Power supply pin (Vcc) for digital circuit 13, 16, Always power supply pin (Vcc) must be connected to the power 43, 46, supply 93 96 15, 18, Vss _ Earth level (Vss) for digital circuit 40, 43, 65, 68, 90 93 "1: FPT-100P-MO05 "2: FPT-100P-M06 Note: In most of the above pins, I/O port and resource I/O are multiplexed e.g. xxx/Pxxx. In case of conflict between output of I/O port and resource I/O, priority is always given to the output of resource I/O. 12m@ DRAM CONTROL PIN MB91106 Series Data bus 16-bit mode Pin name Data bus 8-bit mode Remarks 2CAS/1WR mode 1CAS/2WR mode RASO Area 4 RAS Area 4 RAS Area 4 RAS Correspondence of L H to lower address 1 bit (AO) in data bus 16- RAS1 Area 5 RAS Area 5 RAS Area 5 RAS bit mode pee Q CSOL Area 4 CASL Area 4 CAS Area 4 CAS H": 4 CASL: CAS which AO CSOH Area 4 CASH Area 4 WEL Area 4 CAS corresponds to area CASH: CAS which AO CSI1L Area 5 CASL Area 5 CAS Area 5 CAS corresponds to _1 area CS1H Area 5 CASH Area 5 WEL Area 5 CAS WEL: WE which AO corresponds to DWO Area 4 WE Area 4 WEH Area 4 WE 0 area WEH: WE which AO DW1 Area 5 WE Area 5 WEH Area 5 WE comesponds to 13MB91106 Series @ I/O CIRCUIT TYPE Type Circuit Remarks A * Oscillation feedback resistance 1 MQ approx. Clock input With standby control Standby control signal B * CMOS level hysteresis input Voc Without standby control With pull-up resistance P-ch P-channel C] type transister , ; L N-channel Dittused resistor = | 90 transister Vss -____P0- Digital input Cc * CMOS level I/O With standby control P-ch J} Digital output R = N-ch |]}- Digital output Db; Digital input Standby control signal D * Analog input P-ch HH Digital output R= N-ch _ ]}- Digital output _ "Analog input 14 (Continued)MB91106 Series (Continued) Type Circuit Remarks E * CMOS level output * CMOS level hysteresis input _ With standby control P-ch Digital output R = N-ch + Digital output [p= Digital input Standby control signal F * CMOS level input Without standby control P-ch I R= N-ch an | >o- Digital input G * CMOS level hysteresis input ] P-ch _ N-ch ms -___[i>o+ Digital input ANA VV Without standby control 1516 MB91106 Series @ HANDLING DEVICES 1. 2. Preventing Latchup In CMOS ICs, applying voltage higher than Vcc or lower than Vss to input/output pin or applying voltage over rating across Vcc and Vss may cause latchup. This phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the device. Make sure to prevent the voltage from exceeding the maximum rating. Take care that the analog power supply (AVcc AVR) and the analog input do not exceed the digital power supply (Vcc) when the analog power supply turned on or off. Treatment of Unused Pins Unused pins left open may cause malfunctions. Make sure to connect them to pull-up or pull-down resistors. External Reset Input It takes at least 5 machine cycle to input L level to the RST pin and to ensure inner reset operation properly. Remarks for External Clock Operation When external clock is selected, supply it to XO pin generally, and simultaneously the opposite phase clock to XO must be supplied to X1 pin. However, in this case the stop mode must not be used (because X1 pin stops at H output in stop mode). And can be used to supply only to X0 pin with 5 V power supply at 12.5 MHz and less than. - Using an external clock + 0) Ls x1 MB91106 Using an external clock (normal) Note: Can not be used stop mode (oscillation stop mode). > xo Open x1 MB91106 Using an external clock (can be used at 12.5 MHz and less than.) (5 V power supply only)10. 11. MB91106 Series Power Supply Pins When there are several Vcc and Vss pins, each of them is equipotentially connected to its counterpart inside of the device, minimizing the risk of malfunctions such as latch up. To further reduce the risk of malfunctions, to prevent EMI radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and to observe the total output current standard, connect all Vcc and Vss pins to the power supply or GND. It is preferred to connect Vcc and Vss of MB91106 to power supply with minimal impedance possible. It is also recommended to connect a ceramic capacitor as a bypass capacitor of about 0.1 uF between Vec and Vss at a position as close as possible to MB91106. Crystal Oscillator Circuit Noises around XO and X1 pins may cause malfunctions of MB91106. In designing the PC board, layout XO, X1 and crystal oscillator (or ceramic oscillator) and bypass capacitor for grounding as close as possible. It is strongly recommended to design PC board so that X1 and XO pins are surrounded by grounding area for stable operation. Turning-on Sequence of A/D Converter Power Supply and Analog Input Make sure to turn on the digital power supply (Vcc) before turning on the A/D converter (AVcc, AVRH) and applying voltage to analog input (ANO to AN3). Make sure to turn off digital power supply after power supply to A/D converters and analog inputs have been switched off. (There are no such limitations in turning on power supplies. Analog and digital power supplies may be turned on simultaneously.) Make sure that AVRH never exceeds AVcc when turning on/off power supplies. Treatment of N.C. Pins Make sure to leave N.C. pins open. Fluctuation of Power Supply Voltage Warranty range for normal operation against fluctuation of power supply voltage Vcc is as given in rating. However, sudden fluctuation of power supply voltage within the warranty range may cause malfunctions. It is recommended to make every effort to stabilize the power supply voltage to IC. It is also recommended that by controlling power supply as a reference of stabilizing, Vcc ripple fluctuation (P-P value) at the commercial frequency (50 Hz to 60 Hz) should be less than 10% of the standard Vcc value and the transient regulation should be less than 0.1 V/ms at instantaneous deviation like turning off the power supply. Mode Setting Pins (MDO to MD2) Connect mode setting pins (MDO to MD2) directly to Vcc or Vss. Arrange each mode setting pin and Vcc or Vss patterns on the printed circuit board as close as possible and make the impedance between them minimal to prevent mistaken entrance to the test mode caused by noises. Turning on the Power Supply When turning on the power supply, never fail to start from setting the RST pin to L level. And after the power supply voltage goes to Vcc level, at least after ensuring the time for 5 machine cycle, then set to H level. 17MB91106 Series 18 12. 13. 14. Pin Condition at Turning on the Power Supply The pin condition at turning on the power supply is unstable. The circuit starts being initialized after turning on the power supply and then starting oscillation and then the operation of the internal regulator becomes stable. So it takes about 42 ms for the pin to be initialized from the oscillation starting at the source oscillation 12.5 MHz. Take care that the pin condition may be output condition at initial unstable condition. Source Oscillation Input at Turning on the Power Supply At turning on the power supply, never fail to input the clock before cancellation of the oscillation stabilizing waiting. Initialization Some internal resistors initialized only via power on reset are embedded in the device. To initialize these resistors, run power on reset by returning on the power supply or to set RST pin to H level.MB91106 Series m@ BLOCK DIAGRAM FR CPU RAM (2 Kbytes) 2 oO @ = 5 a ; Bi h dul A 5B Instruction ROM it search module oo a 63 Kbytes, 32bits n ie DREQO to Sey a DREQ2 3 Bus converter DACKO to ~S<| DMA controller (DMAC) (Harvard<Princeton) DACK2 3 (8 ch.) EOPOto = -+><4 EOP2 16 Bus converter (32 bits<>16bits) 35 D16 to D31 52 A00 to A24 Ha RD || }H>= WRO, WR1 XO I] Clock control unit -{ Buscontroller ,* RDY xXi_* (Watchdog timer) g 7 olK AST g H>+ CSO to CS5 r BRQ ++ BGRNT 4 INTO to INT3) >< Interrupt control unit NMI +1 ~ & } RASO ANO to ANS = & - RAS1 AVcc a _> CSOH 2 _| DRAM interface AVss *| 10-bit A/D converter oO i> CSiL AVRH -+ (4 ch.) - CS1H AVRL = = an ATG 9 + +- DWo ~ }+ DW1 n 5 o Instruction ROM ~ L_ and . . 3 J data ROM 16-bit reload timer (3 ch.) a 64 Kbytes 8 7 P20 to P27 hz P30 to P37 H+z=* PAO to P47 3 LS ort 2 B r=*" P50 to P57 PEO to PE? Port E ort2toportB ---= p0 to P67 PFO to PF7 vee Port FE W#>= P70) r><- PASO to P85 peses PAO to PAG +3-+ PBO to PB7 Other pins hee S10 to SI2 UART (3 ch.) |} S00 to SO2 (Baud rate timer) le SCO to SC2 MDO to MD2, Vcc, Vss He OCPAO to OCPAS PWM timer (4 ch.) 4 TRGO to TRG3 Note: Pins are display for functions (Actually some pins are multiplexer). When using REALOS, time control should be done by using external interrupt or inner timer. 1920 MB91106 Series m@ CPU CORE 1. Memory Space The FR family has a logical address space of 4 Gbytes (2 bytes) and the CPU linearly accesses the memory space. Memory space Memory Space Internal ROM/ external bus mode External ROM/ external bus mode Single chip mode Address Direct 0000 0000H | addressing \/0 Area \/0 Area 1/0 Area area 0000 0400n See BI/O MAP V0 Area V0 Area V0 Area 0000 0800n Access inhibited Access inhibited Access inhibited 0000 1000H Embedded RAM Embedded RAM Embedded RAM (2 Kbytes) (2 Kbytes) (2 Kbytes) 0000 1800H Access inhibited Access inhibited Access inhibited 0001 0000H Access inhibited External area 0008 0000n Instruction ROM Instruction ROM (63 Kbytes) (63 Kbytes) 0008 FCOOn Access inhibited Access inhibited External area OOOF 0000u Instruction ROM/data ROM Instruction ROM/data ROM (64 Kbytes) (64 Kbytes) 0010 0000n Access inhibited External area FFFF FFFFu * :Direct addressing area The following areas on the memory space are assigned to direct addressing area for I/O. In these areas, an address can be specified in a direct operand of a code. Direct areas consists of the following areas dependent on accessible data sizes. Byte data access: 000x to OFFu Half word data access: 000n to 1FFu Word data access: 000n to 3FFu Notes: Access to the external area can be execute in the single chip mode. To access to the external area, select internal ROM external bus mode via mode resistor. Never execute data access to the instruction ROM area. e In the instruction/data ROM, images in block of 64 Kbytes can be seen. Make an instruction/data in the area OOOFO000H to OOOFFFFFu.2. Registers The FR family has two types of registers; dedicated registers embedded on the CPU and general-purpose registers on memory. - Dedicated registers Program counter (PC): Program status (PS): Table base register (TBR): Return pointer (RP): 32-bit length, indicates the location of the instruction to be executed. MB91106 Series 32-bit length, register for storing register pointer or condition codes Holds top address of vector table used in EIT (Exceptional/Interrupt/Trap) processing. Holds address to resume operation after returning from a subroutine. System stack pointer (SSP): Indicates system stack space. User's stack pointer (USP): Indicates user's stack space. Multiplication/division result register (MDH/MDL): 32-bit length, register for multiplication/division Program counter Ss TB Ss USP w u ule vU a O)e Program status Table base register Return pointer System stack pointer Users stack pointer MDH Multiplication/division result register Initial value XXXX OOOF XXXX 0000 XXXX XXXX XXXX XXXXH FCOOu XXXXH 0000H XXXXH XXXXH XXXXH Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate - Program status (PS) The PS register is for holding program status and consists of a condition code register (CCR), asystem condition code register (SCR) and a interrupt level mask register (ILM). 31 20 19 18 17 ~ 16 10 9 8 7 5 4 3 2 1 PS JILM4/ILM3]ILM2|ILM1}ILMO; | D1 |} DO T -|- $s N Z Vv esa? Vv ILM SCR CCR 2122 MB91106 Series * Condition code register (CCR) S-flag: I-flag: N-flag: Z-flag: V-flag: C-flag: - System condition code register (SCR) T-flag: Specifies a stack pointer used as R15. Controls user interrupt request enable/disable. Indicates sign bit when division result is assumed to be in the 2s complement format. Indicates whether or not the result of division was O. Assumes the operand used in calculation in the 2s complement format and indicates whether or not overflow has occurred. Indicates if a carry or borrow from the MSB has occurred. Specifies whether or not to enable step trace trap. - Interrupt level mask register (ILM) ILM4 to ILMO: Register for holding interrupt level mask value. The value held by this register is used as a level mask. When an interrupt request issued to the CPU is higher than the level held by ILM, the interrupt request is accepted. ILM4 ILM3 ILM2 ILM1 ILMO Interrupt level High-low 0 0 0 0 0 0 High 0 | 1 0 0 0 15 1 | 1 1 1 1 31 LowMB91106 Series lm GENERAL-PURPOSE REGISTERS RO to R15 are general-purpose registers embedded on the CPU. These registers functions as an accumulator and a memory access pointer (field for indicating address). - Register bank structure . 32 bits : ne , Initial value RO XXXX XXXXH Rt : R12 R13 AC (accumulator) : R14 FP (frame pointer) XXXX XXXXu R15 SP (stack pointer) 0000 0000n Of the above 16 registers, following registers have special functions. To support the special functions, part of the instruction set has been sophisticated to have enhanced functions. R13: Virtual accumulator (AC) R14: Frame pointer (FP) R15: Stack pointer (SP) Upon reset, values in RO to R14 are not fixed. Value in R15 is initialized to be 0000 0000n (SSP value). 23MB91106 Series @ SETTING MODE 1. Pin - Mode setting pins and modes Mode setting R E Id pins Mode name eset vector xternal ata Bus mode access area bus width MD2 | MD1 | MDO 0 0 O | External vector mode 0 External 8 bits External ROM/external bus 0 0 1 External vector mode 1 External 16 bits mode 0 1 0 Inhibited 0 1 1 Internal vector mode Internal (Mode register) | Single-chip mode* 1 _ _ _ _ _ Not use * :MB91106 support single-chip mode. 2. Registers - Mode setting registers (MODR) and modes Address Initial value Access 0000 07FFH M1 Mo * * * * * * XXXX XXXXe Ww W_ t Bus mode setting bit W: Write only X : Indeterminate * : Always write O except for M1 and MO. - Bus mode setting bits and functions M1 MoO Functions Note 0 0 Single-chip mode 0 1 Internal ROM/external bus mode 1 0 External ROM/external bus mode 1 1 Inhibited 24MB91106 Series m@ 1/0 MAP Address Register name Register name Read/write Resources Initial value (abbreviated) name 000000 |PDR3 Port 3 data register R/W Port 3 XXXXXXXXes 0000014 |PDR2 Port 2 data register R/W Port 2 XXXXXXXXes 000002H (Vacancy) 000003H 000004n |PDR7 Port 7 data register R/W Portt7 | ------- XB 0000051 |PDR6 Port 6 data register R/W Port 6 XXXXXXXXes 0000064 |PDR5 Port 5 data register R/W Port 5 XXXXXXXXes 000007H |PDR4 Port 4 data register R/W Port 4 XXXXXXXXes 000008 |PDRB Port B data register R/W Port B XXXXXXX XB 000009xH |PDRA Port A data register R/W PortA XXXXXKXK XB OO000AH (Vacancy) O0000BH | PDR8 Port 8 data register | R/W Port 8 -XXXXKXKXes 00000CH to (Vacancy) 0000114 000012H |PDRE Port E data register R/W PortE XXXXXXX XB 000013h | PDRF Port F data register R/W Port F XXXXXXXXes 0000144 to (Vacancy) 00001 Bx 00001CxH |SSRO Serial status register 0 R/W 00001-008 00001Dx |SIDRo/SODRO |S2t"!al Input data register O/serial R/W XXXXXXXXo output data register 0 UARTO 00001Ex |SCRO Serial control register 0 R/W 000001008 00001FH |SMRO Serial mode register 0 R/W 00--0-008 000020n |SSR1 Serial status register 1 R/W 00001-008 0000214 |SIDR1/SODR1 | Se*!@l input data register 1/serial R/W XXXXXXXXo output data register 1 UARTI 000022h |SCR1 Serial control register 1 R/W 000001008 000023x |SMR1 Serial mode register 1 R/W 00--0-008 000024n |SSR2 Serial status register 2 R/W 00001-008 000025 |SIDR2/SODR2 |Se"al input data register 2/serial R/W XXXXXXXXo output data register 2 UART2 0000261 |SCR2 Serial control register 2 R/W 000001008 0000274 |SMR2 Serial mode register 2 R/W 00--0-008 (Continued) 25MB91106 Series Address Register name Register name Read/write Resources Initial value (abbreviated) name 0000281 XXXXXXXXes TMRLRO 16-bit reload register 0 WwW 000029H 16-bitreload | XXXXXXXXea 00002AH | timer 0 XXXXXXXXeB TMRO 16-bit timer register 0 R 00002BH XXXXXXXXes 00002CH (Vacancy) 00002Du 00002E -bi -bi ----0000 H TMCSRO 16 bit reload timer control status B/W 16 bit reload B 00002FH register 0 timerO | 000000008 0000304 TMALRY 16-bit reload recister 4 W XXXXXXXXes -bit reload register 0000314 9 reo ireload XXXXXXXXe imer 000032H a XXXXXXXXes TMR1 16-bit timer register 1 R 000033H XXXXXXXXes 0000344 (Vacancy) 000035x 000036 -bi -bi ----0000 H TMCSRY1 16 bit reload timer control status B/W 16 bit reload B 0000374 register 1 timer 1 000000008 000038H 000000XXs ADCR A/D converter data register R 000039H 10-bit A/D | XXXXXXXXes 00003Ax converter | 9900000058 ADCS A/D converter control status register R/W 00003BH 000000008 00003CxH XXXXXXXXes TMRLR2 16-bit reload register 2 WwW 00003DxH 16-bitreload| XXXXXXXXa 00003Ex | timer 2 XXXXXXXXes TMR2 16-bit timer register 2 R 00003FH XXXXXXXXes 000040H (Vacancy) 0000414 000042 -bi -bi ----0000 H TMCSR2 16 bit reload timer control status B/W 16 bit reload B 0000431 register 2 timer2 | 900000008 0000444 to (Vacancy) 0000774 26 (Continued)MB91106 Series Register name Resources Address (abbreviated) Register name Read/write name Initial value 000078 - - 00000000 JutimosuTimRo |U-TIMER register ch. 0 /U-TIMER RW | U-TIMERO 000079u reload register ch. 0 000000008 00007AH (Vacancy) 00007Bx | UTIMCO U-TIMER control register ch. 0 R/W U-TIMERO | O--00001.8 00007C - 00000000 "TotimauTimAar |U-TIMER register ch. 1/reload B/W U-TIMER 1 8 00007Dx register ch. 1 000000008 00007Ex (Vacancy) 00007FH |UTIMC1 U-TIMER control register ch. 1 R/W U-TIMER 1] 0--00001.8 000080 - - 00000000 utim2/uTimR2 |U-TIMER register ch. 2/U-TIMER RW | U-TIMER 2 0000811 reload register ch. 2 000000008 000082H (Vacancy) 000083 )UTIMC2 U-TIMER control register ch. 2 R/W U-TIMER2| 0--00001.8 0000844 to (Vacancy) 000093H 000094n |EIRR External interrupt cause register R/W External 000000008 interrupt/ 000095 |ENIR Interrupt enable register R/W NMP 000000008 000096H to (Vacancy) 000098H ; External o0009n |ELVR External interrupt request level RW | interrupt/ | 00000000. setting register NMI O0009AH to (Vacancy) 0000D1H 0000D2y |DDRE Port E data direction register WwW PortE 000000008 0000D3x | DDRF Port F data direction register WwW Port F 000000008 0000D4n to (Vacancy) O0000DBx 0000DCH PWM 001100108 GCN1 General control register 1 R/W 0000DDx timer 1 00010000B O000DEx (Vacancy) O000DFH |GCN2 General control register 2 R/W ines 000000008 (Continued) 2728 MB91106 Series Address Register name Register name Read/write Resources Initial value (abbreviated) name OOOO0E0n 111111118 PTMRO PWM timer register 0 R OOOOE1H 111111118 OO00E2H XXXXXXXXes PCSRO PWM cycle setting register 0 WwW OOO0E3H PWM XXXXXXXXes OO00E41 timer 0 XXXXXXXXes PDUTO PWM duty setting register 0 WwW OOOOE5xH XXXXXXXXes OOOOEE6H | PCNHO Control status register H 0 R/W 0000000-8 0000E7xH | PCNLO Control status register L 0 R/W 000000008 OOOOE8H 111111118 PTMR1 PWM timer register 1 R OOOOESH 111111118 OOOOEAH XXXXXXXXes PCSR1 PWM cycle setting register 1 WwW OOOOEBH PWM XXXXXXXXes OOO0ECH timer 1 XXXXXXXXs PDUT1 PWM duly setting register 1 WwW OOO0EDu XXXXXXXXes OOOCEEn |PCNH1 Control status register H 1 R/W 0000000-8 OOOOEFnH | PCNL1 Control status register L 1 R/W 000000008 O000FOn 111111118 PTMR2 PWM timer register 2 R OO000F 1H 111111118 O000F2x XXXXXXXXes PCSR2 PWM cycle setting register 2 WwW O000F3x PWM XXXXXXXXes OO00F4y timer 2 XXXXXXXX Bs PDUT2 PWM duty setting register 2 WwW OO00F 5x XXXXXXXXes OOOOF6H | PCNH2 Control status register H 2 R/W 0000000-8 O0000F7H |PCNL2 Control status register L 2 R/W 000000008 OO00F8x 111111118 PTMR3 PWM timer register 3 R OO00F9x 111111118 OOOOFAH XXXXXXXXes PCSR3 PWM cycle setting register 3 WwW OOOOFBx PWM XXXXXXXXes OOOOFCH timer 3 XXXXXXXXea PDUT3 PWM duty setting register 3 WwW OOO0OFDH XXXXXXXXes OOOOFEn | PCNH3 Control status register H 3 R/W 0000000-8 OOOOFFH | PCNL3 Control status register L 3 R/W 000000008 (Continued)MB91106 Series Register name Resources Address (abbreviated) Register name Read/write name Initial value 000100H O00T FE (Vacancy) H 000200H XXXXXXXXes 0002014 XXXXXXXXes DPDP DMAC parameter descriptor pointer R/W 000202H XXXXXXXXes 000203H X00000008 0002044 000000008 0002051 DMA 000000008 DACSR DMAC control status register R/W controller 0002064 (DMAC) 000000008 0002074 000000008 000208H XXXXXXXXes 0002094 XX0000008 DATCR DMAC pin control register R/W 00020AnH XX0000008 00020BH XX0000008 00020Cu to (Vacancy) O003EFx 0003F0H XXXXXXXXes 0003F 1H Bspo Bit search module 0-detection data W XXXXXXXXs 0003F2H register XXXXXXXXe 0003F3x XXXXXXXXes 0003F4y XXXXXXXXes 0003F 5x BsD1 Bit search module 1-detection data RAW XXXXXXXXs 0003F6H register XXXXXXXXe 0003F7H Bit search XXXXXXXKXB 0003F8: module | XXXXXXXXe 0003F 9H BSDC Bit search module transition- W XXXXXXXX w O003FAu detection data register XXXXXXXXs 0003FBx XXXXXXXXes 0003FCH XXXXXXXXes 0003FDx BSRR Bit search module detection result R XXXXXXXXs 0003FEH register XXXXXXXXe O0003FFH XXXXXXXXes (Continued) 29MB91106 Series Address etbrovite dy Register name Read/write Resources Initial value 0004001 |ICROO Interrupt control register 0 R/W ---111118 0004014 |ICRO1 Interrupt control register 1 R/W ---111118 000402n |ICRO2 Interrupt control register 2 R/W ---11111.8 000403n |ICRO3 Interrupt control register 3 R/W ---11111.8 0004044 | ICRO4 Interrupt control register 4 R/W ---111118 000405n |ICRO5 Interrupt control register 5 R/W ---11111.8 000406n |ICRO6 Interrupt control register 6 R/W ---11111.8 000407n | ICRO7 Interrupt control register 7 R/W ---11111.8 000408n |ICRO8 Interrupt control register 8 R/W ---11111.8 000409n |ICRO9 Interrupt control register 9 R/W ---11111.8 00040An |ICR10 Interrupt control register 10 R/AW ~--11111.8 00040Bu |ICR11 Interrupt control register 11 R/W ~--11111.8 00040Cu | ICR12 Interrupt control register 12 R/AW ~--11111.8 00040Du JICR13 Interrupt control register 13 R/W ---11111. OO0040Ex |ICR14 Interrupt control register 14 R/W ---11111. 00040Fu |ICR15 Interrupt control register 15 R/W Interrupt ~--11111.8 000410n JICR16 Interrupt control register 16 R/AV controller | _-_44141141. 0004114 jICR17 Interrupt control register 17 R/W ~--11111.8 000412H |ICR18 Interrupt control register 18 R/AW ~--11111.8 000413H |ICR19 Interrupt control register 19 R/AW ~--11111.8 0004144 )ICR20 Interrupt control register 20 R/W ~--11111.8 000415n |ICR21 Interrupt control register 21 R/AW ~--11111.8 000416H |ICR22 Interrupt control register 22 R/AW ~--11111.8 0004174 |ICR23 Interrupt control register 23 R/W ~--11111.8 000418n |ICR24 Interrupt control register 24 R/AW ---11111. 000419n |ICR25 Interrupt control register 25 R/AW ~--11111.8 00041An | ICR26 Interrupt control register 26 R/AW ~--11111.8 00041Bu | ICR27 Interrupt control register 27 R/AW ~--11111.8 00041Cu |ICR28 Interrupt control register 28 R/AW ~--11111.8 00041Du | ICR29 Interrupt control register 29 R/AW ~--11111.8 00041En | ICR30 Interrupt control register 30 R/AW ~--11111.8 00041FH |ICR31 Interrupt control register 31 R/AW ~--11111.8 (Continued) 30MB91106 Series Register name Resources Address (abbreviated) Register name Read/write name Initial value 000420n to (Vacancy) 00042Ex 00042Fu |ICR47 Interrupt control register 47 R/W ---11111.8 000430n |DICR Delayed interrupt control register RAW Interrupt | ------- Os controller 000431n |HRCL Hold request cancel request level B/W --444441:8 setting register 0004324 to (Vacancy) 00047FH 0004804 |RSRR/WTCR [Reset cause register R/W 1XXXX-008 watchdog cycle control register 0004814 |STCR Standby control register R/W 000111--B8 000482, |PDRR DMA controller request squelch B/W Clock -~--_0000s register trol contro 0004834 |CTBR Timebase timer clear register WwW XXXXXXXXes 000484n |GCR Gear control register R/W 110011-1.8 000485, |WPR Watchdog reset occurrence postpone W XXXXXXXXs register 000486H (Vacancy) 0004874 000488h |PCTR PLL control register | R/W PLL control} 00--OQ---B8 0004894 to (Vacancy) OOO5FFH 000600n |DDR3 Port 3 data direction register WwW Port 3 000000008 000601H |DDR2 Port 2 data direction register WwW Port 2 000000008 000602H to (Vacancy) 000603H 00060414 | DDR7 Port 7 data direction register WwW Portt7 | ------- Os 000605x |DDR& Port 6 data direction register WwW Port 6 000000008 000606x |DDR5 Port 5 data direction register WwW Port 5 000000008 000607 |DDR4 Port 4 data direction register WwW Port 4 000000008 0006081 |DDRB Port B data direction register WwW Port B 000000008 0006094 |DDRA Port A data direction register WwW PortA -00000008 OO060AH (Vacancy) OO060BH | DDR8 Port 8 data direction register | WwW Port 8 | --0000008 (Continued) 3132 MB91106 Series Address Register name Register name Read/write Resources Initial value (abbreviated) name 00060Cxu 000000008 ASR1 Area select register 1 WwW 00060DxH 000000018 OOO60Ex 000000008 AMR1 Area mask register 1 WwW OO060FH 000000008 000610H 000000008 ASR2 Area select register 2 WwW 0006114 000000108 000612H 000000008 AMR2 Area mask register 2 WwW 000613x 000000008 0006144 000000008 ASR3 Area select register 3 WwW 000615x 000000118 000616H 000000008 AMR3 Area mask register 3 WwW 0006174 000000008 000618x 000000008 ASR4 Area select register 4 WwW 000619H 000001008 00061AnH 000000008 AMR4 Area mask register 4 WwW 00061 Bu 000000008 00061Cxu 000000008 ASR5 Area select register 5 WwW 00061 Du External bus 000001018 00061Ex interface | 900000008 AMR5 Area mask register 5 WwW 00061 Fx 000000008 0006204 | AMDO Area mode register 0 R/W ---O00111.8 000621 |AMD1 Area mode register 1 R/W 0--000008 000622 |AMD32 Area mode register 32 R/W 000000008 000623 |AMD4 Area mode register 4 R/W 0--000008 0006244 |AMD5 Area mode register 5 R/W 0--000008 0006251 |DSCR DRAM signal control register WwW 000000008 000626H -XXXXXXes RFCR Refresh control register R/W 0006274 00---0008 000628H ----11008 EPCRO External pin control register 0 WwW 0006294 -11111118 00062An ; fe 1. EPCR1 External pin control register 1 WwW 00062BuH 111111118 00062CH 000000008 DMCR4 DRAM control register 4 R/W 00062Du 0000000-s 00062Ex 000000008 DMCR5 DRAM control register 5 R/W 00062Fu 0000000-s (Continued)MB91106 Series (Continued) Address Register name Register name Read/write Resources Initial value (abbreviated) name 0006304 to (Vacancy) 0007FDH 0007FEx |LER Little endian register Ww External bus| --7 0008 0007FFH |MODR Mode register W interface | XXXXXXXXa About Programming R/W: Readable and writable R: Read only W: Write only Explanation of initial values 0: The initial value of this bit is O. 1: The initial value of this bit is 1. X: The initial value of this bit is undefined. : This bit is not used. The initial value of this bit is undefined. RMW system instructions (RMW: Read Modify Write) AND Rj, @ Ri OR Rj, @ Ri EOR Rj, @ Ri ANDH Rj, @ Ri ORH Rj, @ Ri EORH Rj, @ Ri ANDB Rj, @ Ri ORB Rj, @ Ri EORB Rj, @ Ri BANDL #u4,@Ri BORL #u4,@Ri BEORL #4, @Ri BANDH #u4,@Ri BORH #u4,@Ri BEORH #u4, @ Ri Notes: e Never execute a RMW system instruction to the resistor has a write only bit. e The area vacancy on the I/O map is reserved area. Access to this area are deal with to an internal area. No access signals to the external area would be generated. 33MB91106 Series @ INTERRUPT CAUSES, INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTER ALLOCATIONS Interrupt number Interrupt level TBR default Interrupt causes - - - Decimal | Hexadecimal Register Offset address Reset 0 00 3FCuH OOOFFFFCH Reserved for system 1 01 3F8H OOOFFFF8x Reserved for system 2 02 3F4u OOOFFFF4y Reserved for system 3 03 3FOu OOOFFFFOn Reserved for system 4 04 3ECu OOOFFFECH Reserved for system 5 05 3E8H OOOFFFE8x Reserved for system 6 06 3E4u OOOFFFE4H Reserved for system 7 07 3E0u OOOFFFEOn Reserved for system 8 08 8DCH OOOFFFDCu Reserved for system 9 09 3D8x OOOFFFD8x Reserved for system 10 OA 8D4H OOOFFFD4u Reserved for system 11 0B 3D0u OOOFFFDOn Reserved for system 12 OC 38CCH OOOFFFCCH Reserved for system 13 OD 3C8H OOOFFFC8x Exception for undefined instruction 14 OE 3C4H OOOFFFC4n NMI request 15 OF Fu fixed 3C0H OOOFFFCOn External interrupt 0 16 10 ICROO 3BCH OOOFFFBCH External interrupt 1 17 11 ICRO1 3B8x OOOFFFB81 External interrupt 2 18 12 ICRO2 3B4H OOOFFFB4q External interrupt 3 19 13 ICRO3 3B0x OOOFFFBOH UARTO receive complete 20 14 ICRO4 3ACH OOOFFFACH UART1 receive complete 21 15 ICRO5 3A8uH OOOFFFA8H UART2 receive complete 22 16 ICRO6 3A4u OOOFFFA4H UARTO transmit complete 23 17 ICRO7 3A0u OOOFFFAQs UART1 transmit complete 24 18 ICRO8 39CH OQOFFF9CuH UART2 transmit complete 25 19 ICRO9 398H OOOFFF98H DMACO (complete, error) 26 1A ICR10 394H OOOFFF94n DMAC1 (complete, error) 27 1B ICR11 390H OOOFFF90xH DMAC2 (complete, error) 28 1c ICR12 38CuH OOOFFF8CnH DMAC3 (complete, error) 29 1D ICR13 388H OOOFFF88x DMAC4 (complete, error) 30 1E ICR14 384H OOOFFF84x DMAC5 (complete, error) 31 1F ICR15 380H OOOFFF80x (Continued) 34MB91106 Series Interrupt number Interrupt level TBR default Interrupt causes - - - Decimal | Hexadecimal | Register Offset address DMAC6 (complete, error) 32 20 ICR16 37CH OOOFFF7CuH DMAC7 (complete, error) 33 21 ICR17 378H OOOFFF78x aoproximation Conversion typ e) 34 20 ICR18 3741 OOOFFF74: 16-bit reload timer 0 35 23 ICR19 370H OOOFFF 70x 16-bit reload timer 1 36 24 ICR20 36CH OOOFFF6ECH 16-bit reload timer 2 37 25 ICR21 368H OOOFFF68xH PWM 0 38 26 ICR22 364H OOOFFF 64x PWM 1 39 27 ICR23 360H OOOFFF60x PWM 2 40 28 ICR24 35CH OOOFFF5Cu PWM 3 41 29 ICR25 358H OOOFFF58x U-TIMER 0 42 2A ICR26 3544 OOOFFF54x U-TIMER 1 43 2B ICR27 350H OOOFFF50x U-TIMER 2 44 2c ICR28 34CuH OOOFFF4CH Reserved for system 45 2D ICR29 348: OOOFFF481 Reserved for system 46 2E ICR30 3441 OOOFFF441 Reserved for system 47 2F ICR31 3401 OOOFFF401 Reserved for system 48 30 33CH OOOFFF3Cu Reserved for system 49 31 3381 OOOFFF38x Reserved for system 50 32 3344 OOOFFF34x Reserved for system 51 33 330H OOOFFF30x Reserved for system 52 34 32CH OOOFFF2Cu Reserved for system 53 35 3281 OOOFFF28x Reserved for system 54 36 3244 OOOFFF24x Reserved for system 55 37 320H OOOFFF20x Reserved for system 56 38 31CH OOOFFF1Cx Reserved for system 57 39 318 OOOFFF18x Reserved for system 58 3A 3144 OOOFFF 14x Reserved for system 59 3B 310H OOOFFF10x Reserved for system 60 3C 30CH OOOFFFOCH Reserved for system 61 3D 308 OOOFFFO8H Reserved for system 62 3E 3044 OOOFFFO4 Delayed interrupt cause bit 63 3F ICR47 300 OOOFFFOOn (Continued) 3536 MB91106 Series (Continued) Interrupt number Interrupt level TBR default Interrupt causes - - - Decimal | Hexadecimal | Register Offset address Reserved for system (used in REALOS*) 64 40 _ 2FCu OOOFFEFCH Reserved for system (used in REALOS*) 65 44 _ 2F8H OOOFFEF8x 66 42 2F4u OOOFFEF4+ Used in INT instructions to to _ to to 255 FF 000H OOOFFDOOn * When using in REALOS/FR, interrupt 0x40, 0x41 for system code.MB91106 Series m@ PERIPHERAL RESOURCES 1. I/O Ports There are 2 types of I/O port register structure; port data register (PDRO to PDRF) and data direction register (DDRO to DDRF), where bits PDRO to PDRF and bits DDRO to DDRF corresponds respectively. Each bit on the register corresponds to an external pin. In port registers input/output register of the port configures input/ output function of the port, while corresponding bit (pin) configures input/output function in data direction registers. Bit O specifies input and 1 specifies output. * For input (DDR = 0) setting; PDR reading operation: reads level of corresponding external pin. PDR writing operation: writes set value to PDR. * For output (DDR = 1) setting; PDR reading operation: reads PDR value. PDR writing operation: outputs PDR value to corresponding external pin. (1) Register configuration - Port data register Address bit 7 bit 0 Initial value 0000014 | PDR2 | XXXXXXXXes (RAW) 0000001 | PDR3 XXXXXXXXes (RAW) 0000071 | PDR4 | XXXXXXXXes (RAW) 000006 | PDR5 | XXXXXXXXea (RAW) 0000051 | PDR6 | XXXXXXXXes (RAW) 0000041 | PDR7 [| oo ------- Xe (RW) 00000Bx | PDR8 | --XXXXXXes (RW) 0000091 | PDRA | -XXXXXXXes (RW) 0000081 | PDRB | XXXXXXXXes (RAW) 000012 | PDRE | XXXXXXXXea (RAW) 0000131 | PDRF | XXXXXXXXes (RAW) () : Access R/W : Readable and writable X : Indeterminate 37MB91106 Series - Data direction register Address bit 7 bit 0 Initial value 0006011 | DDR2 | 000000008 (W) 0006001 | DDR3 | 000000008 (W) 0006071 | DDR4 | 000000008 (W) 0006061 | DDR5 | 000000008 (W) 0006051 | DDR6 | 000000008 (W) 0006041 | DDR7 [| eee - ee Os (W) 00060Bx | DDR8 | --0000008 (W) 0006091 | DDRA | -00000008_ (W) 0006081 | DDRB | 000000008 (W) o000D21 | DDRE | 000000008 (W) 0000D31 | DDRF 000000008 (W) (): Access W: Write only : Unused (2) Block diagram Resource input ~___ 0 f 7 PDR read vo 0 Pin a PDR oO NK. ie w = a (Port data register) Resource output { } Resource output enable > DDR (Data direction register) 38MB91106 Series DMA Controller (DMAC) The DMA controller is a module embedded in FR family devices, and performs DMA (direct memory access) transfer. DMA transfer performed by the DMA controller transfers data without intervention of CPU, contributing to enhanced performance of the system. * 8 channels * Mode: single/block transfer, burst transfer and continuous transfer: 3 kinds of transfer * Transfer all through the area * Max. 65536 of transfer cycles * Interrupt function right after the transfer * Selectable for address transfer increase/decrease by the software * External transfer request input pin, external transfer request accept output pin, external transfer complete output pin three pins for each (1) Registers configuration *- DMAC internal registers * DMAC parameter descriptor pointer Initial value bit 31 bit 0 XXXXXXXX w Address XXXXXXXXB 00000200 | DPDP XXXXXXXX_e AM) * DMAC control status register x te 00008 nitial value bit 31 bit O 000000008 Address 000000008 000002044 | DACSR 000000008 _ (RW) * DMAC pin control register p00 Initial value bit 31 bit 0 XXXXXXXX es Address XX0000008 (pry 000002081 | DATCR Xx0000008 XX0000008 () : Access R/W : Readable and writable X : Indeterminate 3940 MB91106 Series - DMAC descriptor * The first word of descriptor bit 34 bit 16 | DMACT | (RM) bit15 bit 11 bit8 bit 7 bit 0 io BLK 1 (RM) * The second word of descriptor bit 34 bit 0 | SADR | (RAW) * The third word of descriptor bit 34 bit 0 | DADR | (RW) R/W: Readable and writable(2) Block diagram MB91106 Series 3 DREQO to DREQ2 74 Inner resource Transfer request a DACKO to DACK2 pS EOP0 to EOP2 8 > s Interrupt request _ Edge/level 3 detection circuit Sequencer 5 Data buffer Switcher DMAC parameter descriptor pointer (DPDP) DMAC control status registger (DACSR) DMAC pin control registger (DATCR) Mode BLK DEC BLK The first word of descriptor (DMACT) INC /DEC at p-| [he second word of descriptor (SADR) .| The third word of descriptor (DADR) Data bus 4142 MB91106 Series 3. UART The UART is a serial I/O port for supporting asynchronous (start-stop system) communication or CLK synchronous communication, and it has the following features. The MB91106 consists of 3 channels of UART. Full double double buffer Both a synchronous (start-stop system) communication and CLK synchronous communication are available. Supporting multi-processor mode Perfect programmable baud rate Any baud rate can be set by internal timer (refer to section 4. U-TIMER). Any baud rate can be set by external clock. Error checking function (parity, framing and overrun) Transfer signal: NRZ code Enable DMA transfer/start by interrupt. (1) Register configuration Serial control register 0 to 2 Address bit 15 bit 8 bit 7 bit 0 Initial value SCRO :00001Ex SOHO io SORD oa gonna SCR1 : 0000224 to ' 0000010028 (RW) SCR2 : 000026x Serial model register 0 to 2 Address bit 15 bit 8 bit 7 bit 0 Initial value SMe poe L (SCR) 1 SMR1 :0000234 (SCR) SMROtoSMR2__ ! 00- - 0- 008 (RW) SMR2 : 0000274 Serial status register 0 to 2 Address bit 15 bit 8 bit 7 bit 0 Initial value sent .oowozo, L_SsR0wSsRa_ [Si SSR1 : 0000201 SSRO to SSR2 SID 1 00001- 008 (RW) SSR2 : 000024u Serial input data register 0 to 2 Address bit 15 bit 8 bit 7 bit 0 Initial value SIDRO : 00001Du (SSR) SIDRO to SIDR2 XXXXXXXX o (A) SIDR1 : 0000214 /-_+ - - - - - - ---- - 4 SIDR2 : 000025x Serial output data register 0 to 2 Address bit 15 bit 8 bit 7 bit O Initial value SODRO : 00001Dx (SSR) SODRO to SODR2 | = XXXXXXXXa (W) SODR1 : 0000214 | _/+ - - - - ------- SODR2 : 000025x () : Access R/W : Readable and writable : Unused X : Indeterminate(2) Block diagram MB91106 Series Control signals From U-TIMER From external clock sc + Clock select circuit Receive interrupt (to CPU) Transmit clock Receive clock Sl t Receive control circuit Start bit detect (receive data) circuit Receive bit counter Receive parity counter Receive status judge circuit | SC (clock) Transmit interrupt (to CPU) Transmit control circuit Transmit start circuit Transmit bit counter Transmit parity counter SO (transmit data) Receive error generate signal Receive shifter Receive complete Serial input data register SIDR | Transmit shifter Transmit start Serial output data register for DMA SIOR (to DMAC) R-bus MD1 PEN PE MDO P ORE Serial register Serial control SBL Serial status FRE SMR ist ist un) vase Fm) CL wager +) RDRF cso A/D TDRE REC SCKE RXE RIE SOE TXE TIE Control signals 43MB91106 Series 4. U-TIMER (16-bit Timer for UART Baud Rate Generation) The U-TIMER is a 16-bit timer for generating UART baud rate. Combination of chip operating frequency and reload value of U-TIMER allows flexible setting of baud rate. The U-TIMER operates as an interval timer by using interrupt issued on counter underflow. The MB91106 has 3 channel U-TIMER embedded on the chip. When used as an interval timer, two cupple of U-TIMER (chO, ch1) can be cascaded and an interva of up to 2 x can be counted. (1) Register configuration * U-TIMER register ch.0 to ch.2 Address bit 15 bit 0 0 ovals ) UTIMO : 00000078u 8 UTIMO to UTIM2 UTIM1 :0000007Cu | 000000008 UTIM2 : 00000080u U-TIMER reload register ch.0 to ch.2 Address bit 15 bit O 0 ontalvalue wy UTIMRO : 00000078n B UTIMRO to UTIMR2 UTIMR1 : 0000007CuH | 000000008 UTIMR2 : 00000080n * U-TIMER control register ch.0 to ch.2 Address pit 15 bit8 bit 7 bit 0 Initial value UTIMCO :0000007BH_ err rer 1 UTIMC1 : 0000007Fx (Vacancy) | _ UTIMCO to UTIMC2 _ | = 9 - - 000018 (RAY) UTIMC2 : 00000083x () : Access R/W : Readable and writable : Unused (2) Block diagram bit 15 bit O Reload register (U-TIMER) Load bit 15 ' bit O U-TIMER register (UTIM) Underflow MUX Clock ge) U-TIMER control register (UTIMC) 9 (Peripheral clock) (ch.0 only) Underflow tt. U-TIMER To UART 44MB91106 Series PWM Timer The PWM timer can output high accurate PWM waves efficiently. MB91106 has inner 4-channel PWM timers, and has the following features. * Each channel consists of a 16-bit down counter, a 16-bit data resister with a buffer for scyde setting, a 16- bit compare resister with a buffer for duty setting, and a pin controller. * The count clock of a 16-bit down counter can be selected from the following four inner clocks. Inner clock 6, 0/4, 6/16, 6/64 * The counter value can be initialized FFFFH by the resetting or the counter borrow. * PWM output (each channel) 45MB91106 Series 46 (1) Register configuration PCNHO : PCNH1 : PCNR2 : PCNHS : PCNLO : PCNL1 : PCNL2 : PCNL3 : Address OQOOOE6x QOOOEEx QOOOF6u QOOOFEu Address Q000E7x QOOOEFu QO00F7u QOOOFFu Control status register HO to 3 bit 15 bit8 bit 7 bit O PCNHO to PCNH3 (PCNL) 1 Control status register LO to 3 bit 15 bit O i _(PCNH) ___ | __PCNLO toPCNL3__| * PWM cycle setting register 0 to 3 PCSRO : PCSR1: PCSR2 : PCSRS : PDUTO : PDUT1 : PDUT2 : PDUTS : PTMRO : PTMR1 : PTMR2 : PTMRS : Address QO00E2x QOOOEAn QOOOF2u QOOOFAu Address QO00E4n QOOOECu QOOOF4u QOOOFCu Address OQO00E0n OQOO0E8x QOOOFOu QOOOF8u bit 15 bit 0 | PCSRO to PCSR3 PWM duty setting register 0 to 3 bit 15 bit 0 | PDUTO to PDUT3 PWM timer register 0 to 3 bit 15 bit 0 | PTMRO to PTMR3 General control register 1, 2 Address bit 15 bit O GCN1 : 0000DCx GCN Address bit 15 bit8 bit 7 bit O GCN1 : OOOODFH : Access So ~~ Ri <x!1sn i (Vacancy) | GCN? W : Readable and writable : Read only : Write only : Unused : Indeterminate Initial value 0000000- Bs (RW) Initial value 000000008 (RW) Initial value XXXXXXX Xe (W) Initial value XXXXXXXXs XXXXXXXXe Initial value 001100108 000100008 ) Initial value 000000008 (RW)(2) Block diagram * Block diagram (general construction) MB91106 Series 16-bit reload timer ch.0 16-bit reload timer ch.1 General control register 2 External TRGO to TRG3 sw] > TRG input PWM timer ch.0 TRG input General control register 1 (cause selection) PWM timer ch.1 _ TRG input PWM timer ch.2 TRG input y PWM timer ch.3 PWMO PWM1 PWM2 PWM3 * Block diagram (for one channel) PWM cycle PWM duty setting register setting register (PCSR) (PDUT) Prescaler 1/1; { 174 LN ol ck Load 1/16 F- ee 16-bit down counter Peripheral clock TRG input Start Borrow > cmp PPG mask Enable Edge detect Soft trigger Reverse bit H IRQ Interrupt selection SQ )y>- PWM output 4748 MB91106 Series 6. 16-bit Reload Timer The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload timer, a prescaler for generating internal count clock and control registers. Internal clock can be selected from 3 types of internal clocks (divided by 2/8/32 of machine clock). The DMA transfer can be started by the interruption. The MB91106 consists of 3 channels of the 16-bit reload timer. (1) Register configuration * 16-bit reload timer control status register 0 to 2 Address bit 15 bit O TMCSRO : 00002Ex | TMCSRY1 : 000036u TMCSR2 : 000042u Initial value TMCSRO to TMCSR2 ----00008 000000008 (RW) * 16-bit timer register 0 to 2 Address bit 15 bit 0 Initial value TMR1 : 000032n XXXXXXXXs TMR2 : 00003En * 16-bit reload register 0 to 2 Address bit 15 bit O Initial value TMRLRO : 000028u | TMRLRO to TMRLR2 XXXXXXXXs TMRLR?1 : 0000301 TMRLR2 : 00003CH XX XXXXX Xe | ) () : Access R/W : Readable and writable R_: Read Only W_: Write Only : Unused X : IndeterminateMB91106 Series (2) Block diagram 16 16-bit reload register (TMRLR) Reload 16-bit down counter UF IRQ R-bus Clock selector Retrigger IN CTL. EXCK PWM (ch.0, ch.1) AID (ch.2) 9 o9 Oo ot 2 2s Prescaler clear Internal clock 49MB91106 Series 7. Bit Search Module The bit search module detects transitions of data (0 to 1/1 to 0) on the data written on the input registers and returns locations of the transitions. (1) Register configuration * Bit search module 0, 1-detection data register Initial value Address __ bit 31 bitO XXXXXXXXe BSDO : 000003FO XXXXXXXXe BSD1 .000003F4: | BSDO, BSD" XXXXXXX Xo AW) : 4 XXXXXXXXes * Bit search module transition-detection data register Initial value Address __ bit 31 bitO XXXXXXXXes XXXXXXXXB(w 000003F8H | BSDC XXXXXXX Xo XXXXXXXXes * Bit search module detection result register Initial value Address __ bit 31 bitO XXXXXXXXes XXXXXXXXes 000003FCx | BSRR XXXXXXXX_e (A) XXXXXXXXes () : Access R/W : Readable and writable R_: Read only W_: Write only X : Indeterminate (2) Block diagram - Input latch Address decoder Detection mode D-bus Single-detection data recovery Bit search circuit Search result register (BSRR) 50MB91106 Series 8. 10-bit A/D Converter (Successive Approximation Conversion Type) The A/D converter is the module which converts an analog input voltage to a digital value, and it has following features. * Minimum converting time: 5.6 us/ch. (system clock: 25 MHz) * Inner sample and hold circuit * Resolution: 10 bits * Analog input can be selected from 4 channels by program. Single convert mode: 1 channel is selected and converted. Scan convert mode: Converting continuous channels. Maximum 4 channels are programmable. Continuous convert mode: Converting the specified channel repeatedly. Stop convert mode: After converting one channel then stop and wait till next activation synchronising at the beginning of conversion can be peformed. * DMA transfer operation is available by interruption. * Operating factor can be selected from the software, the external trigger (falling edge), and 16-bit reroad timer (rising edge). (1) Register configuration * A/D converter control status register Address bit 15 bit O 0000003An | ADCS * A/D converter data register Address bit 15 bit O 00000038x | ADCR () : Access R/W : Readable and writable R_: Read only : Unused X : Indeterminate Initial value 000000008 000000008 Initial value 000000XXs XXXXXXXXs (RW) (R) 51MB91106 Series 52 (2) Block diagram AVcc ! AVR AVss 14 Internal voltage generator ZN Successive approximation register \Z A/D Converter Data register (ADCR) - A/D Converter control status register (ADCS) A A MPX ANO ANI | 3 5 T 5 AN2 Comparator AN3 | Sample & hold circuit A G o 9 oO a , Trigger start ATG TIMO Timer start (internal connection) (16-bit reload timer 2) 9 (Peripheral clock) Operating clock Prescaler R-busMB91106 Series 9. Interrupt Controller The interrupt controller processes interrupt acknowledgments and arbitration between interrupts. * Hardware Configuration Interrupt controller is configured by ICR resistor, interrupt priority decision circuit, interrupt level, vector generation and HLDREQ cancel request, and has the following functions. * Main Functions NMI request/Interrupt request detection Priority (judgement) decision (via level and vector) Transfer of judged interrupt level to CPU Transfer of judged interrupt vector to CPU Return instruction from the stop mode via NMl/interrupt Generation of HOLD request cancel request to the bus timer 5354 MB91106 Series (1) Register configuration * Interrupt control register 0 to 31, 47 Address bit 7 bit Initial value 00000400x ICROO --- 111118 (RAW) oO 000004014 ICRO1 --- 111118 (RAW) 00000402h ICRO2 --- 111118 (RAW) 000004031 ICRO3 --- 111118 (RAW) 00000404x ICRO4 --- 111118 (RAW) 00000405x ICRO5 --- 111118 (RAW) 00000406x ICRO6 --- 111118 (RAW) 000004074 ICRO7 --- 111118 (RAW) 000004081 ICRO8 --- 111118 (RAW) 00000409x ICRO9 --- 111118 (RAW) 0000040AH ICR10 --- 111118 (RAW) 0000040Bx ICR11 --- 111118 (RAW) 0000040CH ICR12 --- 111118 (RAW) 0000040Du ICR13 --- 111118 (RAW) 0000040Ex ICR14 --- 111118 (RAW) 0000040FH ICR15 --- 111118 (RAW) 00000410H ICR16 --- 111118 (RAW) * Hold request cancel request level setting register Address bit 7 Address 000004114 00000412h 000004134 000004144 00000415x 00000416x 000004174 00000418x 00000419x 0000041AH 0000041BH 0000041CH 0000041Du 0000041Ex 0000041FuH 0000042FH bit 7 bit ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR47 bit O Initial value 000004314 | HRACL ---111118 () : Access R/W : Redable and writable : Unused oO _ Initial value --- 111118 (RW) --- 111118 (RW) --- 111118 (RW) --- 111118 (RW) --- 111118 (RW) --- 111118 (RW) --- 111118 (RW) --- 111118 (RW) --- 111118 (RW) --- 111118 (RW) --- 111118 (RW) --- 111118 (RW) --- 111118 (RW) --- 111118 (RW) --- 111118 (RW) --- 111118 (B/W) RW)(2) Block diagram MB91106 Series Zz INTO*2 A OR Priority judgment RIOO NMI processing 7 ~ x4 Y Rl47 (DLYIRQ) Level judgment ICROO [creo _| * Vector judgment e Lcra7_] Ko Y Level, vector generation DLYI*" 5 _ LEVEL4 to L 7 > LEVELO* HLDREQ cancel Ht HLDCAN*? request | 6 VCT5 to 7 > VCTO*S R-bus *1: DLYI stands for delayed interrupt module (delayed interrupt generation block) (refer to the section 11. Delayed Interrupt Module for detail). *2: INTO is a wake-up signal to clock control block in the sleep or stop status. *3: HLDCAN is a bus release request signal for bus masters other than CPU. *4: LEVEL5 to LEVELO are interrupt level outputs. *5: VCT5 to VCTO are interrupt vector outputs. 55MB91106 Series 10. External Interrupt/NMI Control Block The external interrupt/NMI control block controls external interrupt request signals input to NMI pin and INTO to INT3 pins. Detecting levels can be selected from H, L, rising edge and falling edge (not for NMI pin). (1) Register configuration * Interrupt enable register Address bit 15 bit 7 bit 0 Initial value 00000095x 1 (EIRR) ENIR 000000008 (RW) * External interrupt cause register Address bit 15 bit 8 bit 0 Initial value 000000941 EIRR (ENIR) 1 000000008 (RW) * External interrupt request level setting register Address bit 15 bit 0 Initial value 00000099x | ELVR 000000008 (RW) () : Access R/W : Redable and writable (2) Block diagram 8 + > Interrupt enable register (ENIR) 9 t 5 Interrupt . oo INTO to INT3 request S Gate | Cause F/F - Edge detection circuit NMI 3 Jj 2 Tl! 8 <t > External interrupt cause register (EIRR) 8 nat | External interrupt request level setting register (ELVR) 56MB91106 Series 11. Delayed Interrupt Module Delayed interrupt module is a module which generates a interrupt for changing a task. By using this delayed interrupt module, an interrupt request to CPU can be generated/cancelled by the software. Refer to the section 9. Interrupt Controller for delayed interrupt module block diagram. - Register configuration * Delayed interrupt control register Address bit 7 bit 0 Initial value 000004301 | DICR ss ee 0 8 (RW) () : Access R/W : Redable and writable : Unused 5758 MB91106 Series 12. Clock Generation (Low-power consumption mechanism) The clock control block is a module which undertakes the following functions. * CPU clock generation (including gear function) * Peripheral clock generation (including gear function) * Reset generation and cause hold * Standby function * DMA request prohibit * PLL (multiplier circuit) embedded (1) Register configuration * Reset cause register/watchdog cycle control register Address bit 15 bit 10 bit 9 bit 8 bit O 000004801 RSRR WTCR (STCR) 1 * Standby control register bit 15 bit 7 bit O Address 00000481 1 * DMA controller request squelch register Address bit 15 bit 8 bit O 000004821 PDRR (CTBR) 1 * Timebase timer clear register Address bit 15 bit 7 bit O 00000483, + (PDRR) CTBR * Gear control register Address 000004841 GCR bit 15 bit 8 bit O Address bit 15 bit 7 bit O WPR 00000485y + (GCR) * PLL control register Address bit 15 bit 8 bit O ooooo4ss: [ == PCTR) ss Ss(Vatcancy) 1 : Access W : Readable and writable : Read Only : Write Only : Unused : Indeterminate So ~~ Ri <x!1sn Initial value 1XXXX- 008 (RW) Initial value 000111-- 8 (RW) Initial value ----00008 (RW) Initial value XXXXXXX Xe (W) Initial value 110011- 18 (RW) Initial value XXXXXXX Xe (W) Initial value 00--0- - - 8 (RW)(2) Block diagram MB91106 Series XO 4 Oscillator X11) -af circuit [Gear control block] |_| Gear control register (GCR) A Internal interrupt request Internal reset CPU hold enable DMA request Power on sel RST pin register (CTBR) i Timebase timer clear Count clock Be ee en ee ee ee ee ee eee eee y | Peripheral 4 1 | PLL control regist arr area] gear 1 | cy]: Y |} CPU clock m} PLL ox Internal clock }____'_. Internal bus clock 8 3 | generation }______- External bus clock 4/2 oO circuit Peripheral ' DMA clock ________+_ Internal peripheral clock io [Stop/sleep control block] -------} ----------------4--- 2222-2222 een nner e en eee ; v v Standby control ' register (STCR) > STOP state i > Status : ' transition i+ SLEEP state ; control circuit CPU hold request ~ Reset |i Internal reset ' generation] : 4 F/F c--- [DMA prohibit circuit] ----p-------2-]-r-r-r-rceprcec ec cen peccc coco rene nc nc nc nc nce t DMA request prohibit register (PDRR) [Reset cause circuit] --------------fperr sn ner repre ence prc cr cc rece r rect cree i oy yy { >| Reset cause register (RSRR) z--> [Watchdog control block] ----------r--r-0rsc re proc neo tcc nepecc nec tcc src scc nec scc nes | Watchdog reset generation postpone register (WPR) Watchdog reset postpone register F/F 5960 MB91106 Series 13. External Bus Interface The external bus interface controls the interface between the device and the external memory and also the external I/O, and has the following features. 25-bit (32 Mbytes) address output 6 independent banks owing to the chip select function. Can be set to anywhere on the logical address space for minimum unit 64 Kbytes. Total 32 Mbytes x 6 area setting is available by the address pin and the chip select pin. 8/16-bit bus width setting are available for every chip select area. Programmable automatic memory wait (max. for 7 cycles) can be inserted. DRAM interface support Three kinds of DRAM interface: Double CAS DRAM (normally DRAM I/F) Single CAS DRAM Hyper DRAM 2 banks independent control (RAS, CAS, etc. control signals) DRAM select is available from 2CAS/1WE and 1CAS/2WE. Hi-speed page mode supported CBR/self refresh supported Programmable wave form Unused address/data pin can be used for I/O port. Little endian mode supported Clock doublure: Internal bus 50 MHz, external bus 25 MHz (at source oscillation 12.5 MHz)(1) Register configuration MB91106 Series * Area select register 1 to 5 Address bit 15 bit 0 0000060Cx | ASRI | 000006101 | ASR2 | 000006141 | ASR3 | 000006181 | ASR4 | 0000061CH | ASR5 | Area mask register 1 to 5 Address bit 15 bit O AMR1 : OOOOO60Ex AMR2 : 0000061 2x | AMR1 to AMR5 | AMR3 : 000006161 AMR4 : 0000061Au AMRS5 : 0000061Ex Area mode register 0, Address AMDO : 000006201 AMD1 : 000006214 AMD32 : 00000622u | AMD4 : 000006231 | 1,32,4,5 bit 15 bit8 bit 7 bit 0 AMDO | AMD1 | AMD32 | AMD4 | cere rcrcccc cc 4 AMD5 : 000006241 AMD5 ! (DSCR) | DRAM signle control register Address 000006251 | bit 15 bit8 bit 7 bit O i (AMDS) =| SCR Refresh control register Address pit 15 bit 0 000006261 | RFCR | External pin control register 0, 1 Address bit 15 bit 0 EPCRO : 00000628 _| EPCRO | EPCR1 :0000062An | EPCR1 | DRAM control register 4, 5 Address bit 15 bit O DMCR44 : 0000062CH | DMCRB : 0000062Ex DMCR4, DMCRS5 | Litter endian register Address 000007FEx Mode register Address 000007FFH | () : Access bit 15 bit8 bit 7 bit O bit 15 bit8 bit 7 bit O R/W : Redable and writable W_: Write only : Unused X : Indeterminate Initial value 000000008 000000018 000000008 000000028 000000008 000000038 000000008 000000048 000000008 000000058 Initial value 000000008 000000008) Initial value ---001118 0--000008 000000008 0--000002 (RW) (RW) 0- - 0000028 (RW) Initial value 000000008 (W) Initial value --XXXXXXBs Q0--- 0002") Initial value ----11008 -1111111.8 cree 1.8 111111118 (W) (W) Initial value 000000008 0000000- 2 (RW) Initial value cree 000. (W) Initial value XXXXXXX Xs (W) 61(2) Block diagram MB91106 Series A-OUT DRAM control register (DMCR) | External data bus Write buffer MUX Read buffer DATA BLOCK ee eee ADDRESS BLOCK ~ + External address bus [finpace} |_| Address buffer Shifter Area select 6 Fan Fok |__reqister(ASR)__| CSO to CS5 register ANT) L__ Comparator RASO, RAS1 8 CSOL, CSIL ontrol CSOH, CS1H DWO, DW1 Underflow Refresh counter register (RFCR) | External pin control block } S RD WRO, WR1 All blocks control : 4 BGRNT qo Registers and control CLKm@ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings MB91106 Series (Vss = AVss = 0.0 V) Parameter Symbol Unit Remarks Min. Max. Power supply voltage Veo Vss 0.3 Vss + 4.0 Vv 4 Analog supply voltage AVcc Vss 0.3 Vss + 4.0 Vv *2 Analog reference voltage AVRH Vss 0.3 Vss + 4.0 Vv *2 Analog pin input voltage Via Vss 0.3 AVcc+ 0.3 Vv Input voltage Vi Vss 0.3 Veco+ 0.3 Vv Output voltage Vo Vss 0.3 Veco+ 0.3 Vv L level maximum output current lou _ 10 mA *3 L level average output current loLav _ 8 mA *4 L level maximum total output current | Zlot _ 100 mA L level average total output current ZloLav _ 50 mA *5 H level maximum output current lon _ -10 mA *3 H level average output current loHav _ 4 mA *4 H level maximum total output current | Zlox _ 50 mA H level average total output current ZloHav _ 20 mA *5 Power consumption Pp _ 500 mw Operating temperature TA 0 +70 C Storage temperature Tstg 55 +150 C 1: Vcc must not be less than Vss 0.3 V. *2: Make sure that the voltage does not exceed Veco + 0.3 V, such as when turning on the device. *3: Maximum output current is a peak current value measured at a corresponding pin. 4: Average output current is an average current for a 100 ms period at a corresponding pin. 5: Average total output current is an average current for a 100 ms period for all corresponding pins. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 63MB91106 Series 64 2. Recommended Operating Conditions (Vss = AVss = 0.0 V) Value Parameter Symbol - Unit Remarks Min. Max. Veco 3.0 3.6 Vv Normal operation Power supply voltage ini pply g Veo 30 36 Vv Retaining the RAM state in stop mode Analog supply voltage AVcc Vss0.3 | Vss + 3.6 Vv Analog reference voltage AVRH AVss AVcc Vv Operating temperature TA 0 +70 CMB91106 Series - Normal operation warranty rage Vee (V) Normal operation warranty range (Ta = 0C to +70C) Net masked area are fcrr D> @ 36}- = a g 3.0 L- fer/fepp 0 0.625 25 50 (MHz) Internal clock - External/Internal clock setting rage fcr/fcpp (MHz) @ fer .-4-50--|----------------------- *, CPU = 1 E l oO l an 1 S PLL system (12.5MHz(Fixed) 4 multiplication) oT I g % ! Oo ! o ' . ug fcpp -;-+-25-4----------------------- Peripheral c ! o = 9 12.5 }----------------------- a. Divide-by-2 system oO I I = ! -E-LE--5-4------------------ ! I 5 ; 0 t 1 + Fe 0 10 12.5 25 (MHz) ! ! $$ External clock 1 rs Self-oscillation Notes: When using PLL, the external clock must be used need 12.5 MHz. PLL oscillation stabilizing period > 100 ps The setting of internal clock must be within above ranges. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 65MB91106 Series 3. DC Characteristics (Voc = 3.0 V to 3.6 V, Vss = AVss = 0.0 V, Ta = 0C to +70C) capacitance AVcc, AVss, Vss Value Parameter |Symbol Pin name Condition - Unit}; Remarks Min. Typ. Max. Input pin except Vi for hysteresis 0.7 x Vec Vec+0.3] V input NMI, RST, P40 to P47, H level input in e Be voltage Orel, 9 V P70, P81, Hysteresis IHS P83 to P85, _ 0.8 x Vcc _ Vec+0.3] V input PAO to PA6, PBO to PB7, PEO to PE7, PFO to PF7 Input other than Vit following Vss 0.3 0.25 x Vec| V symbols NMI, RST, P40 to P47, L level input in e Be voltage Oro, g V P70, P81, Hysteresis Ls P83 to P85, _ Vss 0.3 _ 0.2xVec| V input PAO to PA6, PBO to PB7, PEO to PE7, PFO to PF7 H level output Vec = 3.0 V voltage Vou P2 to PF low = -4.0mA Veco 0.5 _ _ Vv L level output Vec = 3.0 V voltage Vou P8 to PF lo. = 8.0 mA a a 0.4 V Input leakage Voc =3.6V current Vy (Hi-Z output lui P2 to PF avn VeVi -5 _ +5 LA leakage current) ce Pull-up par Veco = 3.6 V resistance Reutt RST Viz045V 25 50 100 kQ _ (4 multiplication) loo Veo Volsewe | 70 150 | mA Operation at co SS 50 MHz Power supply _ current locs Veo ere} wie _ 37 70 mA |Sleep mode loch [Voc Wee 14 150 | uA |Stop mode Input Cn Except for Vec, __ __ 10 __ oF4. AC Characteristics (1) Measurement Conditions MB91106 Series (Vcc = 3.0 V to 3.6 V) Value Parameter Symbol - Unit Min. Typ. H level input voltage Vi _ 1/2* x Vec Vv L level input voltage Vit _ 1/2* x Vec Vv H level output voltage Vou _ 1/2* x Vec Vv L level output voltage Vor _ 1/2* x Vec Vv * : Input rise/fall time is 10 ns. and less. 0.0V Input Vin VitMB91106 Series (2) Clock Timing Rating (Vcc = 3.0 V to 3.6 V, Vss = AVss = 0.0 V, Ta = 0C to +70C) P t Symbol| Pin Conditi Value Unit | Remark arameter mbo ondition ni emarks y name Min. Max. Self-oscillation at 12.5 MHz Fe X0, X1_ | Internal operation 12.5 12.5 MHz at 50 MHz (Via Clock frequency PLL,quadruplex) Self-oscillation Fe XO, X1 (divide-by-2 input) 10 25 MHz External clock Fe XO, X1 (divide-by-2 input) 10 25 MHz Self-oscillation at 12.5 MHz ; tc X0, X1_ | Internal operation 80 ns Clock cycle time at 50 MHz (Via PLL,quadruplex) te XO, X1 40 100 ns Self-oscillation at Frequency shift ratio 12.5 MHz (when locked) Af ___|Internal operation 5 % |*1 at 50 MHz (Via PLL,quadruplex) Input clock Pwu, 12.5 MHz to Pwr XO, X1 25.0 MHz 20 _ ns_ |pulse to XO and X1 Input clock pulse width Input clock Pwo XO 12.5 MHz and less 25 _ ns_ |pulse to XO only Input clock rising/falling time ee XO, X1 _ _ 8 ns | (tor + ter) Internal operating clock for {CPU system 0.625** | 50 MHz frequency fopp |Peripheral system | 0.625*2 25 MHz Internal operating clock tcp |CPU system 20 1600** | ns cycle time tope |Peripheral system 40 1600*2 | ns 1: Frequency shift ratio stands for deviation ratio of the operating clock from the center frequency in the clock multiplication system. +0 At =e x100 (%) Center frequency fo 0 o 2: These values are for a minimum clock of 10 MHz input to XO, a divide-by-2 system of the source oscillation and a 1/8 gear. 68MB91106 Series Load conditions Output pin 7 | C = 50 pF - Clock timing rating measurement conditions tc f 0.8 Vcc \ 0.8 Vcc 0.8 Vcc f \ / Pwu Pwr tcr tcr o / b 0.2 Voc 0.2 Vecq 69MB91106 Series 70 (3) Clock Output Timing (Vcc = 3.0 V to 3.6 V, Vss = AVss = 0.0 V, Ta = 0C to +70C) Parameter Symbol | Pin name | Condition - Value Unit | Remarks Min. Max. teye CLK _ tep! _ ns |*2 Cycle time teve CLK 5a ne 2 x tep! ns CLK T > CLK JL TcHeL CLK 1/2 xteve-5 | 1/2xtevc+5 | ns |*8 CLK / > CLKT tetcH CLK 7 1/2 xteve-5 | 1/2xtevc+5 | ns |*4 1: For information on tce (internal operating clock cycle time), see (2) Clock Timing Rating. 2: teyc is a frequency for 1 clock cycle including a gear cycle. Use the doublure when CPU frequency is above 25 MHz. *3: Rating at a gear cycle of x 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute n in the following equations with 1/2, 1/4, 1/8, respectively. Min. : (1 n/2) x teve - 10 Max. : (1 n/2) x teve + 10 Select a gear cycle of x 1 when using the doublure. 4: Rating at a gear cycle of x 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute n in the following equations with 1/2, 1/4, 1/8, respectively. Min. :n/2 x teve 10 Max. : n/2 x teve + 10 Select a gear cycle of x 1 when using the doublure. CLKMB91106 Series The relation between source oscillation input and CLK pin for configured by CHC/CCK1/CCKO settings of GCR (gear control register) is as follows: However, in this chart source oscillation input means XO input clock. Source oscillation input | | | | | | | | | | | | | | | | | (when using the doublure) | 1 1 1 1 1 ' : ' : ' : ' 1 ' 1 (1) PLL system ' (CHC bit of GCR set to O) : (a) Gear x 1 CLK pin ee tere CCK1/0: 00 i i i Source oscillation input TL JU dU Ur UE Ur UU uo uu (2) 2 dividing system (CHC bit of GCR set to 1) (a) Gear x 1 CLK pin bt teye et i i CCK1/0: 00 | | | | | | (b) Gearx 1/2 CLK pin. 9 HH tere CCK1/0: 01 | | | (c) Gearx 1/4 CLK pin = + i teve CCK1/0: 10 | (d) Gearx 1/8 CLK pin bes CCK1/0: 11 felt Lib 7172 MB91106 Series - Ceramic oscillator applications Recommended circuit (2 contacts) Recommended circuit (3 contacts) x0 x1 X0 x | i | | i | 1 Ci C2 ! C1, C2 internally & CG os : i connected. 7/7 7/7 *: Murata Mfg. Co., Ltd. - Discreet type Oscillation frequency Model Load capacitance Power supply voltage [MHz] Ci = C2 [pF] Vcc [V] CSALILILIMG 30 2.9 to 5.5 CSTOLDOMGw (30) 5.00 to 6.30 CSALILILIMG093 30 2.7 to 5.5 CSTLILILIMGWwog3 (30) CSALIINIMTZ 30 2.9 to 5.5 CSTOUDILIMTW (30) 6.31 to 10.0 CSALINLIMTZ093 30 2.7 to 5.5 CSTLOILILIMTWwog3 (30) CSALIINIMTZ 30 3.0 to 5.5 CSTODOMTW (30) 10.1 to 13.0 CSALILILIMTZ093 30 2.9 to 5.5 CSTLILILIMTwog3 (30) CSALITILIEIMXZ040 15 13.01 to 15.00 3.2 to 5.5 CSTOUUUMxwoc3 (15) (): C1 and Ce internally connected 3 contacts type.MB91106 Series (4) Reset Input Ratings (Vcc = 3.0 V to 3.6 V, Vss = AVss = 0.0 V, Ta = 0C to +70C) ; Value , Parameter Symbol | Pin name | Condition - Unit | Remarks Min. Max. Reset input time trsTL RST _ tor* x 5 _ ns * : For information on tce (internal operating clock cycle time), see (2) Clock Timing Rating. at tRsTL > RST 0.2 Vcc 0.2 Vcc 7374 MB91106 Series (5) Power on Supply Specifications (Power-on Reset) (AVcc = Vec = 3.0 V to 3.6 V, Vss = AVss = 0.0 V, Ta = 0C to +70C) Value Parameter Symbol | Pin name} Condition - Unit Remarks Min. Max. Vee < 0.2 V oa before the Power supply rising time tr Veo Veco =3.3V _ 18 ms power supply rising Power supply shut off time | torr Veo 1 _ ms Repeated operations a: ae 2 x te* x 220 Oscillation stabilizing time | tose _ +100 us _ ns * For information on tc (clock cycle time), see (2) Clock Timing Rating. Note: Sudden change in supply voltage during operation may initiate a power-on sequence. To change supply voltage during operation, it is recommended to smoothly raise the voltage to avoid rapid fluctuations in the supply voltage. Veco A voltage rising rate of 50 mV/ms or less is recommended. Vss 336 ms approx. (@12.5 MHz) | \/ | Veo J lose (Oscillation stabilizing time) ___ 0.8 Vec RST tRsTL + (tc x 219) trstL: Reset input time Notes: Set RST pin to L level when turning on the device, at least the described above duration after the supply voltage reaches Vcc is necessary before turning the RST to H level. Some internal resistors which are initialized only via power on reset are embedded in the device. To initialize these resistors, run power on reset by returning on the power supply.MB91106 Series (6) Normal Bus Access Read/write Operation (AVcc = Vec = 3.0 V to 3.6 V, Vss = AVss = 0.0 V, Ta = 0C to +70C) Value Parameter Symbol) Pinname_ | Condition - Unit Remarks Min. Max. CLK, Le . tcHos GS0 to GS5 15 ns CSO to CS5 delay time t CLK, __ 15 ns nes |CS0 to CS5 ; CLK, Address delay time tcHav A24 to AOO _ 15 ns ; CLK, Data delay time tcHDv D31 to D16 _ 15 ns __ ; ToLRL CLK, RD 6 ns RD delay time = tcLRH CLK, RD 6 ns t CLK, __ _ _ 6 ns oo cow WRO, WR1 WRO, WRi1 delay time t CLK, __ _ 6 ns ow WRO, WR1 Valid address valid data i A24 to AOO, __ 3/2 x teyce! ns *2 input time AYN D31 to D16 25 *3 . , , RD, * * RD J valid data input time |triov D31 to D16 _ teve*1 10] ns |*2 Datasetup > RD 7 time _ |tosaH RD, 10 ns P D31 to D16 RD T- data hold time tRHDx RD, 10 ns D31 to D16 1: For information on tcyc (a cycle time of peripheral system clock), see (3) Clock Output Timing. 2: When bus timing is delayed by automatic wait insertion or RDY input, add (tcye x extended cycle number for delay) to this rating. *3: Rating at a gear cycle of x 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute n in the following equation with 1/2, 1/4, 1/8, respectively. Equation: (2 n/2) x teve 25 7576 MB91106 Series CLK CSO to CS5 A24 to A0O D31 to D16 D31 to D16 BA1 BA2 teye | 2.4V 2.4V 2.4V 0.8V 0.8V tcHcsL tcHcsH 2.4V 10.8 V tcHav t 24V 2.4V x 0.8 V 0.8V tcLRL tcLRH f2.4V Nos V / tRLpv ~ tRHpx tavpv 24V 2.4V O8V KR eet Posy | > T tosrH tcLwL 2.4V 0.8V tcLwH tcHpv 2.4V : 2.4V mi Vv Write 08V x(7) Ready Input Timing (Vcc = 3.0 V to 3.6 V, Vss = AVss = 0.0 V, Ta = 0C to +70C) MB91106 Series Parameter Symbol Pin name Condition Value Min. Max. Unit Remarks RDY set up time > CLK J trpys RDY, CLK CLK J> RDY hold time TRDYH CLK, RDY 15 ns 0 ns CLK RDY When wait(s) is inserted. RDY When no wait is inserted. 24V 60.8 V ~a (RDYH trpys K0.8 VI 0.8V trpys K0.8V / @ (RDYH ~2.4V fo 4 Vi fo av \ K0.8 V 77MB91106 Series 78 (8) Hold Timing (Vcc = 3.0 V to 3.6 V, Vss = AVss = 0.0 V, Ta = 0C to +70C) Value Parameter Symbol | Pin name | Condition - Unit Remarks Min. Max. aaanT ; cHec | BGRNT BGRNT delay time t CLK, _ 6 ns nest | BGRNT _ je ating > BGRNT J TXHAL BGRNT teve* 10 | tevc* + 10] ns BGRNT 7 pin valid time THAHV BGRNT teve* 10 | teve*+ 10] ns * : For information on teyc (a cycle time of peripheral system clock), see (3) Clock Output Timing. Note: There is a delay time of more than 1 cycle from BRQ input to BGRNT change. tcyc 24V 24V 24V 2.4V CLK ara / \ > <ai (cHBGL > <t tcHBGH BGRNT Yoav. \ 0.8V / taal r bhw tHaHv Each pin High impedance(9) Normal DRAM Mode Read/Write Cycle (Vcc = 3.0 V to 3.6 V, Vss = AVss = 0.0 V, Ta = 0C to +70C) MB91106 Series Value Parameter Symbol Pin name | Condition - Unit; Remarks Min. Max. ; TcLRAH CLK, RAS 6 ns RAS delay time TCHRAL CLK, RAS 6 ns CLK, CSOH, tcLcasL CS1H, CSOL, 6 ns . CSiL CAS delay time CLK, CSOH, teLcasH CS1H, CSOL, 6 ns CSiL ROW address delay time | tcurav CLK, 15 ns y A24 to AOO COLUMN address delay CLK, time toncav | 424 to AOO 18 ns ; TcHDWL CLK, DW*2 7 15 ns DW delay time tcHDWH CLK, DW*2 15 ns . CLK, Output data delay time tcHpv1 D31 to D16 _ 15 ns RAS J-> valid data input i RAS, __ 5/2 xteyc! ns *3 time RLDY D31 to D16 -16 *4 . . CSOH, CS1H, nae J valid data input |i. |GSoL, CS1L, |teyot17] ns |*3 D31 to D16 CSOH, CS1H, CAS 7T-> data hold time tcaDH CSOL, CS1L, 10 ns D31 to D16 1: For information on tcyc (a cycle time of peripheral system clock), see (3) Clock Output Timing. *2: DW expresses that DWO, DW1 and CSOH, CS1H are used for WE. *3: When Q1 cycle or Q4 cycle is extended for 1 cycle, add tcyc time to this rating. 4: Rating at a gear cycle of x 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute n in the following equation with 1/2, 1/4, 1/8, respectively. Equation: (3 n/2) x teve 16 79MB91106 Series CLK RAS CSOH, CS1H, CSOL, CSIL, A24 to A0O D31 to D16 D31 to D16 Q1 Q2 Q3 Q4 Q5 fa tcyc r vO AV \ 2.4V ZF 24V 2.4V 2.4V / 0.8 V, 0.8V 0.8V J4 Vv \os V / tcLRaH - a ~ tcHRAL tcLcasL tcLcasH 724 \ 0.8V / tcHcav ~~ tcurav 2.4V 2.4V 2.4V 2.4V O8V ROW address O8V O8V COLUMN address O8V i tRLpv tcapH 2.4V 0.8V 2.4V 08V > tcHDwL ~~ tcHDwH 2.4V . 2A 0.8V Write O8V ~~ tcHpv1 80(10) Normal DRAM Mode Fast Page Read/Write Cycle (Vcc = 3.0 V to 3.6 V, Vss = AVss = 0.0 V, Ta = 0C to +70C) MB91106 Series Value Parameter Symbol; Pinname_ | Condition - Unit Remarks Min. Max. RAS delay time tcLRAH CLK, RAS 6 ns CLK, CSOH, tcLcasL CS1H, CSOL, 6 ns ; CSIL CAS delay time CLK, CSOH, teLcasH CS1H, CSOL, 6 ns CSIL COLUMN address delay CLK, time toroav | 424 to AOO 1S) ns DW delay time tcHowH = | CLK, DW*? 15 ns ; CLK, Output data delay time tcHpv1 D31 to D16 _ 15 ns ; , CSOH, CS1H, nae J valid datainput |i. |GSOL, CSIL, |teve"!-17) ns |*3 D31 to D16 CSOH, CS1H, CAS 7T-> data hold time tcaDH CSOL, CS1L, 10 ns D31 to D16 1: For information on tcyc (a cycle time of peripheral system clock), see (3) Clock Output Timing. *2: DW expresses that DWO, DW1 and CSOH, CS1H are used for WE. *3: When Q4 cycle is extended for 1 cycle, add tcyc time to this rating. 81MB91106 Series 82 CLK RAS CSOH, CS1H, CSOL, CS1L, A24 to A0O D31 to D16 D31 to D16 Qs Q4 Q5 Q4 Q5 feav\ 24V Sf \_A? Nosy 08V av tcLRaAH aa 24V tcLcasL > ~tt > ~ai [cLcasH 2.4V / Noov VN tcucav COLUMN address Sav | COLUMN address 63 COLUMN address oay I- tcLDv |} tcapH 2.4V 2.4 V. 24V Tae Read) Dav ~ tcHDpwH 2.4V tcHpv1 On oR Write On op x on oR << Write xs Vv 0.8V(11) Single DRAM Timing (Vcc = 3.0 V to 3.6 V, Vss = AVss = 0.0 V, Ta = 0C to +70C) MB91106 Series Value Parameter Symbol} Pinname_ | Condition - Unit; Remarks Min. Max. ; ToLRAH2 CLK, RAS 6 ns RAS delay time tcHRAL2 CLK, RAS 6 ns CLK, CSOH, tcHeasLe |CS1H, CSOL, n/2 x teyc*!| ns ; CS1L CAS delay time CLK, CSOH, tcncasHe | CS1H, CSOL, 6 ns CS1L ROW address delay time _| tcnrave CLK, _ 15 ns y A24 to A0O COLUMN address delay CLK, time toroave | a4 to ADO - 18 ns __ ; tcHpwi2 =| CLK, DW*2 15 ns DW delay time tcHpwHe =| CLK, DW*? 15 ns ; CLK, Output data delay time tcHpv2 D31 to D16 _ 15 ns ; CSOH, CS1H, _ CAS 1-> Valid data input io.oye |CSOL, CSIL, {taney | ns D31 to D16 ove CSOH, CS1H, CAS T- data hold time tcaDH2 CSOL, CS1L, 10 ns D31 to D16 1: For information on tcyc (a cycle time of peripheral system clock), see (3) Clock Output Timing. *2: DW expresses that DWO, DW1 and CSOH, CS1H are used for WE. 83MB91106 Series teyc Qi Q2 Q3 Q48 Q48 CLK PAV F24V 2.4V 4V 2.4V 24V ve ee tcLRAH2 ~~ tcHRAL2 tcHcasL2 CSOH, hat (CHCASH2 CS1H ; 4B 4 v\ 24V CSOL, 0.8 V, L0.8 v/ / CS1L, ADA 4V 24V to AOO gy ROWaddress Oey COLUMN-OX COLUMN-1 XL COLUMN-2 } tcHRav2 tcHcav2 ~ tcaDH2 t teL_pv2 D31 to D16 < Read-0 4 Read Read? ) (Read) , DW \ DAV (Read) 40.8 V tcHDWL2 e tcHDwH2 D31 to D16 24V : Oa V 24V\A24V 24V oo ne O8V Write-0 1O8V 08 V KOs v 08 VX Write-2 x (Write) - ~ tcHpv2 tcupv2 Write-1 1: Q4S indicates Q4SR (Read) of Single DRAM cycle or Q4SW (Write) cycle. 2: .... indicates the timing when the bus cycle begins from the high spead page mode.MB91106 Series (12) Hyper DRAM Timing (Vcc = 3.0 V to 3.6 V, Vss = AVss = 0.0 V, Ta = 0C to +70C) Value Parameter Symbol} Pinname_ | Condition - Unit; Remarks Min. Max. ; TcLRAHS CLK, RAS 6 ns RAS delay time tcHRAL3 CLK, RAS 6 ns CLK, CSOH, tcHcasits =| CS1H, CSOL, n/2 x teyc*!| ns CS1L CAS delay time CLK, CSOH, tcucasHs =| CS1H, CSOL, 6 ns CS1L ROW address delay time tcHRAV3 CLK, 15 ns y A24 to AOO COLUMN address delay CLK, time tonoavs | 424 to ADO 18 ns tcHAL3 CLK, RD _ 15 ns RD delay time tcHRHS CLK, RD 15 ns tcLALs CLK, RD 15 ns _ ; TcHDWLs CLK, DW*2 15 ns DW delay time tcHowHs =| CLK, DW*2 15 ns . CLK, Output data delay time tcHovs D31 to D16 _ 15 ns . . CSOH,CS1H, nae +> valid data input tcLovs CSOL, CS1L, tevc 17 ns D31 to D16 CSOH,CS1H, CAS J data hold time tcaDH3 CSOL, CS1L, 10 ns D31 to D16 1: For information on tcyc (a cycle time of peripheral system clock), see (3) Clock Output Timing. *2: DW expresses that DWO, DW1 and CSOH, CS1H are used for WE. 8586 MB91106 Series CLK RAS CSOH, CS1H, CSOL, CSI1L, A24 to A0O DW (Read) D31 to D16 (Read) DW (Read) D31 to D16 (Write) "Ol wae. p+_ tcyc ] *4 Q1 Q2 Q3 Q4H Q4H Q4H 24V 2.4V 2.4V 2.4V 2.4V 2.4 PP Novy \ PE _ JP Now \_f \_ JP 4V 0.8V ~ tcLRAH3 ~ tcHRAL3 tcHcasL3 -4q > tcHCASH3 x 4 W 0.8 V, losy/ Mba / 24V 2.4 Vea 7 . . x O8V ROW address 08 ogy COLUMN-0 COLUMN xX COLUMN-2 See tcurav3 tcHcav3 4 ee 2.4V ~ tcHRH3 tcaDH3 | Nee Vv 0.8V \ 24V 0.8 V > tcHpw13 > tcHDwH3 *2 2.4V ito. wT 2.4V 2.4V ite- O8V Write-O hk OB V O8V x x Write-2 x Write-1 t tcupv3 tcupv3 1: Q4S indicates Q4SR (Read) of Single DRAM cycle or Q4SW (Write) cycle. indicates the timing when the bus cycle begins from the high spead page mode.(13) CBR Refresh (Vcc = 3.0 V to 3.6 V, Vss = AVss = 0.0 V, Ta = 0C to +70C) MB91106 Series Value Parameter Symbol} Pinname_ | Condition - Unit Remarks Min. Max. ; tcLRAH CLK, RAS _ 6 ns RAS delay time TCHRAL CLK, RAS 6 ns CLK, CSOH, tcLcasL CS1H, CSOL, _ 6 ns CSI1L CAS delay time CLK, CSOH, tcLcasH CS1H, CSOL, 6 ns CSI1L bhg Ccyc R1 R2 R3 R4 e24V\ 24V 24V CLK Jf \ J \.0.8 V \.0.8 V \ Sf \o.8 Vv RAS 2.4V \ o8Vv / al tcLRAH > ~<a tcHRAL CSOH, CS1H, / o8v 24V CSOL, CSI1L, aad tcLcasL | tcLcasH 87MB91106 Series 88 (14) Self Refresh (Vcc = 3.0 V to 3.6 V, Vss = AVss = 0.0 V, Ta = 0C to +70C) Value Parameter Symbol} Pin name | Condition - Unit Remarks Min. Max. ; tcLRAH CLK, RAS _ 6 ns RAS delay time TCHRAL CLK, RAS 6 ns CLK, CSOH, tcLcasL CS1H, CSOL, _ 6 ns CSI1L CAS delay time CLK, CSOH, teLcasH CS1H, CSOL, 6 ns CSI1L SR3 SR3 24V CLK \ / J \f \ 0.8V i) tcHRAL ~ tcLRAH y24V RAS 08V / i) CSOH, CS1H, /_ CSOL, \ 08V J 24V CSIL, 5 5 i t tcLcasL > ~a tCLCASH(15) UART Timing (Voc = 3.0 V to 3.6 V, Vss = AVss = 0.0 V, Ta = 0C to +70C) MB91106 Series Value Parameter Symbol | Pin name | Condition - Unit Remarks Min. Max. Serial clock cycle time tscyc _ 8 x teyor _ ns SCLK J SOUT delay time | tstov Internal -80 80 ns Valid SIN + SCLK T tivsH __|shift clock 100 ns : mode SCLK T valid SIN hold : tsHIx _ 60 ns time Serial clock H pulse width | tsHst _ 4 x tevor _ ns Serial clock L pulse width | tstsH _ 4 x tevor _ ns SCLK J> SOUT delay time | tsvov ~__| External 150. | ns shift clock Valid SIN + SCLK T tivsH _ mode 60 ns SCLK TR valid SIN hold tux _ 60 _ ns time * :For information on tcver (a cycle time of peripheral system clock), see (2) Clock Timing Rating. Notes: This rating is for AC characteristics in CLK synchronous mode. Internal shift clock mode SCLK 0.8V SOUT M$ tsex_ SIN External shift clock mode SCLK pw_ IsuHs_ a oll 0.8 Veo(2.6V) 0.8Vcc 3 0.2 Vcc K 0.8 Voo(2.6V) SOUT 2@ $$ tse X SIN 0.8 Vcc 7 0.2 Vcc 3 89MB91106 Series (16) Trigger System Input Timing (Vcc = 3.0 V to 3.6 V, Vss = AVss = 0.0 V, Ta = 0C to +70C) ; Value ; Parameter Symbol Pin name Condition - Unit Remarks Min. Max. A/D start trigger input time | tarex ATG _ 5 x tevor _ ns For information on tevcr (a cycle time of peripheral system clock), see (2) Clock Timing Rating. tarcx > ATG [ \ 0.2 Vec 0.2 Vee 7 90(17) DMA Controller Timing MB91106 Series (Vcc = 3.0 V to 3.6 V, Vss = AVss = 0.0 V, Ta = 0C to +70C) Value Parameter Symbol Pin name Condition - Unit | Remarks Min. Max. DREQ input pulse width | torwH DREQ@O to DREQ2 2 x teyo* _ ns t CLK, _ 6 ns DACK delay time CLDE DACKO to DACK2 (Normal bus) CLK Normal DRAM , _ ( ) totoH | DACKO to DACK2 8 ns t CLK, _ 6 ns EOP delay time CEL EOPO to EOP2 (Normal bus) CLK Normal DRAM , _ \ toe | EOPO to EOP2 6 ns i TcHDL CLK, n/2 x teve* | ns DACK delay time DACKO to DACK2 (Single DRAM) CLK Hyper DRAM , (Hyp ) tox | DACKO to DACK2 8 ns i TCHEL CLK, n/2 x teve* | ns EOP delay time EOPO to EOP2 (Single DRAM) CLK Hyper DRAM , (Hyp ) tcHEH EOPO to EOP? 6 ns * : For information on teyc (a cycle time of peripheral system clock), see (3) Clock Output Timing. DACKO to DACK2 CLK / EOP0 to EOP2 (Normal bus) (Normal DRAM) DACKO to DACK2 (Single DRAM) (Hyper DRAM) EOPO to EOP2 tt tcc > F2.4V \ o8v 7 24V o8v ~ - teLpL tcLDH i tcLEL tcLEH \ 2.4V * 0.8 V \ O08V 24V tcHpL > toupH tcHEL torwH a Vv DREQ0O to DREQ2 JZ 24V 24V 9192 MB91106 Series 5. A/D Converter Block Electrical Characteristics (Vcc = AVcc = 3.0 V to 3.6 V, Vss = AVss = 0.0 V, AVRH = 3.0 V to 3.6 V, Ta = 0C to +70C) : Value ; Parameter Symbol} Pin name - Unit Min. Typ. Max. Resolution _ _ _ 10 10 bit Total error _ _ _ _ +3.0 LSB Linearity error _ _ _ _ +2.5 LSB Differentiation linearity error +1.9 LSB Zero transition voltage Vor ANO to ANS | 1.5LSB +0.5LSB +2.5LSB | mV wa: AVRH AVRH - AVRH + Full-scale transition voltage Vest ANO to AN3 45LSB + 5LSB 05LSB mv Conversion time _ _ 5.6 *1 _ _ us Analog port input current lain ANO to AN3 _ 0.1 10 LA Analog input voltage Vain ANO to AN3 AVss _ AVRH Vv Reference voltage |AVRH AVss AVcc Vv la AVcc 4 mA Power supply current IaH AVcc _ _ 5 *2 LA ln AVRH _ 110 _ LA Reference voltage supply current IRH AVRH _ _ 5 *2 LA Conversion variance between channels _ ANO to AN3 _ _ 4 LSB *1: Veco = AVcc = 3.0 V to 3.6 V, machine clock 25 MHz 2: Current value for A/D converters not in operation, CPU stop mode (Vec = AVcc = AVRH = 3.6 V)MB91106 Series 6. A/D Converter Glossary Resolution The smallest change in analog voltage detected by A/D converter. * Linearity error A deviation of actual conversion characteristic from a line connecting the zero-traction point (between 00 0000 0000 < 00 0000 0001) to the full-scale transition point (between 11 1111 1110" < 11 11111111). * Differential linearity error A deviation of a step voltage for changing the LSB of output code from ideal input voltage. Total error A difference between actual value and theoretical value. The overall error includes zero-transition error, full- scale transition error and linearity error. Total error 3FF + - 1.5 LSB 3FE + poses --4 Actual conversion characteristic 1 SFD$ 0 anne eee + {1 LSB x (N - 1) ! 2 + 0.5 LSB} ' 5 wy eee 3 i oS w 2 004 + poseeeel i ! Vnt 003 + _t __........ (measured value) Actual conversion i ' characteristic 002 4 .--4 Je--n-na---! L! Ideal characteristic 001 +--+ t------! 0.5LSB ~] bet AVRL AVRH Analog input Vat {1 LSB x (N-1)+0.5 LSB} Total error of digital output N = 1 LSB' [LSB] Vor (ideal value) = AVRL + 0.5 LSB [V] Vest (ideal value) = AVRL 1.5 LSB [V] Vn: A voltage for causing transition of digital output from (N 1) to N (Continued) 9394 MB91106 Series (Continued) Linearity error Differential linearity error SFF > Actual conversion Ideal characteristic characteristic 3Fe + NA Net + ! t ! A t {1 LSB x (N 1) + Vor} ! ' 3FD + -4 Actual characteristic 3 3 Vest } 3 % ----f! (measured 3 N+ poste wg i value) a i 2 oo + oe... NT & ' (measured value) ' 003 + ; ! Actual conversion N-1 + renee l--------- ' characteristic ' ' ' ! ' ' Veit 002 + : 4 i i Var (measured value) Ideal characteristic (measured value) 001 + Ht. N-2 Hh ennennaee | Vor (measured value) Actual conversion characteristic AVRL AVRH AVRL AVRH Analog input Analog input Linearity error of Vat {1 LSB x (N1) + Vor} Differential linearity error Vinenyt Vn +1LSB digital outputN = 77 $587 CL SB] of digital outputN = 4, gg | SBI tLsB = Vesta Vor ny 1022 1 LSB (ideal value) - AVR AVRIL [Vv] 1022 Vor: A voltage for causing transition of digital output from (000)x to (001)x Vest: A voltage for causing transition of digital output from (8FE)x to (3FF)x Vn: A voltage for causing transition of digital output from (N 1)H to N7. Notes on Using A/D Converter MB91106 Series Output impedance of external circuit of analog input under following conditions; Output impedance of external circuit < 7 kQ. If output impedance of external circuit is too high, analog voltage sampling time may be too short for accurate sampling (sampling time is 5.6 us for a machine clock of 25 MHz). * Analog input Equivalent Circuit Analog input pin Sample hold circuit Co O | { Comparator Roni Rone Rons Rona L m Ci Roni: 5 kQ Ronz: 620 kQ Rons: 620 kQ Co: 2 pF 7 Rona: 620 kQ Ci: 2 pF * Error As the absolute value of AVRH decreases, relative error increases. 95MB91106 Series 96 m@ EXAMPLE CHARACTERISTICS (1) H Level Output Voltage (2) L Level Output Voltage Vou (V) Von-lox Vec=3.6V Vec=3.3V Vec = 3.0 V Vec=2.7V lon (mA) Vor (V) Vot-lot 0.25 - Veco =2.7V 0.20 [4 Vcc = 3.0 V LF Woo =3.3V 0.15 A Veco = 3.6 V 0.10 Za FA 0.05 Z| Tas +25C 0.00 1 #2 3 4 5 6 7 8 lo. (mA) (3) H Level Input Voltage/L Level Input Voltage (CMOS Input) (4) H Level Input Voltage/L Level Input Voltage (Hysteresis Input) Vin (V) Vin-Vec 24 2.7 3.0 3.3 3.6 Vee (V) Vin: Threshold when input voltage is set to "H" Level. Vit: Threshold when input voltage is set to "L" Level. Vin (V) Vin-Vec 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 2.4 2.7 3.0 3.3 3.6 Vee (V) Vin: Threshold when input voltage in hysteresis characteristics is set to "H" Level. Vit: Threshold when input voltage in hysteresis characteristics is set to "L" Level.(5) Power Supply Current (fcp = Internal clock frequency) MB91106 Series Icc (MA) Icc-Vec Iccs (mA) Iccs-Vec 100 50 Ta = C 90 45 fcp = 50 MHz fcp = 50 MHz 80 40 fcp = 40 MHz 70 fop = 40 MHz 35 60 30 50 25 40 20 fcp = 20 MHz fcp = 20 MHz 30 15 20 for = 10 MHz 10 for = 10 MHz 10 5 0 0 27 3.0 3.3 3.6 3.9 27 3.0 3.3 3.6 3.9 Vee (V) Vee (V) locH(A) lecH- Voc la (mA) la-AVcc 2.0 2.5 Ta = +25C Ta = +25C 1.8 1) 1.6 2.0 7" 1.4 a 1.2 1.5 2 1.0 a 0.8 1.0 oo 0.6 0.4 0.5 0.2 0.0 0.0 27 3.0 3.3 3.6 2.7 3.0 3.3 3.6 3.9 Vee (V) AVcc (V) Ia(WA) : 430 In-AVcc (6) Pull-up Resistance 125 R (kQ) R-Vec 100 120 Ta = +25C 115 110 105 100 95 90 85 80 27 30 33 3.6 3.9 40 AVcc (V) 27 3.0 3.3 3.6 3.9 Vee (V)MB91106 Series 98 @ INSTRUCTIONS (165 INSTRUCTIONS) 1. How to Read Instruction Set Summary Mnemonic Type OP cyc NZVC Operation Remarks ADD Rj, Ri A A&6 1 CCCC Ri + Rj > Ri * ADD #s5, Ri Cc A4 1 CCCC Ri + 85 > Ri L L L L L L L (1) (2) (3) (4) (5) (6) (7) (1) Names of instructions Instructions marked with * are not included in CPU specifications. These are extended instruction codes added/extended at assembly language levels. (2) Addressing modes specified as operands are listed in symbols. Refer to 2. Addressing mode symbols for further information. (3) Instruction types (4) Hexa-decimal expressions of instructions (5) The number of machine cycles needed for execution a: Memory access cycle and it has possibility of delay by Ready function. b: Memory access cycle and it has possibility of delay by Ready function. If an object register in a LD operation is referenced by an immediately following instruction, the interlock function is activated and number of cycles needed for execution increases. c: If an immediately following instruction operates to an object of R15, SSP or USP in read/write mode or if the instruction belongs to instruction format A group, the interlock function is activated and number of cycles needed for execution increases by 1 to make the total number of 2 cycles needed. d: If an immediately following instruction refers to MDH/MDL, the interlock function is activated and number of cycles needed for execution increases by 1 to make the total number of 2 cycles needed. For a, b, c and d, minimum execution cycle is 1. (6) Change in flag sign * Flag change C : Change :No change 0 : Clear 1 : Set * Flag meanings N : Negative flag Z : Zero flag V : Over flag C : Carry flag (7) Operation carried out by instructionMB91106 Series 2. Addressing Mode Symbols Ri Rj R13 Ps Rs CRi CRj #i8 #i20 #32 #s5 #5810 #u4 #u5 #u8 #u10 @dir8 @dir9 @dir10 label9 label12 label20 label32 @Ri @Rj @(R138, Rij) @(R14, disp10) : @(R14, disp9) @(R14, disp8) @(R15, udisp6) : @Ri+ @R13+ @SP+ @-SP (reglist) : Register direct : Register direct : Register direct : Register direct : Register direct : Register direct : Register direct (CRO to CR15) : Unsigned 8-bit immediate (128 to 255) RO to R15, AC, FP, SP) RO to R15, AC, FP, SP) R13, AC) Program status register) TBR, RP, SSP, USP, MDH, MDL) CRO to CR15) ON NN NS Note: 128 to 1 are interpreted as 128 to 255 : Unsigned 20-bit immediate (-OX80000 to OXFFFFF) Note: -OX7FFFF to 1 are interpreted as OX7FFFF to OXFFFFF : Unsigned 32-bit immediate (-OX80000000 to OXFFFFFFFF) Note: -OX80000000 to 1 are interpreted as OX80000000 to OXFFFFFFFF : Signed 5-bit immediate (16 to 15) : Signed 10-bit immediate (512 to 508, multiple of 4 only) : Unsigned 4-bit immediate (0 to 15) : Unsigned 5-bit immediate (0 to 31) : Unsigned 8-bit immediate (0 to 255) : Unsigned 10-bit immediate (0 to 1020, multiple of 4 only) : Unsigned 8-bit direct address (0 to OXFF) : Unsigned 9-bit direct address (0 to OX1FE, multiple of 2 only) : Unsigned 10-bit direct address (0 to OX3FC, multiple of 4 only) : Signed 9-bit branch address (-OX100 to OXFC, multiple of 2 only) : Signed 12-bit branch address (-OX800 to OX7FC, multiple of 2 only) : Signed 20-bit branch address (-OX80000 to OX7FFFF) : Signed 32-bit branch address (-OX80000000 to OX7FFFFFFF) : Register indirect (RO to R15, AC, FP, SP) : Register indirect (RO to R15, AC, FP, SP) : Register relative indirect (Rj: RO to R15, AC, FP, SP) Register relative indirect (disp10: -OX200 to OX1FC, multiple of 4 only) ( : Register relative indirect (disp9: -OX100 to OXFE, multiple of 2 only) : Register relative indirect (disp8: -OX80 to OX7F) Register relative (udisp6: 0 to 60, multiple of 4 only) : Register indirect with post-increment (RO to R15, AC, FP, SP) : Register indirect with post-increment (R13, AC) : Stack pop : Stack push : Register list 99MB91106 Series 3. Instruction Types Type A Type B Type C Type *C Type D Type E Type F 100 MSB ; LSB 1 6 bits OP Rj Ri 8 4 4 OP i8/08 Ri 4 8 4 OP u4/m4 Ri 8 4 4 ADD, ADDN, CMP, LSL, LSR and ASR instructions only OP s5/u5 Ri 7 5 4 OP u8/rel8/dir/reglist 8 8 OP SUB-OP Ri 8 4 4 OP rel11 144. Detailed Description of Instructions - Add/subtract operation instructions (10 instructions) MB91106 Series Mnemonic Type} OP |Cycle;NZVC Operation Remarks ADD Rj, Ri A A6 1 CCCCYIRI+ Rj > Ri * ADD #s5, Ri C A4 1 CCCCI|Ri+s5- Ri MSB is interpreted as a sign in assembly language ADD #i4, Ri Cc A4 1 CCCC)Ri + extu (i4) > Ri Zero-extension ADD2 #i4, Ri Cc A5 1 CCCC)Ri + extu (i4) > Ri Sign-extension ADDC Rj, Ri A A7 1 CCCCI/RI+ Aj +c Ri Add operation with sign ADDN Rj, Ri A A2 1 --|Ri+Rj-> Ri *ADDN #85, Ri C AO 1 ---|Ri+s5- Ri MSB is interpreted as a sign in assembly language ADDN #i4, Ri Cc AO 1 -|Ri + extu (i4) > Ri Zero-extension ADDN2 _ #4, Ri Cc Al 1 -|Ri + extu (i4) > Ri Sign-extension SUB Rj, Ri A AC 1 CCCC|RI-Rj > Ri SUBC Rj, Ri A AD 1 CCCC)RI-Rj-c->Ri Subtract operation with carry SUBN Rj, Ri A AE 1 --|Ri-Rj- Ri - Compare operation instructions (3 instructions) Mnemonic Type} OP |Cycle;NZVC Operation Remarks CMP Rj, Ri A AA 1 CCCCyRI-Aj * CMP #s5, Ri C A& 1 CCCCIRi-s5 MSB is interpreted as a sign in assembly language CMP #i4, Ri Cc A8 1 CCCC)Ri + extu (i4) Zero-extension CMP2 #i4, Ri Cc Ag 1 CCCC)Ri + extu (i4) Sign-extension + Logical operation instructions (12 instructions) Mnemonic Type} OP |Cycle;NZVC Operation Remarks AND Rj, Ri A 82 1 CC--jRi &=Rj Word AND Rj, @Ri A 84 |1+2a)/CC--|(RI)&=Rj Word ANDH Rj, @Ri A 85 |1+2a)/CC--|(RI)&=Rj Half word ANDB Rj, @Ri A 86 |1+2a)/CC-- (RI) &=Rj Byte OR Rj, Ri A 92 1 CC--yjRi | =Rj Word OR Rj, @Ri A 94 /1+2a|CC--|(Ri) | =Rj Word ORH Rj, @Ri A 95 |/1+2a|CC-|(Ri) | =Rj Half word ORB Rj, @Ri A 96 /1+2a|CC-|(Ri) | =Rj Byte EOR Rj, Ri A 9A 1 CC--yJRi * =Rj Word EOR Rj, @Ri A 9C |1+2a|CC--|(Ri)* =Rj Word EORH Rj, @Ri A 9D |/1+2a|CC--|(Ri)* =Rj Half word EORB Rj, @Ri A 9E |1+2a) CC |(Ri)* =Rj Byte 101MB91106 Series - Bit manipulation arithmetic instructions (8 instructions) Mnemonic Type} OP |Cycle;NZVC Operation Remarks BANDL #u4, @Ri(u4: Oto OFu)| C | 80 |1+42a) |(Ri) & = (FO + u4) Manipulate lower 4 bits BANDH #u4, @Ri(u4: 0 to OFH}| C | 81 |1+2a] |(Ri) & = ((u4<<4) + OFH) | Manipulate upper 4 *BAND #u8, @Ri - |----|(Ri) & =u8s bits BORL #u4, @Ri(u4: Oto OFH)} C | 90 |1+2a] ---- (Ri) | =u4 Manipulate lower 4 bits BORH #u4, @Ri(u4: Oto OFH)} C | 91 |1+2a) - |(Ri) | = (u4<<4) Manipulate upper 4 * BOR #u8, @Ri *e - |---|(Ri) | =u8 bits BEORL #u4, @Ri(u4: 0 to OFH)| C | 98 |1+4+2a} --|(Ri)* =u4 Manipulate lower 4 bits BEORH #u4, @Ri(u4: 0 to OFH}| C | 99 |1+2a] |(Ri)* = (u4<<4) Manipulate upper 4 *BEOR- #u8, @Ri *8 - |----|(Ri)* =u8 bits BISTL #u4, @Ri(u4:O0toOFH)} C | 88 | 24+a/]/0C--|(Ri) &u4 Test lower 4 bits BISTH #u4, @Ri(u4: Oto OFH}| C | 89 | 2+a|CC |(Ri) & (U4<<4) Test upper 4 bits 1: Assembler generates BANDL if result of logical operation u8&0x0F leaves an active (set) bit and generates BANDH if u8&0xF0 leaves an active bit. Depending on the value in the u8 format, both BANDL and BANDH may be generated. 2: Assembler generates BORL if result of logical operation u8&0x0F leaves an active (set) bit and generates BORH if u8&0xF0 leaves an active bit. *3: Assembler generates BEORL if result of logical operation u8&0x0F leaves an active (set) bit and generates BEORH if u8&0xFO0 leaves an active bit. - Add/subtract operation instructions (10 instructions) Mnemonic Type} OP |Cycle;NZVC Operation Remarks MUL Rj, Ri A AF 5 CCC |RjxRi-MDH,MDL |32-bit x 32-bit = 64-bit MULU Rj, Ri A AB 5 CCC |Rj x Ri > MDH, MDL Unsigned MULH Rj, Ri A BF 3 CC )|Rj x Ria MDL 16-bit x 16-bit = 32-bit MULUH_ Rj, Ri A BB 3 CC |/Rj x Ri > MDL Unsigned DIVOS Ri E |97-4| 1 ---- Step calculation DIVOU Ri E |97-5] 1 --- 32-bit/32-bit = 32-bit DIV1 Ri E |97-6/] d -C-C DIV2 Ri E |97-7| 14 -C-C DIV3 E |9F-6| 14 ---- DIV4S E |9F-7| 14 ---- *DIV Ri mt - |-C@-Cy|MDL/Ri- MDL, MDL%Ri MDH *DIVU Ri *2 - |C-C{|MDL/Ri- MDL, Unsigned MDL%Ri MDH 4: DIVOS, DIV1 x 32, DIV2, DIV3 and DIV4S are generated. A total instruction code length of 72 bytes. 2: DIVOU and DIV1 x 32 are generated. A total instruction code length of 66 bytes. 102MB91106 Series * Shift arithmetic instructions (9 instructions) Mnemonic Type} OP |Cycle;NZVC Operation Remarks LSL Rj, Ri A B6 1 CC -C)Ri<<Rj > Ri Logical shift *LSL #u5, Ri C B4 1 CC -C|Ri<<u5 > Ri LSL #u4, Ri Cc B4 1 CC -C)Ri<<u4 > Ri LSL2 #u4, Ri Cc B5 1 CC -C)Ri<<(u4 + 16) > Ri LSR Rj, Ri A B2 1 CC C)Ri>>Rj > Ri Logical shift *LSR #u5, Ri C Bo 1 CC -C|Ri>>u5 > Ri LSR #u4, Ri Cc Bo 1 CC -C)Ri>>u4 > Ri LSR2 #u4, Ri Cc Bi 1 CC -C)Ri>>(u4 + 16) > Ri ASR Rj, Ri A BA 1 CC C)Ri>>Rj > Ri Logical shift * ASR #u5, Ri C B8 1 CC -C|Ri>>u5 > Ri ASR #u4, Ri Cc B8 1 CC -C)Ri>>u4 > Ri ASR2 #u4, Ri Cc Bg 1 CC -C)Ri>>(u4 + 16) > Ri - Immediate value data transfer instruction (immediate value set/16-bit/32-bit immediate value transfer instruction) (3 instructions) Mnemonic Type} OP |Cycle;NZVC Operation Remarks LDI:32 = #i32, Ri E |9F-8/ 83 --|i32 > Ri LDI:20 = #i20, Ri Cc 9B 2 --|i20 > Ri Upper 12 bits are zero- extended LDI: 8 #i8, Ri B Co 1 ---|i8> Ri Upper 24 bits are zero- *LDI # {18 | 120 | i32}, Ri - |{i8 | i20 | i832} > Ri extended *4 1: If an immediate value is given in absolute, assembler automatically makes i8, i20 or i32 selection. If an immediate value contains relative value or external reference, assembler selects i32. - Memory load instructions (13 instructions) Mnemonic Type} OP |Cycle;NZVC Operation Remarks LD @Ri, Ri A 04 b ---|(Rj) > Ri LD @(R13, Rij), Ri A 00 b --|(R13 + Rj) > Ri LD @(R14, disp10), Ri} B 20 b --|(R14 + disp10) > Ri LD @(R15, udisp6), Ri} C 03 b --|(R15 + udisp6) > Ri LD @R15 +, Ri E |07-O0/} b --|(R15) > Ri, R15+=4 LD @R15 +, Rs E |07-8/] b --|(R15) > Rs, R15+=4 |Rs: Special-purpose register LD @R15+4+, PS E |079/1+a+b] COC C)(R15) > PS, R15+=4 LDUH @Rj, Ri A 05 b ---|(Rj) > Ri Zero-extension LDUH @(R13, Rij), Ri A 01 b --|(R13 + Rj) > Ri Zero-extension LDUH @(R14, disp9), Ri B 40 b --|(R14 + disp9) > Ri Zero-extension LDUB @Rj, Ri A 06 b ---|(Rj) > Ri Zero-extension LDUB @(R18, Rij), Ri A 02 b --|(R13 + Rj) > Ri Zero-extension LDUB @(R14, disp8), Ri B 60 b -|(R14 + disp8) > Ri Zero-extension Note: The relations between 08 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler description from disp8 to disp10 are as follows: disp8 > 08 = disp8 disp9 08 = disp9>>1 Each disp is a code extension. disp 10 > 08 = disp10>>2 udisp6 > u4 = udisp6>>2 udisp4 is a 0 extension. 103104 MB91106 Series * Memory store instructions (13 instructions) Mnemonic Type} OP |Cycle;NZVC Operation Remarks ST Ri, @Rj A 14 a --J|Ri- (Rj) Word ST Ri, @(R13, Rj) A 10 a --|Ri (R13 + Rj) Word ST Ri, @(R14, disp10)| B 30 a --|Ri (R14 +4 disp10) Word ST Ri, @(R15, udisp6)| C 13 a -|Ri (R15 + usidp6) ST Ri, @-R15 E |17-0 a --|R15-= 4, Ri > (R15) ST Rs, @-R15 E |}17-8|] a --|R15-=4, Rs > (R15) | Rs: Special-purpose register ST PS, @-R15 E |17-9 a --|R15-=4, PS > (R15) STH Ri, @Rj A 15 a --J|Ri- (Rj) Half word STH Ri, @(R13, Rj) A 11 a --|Ri (R13 + Rj) Half word STH Ri, @(R14, disp9) B 50 a --|Ri- (R14 + disp9) Half word STB Ri, @Rj A 16 a --J|Ri- (Rj) Byte STB Ri, @(R13, Rj) A 12 a --|Ri (R13 + Rj) Byte STB Ri, @(R14, disp8) B 70 a --|Ri (R14 + disp8) Byte Note: The relations between 08 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler description from disp8 to disp10 are as follows: disp8 > 08 = disp8 disp9 08 = disp9>>1 Each disp is a code extension. disp 10 > 08 = disp10>>2 udisp6 u4 = udisp6>>2 udisp4 is a 0 extension. - Transfer instructions between registers/special-purpose registers transfer instructions (5 instructions) Mnemonic Type} OP |Cycle;NZVC Operation Remarks MOV Rj, Ri A 8B 1 ----|Rj->Ri Transfer between general-purpose registers MOV Rs, Ri A B7 1 ---|Rs>Ri Rs: Special-purpose register MOV Ri, Rs A B3 1 ---|Ri-Rs Rs: Special-purpose register MOV PS, Ri E |17-1 1 --|PS- Ri MOV Ri, PS E |07-1 Cc CCCC|RI-PSMB91106 Series - Non-delay normal branch instructions (23 instructions) Mnemonic Type} OP |Cycle;NZVC Operation Remarks JMP @Ri E |97-0O} 2 ---|RI-PC CALL label12 F DO 2 --|PC+2RP, PC +2+4+rel11x2>PC CALL @Ri E |97-1 2 ---|PC+24RP Ri-PC RET E |97-2 2 ---|RP>PC Return INT #u8 D 1F | 34+8a | ----|SSP-=4, PS > (SSP), SSP -=4, PC +2 (SSP), 0 > | flag, 0 S flag, (TBR + 3FC u8 x 4) > PC INTE E |9F 3/34 3a] ----|SSP-=4, PS > (SSP),| For emulator SSP -=4, PC +2 (SSP), 0 S flag, (TBR + 3D8 u8 x 4) > PC RETI E |97-3/24+2a| CCC C|(R15) > PC, R15-=4, (R15) > PS, R15-=4 BNO label9 D E1 1 |Non-branch BRA label9 D EO 2 |PC+2+4rel8x27 PC BEQ label9 D E2 2/1 |----|PCifZ==1 BNE label9 D E3 2/1 |----|/PCifZ==0 BC label9 D E4 2/1 |----|PCifC==1 BNC label9 D E5 2/1 |----|PCifC ==0 BN label9 D E6 2/1 |----|PCifN==1 BP label9 D E7 2/1 |---|PCifN==0 BV label9 D E8 2/1 |-----|PCifV==1 BNV label9 D EQ 2/1 |----|PCifV==0 BLT label9 D EA 2/1 | ---|PCif VxorN == 1 BGE label9 D EB 2/1 | ---|PCif VxorN==0 BLE label9 D EC 2/1 | |PCif (V xor N) orZ == 1 BGT label9 D ED 2/1 | - |PCif (V xor N) or Z==0 BLS label9 D EE 2/1 |----|PCifC orZ==1 BHI label9 D EF 2/1 |-----|PCifCorZ==0 Notes: * 2/1 in cycle sections indicates that 2 cycles are needed for branch and 1 cycle needed for non-branch. * The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and assembler discription label9 and label12 are as follows. label9 rel8 = (label9 PC 2)/2 label12 rel11 = (label12 PC -2)/2 * RET! must be operated while S flag = 0. 105MB91106 Series - Branch instructions with delays (20 instructions) Mnemonic Type} OP |Cycle;NZVC Operation Remarks JMP:D @Ri E |9F-0O 1 ---J|RiI-PC CALL:D labeli2 F D8 1 -|PC+4RP, PC +24 rel11x2>PC CALL:D @Ri E |9F-14 1 --|PC +4 RP Ri > PC RET:D E |9F-2 1 ---|RP>PC Return BNO:D label9 D F1 1 |Non-branch BRA:D label9 D FO 1 ---|PC+2+4rel8x2PC BEQ:D label9 D F2 1 ---|PCifZ== BNE:D label9 D F3 1 --|PCifZ==0 BC:D label9 D F4 1 --|PCifC ==1 BNC:D label9 D F5 1 --|PCifC ==0 BN:D label9 D F6 1 --|PCifN==1 BP:D label9 D F7 1 --|PCifN==0 BV:D label9 D F8 1 --|PCifV==1 BNV:D label9 D FQ 1 --|PCifV==0 BLT:D label9 D FA 1 -|PCif V xorN ==1 BGE:D label9 D FB 1 -|PCif V xorN ==0 BLE:D label9 D FC 1 -|PCif (V xor N) or Z == BGT:D label9 D FD 1 -|PCif (V xor N) or Z == BLS:D label9 D FE 1 --|PCif C orZ == BHI:D label9 D FF 1 --|PCif C orZ == Notes: + The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and assembler discription label9 and label12 are as follows. label9 rel8 = (label9 PC 2)/2 label12 > rel11 = (label12 PC 2)/2 * Delayed branch operation always executes next instruction (delay slot) before making a branch. * Instructions allowed to be stored in the delay slot must meet one of the following conditions. If the other instruction is stored, this device may operate other operation than defined. The instruction described 1 in the other cycle column than branch instruction. The instruction described a, b, c or d in the cycle column. 106- Direct addressing instructions MB91106 Series Mnemonic Type} OP |Cycle;NZVC Operation Remarks DMOV- @dir10, R13 D 08 b ---|(dir10) > R13 Word DMOV R13, @dir10 D 18 a ---|R13 > (dir10) Word DMOV_ @dir10, @R13+ D 0c 2a | -|(dir10) > (R13), R13 + =4]Word DMOV @RI13+, @dir10 D 1c 2a_ | - |(R13) > (dir10), R13 +=4)| Word DMOV @dir10, @-R15 D 0B 2a | |R15=4, (dirl0) > (R15)| Word DMOV @R15+, @diri0 | D | 1B | 2a | ](R15) > (dirt0), R1S5=4| Word DMOVH @dir9, R13 D 09 b ---|(dir9) > R13 Half word DMOVH_ R13, @dir9 D 19 a --|R13 > (dir9) Half word DMOVH @dir9, @R13+ D OD 2a | - |(dir9) > (R13), R13 + = 2 | Half word DMOVH @R13+, @dir9 D 1D 2a | J|(R18) > (dir9), R13 + = 2 | Half word DMOVB @dir8, R13 D OA b ---|(dir8) > R13 Byte DMOVB_ R13, @dir8 D 1A a --|R13 > (dir8) Byte DMOVB @dir8, @R13+ D OE 2a | ---|(dir8) > (R13), R13 +4 | Byte DMOVB @RI13+, @dir8 D 1E 2a | --|(R13) > (dir8), R13 +4 | Byte Note: The relations between the dir field of TYPE-D in the instruction format and the assembler description from disp8 to disp10 are as follows: disp8 dir + disp8 disp9 dir = disp9>>1 disep10 > dir = disp10>>2 Each disp is a code extension - Resource instructions (2 instructions) Mnemonic Type} OP |Cycle;NZVC Operation Remarks LDRES @Ri+, #u4 Cc BC a --|(Ri) > u4 resource u4: Channel number Ri+=4 STRES = #u4, @Ri+ Cc BD a |u4 resource (Ri) u4: Channel number Ri+=4 * Co-processor instructions (4 instructions) Mnemonic Type} OP |Cycle;NZVC Operation Remarks COPOP #u4, #CC, CR), CRI} E |9F-C/} 2+a | - )Calculation COPLD #u4,#CC,Rj, CRI} E |9F-D/1+2a) ----]|Rj > CRi COPST #u4, #CC, CR, Ri E |9F-E/1+2a) ----J|CRj > Ri COPSV #u4, #CC, CRij, Ri E |9F-F/1 42a} ----|CRj > Ri No error traps 107MB91106 Series * Other instructions (16 instructions) Mnemonic Type} OP |Cycle;NZVC Operation Remarks NOP E |9F-A| 1 --|No changes ANDCCR #u8 D 83 Cc CCCC|CCR and u8 > CCR ORCCR #u8 D 93 Cc CCC C|CCR or u8 > CCR STILM #u8 D 87 1 ----|i8 > ILM Set ILM immediate value ADDSP_ #s10 1! D A3 1 ---]|R15+=s810 ADD SP instruction EXTSB- Ri E |97-8 1 |Sign extension 8 > 32 bits EXTUB) Ri E |97-9 1 |Zero extension 8 > 32 bits EXTSH Ri E |97-Al 1 |Sign extension 16 32 bits EXTUH Ri E |97-B { _ _ _ _ |Zero extension 16 > 32 bits LDMO (reglist) D 8C *4 --|(R15) - reglist, Load-multi RO to R7 R15 increment LDM1 (reglist) D 8D *4 --|(R15) - reglist, Load-multi R8 to R15 R15 increment *LDM (reglist) *8 --|(R15 ++) - reglist, Load-multi RO to R15 STMO (reglist) D 8E *6 -]|R15 decrement, Store-multi RO to R7 reglist > (R15) STM1 (reglist) D 8F *6 -]|R15 decrement, Store-multi R8 to R15 reglist > (R15) *STM2 (reglist) *5 -- |reglist > (R15 + +) Store-multi RO to R15 ENTER #u10 "2; D OF i+a | ---]|R14> (R15-4), Entrance processing R15-4Ril4, of function R15u1l0 > R15 LEAVE E |9F-9] b ---|R14+4>R15, Exit processing of (R15 4) > R14 function XCHB @Rj, Ri A 8A 2a |---]|Ri- TEMP For SEMAFO (Rj) > Ri, management TEMP -> (Rj) Byte data 1: Inthe ADDSP instruction, the reference between u8 of TYPE-D in the instruction format and assembler description s10 is as follows. s10 > s8=s10>>2 *2. Inthe ENTER instruction, the reference between i8 of TYPE-C in the instruction format and assembler description u10 is as follows. u10 > u8 = ul0>>2 *3: If either of RO to R7 is specified in reglist, assembler generates LDMO. If either of R8 to R15 is specified, assembler generates LDM1. Both LDMO and LDM1 may be generated. 4: The number of cycles needed for execution of LDMO (reglist) and LDM1 (reglist) is given by the following calculation; a x (n 1) + b + 1 when n is number of registers specified. 5: If either of RO to R7 is specified in reglist, assembler generates STMO. If either of R8 to R15 is specified, assembler generates STM1. Both STMO and STM1 may be generated. 6: The number of cycles needed for execution of STMO (reglist) and STM1 (reglist) is given by the following calculation; a x n+ 1 when n is number of registers specified. 108MB91106 Series 20-bit normal branch macro instructions Mnemonic Operation Remarks *CALL20 label20, Ri Next instruction address RP, label20 > PC Ri: Temporary register *1 * BRA20 label20, Ri label20 > PC Ri: Temporary register *? *BEQ20 _ label20, Ri if (Z = = 1) then label20 PC Ri: Temporary register * * BNE20 label20, Ri ifs/Z = = Ri: Temporary register ** *BC20 label20, Ri ifs/C == Ri: Temporary register ** *BNC20 _ label20, Ri ifs/C ==0 Ri: Temporary register 8 * BN20 label20, Ri ifs/N = = 1 Ri: Temporary register 8 * BP20 label20, Ri ifs/N = =0 Ri: Temporary register 8 * BV20 label20, Ri ifs/V = = 1 Ri: Temporary register ** * BNV20 label20, Ri ifs/V = =0 Ri: Temporary register ** * BLT20 label20, Ri ifs/V xor N == Ri: Temporary register 8 *BGE20 _ label20, Ri ifs/V xor N == Ri: Temporary register 8 * BLE2O label20, Ri ifs/(V xor N) or Z == 1 Ri: Temporary register ** * BGT20 label20, Ri ifs/(V xor N) or Z==0 Ri: Temporary register ** * BLS20 label20, Ri ifs/C or Z == Ri: Temporary register 8 * BHI20 label20, Ri ifs/C or Z == Ri: Temporary register 8 1: CALL20 (1) If label20 PC 2 is between 0x800 and +0x7fe, instruction is generated as follows; CALL labeli2 (2) If label20 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:20 = #label20, Ri CALL @Ri *2: BRA20 (1) If label20 PC 2 is between 0x100 and +0xfe, instruction is generated as follows; BRA label9 (2) If label20 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:20 = #label20, Ri JMP @Ri *3: Bec20 (BEQ@20 to BHI20) (1) If label20 PC 2 is between 0x100 and +0xfe, instruction is generated as follows; Bec label9 (2) If label20 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; Bxcc false xcc is a revolt condition of cc LDI:20 =6#label20, Ri JMP @Ri false: 109MB91106 Series * 20-bit delayed branch macro instructions Mnemonic Operation Remarks * CALL20:D label20, Ri Next instruction address + 2 > RP, label20 > PC | Ri: Temporary register ~*' *BRA20:D_label20, Ri label20 > PC Ri: Temporary register *? *BEQ20:D_ label20, Ri if (Z = = 1) then label20 PC Ri: Temporary register * * BNE20:D_ label20, Ri ifs/Z = = Ri: Temporary register ** *BC20:D _ label20, Ri ifs/C == Ri: Temporary register ** *BNC20:D_ label20, Ri ifs/C ==0 Ri: Temporary register 8 *BN20:D _ label20, Ri ifs/N = = 1 Ri: Temporary register 8 *BP20:D _ label20, Ri ifs/N = =0 Ri: Temporary register 8 *BV20:D _ label20, Ri ifs/V = = 1 Ri: Temporary register ** *BNV20:D_ label20, Ri ifs/V = =0 Ri: Temporary register ** *BLT20:D label20, Ri ifs/V xor N == Ri: Temporary register 8 *BGE20:D_ label20, Ri ifs/V xor N == Ri: Temporary register 8 *BLE20:D label20, Ri ifs/(V xor N) or Z == 1 Ri: Temporary register ** *BGT20:D_ label20, Ri ifs/(V xor N) or Z==0 Ri: Temporary register ** *BLS20:D_ label20, Ri ifs/C or Z == Ri: Temporary register 8 *BHI20:D label20, Ri ifs/C or Z == Ri: Temporary register 8 1: CALL20:D (1) If label20 PC 2 is between 0x800 and +0x7fe, instruction is generated as follows; CALL:D label12 (2) If label20 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:20 = #label20, Ri CALL:D @Ri *2: BRA20:D (1) If label20 PC 2 is between 0x100 and +0xfe, instruction is generated as follows; BRA:D _ label9 (2) If label20 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:20 = #label20, Ri JMP:D @Ri *3: Bec20:D (BEQ20:D to BHI20:D) (1) If label20 PC 2 is between 0x100 and +0xfe, instruction is generated as follows; Bee:D _label9 (2) If label20 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; Bxcc false xcc is a revolt condition of cc LDI:20 =6#label20, Ri JMP:D @Ri false: 110MB91106 Series 32-bit normal macro branch instructions Mnemonic Operation Remarks *CALL382 label82, Ri Next instruction address RP, label82 PC Ri: Temporary register *1 * BRA32 label32, Ri label32 > PC Ri: Temporary register *? *BEQ32 _label82, Ri if (Z = = 1) then label32 PC Ri: Temporary register * * BNE32 label32, Ri ifs/Z = = Ri: Temporary register ** * BC32 label32, Ri ifs/C == Ri: Temporary register ** *BNC32 _ label32, Ri ifs/C == Ri: Temporary register 8 * BN32 label32, Ri ifs/N = = 1 Ri: Temporary register 8 * BP32 label32, Ri ifs/N = = Ri: Temporary register 8 * BV32 label32, Ri ifs/V = = Ri: Temporary register ** * BNV32 label32, Ri ifs/V = = Ri: Temporary register ** * BLT32 label32, Ri ifs/V xorN == 1 Ri: Temporary register 8 *BGE32 __ label32, Ri ifs/V xor N == Ri: Temporary register 8 * BLE32 label32, Ri ifs/(V xor N) or Z== Ri: Temporary register ** * BGT32 label32, Ri ifs/(V xor N) or Z== Ri: Temporary register ** * BLS32 label32, Ri ifs/C or Z== 1 Ri: Temporary register 8 * BHI32 label32, Ri ifs/C or Z == Ri: Temporary register 8 1: CALL32 (1) If label82 PC 2 is between 0x800 and +0x7fe, instruction is generated as follows; CALL labeli2 (2) If label82 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:32 = #label32, Ri CALL @Ri *2: BRA32 (1) If label82 PC 2 is between 0x100 and +0xfe, instruction is generated as follows; BRA label9 (2) If label82 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:32 = #label32, Ri JMP @Ri *3: Bec32 (BEQ32 to BHI32) (1) If label82 PC 2 is between 0x100 and +0xfe, instruction is generated as follows; Bec label9 (2) If label82 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; Bxcc false xcc is a revolt condition of cc LDI:32 #label32, Ri JMP @Ri false: 111MB91106 Series * 32-bit delayed macro branch instructions Mnemonic Operation Remarks * CALL82:D label82, Ri Next instruction address + 2 > RP, label82 > PC | Ri: Temporary register ~*' * BRA382:D_ label32, Ri label32 > PC Ri: Temporary register *? * BEQ32:D_ label82, Ri if (Z = = 1) then label32 PC Ri: Temporary register * * BNE82:D _ label32, Ri ifs/Z = = Ri: Temporary register ** *BC32:D label32, Ri ifs/C == Ri: Temporary register ** * BNC32:D_ label32, Ri ifs/C == Ri: Temporary register 8 *BN32:D _ label32, Ri ifs/N = = 1 Ri: Temporary register 8 *BP32:D _ label32, Ri ifs/N = = Ri: Temporary register 8 *BV32:D _ label32, Ri ifs/V = = Ri: Temporary register ** * BNV32:D_ label32, Ri ifs/V = = Ri: Temporary register ** * BLT32:D label32, Ri ifs/V xorN == 1 Ri: Temporary register 8 * BGE32:D_ label32, Ri ifs/V xor N == Ri: Temporary register 8 * BLE82:D label32, Ri ifs/(V xor N) or Z== Ri: Temporary register ** *BGT32:D_ label32, Ri ifs/(V xor N) or Z== Ri: Temporary register ** * BLS32:D label32, Ri ifs/C or Z== 1 Ri: Temporary register 8 * BHI32:D label32, Ri ifs/C or Z == Ri: Temporary register 8 1: CALL32:D (1) If label82 PC 2 is between 0x800 and +0x7fe, instruction is generated as follows; CALL:D label12 (2) If label82 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:32 = #label32, Ri CALL:D @Ri 2: BRA32:D (1) If label82 PC 2 is between 0x100 and +0xfe, instruction is generated as follows; BRA:D _ label9 (2) If label82 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:32 = #label32, Ri JMP:D @Ri *3: Bec32:D (BEQ32:D to BHI32:D) (1) If label382 PC 2 is between 0x100 and +0xfe, instruction is generated as follows; Bee:D _label9 (2) If label82 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; Bxcc false xcc is a revolt condition of cc LDI:32 #label32, Ri JMP:D @Ri false: 112MB91106 Series @ ORDERING INFORMATION Part number Package Remarks 100-pin Plastic LQFP (FPT-100P-M05) 100-pin Plastic QFP (FPT-100P-M06) MB91106PFV-XXX MB91106PF-XXX 113MB91106 Series m@ PACKAGE DIMENSIONS 100-pin Plastic LQFP (FPT-100P-MO5) 16,00+0.20(.630+.008)SQ . 1.50 *5%0 ' 4 coy (Mouting height) oe 14,00+0,10(.551+.004)SQ (.059 ece) WABARR AAR ABRABARBOBAAD RAE C) AL 12.00 15.00 (.472) (591) ro TTT | REF NOM Details of "A" part 0.1 INDEX POOH A OUE ROU O OHA OUTO Ona @) DUG UUUD ORO G OEE ETOH ae "B" Ve : AOL. Ke | +0.08 $008 eee ee ee ee ee 0.50(.0197)TYP 0.18 0.03 [0.08(.003) @ 0.127 0.08 Details of "B" part | +008 +002 | ts ! | 0.10+0.10 | |= (.004,004) (STAND OFF) | | = | | | Sf ral o z 9 (.007 0c; ) (.005 cor ) {(7]0.10(.004) 114MB91106 Series 100-pin Plastic QFP (FPT-100P-M06) 23.90+0.40(.941+.016) .. 3.35(.132)MAX (Mounting height) 20.00+0.20(.787+.008) 0.05(.002)MIN @L_ | | Ae) (STAND OFF) PHT RA RAA AARP AAAARAPRABAAA AE _@ = O OQ EE uss gese | Brae gees = INDEX == o ee = G0 | 4 | | 0.65(.0256)TYP 0.30+0.10 1 0.13(.005) 0.15+0.05(.006+.002) (.012+.004) I ro ! 0.25(.010) Be | Nop I T ly | | I t | | | | | LU 0.30(.012 o~t0 | 18.85(.742)REF | [|o.18.007)MaX. | 0.804020 | 22,30:0.40(,878+.016) 0.53(.021)MAX ! (031.008) | bee Joe ee ee 1994 FUJITSU LIMITED F100008-3C-2 Dimensions in mm (inches) Note: The design may be modified changed without notice, contact to Fujitsu sales division when using the device. 115MB91106 Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329 http-//www. fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7am -5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http//www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www. fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http//www.fmap.com.sg/ F9901 FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.