M366S1724CT0 PC100 Unbuffered DIMM
Rev. 0.0 April. 2000
The Samsung M366S1724CT0 is a 16M bit x 64 Synchronous
Dynamic RAM high density memory module. The Samsung
M366S1724CT0 consists of eight CMOS 8M x 16 bit with
4banks Synchronous DRAMs in TSOP-II 400mil package and a
2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy
substrate. Two 0.1uF decoupling capacitors are mounted on the
printed circuit board in parallel for each SDRAM.
The M366S1724CT0 is a Dual In-line Memory Module and is
intended for mounting into 168-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of
system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high bandwidth,
high performance memory system applications.
• Performance range
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ± 0.3V power supply
• MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB : Height (1,375mil), double sided component
Part No. Max Freq. (Speed)
M366S1724CT0-C1H 100MHz (10ns @ CL=2)
M366S1724CT0-C1L 100MHz (10ns @ CL=3)
FEATUREGENERAL DESCRIPTION
M366S1724CT0 SDRAM DIMM
16Mx64 SDRAM DIMM based on 8Mx16, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD
PIN NAMES
* These pins are not used in this module.
** These pins should be NC in the system
which does not support SPD.
Pin Name Function
A0 ~ A11 Address input (Multiplexed)
BA0 ~ BA1 Select bank
DQ0 ~ DQ63 Data input/output
CLK0 ~ CLK3 Clock input
CKE0 ~ CKE1 Clock enable input
CS0 ~ CS3 Chip select input
RAS Row address strobe
CAS Column address strobe
WE Write enable
DQM0 ~ 7 DQM
VDD Power supply (3.3V)
VSS Ground
*VREF Power supply for reference
SDA Serial data I/O
SCL Serial clock
SA0 ~ 2 Address in EEPROM
WP Write protection
DU Don′t use
NC No connection
PIN CONFIGURATIONS (Front side/back side)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Front
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
*CB0
*CB1
VSS
NC
NC
VDD
WE
DQM0
Pin
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Front
DQM1
CS0
DU
VSS
A0
A2
A4
A6
A8
A10/AP
BA1
VDD
VDD
CLK0
VSS
NC
CS2
DQM2
DQM3
NC
VDD
NC
NC
*CB2
*CB3
VSS
DQ16
DQ17
Pin
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Front
DQ18
DQ19
VDD
DQ20
NC
*VREF
CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
CLK2
NC
WP
**SDA
**SCL
VDD
Pin
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Back
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
*CB4
*CB5
VSS
NC
NC
VDD
CAS
DQM4
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
DQM5
CS1
RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VDD
CLK1
*A12
VSS
CKE0
CS3
DQM6
DQM7
*A13
VDD
NC
NC
*CB6
*CB7
VSS
DQ48
DQ49
Pin
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Back
DQ50
DQ51
VDD
DQ52
NC
*VREF
NC
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
CLK3
NC
**SA0
**SA1
**SA2
VDD
* SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
M366S1724CT0 PC100 Unbuffered DIMM
Rev. 0.0 April. 2000
PIN CONFIGURATION DESCRIPTION
Pin Name Input Function
CLK System clock Active on the positive going edge to sample all inputs.
CS Chip select Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tSS prior to valid command.
A0 ~ A11 Address Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA8
BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE Write enable Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0 ~ 7 Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins.
WP Write protection WP pin is connected to VSS through 47KΩ Resistor.
When WP is "high", EEPROM Programming will be inhibited and the entire memory will
be write-protected.
VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic.
M366S1724CT0 PC100 Unbuffered DIMM
Rev. 0.0 April. 2000
DQM4
FUNCTIONAL BLOCK DIAGRAM
CS0
DQM0
DQM1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQM CS
UDQM DQM5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U2
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
LDQM CS
UDQM
DQM6
CS2
DQM2
DQM3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U1
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
LDQM CS
UDQM DQM7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U3
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
LDQM CS
UDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U4
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQM CS
UDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U6
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQM CS
UDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U5
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQM CS
UDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQM CS
UDQM
CS1
CS3
A0 ~ An, BA0 & 1
CKE0
RAS
CAS
WE
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U3
10Ω
DQn Every DQpin of SDRAM
CKE1 SDRAM U4 ~ U7
10KΩ
VDD
VDD
Vss
Two 0.1uF Capacitors
per each SDRAM To all SDRAMs
•
••
•
•
•••
•
•
•
••
U0/U4/U2/U6
10Ω
CLK0/1/2/3 U1/U5/U3/U7
•
15pF •
Serial PD SDA
SCL A1 A2A0
SA1 SA2SA0
WP
47KΩ
•
M366S1724CT0 PC100 Unbuffered DIMM
Rev. 0.0 April. 2000
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Value Unit
Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD8W
Short circuit current IOS 50 mA
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
DC OPERATING CONDITIONS AND CHARACTERISTICS
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)
Pin Symbol Min Max Unit
Address (A0 ~ A11, BA0 ~ BA1)
RAS, CAS, WE
CKE (CKE0)
Clock (CLK0, CLK2)
CS (CS0, CS2)
DQM (DQM0 ~ DQM7)
DQ (DQ0 ~ DQ63)
CADD
CIN
CCKE
CCLK
CCS
CDQM
COUT
25
25
15
10
10
8
9
45
45
25
13
15
10
12
pF
pF
pF
pF
pF
pF
pF
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter Symbol Min Typ Max Unit Note
Supply voltage VDD, VDDQ 3.0 3.3 3.6 V
Input logic high voltage VIH 2.0 3.0 VDDQ+0.3 V1
Input logic low voltage VIL -0.3 00.8 V2
Output logic high voltage VOH 2.4 - - VIOH = -2mA
Output logic low voltage VOL - - 0.4 VIOL = 2mA
Input leakage current ILI -10 -10 uA 3
1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
Notes :
M366S1724CT0 PC100 Unbuffered DIMM
Rev. 0.0 April. 2000
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ)
Notes :
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter Symbol Test Condition Version Unit Note
-1H -1L
Operating current
(One bank active) ICC1 Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA 680 680 mA 1
Precharge standby current in
power-down mode ICC2PCKE ≤ VIL(max), tCC = 10ns 8mA
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞8
Precharge standby current in
non power-down mode
ICC2NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 160
mA
ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable 56
Active standby current in
power-down mode ICC3PCKE ≤ VIL(max), tCC = 10ns 40 mA
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞40
Active standby current in
non power-down mode
(One bank active)
ICC3NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 240 mA
ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable 160 mA
Operating current
(Burst mode) ICC4
IO = 0 mA
Page burst
4Banks activated
tCCD = 2CLKs
700 700 mA 1
Refresh current ICC5 tRC ≥ tRC(min) 960 960 mA 2
Self refresh current ICC6 CKE ≤ 0.2V 12 mA
M366S1724CT0 PC100 Unbuffered DIMM
Rev. 0.0 April. 2000
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter Value Unit
AC input levels (Vih/Vil) 2.4/0.4 V
Input timing measurement reference level 1.4 V
Input rise and fall time tr/tf = 1/1 ns
Output timing measurement reference level 1.4 V
Output load condition See Fig. 2
3.3V
1200Ω
870Ω
Output
50pF
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Vtt = 1.4V
50Ω
Output
50pF
Z0 = 50Ω
(Fig. 2) AC output load circuit (Fig. 1) DC output load circuit
•
•• •
Notes :
(AC operating conditions unless otherwise noted)
Parameter Symbol Version Unit Note
-1H -1L
Row active to row active delay tRRD(min) 20 20 ns 1
RAS to CAS delay tRCD(min) 20 20 ns 1
Row precharge time tRP(min) 20 20 ns 1
Row active time tRAS(min) 50 50 ns 1
tRAS(max) 100 us
Row cycle time tRC(min) 70 70 ns 1
Last data in to row precharge tRDL(min) 2CLK 2,5
Last data in to Active delay tDAL(min) 2 CLK + 20 ns -5
Last data in to new col. address delay tCDL(min) 1CLK 2
Last data in to burst stop tBDL(min) 1CLK 2
Col. address to col. address delay tCCD(min) 1CLK 3
Number of valid output data CAS latency=3 2ea 4
CAS latency=2 1
OPERATING AC PARAMETER
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. For -1H/1L, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + 20ns.
M366S1724CT0 PC100 Unbuffered DIMM
Rev. 0.0 April. 2000
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Notes :
REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
Parameter Symbol -1H -1L Unit Note
Min Max Min Max
CLK cycle time CAS latency=3 tCC 10 1000 10 1000 ns 1
CAS latency=2 10 12
CLK to valid
output delay CAS latency=3 tSAC 6 6 ns 1,2
CAS latency=2 6 7
Output data
hold time CAS latency=3 tOH 3 3 ns 2
CAS latency=2 3 3
CLK high pulse width tCH 3 3 ns 3
CLK low pulse width tCL 3 3 ns 3
Input setup time tSS 2 2 ns 3
Input hold time tSH 1 1 ns 3
CLK to output in Low-Z tSLZ 1 1 ns 2
CLK to output
in Hi-Z CAS latency=3 tSHZ 6 6 ns
CAS latency=2 6 7
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
M366S1724CT0 PC100 Unbuffered DIMM
Rev. 0.0 April. 2000
SIMPLIFIED TRUTH TABLE
(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
Command CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A11,
A9 ~ A0Note
Register Mode register set HXL L L L XOP code 1,2
Refresh
Auto refresh HHLL LHX X 3
Self
refresh
Entry L 3
Exit LHLH H H X X 3
HX X X 3
Bank active & row addr. HXL L H H XVRow address
Read &
column address Auto precharge disable HXLHLHXVLColumn
address
(A0 ~ A8)
4
Auto precharge enable H4,5
Write &
column address Auto precharge disable HXLHLLXVLColumn
address
(A0 ~ A8)
4
Auto precharge enable H4,5
Burst stop HXLH H LX X 6
Precharge Bank selection HXL L HLXVLX
All banks XH
Clock suspend or
active power down Entry HLHX X X XX
LV V V
Exit LHX X X X X
Precharge power down mode
Entry HLHX X X X
X
LH H H
Exit LHHX X X X
LV V V
DQM HVX7
No operation command HXHX X X X X
LH H H
1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Notes :
X
M366S1724CT0 PC100 Unbuffered DIMM
Rev. 0.0 April. 2000
PACKAGE DIMENSIONS
0.150 Max
0.050 ± 0.0039
(1.270 ± 0.10)
0.250
(6.350)
Detail A
0.123 ± 0.005
(3.125 ± 0.125)
0.250
(6.350)
Detail B
0.123 ± 0.005
(3.125 ± 0.125)
0.079 ± 0.004
(2.000 ± 0.100) 0.079 ± 0.004
(2.000 ± 0.100)
0.200 Min
(5.08 Min)
(3.81 Max)
Tolerances : ± .005(.13) unless otherwise specified
The used device is 8Mx16 SDRAM, TSOP
SDRAM Part No. : K4S281632C
5.250
5.014
Units : Inches (Millimeters)
R 0.079
(R 2.000)
0.250
(6.350)
1.450
(36.830) 2.150
(54.61)
0.118
(3.000)
0.350
0.100 Min
(2.540 Min)
0.700
(17.780)
.118DIA ± 0.004
(3.000DIA ± 0.100)
(8.890)
A B C
0.250
(6.350)
.450
(11.430) 4.550
(115.57)
0.157 ± 0.004
(4.000 ± 0.100)
0.089
(2.26)
(127.350)
(133.350)
1.375
(34.925)
0.118
(3.000)
0.125
(3.175)
0.375
(9.525)
0.096
(2.44)
R 0.050+0.04
(R 1.27+0.1)
0.050
0.039 ± 0.002
0.008 ±0.006
(0.200 ±0.150)
(1.000 ± 0.050)
(1.270)
0.100 Min
(2.540 Min)
Detail C
