10 GHz to 40 GHz, 1:4 Channel, 4x Frequency Multiplier/Filter ADAR2001 Data Sheet FEATURES GENERAL DESCRIPTION 4x input frequency multiplier with programmable harmonic filter Quad differential output PAs with independent enable control Input frequency range: 2.5 GHz to 10 GHz Output frequency range: 10 GHz to 40 GHz Input power: -20 dBm (50 ) Output power: 5 dBm differential (100 ) Harmonic rejection: -20 dBc to -40 dBc at all frequencies 3-wire or 4-wire SPI control of all functions On-chip programmable state machines for fast multiplier/filter and transmitter switching and control On-chip temperature sensor, output power detectors, and ADC DC power: 450 mW (2.5 V supply) 6 mm x 6 mm, 40-terminal LGA package The ADAR2001 is a transmitter IC optimized for millimeter wave body scanning applications. Accepting a single-ended continuous wave (CW) input signal between 2.5 GHz and 10 GHz, the ADAR2001 provides gain, 4x frequency multiplication, harmonic filtering, 1:4 signal splitting, and four independently controllable power amplifiers (PAs) with differential outputs designed to directly drive dipole antennas with differential inputs. All device functions and configuration options can be accessed by a 3-wire or 4-wire Analog Devices, Inc., serial peripheral interface (SPI). Two state machines are also integrated into the ADAR2001, which facilitate easy configuration, control, and fast switching of the frequency multiplier, filter, and transmitter sections. These sequencers are programmed through the SPI and are then operated by pulsed inputs (reset and advance). APPLICATIONS Millimeter wave imaging Security Medical Industrial Wideband local oscillator (LO) multiplier/distributor The output power and chip temperature can be monitored by four on-chip detectors and a temperature sensor whose outputs are multiplexed to an 8-bit ADC. The ADAR2001 requires only a single 2.5 V supply with power consumption of 450 mW with one channel turned on. The ADAR2001 is available in a compact, 40-terminal, 6 mm x 6 mm LGA package and is specified from -40C to +85C. FUNCTIONAL BLOCK DIAGRAM ADAR2001 MULTIPLIER/FILTER SEQUENCER TRANSMITTER SEQUENCER x4 RFIN BUFFER RFOUT1+ RFOUT1- PA RFOUT2+ RFOUT2- PA RFOUT3+ RFOUT3- PA RFOUT4+ RFOUT4- x4 x4 SPI CONTROL MULTIPLIER/FILTER STATE MACHINE (16 STATES) MRST MADV TRANSMITTER STATE MACHINE (70 STATES) TxRST ADC TxADV TEMP. SENSOR 20538-001 CS SDIO SCLK SDO PA Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADAR2001 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information ............................................................. 16 Applications ...................................................................................... 1 SPI Control.................................................................................. 16 General Description ......................................................................... 1 State Machine Modes vs. States................................................ 16 Functional Block Diagram .............................................................. 1 State Machine Setup .................................................................. 17 Revision History ............................................................................... 2 Multiplier/Filter State Machine................................................ 17 Specifications .................................................................................... 3 Transmitter State Machine ....................................................... 18 Timing Specifications .................................................................. 5 Single-Channel Frequency Sweep............................................ 18 Absolute Maximum Ratings ........................................................... 6 Single Frequency Channel Sweep ............................................ 19 Thermal Resistance ...................................................................... 6 Multichannel Frequency Sweep ............................................... 20 Electrostatic Discharge (ESD) Ratings ...................................... 6 Sequencer Sleep Control ........................................................... 20 ESD Caution.................................................................................. 6 Sequencer Sleep Hold ................................................................ 21 Pin Configuration and Function Descriptions ............................ 7 Sequencer Control Latch Bypass.............................................. 21 Typical Performance Characteristics ............................................. 9 Parallel Chip Control ................................................................. 21 Theory of Operation ...................................................................... 13 Multichip Frequency and Channel Sweep.............................. 22 Overview ...................................................................................... 13 Bias Points ....................................................................................... 25 Input Buffer, 4x Multiplier, and Band-Pass Filter................. 13 Register Summary .......................................................................... 26 Digital Step Attenuator.............................................................. 13 Outline Dimensions ....................................................................... 39 Low-Pass/Notch Filter ............................................................... 13 Ordering Guide .......................................................................... 39 1:4 Signal Splitter Network ....................................................... 14 Output Power Amplifiers .......................................................... 14 Power Detectors and Temperature Sensor ............................. 14 ADC Input Multiplexer ............................................................. 14 ADC and ADC Clock ................................................................ 15 REVISION HISTORY 8/2020--Revision 0: Initial Version Rev. 0 | Page 2 of 39 Data Sheet ADAR2001 SPECIFICATIONS VPOS1, VPOS3, VPOS4, VPOS5 = 2.5 V, VPOS2 = VREG, TA = -40C to +85C, unless otherwise noted. Table 1. Parameter RF INPUT Frequency Range Impedance Return Loss Power Range RF OUTPUT Frequency Range Output Power Channel Isolation Channel to Channel Switching Frequency Phase Noise 10 GHz Output Test Conditions/Comments Min Typ 2.5 -25 50 -15 -20 10 Max Unit 10 GHz dB dBm -10 40 GHz dBm dBm dBm dBc dBc MHz Input power (PIN) = -20 dBm Multiplier enabled, PA disabled Multiplier and PA disabled Disabled channel to active channel Ready channel to active channel Using ready mode 5 -30 -80 -50 -50 10 kHz offset 100 kHz offset 1 MHz offset 120 123 129 dBc/Hz dBc/Hz dBc/Hz 10 kHz offset 100 kHz offset 1 MHz offset 121 119 131 dBc/Hz dBc/Hz dBc/Hz 10 kHz offset 100 kHz offset 1 MHz offset 119 117 129 dBc/Hz dBc/Hz dBc/Hz 10 kHz offset 100 kHz offset 1 MHz offset 115 116 127 100 8 dBc/Hz dBc/Hz dBc/Hz dB -40 -40 dBc dBc -25 -20 dBc dBc 100 20 GHz Output 30 GHz Output 40 GHz Output Differential Impedance Differential Return Loss HARMONIC FILTERING Input Frequency Second Harmonic Rejection Third Harmonic Rejection Output Frequency Second Harmonic Rejection Third Harmonic Rejection STATE MACHINES AND TIMING Minimum Pulse Width MADV, MRST TxADV, TxRST Minimum Pulse Separation MADV, MRST TxADV, TxRST Switching Frequency 3 3 ns ns 10 10 ns ns MHz Pulse start to pulse start Using ready mode Rev. 0 | Page 3 of 39 100 ADAR2001 Parameter Switching Time Multiplier Band Sleep to Active Multiplier Band Switch PA Sleep to Active Channel to Channel Switch DIGITAL INPUT LOGIC LEVELS Logic Low Logic High DIGITAL OUTPUT LOGIC LEVELS Logic Low Logic High VREG OUTPUT POWER SUPPLY Analog Supply Voltage Range (VPOS1, VPOS3, VPOS4, VPOS5) Current Consumption Power Consumption Digital Supply Voltage Range (VPOS2) Current Consumption Power Consumption Data Sheet Test Conditions/Comments Min Using ready mode, first channel off to second channel on Unit ns ns ns ns 0 1.8 0.3 V V 0 1.8 1.8 0.4 V V V 2.25 2.5 180 10 450 25 2.75 V mA mA mW mW 1.6 1.8 25 45 2 V A W 1 1.4 One channel active Chip disabled One channel active Chip disabled Rev. 0 | Page 4 of 39 Max 50 10 50 2 Using ready mode Chip enabled Chip enabled Typ Data Sheet ADAR2001 TIMING SPECIFICATIONS VPOS1, VPOS3, VPOS4, VPOS5 = 2.5 V, VPOS2 = VREG, TA = -40C to +85C, unless otherwise noted. Table 2. SPI Timing Parameter fSCLK Description Maximum clock rate Test Conditions/Comments Write only Write and read tPWH tPWL tDS tDH tDV tDCS Minimum pulse width high Minimum pulse width low Setup time, SDIO to SCLK Hold time, SDIO to SCLK Data valid, SDO to SCLK Setup time, CS to SCLK tR tF SDIO, SDO rise time SDIO, SDO fall time Min Outputs loaded with 10 pF, 10% to 90% Outputs loaded with 10 pF, 10% to 90% Typ Max 40 15 10 10 5 5 5 10 Unit MHz MHz ns ns ns ns ns ns 40 40 ns ns Timing Diagrams INSTRUCTION CYCLE DATA TRANSFER CYCLE CS DON'T CARE SDIO DON'T CARE DON'T CARE A14 R/W A13 A2 A1 A0 D7 D6 D5 D2 D1 D0 DON'T CARE 20538-002 SCLK Figure 2. SPI Transaction Structure (MSB First) CS tPWH tDCS DON'T CARE DON'T CARE tDS tPWL SDIO DON'T CARE WRITE A14 A13 A2 tDH A1 A0 D7 D6 D5 D2 D1 D0 DON'T CARE 20538-003 SCLK Figure 3. SPI Write Timing Diagram CS SCLK DON'T CARE SDIO DON'T CARE DON'T CARE READ A14 A13 A2 A1 A0 DON'T CARE DON'T CARE DON'T CARE DON'T CARE DON'T CARE D6 D5 D1 D0 DON'T CARE SDO D7 tR 20538-004 tDV tF Figure 4. SPI 4-Wire Read Timing Diagram SPI Block Write Mode Data can be written to the SPI registers using the block write mode where the register address automatically increments and data for consecutive registers can be written without sending new address bits. Data writing can be continued indefinitely until CS is raised, ending the transaction. See Figure 5. CS SCLK DON'T CARE WRITE A14 A13 A1 A0 FIRST REGISTER ADDRESS D7 D6 D1 FIRST REGISTER DATA Figure 5. SPI Block Write Rev. 0 | Page 5 of 39 D0 D7 D6 D1 D0 (n + FIRST REGISTER) DATA DON'T CARE 20538-005 SDIO DON'T CARE DON'T CARE ADAR2001 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter VPOS1, VPOS3, VPOS4, VPOS5 to GND1 VPOS2 to GND1 Digital Input to GND1 RFIN to GND1 RFIN Power Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Reflow Soldering Peak Temperature 1 Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Rating +3 V, -0.3 V +2.1 V, -0.3 V +2.1 V, -0.3 V 0.3 V -5 dBm -40C to +85C -65C to +150C 135C JA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. JC is the junction to case thermal resistance. Table 4. Thermal Resistance Package Type CC-40-71 260C 1 GND is the common ground to which all GNDx pins are connected. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. JA 33.8 JC 12.2 Unit C/W Pad soldered. ELECTROSTATIC DISCHARGE (ESD) RATINGS The following ESD information is provided for handling of ESD sensitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Charged device model (CDM) per ANSI/ESDA/JEDEC JS-002. ESD Ratings for ADAR2001 Table 5. ADAR2001, 40-Terminal LGA ESD Model HBM CDM ESD CAUTION Rev. 0 | Page 6 of 39 Withstand Threshold (V) 1000 to 2000 500 to 750 Class 1C C2A Data Sheet ADAR2001 GND15 GND14 GND13 RFOUT1+ RFOUT1- GND12 VPOS4 40 39 38 37 36 35 34 33 32 31 GND1 2 30 GND 11 GND2 3 29 RFOUT2+ RFIN 4 28 RFOUT2- GND3 5 27 GND10 26 GND9 25 GND8 VREG ADAR2001 6 TOP VIEW (Not to Scale) 22 GND7 MRST 11 12 13 14 15 16 17 18 19 20 GND6 10 RFOUT4- MADV RFOUT4+ RFOUT3+ GND5 RFOUT3- 23 GND4 24 9 CS 8 TxRST SDO TxADV SDIO 7 SCLK VPOS2 21 VPOS3 NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO A GROUND PLANE WITH LOW THERMAL AND ELECTRICAL IMPEDANCE. 20538-006 GND16 1 VPOS5 V POS1 GND17 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 6. Pin Configuration (Top View, Not to Scale) Table 6. Pin Function Descriptions Pin No. 1, 21, 31, 40 Mnemonic VPOS1, VPOS3, VPOS4, VPOS5 2, 3, 5, 16, 17, 20, 22, 25 to 27, 30, 32, 35 to 39 4 GND1 to GND17 RFIN 6 7 VREG VPOS2 8 TxADV 9 TxRST 10 MADV 11 MRST 12 13 SCLK SDIO Description 2.5 V Power Supply for the Analog Section. Connect decoupling capacitors (one 10 nF and one 100 pF on each pin, and a 1 F for the rail) to the ground plane as close as possible to these pins. Ground. Connect all ground pins to a ground plane with low thermal and electrical impedance. RF Input. RFIN is a single-ended, 50 input operating from 2.5 GHz to 10 GHz, ac-coupled internally. The nominal input power level is -20 dBm. 1.8 V Low Dropout (LDO) Regulator Output. Directly connect VREG to Pin 7 (VPOS2). 1.8 V Power Supply for the Digital Section. Directly connect this supply to Pin 6 (VREG). Place a 1 F capacitor to ground as close as possible to VPOS2. Transmitter State Machine Advance. If the state machine is enabled, pulsing TxADV advances the transmitter state machine to the next state in its cycle. If currently at the end of the cycle, pulsing TxADV returns the pointer to the mode defined in TX_STATE_1 (Register 0x019, Bits[7:4]). Transmitter State Machine Reset. If the state machine is enabled, TxRST immediately sets the transmit control state machine back to the configuration in the TX_EN1_MODE_0 and TX_EN2_MODE_0 registers (Register 0x050 and Register 0x051). Multiplier/Filter State Machine Advance. If the state machine is enabled, pulsing MADV advances the multiplier/filter state machine to the next state in its cycle. If currently at the end of the cycle, pulsing MADV returns the pointer to the mode defined in MULT_STATE_1 (Register 0x03C, Bits[7:4]). Multiplier/Filter State Machine Reset. If the state machine is enabled, MRST immediately sets the multiplier/filter state machine back to the configuration defined in the MULT_EN_MODE_0 and MULT_PASS_MODE_0 registers (Register 0x070 and Register 0x071). Serial Clock. The SCLK pin is used to clock data into and out of the SPI interface. Serial Data Input/Output. The SDIO pin is a high impedance data input for clocking in information. SDIO can also be used to read out data if Register 0x000, Bits[4:3] are set low (default). Rev. 0 | Page 7 of 39 ADAR2001 Data Sheet Pin No. 14 Mnemonic CS 15 SDO 18, 19, 23, 24, 28, 29, 33, 34 RFOUT4+, RFOUT4-, RFOUT3+, RFOUT3-, RFOUT2-, RFOUT2+, RFOUT1-, RFOUT1+ EPAD Description Chip Select Bar. CS is used to activate the SPI port on the ADAR2001 and is active low. When CS goes high, the data previously clocked into the shift registers is latched to the chip. Connect a 200 k pull-up resistor to 1.8 V from CS to ensure that the SPI interface is deactivated when not in use. Serial Data Output. Register states can be read back on the SDO line if Register 0x000, Bits[4:3] are set high. Differential RF Outputs. RFOUTx are 100 differential pairs, ac-coupled internally. RFOUTx operate from 10 GHz to 40 GHz. All eight lines must have equal electrical and mechanical lengths. Exposed Pad. The exposed pad must be connected to a ground plane with low thermal and electrical impedance. Rev. 0 | Page 8 of 39 Data Sheet ADAR2001 TYPICAL PERFORMANCE CHARACTERISTICS 300 200 +85C +25C -40C 250 195 190 185 180 ICC (mA) ICC (mA) 200 150 175 170 165 100 160 155 +85C +25C -40C 150 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 RF OUTPUT FREQUENCY (GHz) 145 2.25 20538-007 0 Figure 7. Supply Current (ICC) vs. RF Output Frequency and Temperature, Supply Voltage = 2.5 V 550 DC POWER CONSUMPTION (mW) +85C +25C -40C 600 500 400 300 200 500 450 400 350 100 RF OUTPUT FREQUENCY (GHz) 300 2.25 20538-008 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 2.50 Figure 8. Power Consumption vs. RF Output Frequency and Temperature, Supply Voltage = 2.5 V Figure 11. DC Power Consumption vs. Supply Voltage and Temperature 30 20 -10dBm -15dBm -20dBm -25dBm +85C +25C -40C 15 2.75 SUPPLY VOLTAGE (V dc) RF OUTPUT POWER (dBm) 15 10 5 0 20538-011 +85C +25C -40C 0 10 5 0 -5 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 RF OUTPUT FREQUENCY (GHz) -5 20538-009 -15 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 RF OUTPUT FREQUENCY (GHz) Figure 9. RF Output Power vs. RF Output Frequency and Temperature, RF Input Power = -20 dBm, Supply Voltage = 2.5 V 20538-012 RF OUTPUT POWER (dBm) 2.75 Figure 10. ICC vs. Supply Voltage and Temperature 700 POWER CONSUMPTION (mW) 2.50 SUPPLY VOLTAGE (V dc) 20538-010 50 Figure 12. RF Output Power vs. RF Output Frequency and RF Input Power Rev. 0 | Page 9 of 39 Data Sheet 20 2.75V 2.50V 2.25V 10 5 RF OUTPUT FREQUENCY (GHz) THIRD RF OUTPUT HARMONIC REJECTION (dBc) +85C +25C -40C -20 -30 -40 -50 -60 -70 -80 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 RF INPUT FREQUENCY (GHz) Figure 14. Second RF Input Harmonic Rejection vs. RF Input Frequency and Temperature -30 -35 -40 -45 10 11 12 13 14 15 16 17 18 19 0 +85C +25C -40C -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 2.0 0.10 CHANNEL 1 MADV 0.08 CHANNEL VOLTAGE (V) -20 -30 -40 -50 -60 14.0 Figure 17. Third RF Output Harmonic Rejection vs. RF Output Frequency and Temperature +85C +25C -40C -10 20 RF OUTPUT FREQUENCY (GHz) 0 1.8 0.06 1.6 0.04 1.4 0.02 1.2 0 1.0 -0.02 0.8 -0.04 0.6 -0.06 0.4 -0.08 0.2 -0.10 0 -70 -80 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 RF INPUT FREQUENCY (GHz) 20538-018 THIRD RF INPUT HARMONIC REJECTION (dBc) -25 Figure 16. Second RF Output Harmonic Rejection vs. RF Output Frequency and Temperature 0 -10 -20 RF OUTPUT FREQUENCY (GHz) 20538-017 SECOND RF INPUT HARMONIC REJECTION (dBc) Figure 13. RF Output Power vs. RF Output Frequency and Supply Voltage, RF Input Power = -20 dBm -15 20538-014 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 -10 MADV VOLTAGE (V) -5 20538-013 0 +85C +25C -40C -5 -0.12 -2 Figure 15. Third RF Input Harmonic Rejection vs. RF Input Frequency and Temperature Rev. 0 | Page 10 of 39 0 2 4 6 8 10 -0.2 12 TIME (ns) Figure 18. 25 GHz RF Frequency Band Switching with MADV 20538-020 RF OUTPUT POWER (dBm) 15 0 20538-016 SECOND RF OUTPUT HARMONIC REJECTION (dBc) ADAR2001 Data Sheet ADAR2001 CHANNEL 1 TxADV 2.0 -5 1.8 0.2 1.6 1.2 0 1.0 0.8 0.6 -0.1 -10 RETURN LOSS (dB) 1.4 0.1 TxADV VOLTAGE (V) CHANNEL VOLTAGE (V) 0 2.2 0.3 0.4 -15 -20 -25 HIGH BAND MID BAND LOW BAND DISABLED -30 0.2 -0.2 -35 CHANNEL 1 CHANNEL 2 TxADV 2.0 10.5 20538-023 9.0 NOTCH FILTER ON NOTCH FILTER OFF DISABLED 5 1.0 0 0.8 -0.1 0.6 RETURN LOSS (dB) 1.2 0 TxADV VOLTAGE (V) 1.4 0.4 -5 -10 -15 -20 0.2 0 2 4 6 8 -0.2 10 -30 20538-022 -0.5 -2 TIME (ns) 5 -5 -10 -30 -35 1 ACTIVE (REFERENCE) 2 READY 3 READY 4 READY 2 DISABLED 3 DISABLED 4 DISABLED ADC CODE (DEC) -25 CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL -40 -45 -50 -55 -60 -65 -70 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 RF OUTPUT FREQUENCY (GHz) 20 25 30 35 40 45 Figure 23. RF Output Return Loss 5 0 -20 15 RF OUTPUT FREQUENCY (GHz) Figure 20. Channel to Channel Switching Time -15 10 20538-024 -25 0 Figure 21. Channel to Channel Isolation vs. RF Output Frequency, RF Input = -20 dBm 170 160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 -40 25 TEMPERATURE (C) Figure 24. ADC Code vs. Temperature Rev. 0 | Page 11 of 39 85 20538-025 -0.3 20538-021 CHANNEL VOLTAGE (V) 9.5 10 1.8 0.1 CHANNEL TO CHANNEL ISOLATION (dBc) 8.5 Figure 22. RF Input Return Loss 1.6 0.3 8.0 RF INPUT FREQUENCY (GHz) Figure 19. RF Output Sleep to Active Switching Time 0.5 10.0 TIME (ns) 7.0 -40 7.5 80 6.5 70 5.5 60 6.0 50 4.5 40 5.0 30 4.0 20 3.0 10 3.5 0 2.5 -0.2 -10 20538-019 -0.3 -20 2.0 0 ADAR2001 Data Sheet 25 20 3 15 2 1 0 -1 -2 -3 CHANNEL CHANNEL CHANNEL CHANNEL -4 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 RF OUTPUT FREQUENCY (GHz) 5 0 -5 -10 -15 1 2 3 4 -5 10 CHANNEL CHANNEL CHANNEL CHANNEL -20 Figure 25. Amplitude Imbalance vs. RF Output Frequency -25 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 RF OUTPUT FREQUENCY (GHz) Figure 26. Phase Imbalance vs. RF Output Frequency Rev. 0 | Page 12 of 39 1 2 3 4 20538-027 PHASE IMBALANCE () 4 20538-026 AMPLITUDE IMBALANCE (dB) 5 Data Sheet ADAR2001 THEORY OF OPERATION OVERVIEW The main elements of the ADAR2001 are an RF input buffer, a 4x frequency multiplier with integrated switchable harmonic filter, a 1:4 signal splitter, and four differential output PAs that can drive dipole or similar antennas with differential inputs. Apply a CW RF input signal between 2.5 GHz and 10 GHz with a power level of approximately -20 dBm to the RFIN port (Pin 4), which results in a nominal PA output power of 5 dBm on each of the differential PA outputs, RFOUTx (Pin 18, Pin 19, Pin 23, Pin 24, Pin 28, Pin 29, Pin 33, and Pin 34). The operation of these subcircuits can be controlled from the SPI port as well as two programmable state machines, one focused on multiplier/filter control and the other focused on transmit control. RF output power on each channel can be monitored using individual, on-chip RF detectors. Temperature can also be observed with a temperature diode. These sensors feed into a 5:1 multiplexer that passes the desired signal to an on-chip, 8-bit ADC. The ADAR2001 also includes an Analog Devices SPI port that is used for device configuration and readback. Although the state machines provide the fastest switching between states, all functions can also be controlled directly through the SPI port. INPUT BUFFER, 4x MULTIPLIER, AND BAND-PASS FILTER The RF input buffer provides approximately 17 dB of gain and provides an optimal driver for the 4x multiplier bands. The bias levels of the input and output stages of the buffer are independently adjustable through the SPI via Register 0x013. See the Bias Points section for more information. The broadband frequency multiplier consists of three parallel subcircuits. Each subcircuit (low band, mid band, high band) is optimized to multiply and filter a segment of the total frequency range (2.5 GHz to 10 GHz input, 10 GHz to 40 GHz output). Recommended ranges and register settings for each band are shown in Table 7. Switches at the input and output of the multiplier block are used to select the subcircuit for the desired frequency of operation. Each subcircuit consists of a 4x multiplier and a band-pass filter (BPF) with an adjustable corner frequency. The bias levels of the 4x multipliers are adjustable through the SPI using Register 0x011 and Register 0x012. See the Bias Points section for more information. When the input frequency is in the low end of the band of the subcircuit, the BPF corner frequency must be set to its low state. Set the associated bit high to set the BPF corner frequency to its low state. See Table 7. To complete a full 10 GHz to 40 GHz frequency sweep, the multiplier/filter block settings must be adjusted seven times to ensure optimum harmonic rejection and output power. These seven settings are shown in Table 7. By using the appropriate subcircuit and filter settings, harmonic distortion across the 10 GHz to 40 GHz range can be kept below -25 dBc. Within the 20 GHz to 40 GHz range, -30 dBc of harmonic rejection can be achieved. In addition to having sleep and active modes, the 4x multipliers can be set to ready mode. Ready mode is a hybrid state between sleep and active mode, which does not pass a signal, but allows fast turn on. Current consumption in ready mode is higher than sleep mode but lower than in active mode. The switching time between ready mode and active mode is significantly faster than from sleep mode to active mode. DIGITAL STEP ATTENUATOR Although there is a digital step attenuator inside the multiplier/ filter block of the ADAR2001, it is not intended to be used as a level control for the output power of the ADAR2001. This attenuator is meant for reducing the level of harmonic content coming out of the multipliers before entering the splitter network. Suggested values for the digital step attenuator vs. RF frequency are shown in Table 7 and represent a balance between harmonic performance and output power level. Therefore, altering these values is not recommended. Note that a value of 0x00 for ATTN_x (which refers to the ATTN_MDx and ATTN_SPI bits) corresponds to maximum attenuation. LOW-PASS/NOTCH FILTER A low-pass/notch filter is included after the PA outputs to help reduce any undesired harmonic content before transmission of the desired signal. RF output frequencies less than 16 GHz benefit from having this filter enabled. RF output frequencies more than 16 GHz must have this filter switched out to reduce any insertion loss due to the filter. Set the associated bit high to enable the filter. See Table 7. Rev. 0 | Page 13 of 39 ADAR2001 Data Sheet Table 7. Multiplier/Filter Settings for Optimal Harmonic Rejection Input Frequency (GHz) 2.50 to 3.00 Output Frequency (GHz) 10 to 12 3.00 to 3.50 12 to 14 3.50 to 4.00 14 to 16 4.00 to 5.00 16 to 20 5.00 to 6.25 20 to 25 6.25 to 8.00 25 to 32 8.00 to 10.00 32 to 40 Multiplier Band Low band active (mid and high bands ready) Low band active (mid and high bands ready) Low band active (mid and high bands ready) Mid band active (low and high bands ready) Mid band active (low and high bands ready) High band active (low and mid bands ready) High band active (low and mid bands ready) BPF Low ATTN_x1 0x13 Low-Pass/ Notch Filter On MULT_EN_x Register Value2 0x7A MULT_PASS_x Register Value3 0xD3 High 0x07 On 0x7A 0x47 High 0x13 On 0x7A 0x53 Low 0x1F Off 0x6E 0x9F High 0x1F Off 0x6E 0x1F Low 0x1F Off 0x6B 0x9F High 0x1F Off 0x6B 0x1F 1 ATTN_x refers to the ATTN_MDx and ATTN_SPI bit fields. MULT_EN_x refers to the MULT_EN_MODE_x and MULT_EN_SPI registers. 3 MULT_PASS_x refers to the MULT_PASS_MODE_x and MULT_PASS_SPI registers. 2 ready mode and active mode is significantly faster than from sleep mode to active mode. The output of the multiplier/filter block is then applied to a 1:4 active power splitting network that is composed of two stages. The first stage is a 1:2 active splitter, which then feeds the second stage, two 1:2 active splitters. Each output path from the second stage drives a single PA, which results in a single input signal being split into four independently controlled output channels. The bias levels of each splitter stage are adjustable through the SPI via Register 0x014. See the Bias Points section for more information. OUTPUT POWER AMPLIFIERS There are four PAs, each with an ac-coupled, differential output operating from 10 GHz to 40 GHz. The differential output is intended to facilitate direct connection to an antenna with differential inputs. In applications where a single-ended output is required, the unused output can be terminated to ground using a 50 resistor. Terminating the unused output results in 3 dB lower output power (that is, a single-ended output power of 2 dBm, nominal) along with some degradation in harmonic rejection. The bias level of the PAs is adjustable through the SPI. One setting, PA_BIAS in Register 0x015, controls all four PA bias points. See the Bias Points section for more information. In normal operation, only one of the four PAs is active at a time, but the programmability allows all four (or any combination thereof) to be turned on simultaneously. For the fastest switching times, use of the ready mode is critical. For example, while Power Amplifier 1 (PA1) is transmitting, Power Amplifier 2 (PA2) can be set to ready mode. The transmitter state machine can then be used to put PA1 to sleep and switch PA2 from ready to active. POWER DETECTORS AND TEMPERATURE SENSOR Each transmit channel on the ADAR2001 has a dedicated power detector with an enable bit in Register 0x049. All the detectors feed into a 5:1 multiplexer along with the local temperature sensor. This multiplexer allows the 8-bit on-chip ADC the flexibility to measure the current output power level of any channel, or the temperature of the chip itself. To calculate the approximate temperature in Celsius from the ADC output code, use the following equation: TA = (1.31 x ADC_OUTPUT) - 118 where ADC_OUTPUT is the ADC output word in Register 0x04B. ADC INPUT MULTIPLEXER The multiplexer position can be programmed using the MUX_SEL bits (Register 0x04A, Bits[3:1]). The multiplexer has five valid states, from 0 to 4. Figure 27 shows the multiplexer mapping. Like the 4x multipliers, each PA has three modes of operation: sleep, ready, and active. Ready mode is a hybrid state between sleep and active, which does not pass a signal, but allows fast turn on. Current consumption in ready mode is higher than sleep mode but lower than active mode. The switching time between Rev. 0 | Page 14 of 39 TO ADC 0 1 OUT 2 3 4 TEMPERATURE SENSOR CHANNEL 1 DETECTOR CHANNEL 2 DETECTOR CHANNEL 3 DETECTOR CHANNEL 4 DETECTOR Figure 27. ADC Input Multiplexer Mapping 20538-032 1:4 SIGNAL SPLITTER NETWORK Data Sheet ADAR2001 ADC AND ADC CLOCK The ADAR2001 has an on-chip, 8-bit ADC and a variable clock input, each with their own enable control bits. To take a measurement from the ADC, the user must first write to the ADC_CTRL register, Register 0x04A. This register contains the following bits: * * * * * * Bit 0: ADC_EOC (read only). This bit is a flag for when the ADC conversion is done. Bit 1 to Bit 3: MUX_SEL (read/write). These bits are used to select the ADC input, according to Figure 27. Bit 4: ST_CONV (read/write). This bit is set to start an ADC conversion cycle. Bit 5: CLK_EN (read/write). This bit enables the ADC clock. Bit 6: ADC_EN (read/write). This bit enables the ADC. Bit 7: ADC_CLKFREQ_SEL (read/write). This bit sets the clock frequency. A low sets the clock to 2 MHz, whereas a high sets the clock to 250 kHz. After the ADC_CTRL register is written, it must be polled to wait for the ADC_EOC bit to go high. When this happens, the measured value can be read out from the ADC_OUTPUT register, Register 0x04B. Rev. 0 | Page 15 of 39 ADAR2001 Data Sheet APPLICATIONS INFORMATION The ADAR2001 is designed to operate as part of a larger array. The built in state machines help to ease the control of multiple chips in parallel and to ensure that the fastest switching speeds are achieved. However, it is possible to operate every aspect of the ADAR2001 using the SPI port alone. When the state machines are disabled by setting MULT_SEQ_EN (Register 0x018, Bit 7) and TX_SEQ_EN (Register 0x016, Bit 7) low, the multiplier/filter and transmitter blocks respond to the SPI controlled registers (Register 0x045 to Register 0x048), rather than stepping through the programmed states. Register 0x047 and Register 0x048 set up the multiplier/filter block when controlling the block with the SPI and have all the same controls as a typical multiplier/filter mode when controlling the block with the multiplier/filter sequencer. Register 0x045 and Register 0x046 set up the transmitter block when controlling the block with the SPI and have all the same controls as a typical transmitter mode when controlling the block with the transmitter sequencer. Operating the ADAR2001 in this manner can be thought of as a manual, rather than an automatic, approach. With the sequencers disabled, any changes to the configuration of the chip must occur through a SPI write. STATE MACHINE MODES vs. STATES Both the multiplier/filter state machine and the transmitter state machine have 16 modes available to set the configuration of their respective subcircuitry. The multiplier/filter state machine has 16 states available to cycle through, whereas the transmitter state machine has 70 available states. Within each mode of the multiplier/filter state machine, the user can define the following: * * * * * The enabled status of the RF input buffer (on or off, one bit) Sleep, ready, or active state of each 4x multiplier band (two bits for each band, six bits in total). The two bits control the ready and active status, and if neither is high, the multiplier band is set to sleep. Both bits must be high to be fully active. Digital step attenuator value (five bits) BPF corner frequency (low or high, one bit controls the filters in all bands) Low-pass/notch filter status (on or off, one bit controls all low-pass/notch filters) Within each mode of the transmitter state machine, the user can define the following: * * * * Sleep, ready, or active state of each PA (two bits for each band, eight bits in total). The two bits control the ready and active status, and if neither is high, the PA is set to sleep. Both bits must be high to be fully active. The enabled status of the first 1:2 signal splitter feeding the second stage of splitters (on or off, one bit) The enabled status of the 1:2 signal splitter feeding PA Channel 1 and Channel 2 (on or off, one bit) The enabled status of the 1:2 signal splitter feeding PA Channel 3 and Channel 4 (on or off, one bit) Each multiplier/filter state is used to select a previously configured operating mode. Each state bit field contains four bits, allowing selection of any mode between 0 and 15 (Register 0x070 to Register 0x08F). There are 16 multiplier/filter states available (Register 0x03C to Register 0x043). When the multiplier/filter state machine is enabled and the sequencer depth set in Register 0x018, Bits[3:0], the state machine cycles through the states in order, up to the defined state machine depth. Similarly, each transmitter state is used to select a previously configured operating mode. Each state bit field has four bits, allowing selection of any mode between 0 and 15 (Register 0x050 to Register 0x06F). There are 70 transmit control states available (Register 0x019 to Register 0x03B). When the transmitter state machine is enabled, and the sequencer depth set in Register 0x017, the state machine cycles through the states in order, up to the defined state machine depth. Figure 28 shows how the state machine pointer moves through a loop. In this diagram, n is the total number of states inside the loop. Because the sequencer depth bit field is 0 indexed, n is equal to one more than the value of the bits in the sequencer depth. n = MULT_STATES + 1 where: n = 1 to 16. MULT_STATES is the multiplier sequencer depth. n = TX_STATES + 1 where: n = 1 to 16. TX_STATES is the transmitter sequence depth. RESET 0 ADVANCE ADVANCE 1 2 ADVANCE ADVANCE n 3 ADVANCE Figure 28. State Machine Position Loop Rev. 0 | Page 16 of 39 20538-033 SPI CONTROL Data Sheet ADAR2001 STATE MACHINE SETUP MULTIPLIER/FILTER STATE MACHINE Both state machines in the ADAR2001 have configuration registers that control various aspects of the state machine. A programmable state machine provides a convenient and fast control mechanism for the multiplier/filter block and avoids the need for SPI writes each time the block must be reconfigured. For the multiplier/filter sequencer, this register is Register 0x018, and contains the following bits: * * * * * Bit 0 to Bit 3: MULT_STATES. Sets the number of states in the loop (see Figure 28). Bit 4: MULT_CTL_LATCH_BYP. Bypasses the latch on the MADV and MRST pins. Setting this bit high bypasses the latch. Regardless of the value of this bit, the new state is preloaded on the rising edge of a MRST or MADV pulse. If the latch is enabled, the new settings are all latched to the appropriate section at the same time on the falling edge of the same pulse. If the latch is bypassed, the new settings are applied as soon as possible after the rising edge of the pulse, with no latching and no guaranteed order. Bit 5: MULT_SLP_HOLD. Prevents the multiplier/filter block from advancing when forced into a sleep state by the transmitter block. Used in conjunction with MULT_SLP_CTRL. See the Sequencer Sleep Control section for more information. Bit 6: MULT_SLP_CTRL. Forces the multiplier/filter block to sleep whenever the transmitter block is sleeping. Bit 7: MULT_SEQ_EN. Enables the multiplier/filter block. MULT_SEQ_EN must be set high for the block to operate with the external pins. For the transmitter sequencer, the two control registers are Register 0x016 and Register 0x017. Register 0x016 contains the following bits: * * * * Bit 4: TX_CTL_LATCH_BYP. Bypasses the latch on the TxADV and TxRST pins. Setting this bit high bypasses the latch. Regardless of the value of this bit, the new state is preloaded on the rising edge of a TxRST or TxADV pulse. If the latch is enabled, the new settings are all latched to the appropriate section at the same time on the falling edge of the same pulse. If the latch is bypassed, the new settings are applied as soon as possible after the rising edge of the pulse, with no latching and no guaranteed order. Bit 5: TX_SLP_HOLD. Prevents the transmitter block from advancing when forced into a sleep state by the multiplier/filter block. Used in conjunction with MULT_SLP_CTRL. See the Sequencer Sleep Control section for more information. Bit 6: TX_SLP_CTRL. Forces the transmitter block to sleep whenever the multiplier/filter block is sleeping. Bit 7: TX_SEQ_EN. Enables the transmitter block. Must be set high for the block to operate with the external pins. Register 0x017 contains Bit 0 to Bit 6, TX_STATES, which sets the number of states in the loop (see Figure 28). To enable the state machine, set the MULT_SEQ_EN bit (Register 0x018, Bit 7) high. Although only seven multiplier/filter modes are required for a complete 10 GHz to 40 GHz sweep as described in Table 7, a maximum state machine depth of 16 is provided for optimum flexibility. Nine preloaded modes can be assigned to any of the 16 states. These nine modes consist of a sleep mode, a ready mode, and the seven modes required to perform a 10 GHz to 40GHz sweep, as shown in Table 7. It is possible to overwrite any of the multiplier/filter modes with a custom set of operating conditions by changing the bits in Register 0x070 to Register 0x08F. After the modes are defined, the order in which the sequencer moves through the desired modes must be set by filling the state bits in Register 0x03C to Register 0x043 in order, with the modes of interest. Any state can point to any mode, except State 0, which always points to Mode 0. Note that the sequencer moves through the states in order, up to the state machine depth. Finally, the user must define how many states are used by setting the state machine depth (MULT_STATES, Register 0x018, Bits[3:0]). MULT_STATES is 0 indexed. Therefore, setting the depth to 0 leaves MULT_STATE_1 (Register 0x03C, Bits[7:4]) as the only state in the loop. After the multiplier/filter state machine is programmed and enabled, operation is controlled by the MRST (multiplier reset, Pin 11) and MADV (multiplier advance, Pin 10) pins. Alternatively, operation can be controlled through the SPI using the MULT_RST_SPI and MULT_ADV_SPI bits (Register 0x044, Bit 3 and Bit 2, respectively). Note that using the SPI is slower than pulsing the sequencer pins directly. MRST moves the pointer on the multiplier/filter state machine to State 0 regardless of the current position of the pointer and can be asserted at any time. State 0 always refers to Mode 0 and cannot be set to another mode. However, Mode 0 can be overwritten with any multiplier/filter configuration. Mode 0 is defined in Register 0x070 and Register 0x071. MADV pulses advance the multiplier/filter state machine pointer one state at a time until the defined sequencer depth is cycled through. At that point, an additional MADV pulse moves the pointer back to State 1, which is normally set to a ready mode (however, State 1 can be set to any mode). State 1 applies the mode defined in the MULT_STATE_1 bits (Register 0x03C, Bits[7:4]). Rev. 0 | Page 17 of 39 ADAR2001 Data Sheet Like the multiplier/filter state machine, the transmitter state machine can be used to quickly cycle through transmit states without using the comparatively slower SPI interface. To enable the state machine, set the TX_SEQ_EN bit (Register 0x016, Bit 7) high. The transmitter state machine controls the status of the four PAs (sleep, ready, or active) and the status of the 1:4 splitter network by defining the desired modes of operation in Register 0x050 to Register 0x06F. The PAs are in sleep mode when the ready and active bits are not enabled. Each mode outlines a custom set of operating conditions. Although only four states are required to cycle through a transmit cycle by each of the PAs, a state machine depth of 70 is provided for optimum flexibility and to lower the total number of control lines required to operate multiple ADAR2001 chips in parallel. It is possible to control up to 16 ADAR2001 ICs using the same four sequencer lines (MADV, MRST, TxADV, TxRST). See the Sequencer Control Latch Bypass section for more information. Following the mode definitions, the user must fill the state bits in Register 0x019 to Register 0x03B with the modes of interest. Any state can point to any mode, except State 0 which always points to Mode 0. Note that the sequencer moves through the states in order, up to the state machine depth. After the states are defined, the user must set the number of states to be used by the sequencer by changing the TX_STATES bits (Register 0x017, Bits[6:0]). TX_STATES is 0 indexed. Therefore, setting the depth to 0 leaves TX_STATE_1 (Register 0x019, Bits[7:4]) as the only state in the loop. After the transmit state machine is programmed, operation is controlled by the TxRST (transmit reset, Pin 9) and TxADV (transmit advance, Pin 8) pins. Alternatively, operation can be controlled through the SPI using the TX_RST_SPI and TX_ADV_SPI bits (Register 0x044, Bit 1 and Bit 0, respectively). TxRST moves the pointer on the transmit state machine to State 0 regardless of the current position of the pointer and can TxADV pulses advance the transmitter state machine pointer one state at a time until the defined sequencer depth is cycled through. At that point, an additional TxADV pulse moves the pointer back to State 1. State 1 applies the mode defined in the TX_STATE_1 bits (Register 0x019, Bits[7:4]). SINGLE-CHANNEL FREQUENCY SWEEP Figure 29 shows a method of operation that can be used during a 20 GHz to 40 GHz frequency sweep of Channel 1. Based on Table 7, three multiplier/filter states are required during a 20 GHz to 40 GHz sweep. In this example, the defined state machine depth, MULT_STATES (Register 0x018, Bits[3:0]), is 3 because there are four states inside the loop, and MULT_STATES is 0 indexed. As shown in Figure 29, * * * * * Multiplier/Filter State 0 = sleep (outside the loop) Multiplier/Filter State 1 = mid band multiplier ready Multiplier/Filter State 2 = output 20 GHz to 25 GHz to PAs Multiplier/Filter State 3 = output 25 GHz to 30 GHz to PAs Multiplier/Filter State 4 = output 30 GHz to 40 GHz to PAs The initial state is the sleep state where power consumption is at a minimum. This state is reached by pulsing the MRST pin. A pulse on MADV then advances the state machine to the first state inside the loop, which is defined as a ready state, where the mid band multiplier is partially powered but not active, and the BPF is disabled to pass the higher portion of the mid band. By using this ready state, an additional pulse on MADV makes this subcircuit path active in less than 10 ns. By making use of the ready mode for the upcoming state throughout the sweep, the multiplier/filter switching and settling time can be kept less than 10 ns between all states. After the appropriate number of pulses is applied to MADV (5, in this case), the state machine automatically returns to the first state in the loop (ready). CHANNEL 1 READY CHANNEL 1 20GHz TO 25GHz MULT_STATE_0 TX_STATE_0 MULT_STATE_1 TX_STATE_1 MULT_STATE_2 TX_STATE_2 MULT: ALL SLEEP BPF: N/A PA: ALL SLEEP MULT: MID RDY BPF: N/A PA: CH. 1 RDY MULT: MID ACT BPF: HIGH PA: CH. 1 ACT SLEEP MULTIPLIER TRANSMITTER RESET RESET be asserted at any time. State 0 always refers to Mode 0 and cannot be set to another mode. However, Mode 0 can be overwritten with any transmitter configuration. Mode 0 is defined in Register 0x050 and Register 0x051. MULTIPLIER TRANSMITTER ADVANCE ADVANCE MULTIPLIER TRANSMITTER ADVANCE ADVANCE MULTIPLIER ADVANCE CHANNEL 1 25GHz TO 30GHz CHANNEL 1 30GHz TO 40GHz MULT_STATE_3 TX_STATE_2 MULT: HIGH ACT BPF: LOW PA: CH. 1 ACT MULT_STATE_4 TX_STATE_2 MULT: HIGH ACT BPF: HIGH PA: CH. 1 ACT MULTIPLIER ADVANCE MULTIPLIER TRANSMITTER ADVANCE ADVANCE Figure 29. State Machine Loop Example for a Frequency Sweep from 20 GHz to 40 GHz on a Single Channel Rev. 0 | Page 18 of 39 20538-034 TRANSMITTER STATE MACHINE Data Sheet ADAR2001 Figure 30 shows how the transmitter state machine can be used to cycle through the four PAs on a single ADAR2001 while at a fixed frequency. In this example, the defined state machine depth, TX_STATES (Register 0x017, Bits[6:0]), is 5 because there are 6 states inside the loop, and TX_STATES is 0 indexed. As shown in Figure 30, * * * * * * Transmit State 0 = sleep (outside the loop) Transmit State 1 = Channel 1 PA ready Transmit State 2 = transmit on Channel 1, Channel 2 PA ready Transmit State 3 = transmit on Channel 2, Channel 3 PA ready Transmit State 4 = transmit on Channel 3, Channel 4 PA ready Transmit State 5 = transmit on Channel 4 SLEEP MULT_STATE_0 TX_STATE_0 MULT: ALL SLEEP BPF: N/A PA: ALL SLEEP MULTIPLIER TRANSMITTER RESET RESET The initial state is the sleep state, where power consumption is at a minimum. This state is reached by pulsing the TxRST pin. A pulse on TxADV then advances the state machine to the first state inside the loop, which is defined as a ready state, where Channel 1 is partially powered but not active. The splitters feeding Channel 1 are active to speed up the switching speed of the next state. An additional pulse on TxADV then makes this subcircuit path fully active. Continuing to make use of the ready mode for the upcoming state throughout the sweep, the PA switching and settling time can be minimized for all states. After the appropriate number of pulses are applied to TxADV (6, in this case), the state machine automatically returns to the first state in the loop (ready). CHANNEL 1 READY CHANNEL 1 10GHz TO 12GHz MULT_STATE_1 TX_STATE_1 MULT_STATE_2 TX_STATE_2 MULT: LOW RDY BPF: N/A PA: CH. 1 RDY MULT: LOW ACT BPF: LOW PA: CH. 1 ACT MULTIPLIER TRANSMITTER ADVANCE ADVANCE MULTIPLIER TRANSMITTER ADVANCE ADVANCE TRANSMITTER ADVANCE CHANNEL 2 10GHz TO 12GHz CHANNEL 3 10GHz TO 12GHz CHANNEL 4 10GHz TO 12GHz MULT_STATE_2 TX_STATE_3 MULT: LOW ACT BPF: LOW PA: CH. 2 ACT MULT_STATE_2 TX_STATE_4 MULT: LOW ACT BPF: LOW PA: CH. 3 ACT MULT_STATE_2 TX_STATE_5 MULT: LOW ACT BPF: LOW PA: CH. 4 ACT TRANSMITTER ADVANCE TRANSMITTER ADVANCE Figure 30. State Machine Loop Example for a Channel Sweep with a Fixed Frequency Rev. 0 | Page 19 of 39 MULTIPLIER TRANSMITTER ADVANCE ADVANCE 20538-035 SINGLE FREQUENCY CHANNEL SWEEP ADAR2001 Data Sheet Figure 31 shows an example of how the two state machines can be used to perform a multichannel frequency sweep from 20 GHz to 40 GHz (that is, sweep through a frequency range while on one channel, move to the next channel, and repeat the sweep). In this example, because both MULT_STATES (Register 0x018, Bits[3:0]) and TX_STATES (Register 0x017 Bits[6:0]) are 0 indexed, MULT_STATES is defined as 2 because there are three states inside the multiplier/filter loop and TX_STATES as 3 because there are four states inside the transmitter loop. As shown in Figure 31, * * * * * * * * * Multiplier/Filter State 0 = sleep (outside the loop) Multiplier/Filter State 1 = output 20 GHz to 25 GHz to PAs Multiplier/Filter State 2 = output 25 GHz to 30 GHz to PAs Multiplier/Filter State 3 = output 30 GHz to 40 GHz to PAs Transmit State 0 = sleep (outside the loop) Transmit State 1 = transmit on Channel 1 Transmit State 2 = transmit on Channel 2 Transmit State 3 = transmit on Channel 3 Transmit State 4 = transmit on Channel 4 Reset pulses on TxRST and MRST put both state machines in their initial states, which in this case are defined as sleep modes. MULTIPLIER TRANSMITTER RESET RESET Pulses on MADV and TxADV then advance both state machines to their first active state. In this example, an initial ready state is skipped, and the circuit goes directly from sleep mode to active mode. Additional pulses on MADV are applied as the frequency is swept. Multiplier ready modes are used to ensure the fastest switching of the multiplier/filter circuitry. After the frequency sweep is completed on Channel 1, both MADV and TxADV are pulsed to put the multiplier/filter back into its first state and the transmitter switches the active channel from 1 to 2. Then, the frequency sweep repeats itself using repeated pulses on the MADV pin. In this example, after the four channels are frequency swept, both state machines loop back to their first active state. In a large array, it is recommended to loop them back to a sleep or ready state to wait for their turn to transmit again. SEQUENCER SLEEP CONTROL To further simplify the control of the ADAR2001, it is possible to link the sleep states of the two state machines so that one sequencer going to sleep forces the other to sleep as well. This link helps to limit the total number of required states to achieve a desired type of operation. To use this feature, one of the two sleep control bits must be set, but not both. SLEEP CHANNEL 1 20GHz TO 25GHz CHANNEL 1 25GHz TO 30GHz CHANNEL 1 30GHz TO 40GHz MULT_STATE_0 TX_STATE_0 MULT: ALL SLEEP BPF: N/A PA: ALL SLEEP MULT_STATE_1 TX_STATE_1 MULT: MID ACT BPF: HIGH PA: CH. 1 ACT MULT_STATE_2 TX_STATE_1 MULT: HIGH ACT BPF: LOW PA: CH. 1 ACT MULT_STATE_3 TX_STATE_1 MULT: HIGH ACT BPF: HIGH PA: CH. 1 ACT MULTIPLIER ADVANCE MULTIPLIER TRANSMITTER ADVANCE ADVANCE MULTIPLIER TRANSMITTER ADVANCE ADVANCE CHANNEL 2 20GHz TO 25GHz CHANNEL 2 25GHz TO 30GHz CHANNEL 2 30GHz TO 40GHz MULT_STATE_1 TX_STATE_2 MULT: MID ACT BPF: HIGH PA: CH. 2 ACT MULT_STATE_2 TX_STATE_2 MULT: HIGH ACT BPF: LOW PA: CH. 2 ACT MULT_STATE_3 TX_STATE_2 MULT: HIGH ACT BPF: HIGH PA: CH. 2 ACT MULTIPLIER ADVANCE MULTIPLIER ADVANCE CHANNEL 3 20GHz TO 25GHz CHANNEL 3 25GHz TO 30GHz CHANNEL 3 30GHz TO 40GHz MULT_STATE_1 TX_STATE_3 MULT_STATE_2 TX_STATE_3 MULT: MID ACT BPF: HIGH PA: CH. 3 ACT MULT: HIGH ACT BPF: LOW PA: CH. 3 ACT MULT_STATE_3 TX_STATE_3 MULT: HIGH ACT BPF: HIGH PA: CH. 3 ACT MULTIPLIER TRANSMITTER ADVANCE ADVANCE MULTIPLIER TRANSMITTER ADVANCE ADVANCE MULTIPLIER ADVANCE MULTIPLIER ADVANCE MULTIPLIER ADVANCE CHANNEL 4 20GHz TO 25GHz CHANNEL 4 25GHz TO 30GHz CHANNEL 4 30GHz TO 40GHz MULT_STATE_1 TX_STATE_4 MULT: MID ACT BPF: HIGH PA: CH. 4 ACT MULT_STATE_2 TX_STATE_4 MULT: HIGH ACT BPF: LOW PA: CH. 4 ACT MULT_STATE_3 TX_STATE_4 MULT: HIGH ACT BPF: HIGH PA: CH. 4 ACT MULTIPLIER ADVANCE MULTIPLIER ADVANCE Figure 31. State Machine Loop Example for 4-Channel Frequency Sweep Rev. 0 | Page 20 of 39 MULTIPLIER TRANSMITTER ADVANCE ADVANCE 20538-036 MULTICHANNEL FREQUENCY SWEEP Data Sheet ADAR2001 For example, when the ADAR2001 is configured for a frequency sweep (as shown in Figure 29), if the TX_SLP_CTRL bit (Register 0x016, Bit 6) is set, when the multiplier/filter sequencer is reset, the transmitter state machine is forced to sleep as well. This means that the transmitter state machine does not need to have a state dedicated to sleep if it only needs to sleep when the multiplier/ filter sleeps. Furthermore, because the multiplier/ filter sleep state is controlling the sleep state of the transmitter, bringing the multiplier/filter out of sleep also brings the transmitter out of sleep, all of which is controlled with either the SPI or one external line (MADV). SEQUENCER SLEEP HOLD By default, when one of the sequencers is forced asleep using one of the sleep control bits (MULT_SLP_CTRL or TX_SLP_CTRL), the counter for the sequencer being controlled can still be advanced. Because of this behavior, it is possible for a state machine to be put to sleep in one condition and brought out of sleep in another, depending on whether the sequencer advance or reset signals were exercised while the sequencer was sleeping. If this behavior is undesired, the sleep hold bits (MULT_SLP_ HOLD and TX_SLP_HOLD) can be asserted to force the associated state machine counter to ignore any inputs on the sequencer advance line. The counter also ignores advance signals coming from the SPI. Note that the state machine counters always respond to a reset signal, even when the sleep hold bit is high. When sleep hold is used, care must be taken when bringing the state machines out of sleep mode to ensure that the desired modes are reached. If the advance pins for both sequencers are pulsed too closely together under this condition, it is possible for the sequencer being controlled to not move into the expected state. To prevent this, the advance pulses must be staggered such that the rising edges are separated by a minimum of 3 ns with the pulse of the controlled sequencer coming second. See Figure 32 for an example of how to pulse the sequencers under this condition. It is possible to bypass the latching of the internal control signals by setting the bypass bits (TX_CTL_LATCH_BYP and MULT_CTL_LATCH_BYP) in the sequencer setup registers (Register 0x016, Bit 4 and Register 0x018, Bit 4). Bypassing the latch results in the new state taking effect as soon as possible after the rising edge. Because the internal control signals are not aligned, the overall switching time between states can increase when compared to using the latch. Also, glitches are more likely to occur in the internal control signals, resulting in undesired transients in the RF blocks. Note that this latch is the last check before any new data is sent to the various individual blocks. Therefore, when using the ADAR2001 in manual or SPI mode (sequencers disabled), the latching must be bypassed. If latching is not bypassed, the blocks never receive the new instructions unless the external sequencer pins are pulsed. However, this issue is uncommon because the sequencers are disabled in this mode of operation. PARALLEL CHIP CONTROL Up to 16 devices (a total of 64 channels) can be driven by a single set of four state machine control lines, three common SPI lines, and a CS line for each chip. Using this method, the total number of digital control lines is 7 + N, where N is the number of ADAR2001 ICs (see Figure 33 for a basic diagram). Parallel chip control can be used to minimize the total number of digital control lines. The SPI lines can be reduced to two common lines if 3-wire mode is selected by setting the SDOACTIVE and SDOACTIVE_ bits (Register 0x00, Bit 4 and Bit 3, respectively) to low. If 3-wire SPI mode is used, the total number of digital lines to 6 + N. TX_SLP_HOLD REGISTER 0x016, BIT 5 = 1 MULT_SLP_HOLD REGISTER 0x018, BIT 5 = 0 TX_SLP_CTRL REGISTER 0x016, BIT 6 = 1 MULT_SLP_CTRL REGISTER 0x018, BIT 6 = 0 ADAR2001 (1) SPI SEQUENCERS COMMON SEQUENCER LINES ADAR2001 (2) SPI SEQUENCERS 3ns COMMON SPI LINES 20538-037 MADV TxADV Figure 32. Example of How to Pulse the Sequencer Advance Pins to Ensure Advancement with Transmitter State Machine Sleep Hold Enabled ADAR2001 (16) Typically, when a sequencer control line is pulsed, the upcoming state is loaded on the rising edge of the control pulse and latched to the various signal blocks on the falling edge of the same pulse. The latching helps to line up all the internal control signals so that the changes take place simultaneously. Rev. 0 | Page 21 of 39 SEQUENCERS 20538-038 SPI SEQUENCER CONTROL LATCH BYPASS SPI CS LINES Figure 33. SPI and State Machine Digital Lines for Addressing and Controlling Up to 16 ADAR2001 Devices in Parallel ADAR2001 Data Sheet MULTICHIP FREQUENCY AND CHANNEL SWEEP Figure 34 shows an example of how the two state machines can be used to perform a multichip frequency and channel sweep from 10 GHz to 16 GHz (that is, sweep through all four channels on a single chip while at a fixed frequency range, move to the next chip to repeat the channel sweep, then move to the next frequency to repeat the process). This example assumes that the state machine control lines are connected in parallel for up to 16 devices (64 channels, see Figure 33). Initially, pulses on TxRST and MRST put both state machines in State 0, which in this case, is a sleep mode. Next, pulses on MADV and TxADV advance both state machines to their first active state (transmitting on Channel 1 of ADAR2001 IC 1). Additional pulses on the TxADV line are applied to successively switch through all the transmit channels of the first ADAR2001. After all four channels are swept on the first device, an additional pulse on TxADV activates Channel 1 on ADAR2001 IC 2 while putting the Channel 4 PA on the first chip into a ready mode to prevent disrupting the multiplier/filter signal before the PA turns off. This sequence continues until all 64 channels on all 16 ADAR2001 ICs have transmitted at the first frequency or range. At that point, a pulse is applied to both MADV and TxADV to advance the multiplier/filter sequencer to the next frequency range of interest and set the Channel 1 PA on ADAR2001 IC 1 back into an active mode. Another series of TxADV pulses follows until the last channel on ADAR2001 IC 16 is transmitting the new frequency or range. SLEEP MULT_STATE_0 TX_STATE_0 MULT: ALL SLEEP BPF: N/A PA: ALL SLEEP MULTIPLIER Tx RESET RESET IC 1 10GHz TO 13GHz MULT_STATE_1 TX_STATE_1 MULT: LOW ACT BPF: LOW PA: CH. 1 ACT ...... IC 16 10GHz TO 13GHz IC 1 13GHz TO 16GHz MULT_STATE_1 TX_STATE_61 MULT: LOW ACT BPF: LOW PA: CH. 1 ACT MULT_STATE_2 TX_STATE_1 MULT: LOW ACT BPF: HIGH PA: CH. 1 ACT ...... IC 16 13GHz TO 16GHz MULT_STATE_2 TX_STATE_61 MULT: LOW ACT BPF: HIGH PA: CH. 1 ACT MULTIPLIER TX ADVANCE ADVANCE MULT_STATE_1 TX_STATE_2 MULT: LOW ACT BPF: LOW PA: CH. 2 ACT Tx ADVANCE MULT_STATE_1 TX_STATE_3 MULT: LOW ACT BPF: LOW PA: CH. 3 ACT Tx ADVANCE MULT_STATE_1 TX_STATE_4 MULT: LOW ACT BPF: LOW PA: CH. 4 ACT Tx ADVANCE Tx ADVANCE Tx ADVANCE MULT_STATE_2 TX_STATE_2 MULT: LOW ACT BPF: HIGH PA: CH. 2 ACT MULT_STATE_1 TX_STATE_62 MULT: LOW ACT BPF: LOW PA: CH. 2 ACT Tx ADVANCE Tx ADVANCE MULT_STATE_2 TX_STATE_3 MULT: LOW ACT BPF: HIGH PA: CH. 3 ACT MULT_STATE_1 TX_STATE_63 MULT: LOW ACT BPF: LOW PA: CH. 3 ACT Tx ADVANCE Tx ADVANCE MULT_STATE_2 TX_STATE_4 MULT: LOW ACT BPF: HIGH PA: CH. 4 ACT MULT_STATE_1 TX_STATE_64 MULT: LOW ACT BPF: LOW PA: CH. 4 ACT MULT ADV Tx ADVANCE Tx ADVANCE Tx ADVANCE MULT_STATE_2 TX_STATE_62 MULT: LOW ACT BPF: HIGH PA: CH. 2 ACT Tx ADVANCE MULT_STATE_2 TX_STATE_63 MULT: LOW ACT BPF: HIGH PA: CH. 3 ACT Tx ADVANCE MULT_STATE_2 TX_STATE_64 MULT: LOW ACT BPF: HIGH PA: CH. 4 ACT MULT ADVANCE Tx ADVANCE Figure 34. State Machine Loop Example for a 16-Chip Frequency and Channel Sweep Rev. 0 | Page 22 of 39 ANY ADDITIONAL MULTIPLIER BANDS 20538-039 Tx ADVANCE Data Sheet ADAR2001 In Table 8, SLP is the sleep state (State 0), CH1 to CH4 indicates the actively transmitting channel (Channel 1, Channel 2, Channel 3, or Channel 4), and RDY is ready mode. Table 8 shows how the transmitter state machine for each ADAR2001 can be set up to work in sequence, as described. Each device is turned fully on for only four states, but these four on states are all offset from each other. To run this sequence where up to 64 channels are swept with the state machines of all devices driven in parallel, 64 transmit states are used inside the loop, with the sleep state (State 0) used as a reset condition. If there are more tiles of 16 chips in the array that need to transmit after the tile shown in Table 8, this tile can have a reset pulse sent to put the sequencers into the initial sleep mode to wait for their turn to transmit again. Table 8. Transmitter Sequencer Settings for 16 ADAR2001 Chips Using Shared Sequencer Lines for a Chip and Channel Sweep Tx State (Reset) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 ADAR2001 Chip Number 1 SLP 2 SLP 3 SLP 4 SLP 5 SLP 6 SLP 7 SLP 8 SLP 9 SLP 10 SLP 11 SLP 12 SLP 13 SLP 14 SLP 15 SLP 16 SLP Function All sleep CH1 CH2 CH3 CH4 RDY SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP RDY CH1 CH2 CH3 CH4 RDY SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP RDY CH1 CH2 CH3 CH4 RDY SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP RDY CH1 CH2 CH3 CH4 RDY SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP RDY CH1 CH2 CH3 CH4 RDY SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP RDY CH1 CH2 CH3 CH4 RDY SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP RDY CH1 CH2 CH3 CH4 RDY SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP RDY CH1 CH2 CH3 CH4 RDY SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP RDY CH1 CH2 CH3 CH4 SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP RDY SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP RDY SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP Chip 1 transmitting Rev. 0 | Page 23 of 39 Chip 2 transmitting Chip 3 transmitting Chip 4 transmitting Chip 5 transmitting Chip 6 transmitting Chip 7 transmitting Chip 8 transmitting Chip 9 transmitting ADAR2001 Tx State 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Data Sheet ADAR2001 Chip Number 1 SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP RDY 2 SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP 3 SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP 4 SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP 5 SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP 6 SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP 7 SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP 8 SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP 9 RDY SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP 10 CH1 CH2 CH3 CH4 RDY SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP Rev. 0 | Page 24 of 39 11 SLP SLP SLP RDY CH1 CH2 CH3 CH4 RDY SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP 12 SLP SLP SLP SLP SLP SLP SLP RDY CH1 CH2 CH3 CH4 RDY SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP 13 SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP RDY CH1 CH2 CH3 CH4 RDY SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP 14 SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP RDY CH1 CH2 CH3 CH4 RDY SLP SLP SLP SLP SLP SLP SLP 15 SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP RDY CH1 CH2 CH3 CH4 RDY SLP SLP SLP 16 SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP RDY CH1 CH2 CH3 CH4 Function Chip 10 transmitting Chip 11 transmitting Chip 12 transmitting Chip 13 transmitting Chip 14 transmitting Chip 15 transmitting Chip 16 transmitting Data Sheet ADAR2001 BIAS POINTS Table 9. Default Bias Points Register Address 0x011 0x012 0x013 0x014 0x015 Register Name BIAS_CURRENT_MULT1 Bit Field Name(s) Register Bit(s) MULT_LOW_BIAS MULT_MID_BIAS [3:0] [7:4] MULT_HIGH_BIAS [3:0] RF_AMP1_BIAS RF_AMP2_BIAS [3:0] [7:4] SPLT1_BIAS SPLT2_BIAS [3:0] [7:4] PA_BIAS [3:0] BIAS_CURRENT_MULT2 BIAS_CURRENT_RFAMP BIAS_CURRENT_SPLT BIAS_CURRENT_PA Default Value 0xBB 0xB 0xB 0x0B 0xB 0x75 0x05 0x07 0xB5 0x5 0xB 0x0C 0xC Rev. 0 | Page 25 of 39 Description Low and mid band multiplier bias current Low band multiplier bias current Mid band multiplier bias current High band multiplier bias current High band multiplier bias current RF buffer amplifier bias current RF buffer input stage bias current RF buffer output stage bias current Active splitter bias current First stage active splitter bias current Second stage active splitter bias current Power amplifier bias current Power amplifier bias current ADAR2001 Data Sheet REGISTER SUMMARY Table 10. ADAR2001 Register Summary Addr Name 0x000 INTERFACE_CONFIG_A 0x001 INTERFACE_CONFIG_B 0x002 DEV_CONFIG 0x003 0x004 0x005 0x00A 0x00B 0x00C 0x00D 0x00F CHIP_TYPE PRODUCT_ID_H PRODUCT_ID_L SCRATCH_PAD SPI_REV VENDOR_ID_H VENDOR_ID_L TRANSFER_REG 0x010 PWRON 0x011 BIAS_CURRENT_MULT1 0x012 BIAS_CURRENT_MULT2 0x013 BIAS_CURRENT_RFAMP 0x014 BIAS_CURRENT_SPLT 0x015 BIAS_CURRENT_PA 0x016 TX_SEQUENCER_SETUP Bits 7 6 5 4 3 2 1 0 7 6 Bit Name SOFTRESET LSB_FIRST ADDR_ASCN SDOACTIVE SDOACTIVE_ ADDR_ASCN_ LSB_FIRST_ SOFTRESET_ SINGLE_INSTRUCTION CS_STALL Description Soft Reset LSB First Address Ascension SDO Active SDO Active Address Ascension LSB First Soft Reset Single Instruction CS Stall Reset 0x0 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 5 4 3 [2:1] 0 [7:4] [3:2] [1:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:1] 0 [7:1] 0 [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] 7 6 5 MASTER_SLAVE_RB SLOW_INTERFACE_CTRL RESERVED SOFT_RESET RESERVED DEV_STATUS CUST_OPERATING_MODE NORM_OPERATING_MODE CHIP_TYPE PRODUCT_ID[15:8] PRODUCT_ID[7:0] SCRATCHPAD SPI_REV VENDOR_ID[15:8] VENDOR_ID[7:0] RESERVED MASTER_SLAVE_XFER RESERVED PWRON MULT_MID_BIAS MULT_LOW_BIAS RESERVED MULT_HIGH_BIAS RF_AMP2_BIAS RF_AMP1_BIAS SPLT2_BIAS SPLT1_BIAS RESERVED PA_BIAS TX_SEQ_EN TX_SLP_CTRL TX_SLP_HOLD Master Slave Readback Slow Interface Control Reserved. Soft Reset Reserved Device Status Custom Operating Modes Normal Operating Modes Chip Type Product ID High Product ID Low Scratch Pad SPI Revision Vendor ID High Vendor ID Low Reserved Master Slave Transfer Reserved Chip Power-Up Multiplier Mid Band 4x Bias Current Setting Multiplier Low Band 4x Bias Current Setting Reserved Multiplier High Band 4x Bias Current Setting RF Amp Output Stage Bias Current Setting RF Amp Input Stage Bias Current Setting Second Active Splitter Stages Bias Current Setting First Active Splitter Stage Bias Current Setting Reserved PA Bias Current Setting Enables Transmit Sequencer Sets Transmit Sleep Mode Control Holds the Transmit Sequencer State When Multiplier Is in Sleep Mode Bypasses the Control Latch for Transmit Controls Reserved 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0xB 0xB 0x0 0xB 0x7 0x5 0xB 0x5 0x0 0xC 0x0 0x0 0x0 R/W R/W R R/W R R/W R/W R/W R R R R/W R R R R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W 0x1 0x0 R/W R 4 TX_CTL_LATCH_BYP [3:0] RESERVED Rev. 0 | Page 26 of 39 Data Sheet ADAR2001 Addr Name 0x017 TX_SEQUENCER_SETUP2 Bits 7 [6:0] 0x018 MULT_SEQUENCER_SETUP 7 6 5 0x019 TX_STATES_1_2 0x01A TX_STATES_3_4 0x01B TX_STATES_5_6 0x01C TX_STATES_7_8 0x01D TX_STATES_9_10 0x01E TX_STATES_11_12 0x01F TX_STATES_13_14 0x020 TX_STATES_15_16 0x021 TX_STATES_17_18 0x022 TX_STATES_19_20 0x023 TX_STATES_21_22 0x024 TX_STATES_23_24 0x025 TX_STATES_25_26 0x026 TX_STATES_27_28 0x027 TX_STATES_29_30 0x028 TX_STATES_31_32 0x029 TX_STATES_33_34 0x02A TX_STATES_35_36 0x02B TX_STATES_37_38 0x02C TX_STATES_39_40 0x02D TX_STATES_41_42 4 [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] Bit Name RESERVED TX_STATES MULT_SEQ_EN MULT_SLP_CTRL MULT_SLP_HOLD MULT_CTL_LATCH_BYP MULT_STATES TX_STATE_1 TX_STATE_2 TX_STATE_3 TX_STATE_4 TX_STATE_5 TX_STATE_6 TX_STATE_7 TX_STATE_8 TX_STATE_9 TX_STATE_10 TX_STATE_11 TX_STATE_12 TX_STATE_13 TX_STATE_14 TX_STATE_15 TX_STATE_16 TX_STATE_17 TX_STATE_18 TX_STATE_19 TX_STATE_20 TX_STATE_21 TX_STATE_22 TX_STATE_23 TX_STATE_24 TX_STATE_25 TX_STATE_26 TX_STATE_27 TX_STATE_28 TX_STATE_29 TX_STATE_30 TX_STATE_31 TX_STATE_32 TX_STATE_33 TX_STATE_34 TX_STATE_35 TX_STATE_36 TX_STATE_37 TX_STATE_38 TX_STATE_39 TX_STATE_40 TX_STATE_41 TX_STATE_42 Description Reserved Sets Transmit Sequencer Depth Enables Multiplier Sequencer Sets Multiplier Sleep Mode Control Holds the Multiplier Sequencer State When Transmit Is in Sleep Mode Bypasses the Control Latch for Multiplier Controls Sets Multiplier Sequencer Depth Mode Select for Transmit Sequencer State 1 Mode Select for Transmit Sequencer State 2 Mode Select for Transmit Sequencer State 3 Mode Select for Transmit Sequencer State 4 Mode Select for Transmit Sequencer State 5 Mode Select for Transmit Sequencer State 6 Mode Select for Transmit Sequencer State 7 Mode Select for Transmit Sequencer State 8 Mode Select for Transmit Sequencer State 9 Mode Select for Transmit Sequencer State 10 Mode Select for Transmit Sequencer State 11 Mode Select for Transmit Sequencer State 12 Mode Select for Transmit Sequencer State 13 Mode Select for Transmit Sequencer State 14 Mode Select for Transmit Sequencer State 15 Mode Select for Transmit Sequencer State 16 Mode Select for Transmit Sequencer State 17 Mode Select for Transmit Sequencer State 18 Mode Select for Transmit Sequencer State 19 Mode Select for Transmit Sequencer State 20 Mode Select for Transmit Sequencer State 21 Mode Select for Transmit Sequencer State 22 Mode Select for Transmit Sequencer State 23 Mode Select for Transmit Sequencer State 24 Mode Select for Transmit Sequencer State 25 Mode Select for Transmit Sequencer State 26 Mode Select for Transmit Sequencer State 27 Mode Select for Transmit Sequencer State 28 Mode Select for Transmit Sequencer State 29 Mode Select for Transmit Sequencer State 30 Mode Select for Transmit Sequencer State 31 Mode Select for Transmit Sequencer State 32 Mode Select for Transmit Sequencer State 33 Mode Select for Transmit Sequencer State 34 Mode Select for Transmit Sequencer State 35 Mode Select for Transmit Sequencer State 36 Mode Select for Transmit Sequencer State 37 Mode Select for Transmit Sequencer State 38 Mode Select for Transmit Sequencer State 39 Mode Select for Transmit Sequencer State 40 Mode Select for Transmit Sequencer State 41 Mode Select for Transmit Sequencer State 42 Rev. 0 | Page 27 of 39 Reset 0x0 0x0 0x0 0x0 0x0 Access R R/W R/W R/W R/W 0x1 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ADAR2001 Addr Name 0x02E TX_STATES_43_44 0x02F TX_STATES_45_46 0x030 TX_STATES_47_48 0x031 TX_STATES_49_50 0x032 TX_STATES_51_52 0x033 TX_STATES_53_54 0x034 TX_STATES_55_56 0x035 TX_STATES_57_58 0x036 TX_STATES_59_60 0x037 TX_STATES_61_62 0x038 TX_STATES_63_64 0x039 TX_STATES_65_66 0x03A TX_STATES_67_68 0x03B TX_STATES_69_70 0x03C MULT_STATES_1_2 0x03D MULT_STATES_3_4 0x03E MULT_STATES_5_6 0x03F MULT_STATES_7_8 0x040 MULT_STATES_9_10 0x041 MULT_STATES_11_12 0x042 MULT_STATES_13_14 0x043 MULT_STATES_15_16 0x044 SEQUENCER_CTRL_SPI Data Sheet Bits [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] 3 2 1 0 Bit Name TX_STATE_43 TX_STATE_44 TX_STATE_45 TX_STATE_46 TX_STATE_47 TX_STATE_48 TX_STATE_49 TX_STATE_50 TX_STATE_51 TX_STATE_52 TX_STATE_53 TX_STATE_54 TX_STATE_55 TX_STATE_56 TX_STATE_57 TX_STATE_58 TX_STATE_59 TX_STATE_60 TX_STATE_61 TX_STATE_62 TX_STATE_63 TX_STATE_64 TX_STATE_65 TX_STATE_66 TX_STATE_67 TX_STATE_68 TX_STATE_69 TX_STATE_70 MULT_STATE_1 MULT_STATE_2 MULT_STATE_3 MULT_STATE_4 MULT_STATE_5 MULT_STATE_6 MULT_STATE_7 MULT_STATE_8 MULT_STATE_9 MULT_STATE_10 MULT_STATE_11 MULT_STATE_12 MULT_STATE_13 MULT_STATE_14 MULT_STATE_15 MULT_STATE_16 RESERVED MULT_RST_SPI MULT_ADV_SPI TX_RST_SPI TX_ADV_SPI Description Mode Select for Transmit Sequencer State 43 Mode Select for Transmit Sequencer State 44 Mode Select for Transmit Sequencer State 45 Mode Select for Transmit Sequencer State 46 Mode Select for Transmit Sequencer State 47 Mode Select for Transmit Sequencer State 48 Mode Select for Transmit Sequencer State 49 Mode Select for Transmit Sequencer State 50 Mode Select for Transmit Sequencer State 51 Mode Select for Transmit Sequencer State 52 Mode Select for Transmit Sequencer State 53 Mode Select for Transmit Sequencer State 54 Mode Select for Transmit Sequencer State 55 Mode Select for Transmit Sequencer State 56 Mode Select for Transmit Sequencer State 57 Mode Select for Transmit Sequencer State 58 Mode Select for Transmit Sequencer State 59 Mode Select for Transmit Sequencer State 60 Mode Select for Transmit Sequencer State 61 Mode Select for Transmit Sequencer State 62 Mode Select for Transmit Sequencer State 63 Mode Select for Transmit Sequencer State 64 Mode Select for Transmit Sequencer State 65 Mode Select for Transmit Sequencer State 66 Mode Select for Transmit Sequencer State 67 Mode Select for Transmit Sequencer State 68 Mode Select for Transmit Sequencer State 69 Mode Select for Transmit Sequencer State 70 Mode Select for Multiplier Sequencer State 1 Mode Select for Multiplier Sequencer State 2 Mode Select for Multiplier Sequencer State 3 Mode Select for Multiplier Sequencer State 4 Mode Select for Multiplier Sequencer State 5 Mode Select for Multiplier Sequencer State 6 Mode Select for Multiplier Sequencer State 7 Mode Select for Multiplier Sequencer State 8 Mode Select for Multiplier Sequencer State 9 Mode Select for Multiplier Sequencer State 10 Mode Select for Multiplier Sequencer State 11 Mode Select for Multiplier Sequencer State 12 Mode Select for Multiplier Sequencer State 13 Mode Select for Multiplier Sequencer State 14 Mode Select for Multiplier Sequencer State 15 Mode Select for Multiplier Sequencer State 16 Reserved Resets Multiplier Sequencer Advances Multiplier Sequencer State Resets Transmit Sequencer Advances Transmit Sequencer State Rev. 0 | Page 28 of 39 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W Data Sheet Addr Name 0x045 TX_EN1_SPI 0x046 TX_EN2_SPI 0x047 MULT_EN_SPI 0x048 MULT_PASS_SPI 0x049 DET_ENABLES 0x04A ADC_CTRL 0x04B ADC_OUTPUT 0x04C TX_CURR_MODE 0x04D TX_CURR_STATE 0x04E MULT_STATUS 0x04F REV_ID ADAR2001 Bits 7 6 5 4 3 2 1 0 [7:3] 2 1 Bit Name CH1_RDY_SPI CH1_ACT_SPI CH2_RDY_SPI CH2_ACT_SPI CH3_RDY_SPI CH3_ACT_SPI CH4_RDY_SPI CH4_ACT_SPI RESERVED SPLT1_EN_SPI SPLT12_EN_SPI 0 SPLT34_EN_SPI 7 6 5 4 3 2 1 0 7 6 5 [4:0] [7:4] 3 2 1 0 7 6 5 4 [3:1] 0 [7:0] [7:4] [3:0] 7 [6:0] [7:4] [3:0] [7:0] RESERVED RFAMP_EN_SPI MULT_LOW_RDY_SPI MULT_LOW_ACT_SPI MULT_MID_RDY_SPI MULT_MID_ACT_SPI MULT_HIGH_RDY_SPI MULT_HIGH_ACT_SPI BPF_SPI PA_NOTCH_SPI RESERVED ATTN_SPI RESERVED CH4_DET_EN CH3_DET_EN CH2_DET_EN CH1_DET_EN ADC_CLKFREQ_SEL ADC_EN CLK_EN ST_CONV MUX_SEL ADC_EOC ADC RESERVED TX_CURR_MODE RESERVED TX_CURR_STATE MULT_CURR_STATE MULT_CURR_MODE REV_ID Description SPI Mode Channel 1 Ready Enable SPI Mode Channel 1 Active Enable SPI Mode Channel 2 Ready Enable SPI Mode Channel 2 Active Enable SPI Mode Channel 3 Ready Enable SPI Mode Channel 3 Active Enable SPI Mode Channel 4 Ready Enable SPI Mode Channel 4 Active Enable Reserved SPI Mode Active Splitter1 Enable SPI Mode Channel 1 to Channel 2 Active Splitter Enable SPI Mode Channel 3 to Channel 4 Active Splitter Enable Reserved SPI Mode RF Amplifier Enable SPI Mode Low Band Ready Enable SPI Mode Low Band Active Enable SPI Mode Mid Band Ready Enable SPI Mode Mid Band Active Enable SPI Mode High Band Ready Enable SPI Mode High Band Active Enable SPI Mode BPF Select SPI Mode Notch Filter Select Reserved SPI Mode Attenuator Setting Reserved Enables Channel 4 Power Detector Enables Channel 3 Power Detector Enables Channel 2 Power Detector Enables Channel 1 Power Detector ADC Clock Frequency Selection Turns on Comparator and Resets State Machine Turns on Clock Oscillator Pulse Triggers Conversion Cycle ADC Input Signal Select ADC End of Conversion Signal ADC Output Word Reserved Read Back Current Transmit Mode Reserved Read Back Current Transmit Sequencer Count Read Back Current Multiplier Sequencer Count Read Back Current Multiplier Mode Chip Revision ID Rev. 0 | Page 29 of 39 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W 0x0 R/W 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R ADAR2001 Addr Name 0x050 TX_EN1_MODE_0 0x051 TX_EN2_MODE_0 0x052 TX_EN1_MODE_1 0x053 TX_EN2_MODE_1 0x054 TX_EN1_MODE_2 0x055 TX_EN2_MODE_2 0x056 TX_EN1_MODE_3 Data Sheet Bits 7 6 5 4 3 2 1 0 [7:3] 2 1 Bit Name CH1_RDY_MD0 CH1_ACT_MD0 CH2_RDY_MD0 CH2_ACT_MD0 CH3_RDY_MD0 CH3_ACT_MD0 CH4_RDY_MD0 CH4_ACT_MD0 RESERVED SPLT1_EN_MD0 SPLT12_EN_MD0 0 SPLT34_EN_MD0 7 6 5 4 3 2 1 0 [7:3] 2 1 CH1_RDY_MD1 CH1_ACT_MD1 CH2_RDY_MD1 CH2_ACT_MD1 CH3_RDY_MD1 CH3_ACT_MD1 CH4_RDY_MD1 CH4_ACT_MD1 RESERVED SPLT1_EN_MD1 SPLT12_EN_MD1 0 SPLT34_EN_MD1 7 6 5 4 3 2 1 0 [7:3] 2 1 CH1_RDY_MD2 CH1_ACT_MD2 CH2_RDY_MD2 CH2_ACT_MD2 CH3_RDY_MD2 CH3_ACT_MD2 CH4_RDY_MD2 CH4_ACT_MD2 RESERVED SPLT1_EN_MD2 SPLT12_EN_MD2 0 SPLT34_EN_MD2 7 6 5 4 3 2 1 0 CH1_RDY_MD3 CH1_ACT_MD3 CH2_RDY_MD3 CH2_ACT_MD3 CH3_RDY_MD3 CH3_ACT_MD3 CH4_RDY_MD3 CH4_ACT_MD3 Description Transmit Mode 0 Channel 1 Ready Enable Transmit Mode 0 Channel 1 Active Enable Transmit Mode 0 Channel 2 Ready Enable Transmit Mode 0 Channel 2 Active Enable Transmit Mode 0 Channel 3 Ready Enable Transmit Mode 0 Channel 3 Active Enable Transmit Mode 0 Channel 4 Ready Enable Transmit Mode 0 Channel 4 Active Enable Reserved Transmit Mode 0 Active Splitter 1 Enable Transmit Mode 0 Channel 1 to Channel 2 Active Splitter Enable Transmit Mode 0 Channel 3 to Channel 4 Active Splitter Enable Transmit Mode 1 Channel 1 Ready Enable Transmit Mode 1 Channel 1 Active Enable Transmit Mode 1 Channel 2 Ready Enable Transmit Mode 1 Channel 2 Active Enable Transmit Mode 1 Channel 3 Ready Enable Transmit Mode 1 Channel 3 Active Enable Transmit Mode 1 Channel 4 Ready Enable Transmit Mode 1 Channel 4 Active Enable Reserved Transmit Mode 1 Active Splitter 1 Enable Transmit Mode 1 Channel 1 to Channel 2 Active Splitter Enable Transmit Mode 1 Channel 3 to Channel 4 Active Splitter Enable Transmit Mode 2 Channel 1 Ready Enable Transmit Mode 2 Channel 1 Active Enable Transmit Mode 2 Channel 2 Ready Enable Transmit Mode 2 Channel 2 Active Enable Transmit Mode 2 Channel 3 Ready Enable Transmit Mode 2 Channel 3 Active Enable Transmit Mode 2 Channel 4 Ready Enable Transmit Mode 2 Channel 4 Active Enable Reserved Transmit Mode 2 Active Splitter 1 Enable Transmit Mode 2 Channel 1 to Channel 2 Active Splitter Enable Transmit Mode 2 Channel 3 to Channel 4 Active Splitter Enable Transmit Mode 3 Channel 1 Ready Enable Transmit Mode 3 Channel 1 Active Enable Transmit Mode 3 Channel 2 Ready Enable Transmit Mode 3 Channel 2 Active Enable Transmit Mode 3 Channel 3 Ready Enable Transmit Mode 3 Channel 3 Active Enable Transmit Mode 3 Channel 4 Ready Enable Transmit Mode 3 Channel 4 Active Enable Rev. 0 | Page 30 of 39 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W 0x0 R/W 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x0 0x1 0x1 R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W 0x1 R/W 0x1 0x1 0x1 0x0 0x1 0x0 0x1 0x0 0x0 0x1 0x1 R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W 0x1 R/W 0x1 0x0 0x1 0x1 0x1 0x0 0x1 0x0 R/W R/W R/W R/W R/W R/W R/W R/W Data Sheet Addr Name 0x057 TX_EN2_MODE_3 0x058 TX_EN1_MODE_4 0x059 TX_EN2_MODE_4 0x05A TX_EN1_MODE_5 0x05B TX_EN2_MODE_5 0x05C TX_EN1_MODE_6 0x05D TX_EN2_MODE_6 ADAR2001 Bits [7:3] 2 1 Bit Name RESERVED SPLT1_EN_MD3 SPLT12_EN_MD3 0 SPLT34_EN_MD3 7 6 5 4 3 2 1 0 [7:3] 2 1 CH1_RDY_MD4 CH1_ACT_MD4 CH2_RDY_MD4 CH2_ACT_MD4 CH3_RDY_MD4 CH3_ACT_MD4 CH4_RDY_MD4 CH4_ACT_MD4 RESERVED SPLT1_EN_MD4 SPLT12_EN_MD4 0 SPLT34_EN_MD4 7 6 5 4 3 2 1 0 [7:3] 2 1 CH1_RDY_MD5 CH1_ACT_MD5 CH2_RDY_MD5 CH2_ACT_MD5 CH3_RDY_MD5 CH3_ACT_MD5 CH4_RDY_MD5 CH4_ACT_MD5 RESERVED SPLT1_EN_MD5 SPLT12_EN_MD5 0 SPLT34_EN_MD5 7 6 5 4 3 2 1 0 [7:3] 2 1 CH1_RDY_MD6 CH1_ACT_MD6 CH2_RDY_MD6 CH2_ACT_MD6 CH3_RDY_MD6 CH3_ACT_MD6 CH4_RDY_MD6 CH4_ACT_MD6 RESERVED SPLT1_EN_MD6 SPLT12_EN_MD6 0 SPLT34_EN_MD6 Description Reserved Transmit Mode 3 Active Splitter 1 Enable Transmit Mode 3 Channel 1 to Channel 2 Active Splitter Enable Transmit Mode 3 Channel 3 to Channel 4 Active Splitter Enable Transmit Mode 4 Channel 1 Ready Enable Transmit Mode 4 Channel 1 Active Enable Transmit Mode 4 Channel 2 Ready Enable Transmit Mode 4 Channel 2 Active Enable Transmit Mode 4 Channel 3 Ready Enable Transmit Mode 4 Channel 3 Active Enable Transmit Mode 4 Channel 4 Ready Enable Transmit Mode 4 Channel 4 Active Enable Reserved Transmit Mode 4 Active Splitter 1 Enable Transmit Mode 4 Channel 1 to Channel 2 Active Splitter Enable Transmit Mode 4 Channel 3 to Channel 4 Active Splitter Enable Transmit Mode 5 Channel 1 Ready Enable Transmit Mode 5 Channel 1 Active Enable Transmit Mode 5 Channel 2 Ready Enable Transmit Mode 5 Channel 2 Active Enable Transmit Mode 5 Channel 3 Ready Enable Transmit Mode 5 Channel 3 Active Enable Transmit Mode 5 Channel 4 Ready Enable Transmit Mode 5 Channel 4 Active Enable Reserved Transmit Mode 5 Active Splitter 1 Enable Transmit Mode 5 Channel 1 to Channel 2 Active Splitter Enable Transmit Mode 5 Channel 3 to Channel 4 Active Splitter Enable Transmit Mode 6 Channel 1 Ready Enable Transmit Mode 6 Channel 1 Active Enable Transmit Mode 6 Channel 2 Ready Enable Transmit Mode 6 Channel 2 Active Enable Transmit Mode 6 Channel 3 Ready Enable Transmit Mode 6 Channel 3 Active Enable Transmit Mode 6 Channel 4 Ready Enable Transmit Mode 6 Channel 4 Active Enable Reserved Transmit Mode 6 Active Splitter 1 Enable Transmit Mode 6 Channel 1 to Channel 2 Active Splitter Enable Transmit Mode 6 Channel 3 to Channel 4 Active Splitter Enable Rev. 0 | Page 31 of 39 Reset 0x0 0x1 0x1 Access R R/W R/W 0x1 R/W 0x1 0x0 0x1 0x0 0x1 0x1 0x1 0x0 0x0 0x1 0x1 R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W 0x1 R/W 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x1 0x0 0x1 0x1 R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W 0x1 R/W 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x0 0x1 0x1 R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W 0x1 R/W ADAR2001 Addr Name 0x05E TX_EN1_MODE_7 0x05F TX_EN2_MODE_7 0x060 TX_EN1_MODE_8 0x061 TX_EN2_MODE_8 0x062 TX_EN1_MODE_9 0x063 TX_EN2_MODE_9 0x064 TX_EN1_MODE_10 Data Sheet Bits 7 6 5 4 3 2 1 0 [7:3] 2 1 Bit Name CH1_RDY_MD7 CH1_ACT_MD7 CH2_RDY_MD7 CH2_ACT_MD7 CH3_RDY_MD7 CH3_ACT_MD7 CH4_RDY_MD7 CH4_ACT_MD7 RESERVED SPLT1_EN_MD7 SPLT12_EN_MD7 0 SPLT34_EN_MD7 7 6 5 4 3 2 1 0 [7:3] 2 1 CH1_RDY_MD8 CH1_ACT_MD8 CH2_RDY_MD8 CH2_ACT_MD8 CH3_RDY_MD8 CH3_ACT_MD8 CH4_RDY_MD8 CH4_ACT_MD8 RESERVED SPLT1_EN_MD8 SPLT12_EN_MD8 0 SPLT34_EN_MD8 7 6 5 4 3 2 1 0 [7:3] 2 1 CH1_RDY_MD9 CH1_ACT_MD9 CH2_RDY_MD9 CH2_ACT_MD9 CH3_RDY_MD9 CH3_ACT_MD9 CH4_RDY_MD9 CH4_ACT_MD9 RESERVED SPLT1_EN_MD9 SPLT12_EN_MD9 0 SPLT34_EN_MD9 7 6 5 4 3 2 1 0 CH1_RDY_MD10 CH1_ACT_MD10 CH2_RDY_MD10 CH2_ACT_MD10 CH3_RDY_MD10 CH3_ACT_MD10 CH4_RDY_MD10 CH4_ACT_MD10 Description Transmit Mode 7 Channel 1 Ready Enable Transmit Mode 7 Channel 1 Active Enable Transmit Mode 7 Channel 2 Ready Enable Transmit Mode 7 Channel 2 Active Enable Transmit Mode 7 Channel 3 Ready Enable Transmit Mode 7 Channel 3 Active Enable Transmit Mode 7 Channel 4 Ready Enable Transmit Mode 7 Channel 4 Active Enable Reserved Transmit Mode 7 Active Splitter 1 Enable Transmit Mode 7 Channel 1 to Channel 2 Active Splitter Enable Transmit Mode 7 Channel 3 to Channel 4 Active Splitter Enable Transmit Mode 8 Channel 1 Ready Enable Transmit Mode 8 Channel 1 Active Enable Transmit Mode 8 Channel 2 Ready Enable Transmit Mode 8 Channel 2 Active Enable Transmit Mode 8 Channel 3 Ready Enable Transmit Mode 8 Channel 3 Active Enable Transmit Mode 8 Channel 4 Ready Enable Transmit Mode 8 Channel 4 Active Enable Reserved Transmit Mode 8 Active Splitter 1 Enable Transmit Mode 8 Channel 1 to Channel 2 Active Splitter Enable Transmit Mode 8 Channel 3 to Channel 4 Active Splitter Enable Transmit Mode 9 Channel 1 Ready Enable Transmit Mode 9 Channel 1 Active Enable Transmit Mode 9 Channel 2 Ready Enable Transmit Mode 9 Channel 2 Active Enable Transmit Mode 9 Channel 3 Ready Enable Transmit Mode 9 Channel 3 Active Enable Transmit Mode 9 Channel 4 Ready Enable Transmit Mode 9 Channel 4 Active Enable Reserved Transmit Mode 9 Active Splitter 1 Enable Transmit Mode 9 Channel 1 to Channel 2 Active Splitter Enable Transmit Mode 9 Channel 3 to Channel 4 Active Splitter Enable Transmit Mode 10 Channel 1 Ready Enable Transmit Mode 10 Channel 1 Active Enable Transmit Mode 10 Channel 2 Ready Enable Transmit Mode 10 Channel 2 Active Enable Transmit Mode 10 Channel 3 Ready Enable Transmit Mode 10 Channel 3 Active Enable Transmit Mode 10 Channel 4 Ready Enable Transmit Mode 10 Channel 4 Active Enable Rev. 0 | Page 32 of 39 Reset 0x1 0x1 0x1 0x1 0x1 0x0 0x1 0x0 0x0 0x1 0x1 Access R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W 0x1 R/W 0x1 0x1 0x1 0x0 0x1 0x1 0x1 0x0 0x0 0x1 0x1 R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W 0x1 R/W 0x1 0x1 0x1 0x0 0x1 0x0 0x1 0x1 0x0 0x1 0x1 R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W 0x1 R/W 0x1 0x0 0x1 0x1 0x1 0x1 0x1 0x0 R/W R/W R/W R/W R/W R/W R/W R/W Data Sheet Addr Name 0x065 TX_EN2_MODE_10 0x066 TX_EN1_MODE_11 0x067 TX_EN2_MODE_11 0x068 TX_EN1_MODE_12 0x069 TX_EN2_MODE_12 0x06A TX_EN1_MODE_13 0x06B TX_EN2_MODE_13 ADAR2001 Bits [7:3] 2 1 Bit Name RESERVED SPLT1_EN_MD10 SPLT12_EN_MD10 0 SPLT34_EN_MD10 7 6 5 4 3 2 1 0 [7:3] 2 1 CH1_RDY_MD11 CH1_ACT_MD11 CH2_RDY_MD11 CH2_ACT_MD11 CH3_RDY_MD11 CH3_ACT_MD11 CH4_RDY_MD11 CH4_ACT_MD11 RESERVED SPLT1_EN_MD11 SPLT12_EN_MD11 0 SPLT34_EN_MD11 7 6 5 4 3 2 1 0 [7:3] 2 1 CH1_RDY_MD12 CH1_ACT_MD12 CH2_RDY_MD12 CH2_ACT_MD12 CH3_RDY_MD12 CH3_ACT_MD12 CH4_RDY_MD12 CH4_ACT_MD12 RESERVED SPLT1_EN_MD12 SPLT12_EN_MD12 0 SPLT34_EN_MD12 7 6 5 4 3 2 1 0 [7:3] 2 1 CH1_RDY_MD13 CH1_ACT_MD13 CH2_RDY_MD13 CH2_ACT_MD13 CH3_RDY_MD13 CH3_ACT_MD13 CH4_RDY_MD13 CH4_ACT_MD13 RESERVED SPLT1_EN_MD13 SPLT12_EN_MD13 0 SPLT34_EN_MD13 Description Reserved Transmit Mode 10 Active Splitter 1 Enable Transmit Mode 10 Channel 1 to Channel 2 Active Splitter Enable Transmit Mode 10 Channel 3 to Channel 4 Active Splitter Enable Transmit Mode 11 Channel 1 Ready Enable Transmit Mode 11 Channel 1 Active Enable Transmit Mode 11 Channel 2 Ready Enable Transmit Mode 11 Channel 2 Active Enable Transmit Mode 11 Channel 3 Ready Enable Transmit Mode 11 Channel 3 Active Enable Transmit Mode 11 Channel 4 Ready Enable Transmit Mode 11 Channel 4 Active Enable Reserved Transmit Mode 11 Active Splitter 1 Enable Transmit Mode 11 Channel 1 to Channel 2 Active Splitter Enable Transmit Mode 11 Channel 3 to Channel 4 Active Splitter Enable Transmit Mode 12 Channel 1 Ready Enable Transmit Mode 12 Channel 1 Active Enable Transmit Mode 12 Channel 2 Ready Enable Transmit Mode 12 Channel 2 Active Enable Transmit Mode 12 Channel 3 Ready Enable Transmit Mode 12 Channel 3 Active Enable Transmit Mode 12 Channel 4 Ready Enable Transmit Mode 12 Channel 4 Active Enable Reserved Transmit Mode 12 Active Splitter 1 Enable Transmit Mode 12 Channel 1 to Channel 2 Active Splitter Enable Transmit Mode 12 Channel 3 to Channel 4 Active Splitter Enable Transmit Mode 13 Channel 1 Ready Enable Transmit Mode 13 Channel 1 Active Enable Transmit Mode 13 Channel 2 Ready Enable Transmit Mode 13 Channel 2 Active Enable Transmit Mode 13 Channel 3 Ready Enable Transmit Mode 13 Channel 3 Active Enable Transmit Mode 13 Channel 4 Ready Enable Transmit Mode 13 Channel 4 Active Enable Reserved Transmit Mode 13 Active Splitter 1 Enable Transmit Mode 13 Channel 1 to Channel 2 Active Splitter Enable Transmit Mode 13 Channel 3 to Channel 4 Active Splitter Enable Rev. 0 | Page 33 of 39 Reset 0x0 0x1 0x1 Access R R/W R/W 0x1 R/W 0x1 0x0 0x1 0x1 0x1 0x0 0x1 0x1 0x0 0x1 0x1 R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W 0x1 R/W 0x1 0x0 0x1 0x0 0x1 0x1 0x1 0x1 0x0 0x1 0x1 R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W 0x1 R/W 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x0 0x0 0x1 0x1 R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W 0x1 R/W ADAR2001 Addr Name 0x06C TX_EN1_MODE_14 0x06D TX_EN2_MODE_14 0x06E TX_EN1_MODE_15 0x06F TX_EN2_MODE_15 0x070 MULT_EN_MODE_0 0x071 MULT_PASS_MODE_0 0x072 MULT_EN_MODE_1 Data Sheet Bits 7 6 5 4 3 2 1 0 [7:3] 2 1 Bit Name CH1_RDY_MD14 CH1_ACT_MD14 CH2_RDY_MD14 CH2_ACT_MD14 CH3_RDY_MD14 CH3_ACT_MD14 CH4_RDY_MD14 CH4_ACT_MD14 RESERVED SPLT1_EN_MD14 SPLT12_EN_MD14 0 SPLT34_EN_MD14 7 6 5 4 3 2 1 0 [7:3] 2 1 CH1_RDY_MD15 CH1_ACT_MD15 CH2_RDY_MD15 CH2_ACT_MD15 CH3_RDY_MD15 CH3_ACT_MD15 CH4_RDY_MD15 CH4_ACT_MD15 RESERVED SPLT1_EN_MD15 SPLT12_EN_MD15 0 SPLT34_EN_MD15 7 6 5 4 3 2 1 0 7 6 5 [4:0] 7 6 5 4 3 2 1 0 RESERVED RFAMP_EN_MD0 MULT_LOW_RDY_MD0 MULT_LOW_ACT_MD0 MULT_MID_RDY_MD0 MULT_MID_ACT_MD0 MULT_HIGH_RDY_MD0 MULT_HIGH_ACT_MD0 BPF_MD0 PA_NOTCH_MD0 RESERVED ATTN_MD0 RESERVED RFAMP_EN_MD1 MULT_LOW_RDY_MD1 MULT_LOW_ACT_MD1 MULT_MID_RDY_MD1 MULT_MID_ACT_MD1 MULT_HIGH_RDY_MD1 MULT_HIGH_ACT_MD1 Description Transmit Mode 14 Channel 1 Ready Enable Transmit Mode 14 Channel 1 Active Enable Transmit Mode 14 Channel 2 Ready Enable Transmit Mode 14 Channel 2 Active Enable Transmit Mode 14 Channel 3 Ready Enable Transmit Mode 14 Channel 3 Active Enable Transmit Mode 14 Channel 4 Ready Enable Transmit Mode 14 Channel 4 Active Enable Reserved Transmit Mode 14 Active Splitter 1 Enable Transmit Mode 14 Channel 1 to Channel 2 Active Splitter Enable Transmit Mode 14 Channel 3 to Channel 4 Active Splitter Enable Transmit Mode 15 Channel 1 Ready Enable Transmit Mode 15 Channel 1 Active Enable Transmit Mode 15 Channel 2 Ready Enable Transmit Mode 15 Channel 2 Active Enable Transmit Mode 15 Channel 3 Ready Enable Transmit Mode 15 Channel 3 Active Enable Transmit Mode 15 Channel 4 Ready Enable Transmit Mode 15 Channel 4 Active Enable Reserved Transmit Mode 15 Active Splitter 1 Enable Transmit Mode 15 Channel 1 to Channel 2 Active Splitter Enable Transmit Mode 15 Channel 3 to Channel 4 Active Splitter Enable Reserved Multiplier Mode 0 RF Amplifier Enable Multiplier Mode 0 Low Band Ready Enable Multiplier Mode 0 Low Band Active Enable Multiplier Mode 0 Mid Band Ready Enable Multiplier Mode 0 Mid Band Active Enable Multiplier Mode 0 High Band Ready Enable Multiplier Mode 0 High Band Active Enable Multiplier Mode 0 BPF Select Multiplier Mode 0 Notch Filter Select Reserved Multiplier Mode 0 Attenuator Setting Reserved Multiplier Mode 1 RF Amplifier Enable Multiplier Mode 1 Low Band Ready Enable Multiplier Mode 1 Low Band Active Enable Multiplier Mode 1 Mid Band Ready Enable Multiplier Mode 1 Mid Band Active Enable Multiplier Mode 1 High Band Ready Enable Multiplier Mode 1 High Band Active Enable Rev. 0 | Page 34 of 39 Reset 0x1 0x0 0x1 0x1 0x1 0x1 0x1 0x1 0x0 0x1 0x1 Access R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W 0x1 R/W 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W 0x0 R/W 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1 0x0 0x1 0x0 0x1 0x0 R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R/W R/W R/W R/W R/W R/W Data Sheet Addr Name 0x073 MULT_PASS_MODE_1 0x074 MULT_EN_MODE_2 0x075 MULT_PASS_MODE_2 0x076 MULT_EN_MODE_3 0x077 MULT_PASS_MODE_3 0x078 MULT_EN_MODE_4 0x079 MULT_PASS_MODE_4 0x07A MULT_EN_MODE_5 ADAR2001 Bits 7 6 5 [4:0] 7 6 5 4 3 2 1 0 7 6 5 [4:0] 7 6 5 4 3 2 1 0 7 6 5 [4:0] 7 6 5 4 3 2 1 0 7 6 5 [4:0] 7 6 5 4 3 2 1 0 Bit Name BPF_MD1 PA_NOTCH_MD1 RESERVED ATTN_MD1 RESERVED RFAMP_EN_MD2 MULT_LOW_RDY_MD2 MULT_LOW_ACT_MD2 MULT_MID_RDY_MD2 MULT_MID_ACT_MD2 MULT_HIGH_RDY_MD2 MULT_HIGH_ACT_MD2 BPF_MD2 PA_NOTCH_MD2 RESERVED ATTN_MD2 RESERVED RFAMP_EN_MD3 MULT_LOW_RDY_MD3 MULT_LOW_ACT_MD3 MULT_MID_RDY_MD3 MULT_MID_ACT_MD3 MULT_HIGH_RDY_MD3 MULT_HIGH_ACT_MD3 BPF_MD3 PA_NOTCH_MD3 RESERVED ATTN_MD3 RESERVED RFAMP_EN_MD4 MULT_LOW_RDY_MD4 MULT_LOW_ACT_MD4 MULT_MID_RDY_MD4 MULT_MID_ACT_MD4 MULT_HIGH_RDY_MD4 MULT_HIGH_ACT_MD4 BPF_MD4 PA_NOTCH_MD4 RESERVED ATTN_MD4 RESERVED RFAMP_EN_MD5 MULT_LOW_RDY_MD5 MULT_LOW_ACT_MD5 MULT_MID_RDY_MD5 MULT_MID_ACT_MD5 MULT_HIGH_RDY_MD5 MULT_HIGH_ACT_MD5 Description Multiplier Mode 1 BPF Select Multiplier Mode 1 Notch Filter Select Reserved Multiplier Mode 1 Attenuator Setting Reserved Multiplier Mode 2 RF Amplifier Enable Multiplier Mode 2 Low Band Ready Enable Multiplier Mode 2 Low Band Active Enable Multiplier Mode 2 Mid Band Ready Enable Multiplier Mode 2 Mid Band Active Enable Multiplier Mode 2 High Band Ready Enable Multiplier Mode 2 High Band Active Enable Multiplier Mode 2 BPF Select Multiplier Mode 2 Notch Filter Select Reserved Multiplier Mode 2 Attenuator Setting Reserved Multiplier Mode 3 RF Amplifier Enable Multiplier Mode 3 Low Band Ready Enable Multiplier Mode 3 Low Band Active Enable Multiplier Mode 3 Mid Band Ready Enable Multiplier Mode 3 Mid Band Active Enable Multiplier Mode 3 High Band Ready Enable Multiplier Mode 3 High Band Active Enable Multiplier Mode 3 BPF Select Multiplier Mode 3 Notch Filter Select Reserved Multiplier Mode 3 Attenuator Setting Reserved Multiplier Mode 4 RF Amplifier Enable Multiplier Mode 4 Low Band Ready Enable Multiplier Mode 4 Low Band Active Enable Multiplier Mode 4 Mid Band Ready Enable Multiplier Mode 4 Mid Band Active Enable Multiplier Mode 4 High Band Ready Enable Multiplier Mode 4 High Band Active Enable Multiplier Mode 4 BPF Select Multiplier Mode 4 Notch Filter Select Reserved Multiplier Mode 4 Attenuator Setting Reserved Multiplier Mode 5 RF Amplifier Enable Multiplier Mode 5 Low Band Ready Enable Multiplier Mode 5 Low Band Active Enable Multiplier Mode 5 Mid Band Ready Enable Multiplier Mode 5 Mid Band Active Enable Multiplier Mode 5 High Band Ready Enable Multiplier Mode 5 High Band Active Enable Rev. 0 | Page 35 of 39 Reset 0x0 0x0 0x0 0x13 0x0 0x1 0x1 0x1 0x1 0x0 0x1 0x0 0x1 0x1 0x0 0x13 0x0 0x1 0x1 0x1 0x1 0x0 0x1 0x0 0x0 0x1 0x0 0x7 0x0 0x1 0x1 0x1 0x1 0x0 0x1 0x0 0x0 0x1 0x0 0x13 0x0 0x1 0x1 0x0 0x1 0x1 0x1 0x0 Access R/W R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R/W R/W R/W R/W R/W R/W ADAR2001 Addr Name 0x07B MULT_PASS_MODE_5 0x07C MULT_EN_MODE_6 0x07D MULT_PASS_MODE_6 0x07E MULT_EN_MODE_7 0x07F MULT_PASS_MODE_7 0x080 MULT_EN_MODE_8 0x081 MULT_PASS_MODE_8 0x082 MULT_EN_MODE_9 Data Sheet Bits 7 6 5 [4:0] 7 6 5 4 3 2 1 0 7 6 5 [4:0] 7 6 5 4 3 2 1 0 7 6 5 [4:0] 7 6 5 4 3 2 1 0 7 6 5 [4:0] 7 6 5 4 3 2 1 0 Bit Name BPF_MD5 PA_NOTCH_MD5 RESERVED ATTN_MD5 RESERVED RFAMP_EN_MD6 MULT_LOW_RDY_MD6 MULT_LOW_ACT_MD6 MULT_MID_RDY_MD6 MULT_MID_ACT_MD6 MULT_HIGH_RDY_MD6 MULT_HIGH_ACT_MD6 BPF_MD6 PA_NOTCH_MD6 RESERVED ATTN_MD6 RESERVED RFAMP_EN_MD7 MULT_LOW_RDY_MD7 MULT_LOW_ACT_MD7 MULT_MID_RDY_MD7 MULT_MID_ACT_MD7 MULT_HIGH_RDY_MD7 MULT_HIGH_ACT_MD7 BPF_MD7 PA_NOTCH_MD7 RESERVED ATTN_MD7 RESERVED RFAMP_EN_MD8 MULT_LOW_RDY_MD8 MULT_LOW_ACT_MD8 MULT_MID_RDY_MD8 MULT_MID_ACT_MD8 MULT_HIGH_RDY_MD8 MULT_HIGH_ACT_MD8 BPF_MD8 PA_NOTCH_MD8 RESERVED ATTN_MD8 RESERVED RFAMP_EN_MD9 MULT_LOW_RDY_MD9 MULT_LOW_ACT_MD9 MULT_MID_RDY_MD9 MULT_MID_ACT_MD9 MULT_HIGH_RDY_MD9 MULT_HIGH_ACT_MD9 Description Multiplier Mode 5 BPF Select Multiplier Mode 5 Notch Filter Select Reserved Multiplier Mode 5 Attenuator Setting Reserved Multiplier Mode 6 RF Amplifier Enable Multiplier Mode 6 Low Band Ready Enable Multiplier Mode 6 Low Band Active Enable Multiplier Mode 6 Mid Band Ready Enable Multiplier Mode 6 Mid Band Active Enable Multiplier Mode 6 High Band Ready Enable Multiplier Mode 6 High Band Active Enable Multiplier Mode 6 BPF Select Multiplier Mode 6 Notch Filter Select Reserved Multiplier Mode 6 Attenuator Setting Reserved Multiplier Mode 7 RF Amplifier Enable Multiplier Mode 7 Low Band Ready Enable Multiplier Mode 7 Low Band Active Enable Multiplier Mode 7 Mid Band Ready Enable Multiplier Mode 7 Mid Band Active Enable Multiplier Mode 7 High Band Ready Enable Multiplier Mode 7 High Band Active Enable Multiplier Mode 7 BPF Select Multiplier Mode 7 Notch Filter Select Reserved Multiplier Mode 7 Attenuator Setting Reserved Multiplier Mode 8 RF Amplifier Enable Multiplier Mode 8 Low Band Ready Enable Multiplier Mode 8 Low Band Active Enable Multiplier Mode 8 Mid Band Ready Enable Multiplier Mode 8 Mid Band Active Enable Multiplier Mode 8 High Band Ready Enable Multiplier Mode 8 High Band Active Enable Multiplier Mode 8 BPF Select Multiplier Mode 8 Notch Filter Select Reserved Multiplier Mode 8 Attenuator Setting Reserved Multiplier Mode 9 RF Amplifier Enable Multiplier Mode 9 Low Band Ready Enable Multiplier Mode 9 Low Band Active Enable Multiplier Mode 9 Mid Band Ready Enable Multiplier Mode 9 Mid Band Active Enable Multiplier Mode 9 High Band Ready Enable Multiplier Mode 9 High Band Active Enable Rev. 0 | Page 36 of 39 Reset 0x1 0x0 0x0 0x1F 0x0 0x1 0x1 0x0 0x1 0x1 0x1 0x0 0x0 0x0 0x0 0x1F 0x0 0x1 0x1 0x0 0x1 0x0 0x1 0x1 0x1 0x0 0x0 0x1F 0x0 0x1 0x1 0x0 0x1 0x0 0x1 0x1 0x0 0x0 0x0 0x1F 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R/W R/W R/W R/W R/W R/W Data Sheet Addr Name 0x083 MULT_PASS_MODE_9 0x084 MULT_EN_MODE_10 0x085 MULT_PASS_MODE_10 0x086 MULT_EN_MODE_11 0x087 MULT_PASS_MODE_11 0x088 MULT_EN_MODE_12 0x089 MULT_PASS_MODE_12 0x08A MULT_EN_MODE_13 ADAR2001 Bits 7 6 5 [4:0] 7 6 5 4 3 2 1 0 7 6 5 [4:0] 7 6 5 4 3 2 1 0 7 6 5 [4:0] 7 6 5 4 3 2 1 0 7 6 5 [4:0] 7 6 5 4 3 2 1 0 Bit Name BPF_MD9 PA_NOTCH_MD9 RESERVED ATTN_MD9 RESERVED RFAMP_EN_MD10 MULT_LOW_RDY_MD10 MULT_LOW_ACT_MD10 MULT_MID_RDY_MD10 MULT_MID_ACT_MD10 MULT_HIGH_RDY_MD10 MULT_HIGH_ACT_MD10 BPF_MD10 PA_NOTCH_MD10 RESERVED ATTN_MD10 RESERVED RFAMP_EN_MD11 MULT_LOW_RDY_MD11 MULT_LOW_ACT_MD11 MULT_MID_RDY_MD11 MULT_MID_ACT_MD11 MULT_HIGH_RDY_MD11 MULT_HIGH_ACT_MD11 BPF_MD11 PA_NOTCH_MD11 RESERVED ATTN_MD11 RESERVED RFAMP_EN_MD12 MULT_LOW_RDY_MD12 MULT_LOW_ACT_MD12 MULT_MID_RDY_MD12 MULT_MID_ACT_MD12 MULT_HIGH_RDY_MD12 MULT_HIGH_ACT_MD12 BPF_MD12 PA_NOTCH_MD12 RESERVED ATTN_MD12 RESERVED RFAMP_EN_MD13 MULT_LOW_RDY_MD13 MULT_LOW_ACT_MD13 MULT_MID_RDY_MD13 MULT_MID_ACT_MD13 MULT_HIGH_RDY_MD13 MULT_HIGH_ACT_MD13 Description Multiplier Mode 9 BPF Select Multiplier Mode 9 Notch Filter Select Reserved Multiplier Mode 9 Attenuator Setting Reserved Multiplier Mode 10 RF Amplifier Enable Multiplier Mode 10 Low Band Ready Enable Multiplier Mode 10 Low Band Active Enable Multiplier Mode 10 Mid Band Ready Enable Multiplier Mode 10 Mid Band Active Enable Multiplier Mode 10 High Band Ready Enable Multiplier Mode 10 High Band Active Enable Multiplier Mode 10 BPF Select Multiplier Mode 10 Notch Filter Select Reserved Multiplier Mode 10 Attenuator Setting Reserved Multiplier Mode 11 RF Amplifier Enable Multiplier Mode 11 Low Band Ready Enable Multiplier Mode 11 Low Band Active Enable Multiplier Mode 11 Mid Band Ready Enable Multiplier Mode 11 Mid Band Active Enable Multiplier Mode 11 High Band Ready Enable Multiplier Mode 11 High Band Active Enable Multiplier Mode 11 BPF Select Multiplier Mode 11 Notch Filter Select Reserved Multiplier Mode 11 Attenuator Setting Reserved Multiplier Mode 12 RF Amplifier Enable Multiplier Mode 12 Low Band Ready Enable Multiplier Mode 12 Low Band Active Enable Multiplier Mode 12 Mid Band Ready Enable Multiplier Mode 12 Mid Band Active Enable Multiplier Mode 12 High Band Ready Enable Multiplier Mode 12 High Band Active Enable Multiplier Mode 12 BPF Select Multiplier Mode 12 Notch Filter Select Reserved Multiplier Mode 12 Attenuator Setting Reserved Multiplier Mode 13 RF Amplifier Enable Multiplier Mode 13 Low Band Ready Enable Multiplier Mode 13 Low Band Active Enable Multiplier Mode 13 Mid Band Ready Enable Multiplier Mode 13 Mid Band Active Enable Multiplier Mode 13 High Band Ready Enable Multiplier Mode 13 High Band Active Enable Rev. 0 | Page 37 of 39 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R/W R/W R/W R/W R/W R/W ADAR2001 Addr Name 0x08B MULT_PASS_MODE_13 0x08C MULT_EN_MODE_14 0x08D MULT_PASS_MODE_14 0x08E MULT_EN_MODE_15 0x08F MULT_PASS_MODE_15 0x100 SCAN_MODE_EN Data Sheet Bits 7 6 5 [4:0] 7 6 5 4 3 2 1 0 7 6 5 [4:0] 7 6 5 4 3 2 1 0 7 6 5 [4:0] [7:1] 0 Bit Name BPF_MD13 PA_NOTCH_MD13 RESERVED ATTN_MD13 RESERVED RFAMP_EN_MD14 MULT_LOW_RDY_MD14 MULT_LOW_ACT_MD14 MULT_MID_RDY_MD14 MULT_MID_ACT_MD14 MULT_HIGH_RDY_MD14 MULT_HIGH_ACT_MD14 BPF_MD14 PA_NOTCH_MD14 RESERVED ATTN_MD14 RESERVED RFAMP_EN_MD15 MULT_LOW_RDY_MD15 MULT_LOW_ACT_MD15 MULT_MID_RDY_MD15 MULT_MID_ACT_MD15 MULT_HIGH_RDY_MD15 MULT_HIGH_ACT_MD15 BPF_MD15 PA_NOTCH_MD15 RESERVED ATTN_MD15 RESERVED SCAN_MODE_EN Description Multiplier Mode 13 BPF Select Multiplier Mode 13 Notch Filter Select Reserved Multiplier Mode 13 Attenuator Setting Reserved Multiplier Mode 14 RF Amplifier Enable Multiplier Mode 14 Low Band Ready Enable Multiplier Mode 14 Low Band Active Enable Multiplier Mode 14 Mid Band Ready Enable Multiplier Mode 14 Mid Band Active Enable Multiplier Mode 14 High Band Ready Enable Multiplier Mode 14 High Band Active Enable Multiplier Mode 14 BPF Select Multiplier Mode 14 Notch Filter Select Reserved Multiplier Mode 14 Attenuator Setting Reserved Multiplier Mode 15 RF Amplifier Enable Multiplier Mode 15 Low Band Ready Enable Multiplier Mode 15 Low Band Active Enable Multiplier Mode 15 Mid Band Ready Enable Multiplier Mode 15 Mid Band Active Enable Multiplier Mode 15 High Band Ready Enable Multiplier Mode 15 High Band Active Enable Multiplier Mode 15 BPF Select Multiplier Mode 15 Notch Filter Select Reserved Multiplier Mode 15 Attenuator Setting Reserved Scan Mode Enable Rev. 0 | Page 38 of 39 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W Data Sheet ADAR2001 OUTLINE DIMENSIONS PIN 1 INDICATOR AREA 6.10 6.00 5.90 0.30 0.25 SQ 0.20 0.42 BSC PIN 1 INDICATOR 31 40 1 4.40 BSC SQ 4.00 REF SQ 2.08 BSC SQ 0.50 BSC 21 11 BOTTOM VIEW TOP VIEW 0.20 REF SIDE VIEW 0.25 0.45 REF 0.26 0.23 0.20 SEATING PLANE 0.175 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 02-14-2020-B PKG-006405 0.78 0.68 0.58 Figure 35. 40-Terminal Land Grid Array [LGA] 6 mm x 6 mm Body and 0.75 mm Package Height (CC-40-7) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADAR2001ACCZ ADAR2001ACCZ-R7 ADAR2001-EVALZ 1 Temperature Range -40C to +85C -40C to +85C Package Description 40-Terminal Land Grid Array [LGA], Tray 40-Terminal Land Grid Array [LGA], 7" Tape and Reel Evaluation Board Z = RoHS Compliant part. (c)2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D20538-8/20(0) Rev. 0 | Page 39 of 39 Package Option CC-40-7 CC-40-7