Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1
Rev. F
12/15/2011
IS61LV25616AL
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
FEATURES
• High-speed access time:
— 10, 12 ns
• CMOS low power operation
• Low stand-by power:
— Less than 5 mA (typ.) CMOS stand-by
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Lead-free available
256K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
DESCRIPTION
The ISSI IS61LV25616AL is a high-speed, 4,194,304-bit
static RAM organized as 262,144 words by 16 bits. It is
fabricated using ISSI's high-performance CMOS technol-
ogy. This highly reliable process coupled with innovative
circuit design techniques, yields high-performance and low
power consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be re-
duced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61LV25616AL is packaged in the JEDEC standard
44-pin 400-mil SOJ, 44-pin TSOP Type II, 44-pin LQFP
and 48-pin Mini BGA (8mm x 10mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A17
CE
OE
WE
256K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
DECEMBER 2011
2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
12/15/2011
IS61LV25616AL
TRUTH TABLE
I/O PIN
Mode WE CE OE LB UB I/O0-I/O7 I/O8-I/O15 VDD Current
Not Selected X H X X X High-Z High-Z Isb1, Isb2
Output Disabled H L H X X High-Z High-Z Icc
X L X H H High-Z High-Z
Read H L L L H Dout High-Z Icc
H L L H L High-Z Dout
H L L L L Dout Dout
Write L L X L H DIn High-Z Icc
L L X H L High-Z DIn
L L X L L DIn DIn
PIN DESCRIPTIONS
A0-A17 Address Inputs
I/O0-I/O15 Data Inputs/Outputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)
NC No Connection
VDD Power
GND Ground
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A0
A1
A2
A3
A4
CE
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A5
A6
A7
A8
A9
A17
A16
A15
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
PIN CONFIGURATIONS
44-Pin TSOP (Type II) and SOJ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 3
Rev. F
12/15/2011
IS61LV25616AL
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34
CE
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
TOP VIEW
WE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A17
A16
A15
A14
A13
A12
A11
A10
OE
UB
LB
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB OE A0 A1 A2 N/C
I/O
8
UB A3 A4 CE I/O
0
I/O
9
I/O
10
A5 A6 I/O
1
I/O
2
GND I/O
11
A17 A7 I/O
3
V
DD
V
DD
I/O
12
NC A16 I/O
4
GND
I/O
14
I/O
13
A14 A15 I/O
5
I/O
6
I/O
15
NC A12 A13 WE I/O
7
NC A8 A9 A10 A11 NC
48-Pin mini BGA
PIN CONFIGURATIONS
44-Pin LQFP
PIN DESCRIPTIONS
A0-A17 Address Inputs
I/O0-I/O15 Data Inputs/Outputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)
NC No Connection
VDD Power
GND Ground
4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
12/15/2011
IS61LV25616AL
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VoH Output HIGH Voltage VDD = Min., IoH = –4.0 mA 2.4 — V
VoL Output LOW Voltage VDD = Min., IoL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2.0 VDD + 0.3 V
VIL Input LOW Voltage(1) –0.3 0.8 V
ILI Input Leakage GND ≤ VIn ≤ VDD Com. –2 2 µA
Ind. –5 5
ILo Output Leakage GND ≤ Vout ≤ VDD Com. –2 2 µA
Outputs Disabled Ind. –5 5
Notes:
1. VIL (min.) = –2.0V for pulse width less than 10 ns.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
Vterm Terminal Voltage with Respect to GND –0.5 to VDD+0.5 V
tstg Storage Temperature –65 to +150 °C
Pt Power Dissipation 1.0 W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
OPERATING RANGE
VDD
Range Ambient Temperature 10ns 12ns
Commercial 0°C to +70°C 3.3V +10%, -5% 3.3V + 10%
Industrial –40°C to +85°C 3.3V +10%, -5% 3.3V + 10%
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 5
Rev. F
12/15/2011
IS61LV25616AL
CAPACITANCE(1)
Symbol Parameter Conditions Max. Unit
cIn Input Capacitance VIn = 0V 6 pF
cout Input/Output Capacitance Vout = 0V 8 pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-10 -12
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
Icc VDD Dynamic Operating VDD = Max., Com. — 100 — 90 mA
Supply Current Iout = 0 mA, f = fmaX Ind. — 110 — 100
Isb TTL Standby Current VDD = Max., Com. — 50 — 45 mA
(TTL Inputs) VIn = VIH or VIL Ind. — 55 — 50
CE ≥ VIH, f = fmaX.
Isb1 TTL Standby Current VDD = Max., Com. — 20 — 20 mA
(TTL Inputs) VIn = VIH or VIL Ind. — 25 — 25
CE ≥ VIH, f = 0
Isb2 CMOS Standby VDD = Max., Com. — 15 — 15 mA
Current (CMOS Inputs) CE ≥ VDD – 0.2V, Ind. — 20 — 20
VIn ≥ VDD – 0.2V, or
VIn ≤ 0.2V, f = 0
Note:
1. At f = fmaX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Shaded area product in development
6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
12/15/2011
IS61LV25616AL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-10 -12
Symbol Parameter Min. Max. Min. Max. Unit
trc Read Cycle Time 10 — 12 — ns
taa Address Access Time — 10 — 12 ns
toHa Output Hold Time 2 — 2 — ns
tace CE Access Time — 10 — 12 ns
tDoe OE Access Time — 4 — 5 ns
tHzoe(2) OE to High-Z Output — 4 — 5 ns
tLzoe(2) OE to Low-Z Output 0 — 0 — ns
tHzce(2 CE to High-Z Output 0 4 0 6 ns
tLzce(2) CE to Low-Z Output 3 — 3 — ns
tba LB, UB Access Time — 4 — 5 ns
tHzb(2) LB, UB to High-Z Output 0 3 0 4 ns
tLzb(2) LB, UB to Low-Z Output 0 — 0 — ns
tPu Power Up Time 0 — 0 — ns
tPD Power Down Time — 10 — 12 ns
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing and Reference Level 1.5V
Output Load See Figures 1 and 2
AC TEST LOADS
Figure 1 Figure 2
319 Ω
5 pF
Including
jig and
scope
353 Ω
OUTPUT
3.3V
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of
0V to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.
319 Ω
30 pF
Including
jig and
scope
353 Ω
OUTPUT
3.3V
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 7
Rev. F
12/15/2011
IS61LV25616AL
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
DOUT
ADDRESS
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z DATA VALID
UB_CEDR2.eps
t
HZB
ADDRESS
OE
CE
LB, UB
D
OUT
t
HZCE
t
BA
t
LZB
t
RC
t
PD
I
SB
I
CC
50%
V
DD
Supply
Current
50%
t
PU
READ CYCLE NO. 2(1,3)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
12/15/2011
IS61LV25616AL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-10 -12
Symbol Parameter Min. Max. Min. Max. Unit
twc Write Cycle Time 10 — 12 — ns
tsce CE to Write End 8 — 8 — ns
taw Address Setup Time to Write End 8 — 8 — ns
tHa Address Hold from Write End 0 — 0 — ns
tsa Address Setup Time 0 — 0 — ns
tPwb LB, UB Valid to End of Write 8 — 8 — ns
tPwe1 WE Pulse Width 8 — 8 — ns
tPwe2 WE Pulse Width (OE = LOW) 10 — 12 — ns
tsD Data Setup to Write End 6 — 6 — ns
tHD Data Hold from Write End 0 — 0 — ns
tHzwe(2) WE LOW to High-Z Output — 5 — 6 ns
tLzwe(2) WE HIGH to Low-Z Output 2 — 2 — ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V
to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB and WE LOW. All signals must be in valid
states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing
are referenced to the rising or falling edge of the signal that terminates the write.
tRC
tOHA
tAA
tDOE
tLZOE
tACE
tLZCE
tHZOE
HIGH-Z DATA VALID
UB_CEDR2.eps
tHZB
ADDRESS
OE
CE
LB, UB
D
OUT
tHZCE
tBA
tLZB tRC
tPD
ISB
ICC
50%
V
DD
Supply
Current
50%
tPU
READ CYCLE NO. 2(1,3)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 9
Rev. F
12/15/2011
IS61LV25616AL
WRITE CYCLE NO. 2
(WE Controlled. OE is HIGH During Write Cycle) (1,2)
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
DOUT
DIN
OE
DATA
IN
VALID
t
LZWE
t
SD
UB_CEWR2.eps
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least
one of the LB and UB inputs being in the LOW state.
2. WRITE = (CE) [ (LB) = (UB) ] (WE).
AC WAVEFORMS
WRITE CYCLE NO. 1
(CE Controlled, OE is HIGH or LOW) (1 )
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN DATA
IN
VALID
t
LZWE
t
SD
UB_CEWR1.eps
10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
12/15/2011
IS61LV25616AL
AC WAVEFORMS
WRITE CYCLE NO. 3
(WE Controlled. OE is LOW During Write Cycle) (1)
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN
OE
DATAIN VALID
t
LZWE
t
SD
UB_CEWR3.eps
WRITE CYCLE NO. 4
(LB, UB Controlled, Back-to-Back Write) (1,3)
DATA UNDEFINED
t
WC
ADDRESS 1 ADDRESS 2
t
WC
HIGH-Z
t
PBW
WORD 1
LOW
WORD 2
UB_CEWR4.eps
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN
OE
DATAIN
VALID
t
LZWE
t
SD
t
PBW
DATAIN
VALID
t
SD
t
HD
t
SA
t
HA
t
HA
Notes:
1. The internal Write time is defined by the overlap of CE = Low, UB and/or LB = Low, and WE = LOW. All signals must be in
valid states to initiate a Write, but any can be deasserted to terminate the Write. The t sa, t Ha, t sD, and t HD timing is referenced
to the rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 11
Rev. F
12/15/2011
IS61LV25616AL
DATA RETENTION WAVEFORM (CE Controlled)
DATA RETENTION SWITCHING CHARACTERISTICS (LL)
Symbol Parameter Test Condition Options Min. Typ.(1) Max. Unit
VDr VDD for Data Retention See Data Retention Waveform 2.0 — 3.6 V
IDr Data Retention Current VDD = 2.0V, CE ≥ VDD – 0.2V Com. — 5 10 mA
Ind. — — 15
tsDr Data Retention Setup Time See Data Retention Waveform 0 — — ns
trDr Recovery Time See Data Retention Waveform trc — — ns
Note 1: Typical values are measured at VDD = 3.0V, Ta = 25
o
c and not 100% tested.
V
DD
CE ≥ VDD
- 0.2V
tSDR tRDR
VDR
CE
GND
1.65V
1.4V
Data Retention Mode
12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
12/15/2011
IS61LV25616AL
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
10 IS61LV25616AL-10T TSOP (Type II)
IS61LV25616AL-10TL TSOP (Type II), Lead-free
IS61LV25616AL-10K 400-mil SOJ
12 IS61LV25616AL-12T TSOP (Type II)
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
10 IS61LV25616AL-10TI TSOP (Type II)
IS61LV25616AL-10TLI TSOP (Type II), Lead-free
IS61LV25616AL-10KI 400-mil SOJ
IS61LV25616AL-10KLI 400-mil SOJ, Lead-free
IS61LV25616AL-10LQI LQFP
IS61LV25616AL-10LQLI LQFP, Lead-free
IS61LV25616AL-10BI Mini BGA
(8mm x 10mm)
IS61LV25616AL-10BLI Mini BGA
(8mm x 10mm), Lead-free
12 IS61LV25616AL-12TI TSOP (Type II)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 13
Rev. F
12/15/2011
IS61LV25616AL
14 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
12/15/2011
IS61LV25616AL
3. Dimension b2 does not include dambar protrusion/intrusion.
4. Formed leads shall be planar with respect to one another within 0.1mm
2. Dimension D and E1 do not include mold protrusion .
at the seating plane after final test.
1. Controlling dimension : mm
NOTE :
SEATING PLANE
5. Reference document : JEDEC SPEC MS-027.
12/21/2007
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 15
Rev. F
12/15/2011
IS61LV25616AL
2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION.
1. CONTROLLING DIMENSION : MM
NOTE :
Θ
Θ
06/04/2008
Package Outline
16 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
12/15/2011
IS61LV25616AL
1. Controlling dimension : mm
2. Reference document : JEDEC MO-207
NOTE :
08/12/2008
Package Outline
