RT7736LGE - Richtek USA Inc. - Datasheet.Directory

RT7736

DS7736-04 September 2014 www.richtek.com

General Description

The RT7736 series is a high performance enhanced PWM

flyback controller with proprietary SmartJitterTM technology.

The innovative SmartJitterTM technology not only reduces

EMI emissions of SMPS when the system enters burst

switching green mode, but also eliminates output jittering

ripple.

The RT7736 is a current mode PWM controller including

built-in slope compensation, internal Leading Edge

Blanking (LEB) and cycle-by-cycle current limit. It provides

excellent green power performance, especially under light

load and no load conditions. It allows for simpler design

and reduces external component count.

This controller integrates comprehensive safety protection

functions for robust designs including input Under-Voltage

Lockout (UVLO), Over-Voltage Protection (OVP), Over-

Load Protection (OLP), Secondary Rectifier Short

Protection (SRSP), CS pin open protection and cycle-by-

cycle current limit.

The RT7736 is a cost-effective and compact solution for

NB adaptor applications. It is available in the SOT-23-6

package.

SmartJitterTM PWM Flyback Controller

Applications

Switching AC/DC Adaptor

DVD Open Frame Power Supply

Set-Top Box (STB)

ATX Standby Power

TV/Monitor Standby Power

PC Peripherals

NB Adaptor

Features



Proprietary SmartJitterTM Technology



 Reducing EMI Emissions of SMPS



 Output Jittering Ripple Elimination



No Load Input Power Under 100mW (RT7736G/R/L/E)



Accurate Over Load Protection



UVLO 9V/14.5V



PRO Pin for External Arbitrary OVP/OTP



IC ON/OFF Control (RT7736G/R/L)



BNO Pin for Brown-In/Out (RT7736B/D/F)



Soft Driving for EMI Noise Reduction



Driver Capability : 300mA/−−

−−

−300mA



High Noise Immunity



RoHS Compliant and Halogen Free

Simplified Application Circuit

AC Mains

(90V to 265V)

PRO

COMP

GND

GATE

RT7736

VDD

Vo+

Vo-

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Ordering Information

RT7736

Package Type

E : SOT-23-6

Lead Plating System

G : Green (Halogen Free and Pb Free)

RT7736 Version (Refer to Version Table)

Marking Information

Note :

Richtek products are :

 RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

 Suitable for use in SnPb or Pb-free soldering processes.

RT7736 Version Table

Version RT7736G RT7736R RT7736L RT7736E RT7736B RT7736D RT7736F

Frequency 65kHz 65kHz 65kHz 65kHz 65kHz 65kHz 65kHz

OLP Delay

Time 56ms 56ms 56ms 56ms 56ms 88ms 64ms

Internal OVP Auto

Recovery

Auto

Recovery Latch Latch Auto

Recovery

Auto

Recovery

Auto

Recovery

OLP & SRSP Auto

Recovery

Auto

Recovery

Auto

Recovery

Auto

Recovery

Auto

Recovery

Auto

Recovery

Auto

Recovery

PRO Pin High Latch Auto

Recovery Latch Latch X X X

PRO Pin Low Auto

Recovery

Auto

Recovery

Auto

Recovery Latch X X X

External OTP

by PRO

Auto

Recovery

Auto

Recovery Latch Latch X X X

External

Brown-In/Out X X X X ○ ○ ○

IFF= : Product Code

DNN : Date Code

RT7736GGE

IFF=DNN

RT7736FGE

0P= : Product Code

DNN : Date Code

0P=DNN

09= : Product Code

DNN : Date Code

RT7736LGE

09=DNN 0F=DNN

RT7736EGE

0F= : Product Code

DNN : Date Code

RT7736DGE

0N= : Product Code

DNN : Date Code

0N=DNN

00= : Product Code

DNN : Date Code

RT7736BGE

00=DNN

RT7736RGE

2B= : Product Code

DNN : Date Code

2B=DNN

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Pin Configurations

(TOP VIEW)

RT7736B/D/F

SOT-23-6

GND COMP BNO

GATE VDD CS

RT7736G/R/L/E

SOT-23-6

GND COMP PRO

GATE VDD CS

Pi n No. Pi n Name Pi n Fu nction

1 GND Ground of the Controller.

2 COMP Feedback Voltage Input. Connect an opto-coupler to close the control loop and

achieve output voltage regulation.

3 PRO Protection Input for OVP, OTP or ON/OFF Control. (RT7736G/R/L/E)

BNO Brown-In/Out Detection Input for RT7736B/D/F Only.

4 CS Current Sense Input. The current sense resistor between this pin and GND is used for

current limit setting.

5 VDD Supply Voltage Input. The controller will be enabled when VDD exceeds VTH_ON

(14.5V typ.) and disabled when VDD decreases lower than VTH_OFF (9V typ.)

6 GATE Gate Driver Output for External Power MOSFET.

Functional Pin Description

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Function Block Diagram

Figure 1. Block Diagram for RT7736G, RT7736R, RT7736L and RT7736E

Counter

VDD

GATE

LEB

Slope

Ramp

Burst Switching Green

Mode

COMP

VBURH

VBURL

PWM

Comparator

Shutdown

Logic

COMP Open

Sensing

Dmax

Oscillator

POR

27V

Bias &

Bandgap

UVLO

OVP

9V/14.5V

Constant

Power

Soft Driver

Secondary Rectifier

Short Protection

COMP

PRO

GND

VDD

5.2V

OTP

OLP

VTH_OTP

VTH_H

VTH_L

IBias

TOLP : 56ms

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Figure 2. Block Diagram for RT7736B, RT7736D and RT7736F

Counter

VDD

GATE

LEB

Slope

Ramp

Burst Switching Green

Mode

COMP

VBURH

VBURL

PWM

Comparator

Shutdown

Logic

COMP Open

Sensing

Dmax

Oscillator

POR

27V

Bias &

Bandgap

UVLO

OVP

9V/14.5V

Constant

Power Soft Driver

Secondary Rectifier

Short Protection

COMP

BNO

GND

VDD

5.2V

OTP

VBIN_TH/VBNO_TH

OLP

TOLP : 56ms (RT7736B)

TOLP : 88ms (RT7736D)

TOLP : 64ms (RT7736F)

Operation

Burst Switching Green Mode

The burst mode is designed to reduce switching loss.

When the output load reduces, and the VCOMP drops and

reaches VBURL, the controller will cease switching. After

output voltage decreases and the VCOMP goes up to VBURH,

the switching will be resumed.

VDD Holdup Mode

Under very light load conditions, the VDD may drop down

to turn-off threshold voltage. To avoid this situation when

VDD drops to a set threshold, VDD_ET, the hysteresis

comparator will bypass PWM and burst mode loop, and

then force switching at a very low level to supply energy

to VDD pin. VDD holdup mode is also improved to hold up

VDD by less switching cycles. This mode is very useful

for reducing start-up resistor loss and keeping start-up

time within specification. This function makes bias winding

design and transient design easier.

Oscillator

The oscillator runs at 65kHz and features frequency

jittering function. Its jittering depth is Δf with about TJIT

envelope frequency at fOSC. It also generates slope

compensation saw-tooth, maximum duty cycle pulse and

overload protection slope.

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Leading Edge Blanking (LEB)

To prevent unexpectedly gate switching interruption from

the initial spike on CS pin, the LEB delay is designed to

block this spike at the beginning of gate switching.

Gate Driver

A totem pole gate driver is designed to meet both EMI

and efficiency requirements in low power applications. An

internal pull-low circuit is activated after pretty low VDD to

prevent external MOSFET from accidentally turning on

during UVLO.

PRO Pin (RT7736G/R/L/E)

The RT7736G/R/L/E features a PRO pin, and it can be

applied for external arbitrary OVP or OTP applications

(RT7736G/R/L/E), and also can be applied for IC ON/OFF

control (RT7736G/R/L).

BNO Pin (RT7736B/D/F)

The RT7736B/D/F features a BNO pin, and it can be applied

for external arbitrary brown-in/out. The BNO pin is

connected to the AC line input or bulk capacitor with a

resistive divider to achieve brown-in/out protection.

Cycle-by-Cycle Current Limit

This is a basic but very useful function and it can be

implemented easily in current mode controller.

Over-Load Protection

In over load conditions, long time current limit will lead to

system thermal stress problem. To further protect the

system, the RT7736 is designed with a proprietary

prolonged turn-off period during hiccup. The power loss

and temperature during OLP will be averaged to an

acceptable level over the ON/OFF cycle.

CS Pin Open Protection

When the CS pin is opened, the controller will shut down

after a few cycles.

Over-Voltage Protection

Output voltage can be roughly sensed by the VDD pin. If

the sensed voltage reaches VOVP threshold, the controller

will shut down after deglitch delay. The controller will

resume once the fault is removed.

Feedback Open and Opto-Coupler Short

If the output voltage feedback loop is open or the opto-

coupler is shorted, the OVP/OLP function will be triggered

depending on which one occurs first.

Secondary Rectifier Short Protection

The current spike during secondary rectifier short test is

extremely high because of the saturated main transformer.

Meanwhile, the transformer acts like a leakage inductance.

During high line, the current in power MOSFET is

sometimes too high for OLP delay time. To offer better

and easier protection design, the RT7736 will shut down

after a few of cycles before fuse is impacted.

Output Short Protection

The RT7736 implements output short protection by

detecting GATE width with delay time. It could minimize

the power loss and temperature during output short,

especially at high line input voltage.

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Electrical Characteristics

Recommended Operating Conditions (Note 4)

Supply Input Voltage, VDD ----------------------------------------------------------------------------------------------- 12V to 25V

Junction Temperature Range --------------------------------------------------------------------------------------------- −40°C to 125°C

Ambient Temperature Range --------------------------------------------------------------------------------------------- −40°C to 85°C

Absolute Maximum Ratings (Note 1)

Supply Input Voltage, VDD to GND ------------------------------------------------------------------------------------- −0.3V to 30V

GATE to GND --------------------------------------------------------------------------------------------------------------- −0.3V to 16.5V

PRO, BNO, COMP, CS to GND ---------------------------------------------------------------------------------------- −0.3V to 6.5V

Power Dissipation, PD @ TA = 25°C

SOT-23-6 --------------------------------------------------------------------------------------------------------------------- 0.38W

Package Thermal Resistance (Note 2)

SOT-23-6, θJA ---------------------------------------------------------------------------------------------------------------- 260.7°C/W

Junction Temperature ------------------------------------------------------------------------------------------------------ 150°C

Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------------- 260°C

Storage Temperature Range --------------------------------------------------------------------------------------------- −65°C to 150°C

ESD Susceptibility (Note 3)

HBM (Human Body Model) ----------------------------------------------------------------------------------------------- 3kV

MM (Machine Model) ------------------------------------------------------------------------------------------------------ 250V

(VDD = 15V, TA = 25°C, unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Unit

VDD Se cti on

VDD Over-Voltage Protection Level VOVP 26 27 28 V

VDD Zener Clamp VZ 29 -- -- V

On Threshold Voltage VTH_ON 13.5 14.5 15.5 V

Off Threshold Voltage VTH_OFF 8.5 9 9.5 V

Disable Brown-in Detection to

Avoid Start-up Failed VDD_BNI 11 12 13 V

VDD Holdup Mode Entry Point VDD_ET VCOMP < 1.3V 9.5 10 10.5 V

VDD Holdup Mode Ending Point VDD_ED VCOMP < 1.3V 10 10.5 11 V

Latch-off Clamping Voltage VDD_LH -- 5.5 -- V

Threshold Voltage for Latch-off

Release VLH_OFF -- 5 -- V

Start-up Current IDD_ST VDD < VTH_ON  0.1V,

TA = 40°C to 80°C -- 5 10 A

Latch-off Operating Current IDD_LH TA = 40°C to 80°C 2 -- 10 A

Operating Supply Current IDD_OP1 VDD = 15V, GATE pin open,

VCOMP = 2.5V -- 1 -- mA

Operating Supply Current IDD_OP2 VDD = 15V, GATE pin open,

VCOMP = 1.7V -- 0.9 -- mA

IDD Sinking Current of Waiting

Brown-in After Start-up IDD_BNI For RT7736B/D/F ; VDD = 15V,

GATE and COMP pin open 100 150 200 A

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Parameter Symbol Test Conditions Min Typ Max Unit

IDD Sinking Current IDD_ARP During entering auto recovery

protection 300 400 500 A

Oscillator Secti on

Normal PWM Frequency fOSC VCOMP > VBS_ET 60 65 70 kHz

Maximum Duty Cycle DCYMAX 70 75 80 %

Minimum Burst Switching Green

Mode Frequency fBS_MIN 18.5 22 25.5 kHz

PWM Frequency Jittering Range f -- ±6 -- %

PWM Frequency Jittering Period TJIT -- 16 -- ms

Frequency Variation Versus VDD

Deviation fDV V

DD = 9V to 23V -- -- 2 %

Frequency Variation Versus

Temperature Deviation fDT T

A = 30°C to105°C -- -- 5 %

COMP Input Secti on

Open Loop Voltage VCOMP_OP COMP pin open 5 5.2 5.4 V

Short Circuit Current of COMP IZERO V

COMP = 0V 0.24 0.29 0.34 mA

Delay Time of COMP Open-loop

Protection TOLP f

OSC = 65kHz

RT7736G/R/L/E/B -- 56 --

ms RT7736D -- 88 --

RT7736F -- 64 --

Burst Switching Green Mode Entry

Voltage VBS_ET 2.3 2.35 2.4 V

Burst Switching Green Mode

Ending Voltage VBS_ED 2.1 2.15 2.2 V

Delay Time of Output Short

Protection TD_OSP fOSC = 65kHz,

RT7736G/R/L/E/B -- 8 -- ms

Current Sense S ect ion

Maximum Current Limit VCS_MAX (Note 5) 1.05 1.1 1.15 V

Leading Edge Blanking Time TLEB (Note 5) 150 250 350 ns

Internal Propagation Delay Time TPD (Note 5) -- 100 -- ns

Minimum On-Time TON_MIN 250 350 450 ns

Detection On-Time of Output Short

Protection TON_OSP fOSC = 65kHz,

RT7736G/R/L/E/B (Note 6) 0.7 1.1 1.5 s

GATE Sectio n

Rising Time TR V

DD = 15V, CL = 1nF -- 60 -- ns

Falling Time TF V

DD = 15V, CL = 1nF -- 40 -- ns

Gate Output Clamping Voltage VCLAMP V

DD = 23V -- 13.5 -- V

PRO Interf ace S ect ion (RT 7 736G/R/L/E)

Pull High Threshold VTH_H 1.75 1.8 1.85 V

Pull Low OTP Threshold VTH_OTP 0.47 0.5 0.53 V

Pull Low Threshold VTH_L 0.25 0.3 0.35 V

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Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in

the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may

affect device reliability.

Note 2. θJA is measured in natural convection (still air) at TA = 25°C with the component mounted on a low effective thermal

conductivity test board of JEDEC 51-3 thermal measurement standard.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

Note 5. Leading edge blanking time and internal propagation delay time are guaranteed by design.

Note 6. Guaranteed by design.

Parameter Symbol Test Conditions Min Typ Max Unit

Open Loop Voltage VPRO_OP PRO pin open -- 1.3 -- V

Internal Bias Current IBIAS 90 100 110 A

Pull High Sinking Current ISIN -- -- 500 A

Delay Time of OTP by PRO TD_OT P f

OSC = 65kHz -- 56 -- ms

BNO Interface Section (RT7736B/D/F)

Brown-In Threshold VBNI_TH 0.96 1 1.04 V

Brown-Out Threshold VBNO_TH 0.81 0.85 0.89 V

RT7736B -- 56 --

RT7736D -- 88 -- De-bounce Time of VBNO_TH T

D_BNO f

OSC = 65kHz

RT7736F -- 24 --

Over-Temperature Protection (OTP) Section

Over-Temperature Protection TOTP On Chip OTP (Note 6) -- 140 -- C

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Typical Application Circuit

Figure 3. Application Circuit For RT7736G, RT7736R, RT7736L and RT7736E

Figure 4. Application Circuit for RT7736B, RT7736D and RT7736F

AC Mains

(90V to 265V)

BNO

COMP

GND

GATE

RT7736B/D/F

VDD

Vo+

Vo-

(Optional)

AC Mains

(90V to 265V)

PRO

COMP

GND

GATE

RT7736G /R/L/E

VDD

Vo+

Vo-

(Optional)

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Typical Operating Characteristics

IDD_ST vs. VDD

03691215

VDD (V)

IDD_ST (µA)

IDD_ST vs. Temperature

-50-250 255075100125

Temperature (°C)

IDD_ST (µA)

VTH_ON vs. Temperature

13.0

13.5

14.0

14.5

15.0

15.5

16.0

-50-25 0 25 50 75100125

Temperature (°C)

VTH_ON

(V)

VOVP vs. Temperature

26.00

26.25

26.50

26.75

27.00

27.25

27.50

27.75

28.00

-50-25 0 25 50 75100125

Temperature (°C)

VOVP (V)

VTH_OFF vs. Temperature

8.0

8.5

9.0

9.5

10.0

-50 -25 0 25 50 75 100 125

Temperature (°C)

VTH_OFF (V)

VDD_LH & VLH_OFF vs. Temperature

4.8

5.0

5.2

5.4

5.6

5.8

-50-25 0 25 50 75100125

Temperature (°C)

VDD_LH & VLH_OFF (V)

VDD_LH

VLH_OFF

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fOSC vs. VDD

63.0

63.5

64.0

64.5

65.0

65.5

66.0

66.5

67.0

10 13 16 19 22 25

VDD (V)

fOSC (kHz)

fOSC vs. Temperature

-50-25 0 25 50 75100125

Temperature (°C)

fOSC (kHz)

IDD_LH vs. Temperature

-50-25 0 25 50 75100125

Temperature (°C)

IDD_LH (µA)

IDD_BNI vs. Temperature

120

140

160

180

200

-50-25 0 25 50 75100125

Temperature (°C)

IDD_BNI

(µA)

IDD_ARP vs. Temperature

325

350

375

400

425

-50-25 0 25 50 75100125

Temperature (°C)

IDD_ARP (µA)

fBS_MIN vs. Temperature

-50 -25 0 25 50 75 100 125

Temperature (°C)

fBS_MIN

(kHz)

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IDD_OP1 vs. Temperature

650

700

750

800

850

-50-25 0 25 50 75100125

Temperature (°C)

IDD_OP1 (µA)

IDD_OP2 vs. Temperature

650

700

750

800

850

-50-25 0 25 50 75100125

Temperature (°C)

IDD_OP2 (µA)

VCOMP_OP vs. Temperature

5.1

5.2

5.3

5.4

-50-25 0 25 50 75100125

Temperature (°C)

VCOMP_OP (V)

IZERO vs. Temperature

270

280

290

300

310

-50-25 0 25 50 75100125

Temperature (°C)

IZERO (µA)

TOLP vs. Temperature

-50-25 0 25 50 75100125

Temperature (°C)

TOLP (ms)

RT7736G/R/L/E/B

TOLP vs. Temperature

-50 -25 0 25 50 75 100 125

Temperature (°C)

TOLP (ms)

RT7736D

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tR vs. Temperature

-50-25 0 25 50 75100125

Temperature (°C)

tR (ns)

tF vs. Temperature

-50-25 0 25 50 75100125

Temperature (°C)

tF (ns)

IBIAS vs. Temperature

102

106

-50-25 0 25 50 75100125

Temperature (°C)

IBIAS (µA)

VCLAMP vs. Te mperature

11.5

12.5

13.5

14.5

15.5

-50-25 0 25 50 75100125

Temperature (°C)

VCLAMP (V)

TOLP vs. Temperature

-50 -25 0 25 50 75 100 125

Temperature (°C)

TOLP (ms)

RT7736F

TD_BNO vs. Te m perature

-50 -25 0 25 50 75 100 125

Temperature (°C)

TD_BNO (ms)

RT7736F

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VBNI_TH vs. Temperature

0.90

0.95

1.00

1.05

1.10

-50-250 255075100125

Temperature (°C)

VBNI_TH

(V)

VBNO_TH vs. Temperature

0.75

0.80

0.85

0.90

0.95

-50-25 0 25 50 75100125

Temperature (°C)

VBNO_TH

(V)

VTH_H vs. Temperature

1.70

1.75

1.80

1.85

1.90

-50-25 0 25 50 75100125

Temperature (°C)

VTH_H

(V)

VTH_OTP vs. Temperature

0.40

0.45

0.50

0.55

0.60

-50 -25 0 25 50 75 100 125

Temperature (°C)

VTH_OTP

(V)

VTH_L vs. Temperature

0.20

0.25

0.30

0.35

0.40

-50-25 0 25 50 75100125

Temperature (°C)

VTH_L (V)

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Figure 5. Frequency Jittering Range During Green Mode : General PWM Controller vs. RT7736

Application Information

SmartJitterTM T echnology

The RT7736 series applies RICHTEK proprietary

SmartJitterTM technology.

In order to reduce switching loss for lower power

consumption during light load or no load, general PWM

controllers have green mode function according to the

feedback voltage VCOMP.

The output power equation is : 2

1COMP

o_DCM COMP p s COMP

P(V) = L f(V)







  





Where LP is the magnetizing inductance of the transformer,

RCS is the current sense resistor, VCOMP is the feedback

voltage of the COMP pin. fS is the switching frequency of

the power switch, η is the conversion efficiency, and x1 is

a constant coefficient.

Output power is a function of feedback voltage VCOMP.

Frequency jittering technique is typically used to improve

EMI problems in general PWM controllers, and the

frequency jittering period is based on PWM switching

frequency.

When the system enters green mode, a output power

relationship is formed between the feedback voltage VCOMP

and the PWM switching frequency, and a new stable

equilibrium point is eventually reached after back-and-forth

adjustments. It limits the frequency jittering range is

limited and the improving EMI function is poor, as shown

in Figure 5.

The innovative SmartJitterTM technology not only helps

reduce EMI emissions of SMPS when the system entering

green mode, but also eliminates output jittering ripple.

Accurate Over-Load Protection and Tight Current

Limit Tolerance

Generally, the saw current limit is applied to low cost

flyback controllers because of simple design. The RT7736

series applies with RICHTEK proprietary technology

through well foundry control, design and test/trim mode

in final test. Therefore, the current limit tolerance is tight

enough to make design and mass production easier, and

it provides accurate over-load protection.

Jittering Freq.

fs mean = 64.85kHz

Jittering Range = 6.3%

Normal

Operating

General PWM

Controller



Jittering Freq.

fs mean = 42.99kHz

Jittering Range = 3.3%

General PWM

Controller

Green Mode



Jittering Freq.

fs mean = 42.58kHz

Jittering Range = 7.7%

RT7736

Green Mode



Jittering Freq.

fs mean = 64.61kHz

Jittering Range = 6.0%

RT7736

Normal

Operating



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Start-Up Circuit

To minimize power loss, it's recommended to connect

the start-up circuit to the bleeding resistors. It's power

saving and also could reset latch mode protection quickly.

Figure 6 shows IDD_Avg vs. RBleeding curve. Users can apply

this curve to design the adequate bleeding resistors.

In order to prolong turn-off period and minimize the power

loss and thermal rising during hiccup, the controller is

designed to have smaller sinking current during entering

auto-recovery protection, IDD_ARP. Therefore, the start-up

current at maximum AC line input voltage must be smaller

than IDD_ARP (IDD_ARP(min) = 300μA). Otherwise, when the

controller enters auto-recovery protection, the VDD

capacitor won't be dropped down to VTH_OFF by IC's sinking

current and then restart. The controller behaves like latch

protection or triggers the SCR of VDD.

The RT7736 implemented brown-in detected function

(RT7736B/D/F) as described in “BNO Pin Application”

section. In order to avoid start-up failure, the controller is

designed to have smaller sinking current after start-up

and then wait for brown-in, IDD_BNI. Therefore, the start-up

current at brown-in voltage of AC line input must be smaller

than IDD_BNI (IDD_BN (min) = 100μA). Otherwise, the VDD

voltage will rise up continuously and then trigger the SCR

of VDD.

VDD Discharge Time in Auto Recovery Mode

Figure 7 shows the VDD and VGATE waveforms during an

auto recovery protection (e.g., OLP). In this mode, the

start-up resistors, VDD sinking current and VDD decoupling

capacitor will affect the restart time. The discharge time

tD_Discharge of VDD voltage can be calculated by using the

following equation :

VDD DD_DIS TH_OFF

D_Discharge DD_ARP ST

C(V V )

tII





Where the CVDD is the VDD decoupling capacitor, the

VDD_DIS is the initial VDD voltage after entering the auto

recovery mode, the VTH_OFF (9V typ.) is the falling UVLO

voltage threshold of the controller, the IDD_ARP (300μA typ.)

is the sinking current of the VDD pin in the auto recovery

mode, and IST is the start-up current of the power system.

Please note that the start-up current at high input voltage

must be smaller than the IDD_ARP. Otherwise, the VDD

voltage can't reach the VTH_OFF to activate the next start-

up process after an auto recovery protection. Therefore,

the system behavior resembles the behavior of latch mode.

Figure 6. IDD_Avg vs. RBleeding Curve

IDD_Avg vs. RBleeding Cu rve

0.6 1.0 1.4 1.8 2.2 2.6 3.0

RBleeding (M )

IDD_Avg (μA)

VDD

IDD_Avg

RBleeding

90Vac

85Vac

80Vac

IDD_Avg vs. RBleeding Cu rve

100

125

150

175

200

225

250

0.6 1.0 1.4 1.8 2.2 2.6 3.0

RBleeding (M )

IDD_Avg (μA)

VDD

IDD_Avg

RBleeding

265Vac

230Vac

Figure 7. Auto Recovery Mode (e.g., OLP)

VTH_ON

VDD_DIS

VTH_OFF

OLP Delay

Time tD_Discharge

VGATE

VDD

DS7736-04 September 2014

RT7736

www.richtek.com

VDD Holdup Mode

The VDD holdup mode is only designed to prevent VDD

from decreasing to the turn-off threshold voltage under

light load or load transient. Relative to burst mode, the

VDD holdup mode brings higher switching. Hence, it is

highly recommended that the system should avoid

operating at this mode during light load or no load

conditions, normally.

BNO Pin Application (RT7736B/D/F)

The RT7736 features a BNO pin (RT7736B/D/F), and it

can be applied for external arbitrary brown-in/out. The BNO

pin is connected to the AC line input or bulk capacitor by

resistive divider to achieve brown-in/out function.

Comparing the BNO pin connected to the AC line input

with bulk capacitor, the advantage of the BNO pin

connected to the AC line input is having brown-in/out

function regardless of output loads.

Figure 8 shows the application circuit of the BNO pin

connected to AC line input with resistive divider. The

resistive divider (RA and RB) can be calculated by the

following equations :

Brown-in_AC_rms BNI_TH B

Brown-out_AC_rms BNO_TH B

V2V1



 







 





The sum of resistor values (RA and RB) should be smaller

than 1.5MΩ because parasitic capacitors of bridge of diode

may make hysteresis of brown-in/out function invalid.

Figure 8. Brown-in/out Detected from AC Line Input

The Brown-in/out detected from bulk capacitor is shown

in Figure 9, and the resistive divider (RC and RD) can be

calculated by the following equations :

Bulk_Brown-in BNI_TH D

Bulk_Brown-out BNO_TH D

VV1

















RBRT7736

BNO

GND

AC Mains

(90V to 265V)

CBNO

The BNO pin application from bulk capacitor can use higher

resistance on the divider for power saving, but this method

can't have brown-in/out function at light load because bulk

capacitor still has energy stored when AC line input is

turned off. The recommended bypass capacitor CBNO is

smaller than 1nF.

To avoid start-up failure, the RT7736 implements brown-

in detected function, as shown in Figure 10. When VDD is

greater than VTH_ON, the controller starts to operate and

waits for brown-in signal. If brown-in signal is not enabled

before VDD falls below VDD_BNI, the controller will be shut

down and then re-start. If the brown-in signal VBNO is higher

than VBNI_TH, the controller will be enabled.

RT7736

BNO

GND

AC Mains

(90V to 265V)

CBNO

CBulk

Figure 9. Brown-in/out Detected from Bulk Capacitor

DS7736-04 September 2014

RT7736

www.richtek.com

Figure 11. PRO Pin Diagram

Figure 10. RT7736 Brown-in Detected Function

PRO Pin Application (RT7736G/R/L/E)

The RT7736 provides a PRO pin for external arbitrary OVP/

OTP or IC ON/OFF applications as shown in Figure 12 to

Figure 15.

In Figure 11, when the voltage of the PRO pin is between

VTH_OTP and VTH_H, the controller is enabled for normal

operation. If the voltage of the PRO pin is lower than

VTH_OTP and higher than VTH_L after delay time TD_OTP, the

controller will be shut down and cease switching. If the

voltage of the PRO pin is higher than VTH_H or lower than

VTH_L, the controller will be shut down and cease switching

after deglitch delay.

When the voltage of the PRO pin is pulled above VTH_H,

the supply current of the PRO pin must be higher than

500μA and be limited below 5mA. When IC enters latch

mode, VDD will be clamped at latched voltage VDD_LH, and

it will be released until VDD falls to latched reset voltage

VLH_OFF.

When the PRO pin is open, it is set at 1.3V internally.

Leave the PRO pin open if it is not used. If designer needs

to apply a bypass capacitor on the PRO pin, the

capacitance should be less than 1nF. The internal bias

current of the PRO pin is 100μA (typ.).

PRO

VTH_OTP

VTH_H

VTH_L

Deglitch

56ms

Delay Time

Auto

Recovery

Latch

Auto

Recovery

Latch

Auto

Recovery

Latch

VTH_H

VTH_L

Auto Recovery/Latch

Normal Operating

Auto Recovery/Latch

VTH_OTP

VPRO

1.6mA (typ.)

VAC

Operating

Current

VTH_ON

VTH_OFF

VDD_BNI

VDD

GATE

Brown-in

(VBNO > VBNI_TH)

VBNO > VBNI_TH

IDD

VBNO < VBNI_TH

Brown-in

Detection

IDD_ST

IDD_BNI

IDD_ARP

Entering Auto Recovery Protection (Ex : OLP)

VBNO < VBNI_TH

DS7736-04 September 2014

RT7736

www.richtek.com

PRO

NTC

(Option)

Figure 12. External OTP

Figure 13. OVP for VDD

Figure 14. OVP for VDD

Figure 15. OVP for Output Voltage

Vo+

(Option)

PRO

(Option)

VDD

(Option)

PRO

Output Short Protection (RT7736G/R/L/E/B)

The RT7736 implements output short protection (RT7736G/

R/L/E/B) by detecting GATE width with delay time TD_OSP.

It can minimize the power loss during output short,

especially at high line input voltage.

VDD PRO

(Option)

Figure 16. Resistors on Gate Pin

AC Mains

(90V to 265V)

GND

GATE

RT7736

RED

CGD

RID

Soft

Driver

It is recommend to add the external discharge-

resistor to avoid MOSFET false triggering.

The built-in internal discharge-resistor prevents

the MOSFET from any uncertain conditions.

Because it is hard to distinguish the difference between

output short and big capacitance load, circuit design must

be careful to make sure GATE width is larger than TON_OSP

(tON > tON_OSP(MAX)) after delay time TD_OSP during start-

up.

Resistors on GA TE Pin

In Figure 16, RG is applied to alleviate ringing spike of

gate drive loop in typical application circuits. The value of

RG must be considered carefully with respect to EMI and

efficiency for the system.

The built-in internal discharge resistor RID in parallel with

GATE pin prevents the MOSFET from any uncertain

conditions. If the connection between the GATE pin and

the Gate of the MOSFET is disconnected, the MOSFET

will be false triggered by the residual energy through the

Gate-to-Drain parasitic capacitor CGD of the MOSFET and

the system will be damaged. Therefore, it’s highly

recommended to add an external discharge-resistor RED

connected between the Gate of MOSFET and GND

terminals. The energy through the CGD is discharged by

the external discharge-resistor to avoid MOSFET false

triggering.

DS7736-04 September 2014

RT7736

www.richtek.com

Over-Temperature Protection (OTP)

The RT7736 provides an internal OTP function to protect

the controller itself from suffering thermal stress and

permanent damage. It's not suggested to use the function

as precise control of over temperature. Once the junction

temperature is higher than the OTP threshold, the

controller will shut down until the temperature cools down.

Meanwhile, if VDD reaches turn-off threshold voltage

VTH_OFF, the controller will hiccup till the over-temperature

condition is removed.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

PD(MAX) = (TJ(MAX) − TA) / θJA

where TJ(MAX) is the maximum junction temperature, TA is

the ambient temperature, and θJA is the junction to ambient

thermal resistance.

For recommended operating condition specifications, the

maximum junction temperature is 125°C. The junction to

ambient thermal resistance, θJA, is layout dependent. For

Feedback Resistor

In order to enhance light load efficiency, the loss of the

feedback resistor in parallel with photo-coupler is reduced,

as shown in Figure 17. Due to small feedback resistor

current, shunt regulator selection (e.g. TL-431) and

minimum regulation current design must be considered

carefully to make sure it's able to regulate under low

cathode current.

Figure 17. Feedback Resistor

Vo+

Vo-

Feedback

Resistor

Negative Voltage Spike on Each Pin

Negative voltage (< −0.3V) to the controller pins will cause

substrate injection and lead to controller damage or circuit

false triggering. For example, the negative spike voltage

at the CS pin may come from improper PCB layout or

inductive current sense resistor. Therefore, it is highly

recommended to add an R-C filter to avoid the CS pin

damage, as shown in Figure 18. Proper PCB layout and

component selection should be considered during circuit

design.

Figure 18. R-C Filter on CS Pin

AC Mains

(90V to 265V)

PRO

COMP

GND

GATE

RT7736

VDD

R-C Filter

DS7736-04 September 2014

RT7736

www.richtek.com

Figure 19. Derating Curve of Maximum Power

Dissipation

Layout Consideration

A proper PCB layout can abate unknown noise interference

and EMI issue in the switching power supply. Please refer

to the guidelines when you want to design PCB layout for

switching power supply :

The current path (1) through bulk capacitor, transformer,

MOSFET, RCS returns to bulk capacitor is a high

frequency current loop. It must be as short as possible

to decrease noise coupling and keep away from other

low voltage traces, such as IC control circuit paths,

especially.

The path (2) of the RCD snubber circuit is also a high

switching loop. Keep it as small as possible.

Separate the ground traces of bulk capacitor(a),

MOSFET(b), auxiliary winding(c) and IC control circuit(d)

for reducing noise, output ripple and EMI issue. Connect

these ground traces together at bulk capacitor ground

(a). The areas of these ground traces should be large

enough.

Place the bypass capacitor as close to the controller as

possible.

In order to reduce reflected trace inductance and EMI,

minimize the area of the loop connecting the secondary

winding, output diode and output filter capacitor. In

additional, apply sufficient copper area at the anode and

cathode terminal of the diode for heatsinking.

Figure 20. PCB Layout Guide

SOT-23-6 package, the thermal resistance, θJA, is

260.7°C/W on a standard JEDEC 51-3 single-layer thermal

test board. The maximum power dissipation at TA = 25°C

can be calculated by the following formula :

PD(MAX) = (125°C − 25°C) / (260.7°C/W) = 0.38W for

SOT-23-6 package

The maximum power dissipation depends on the operating

ambient temperature for fixed TJ(MAX) and thermal

resistance, θJA. The derating curve in Figure 19 allows

the designer to see the effect of rising ambient temperature

on the maximum power dissipation.

0.0

0.1

0.2

0.3

0.4

0.5

0 25 50 75 100 125

Ambient Temperature (°C)

Maximum Power Dissipation (W) 1

Single-Layer PCB

Auxiliary

Ground (c)

Ground (d)

Trace Trace Trace

MOSFET

Ground (b)

CBULK Ground (a)

(a)

(d) (b)

(1)

(c)

(2)

AC Mains

(90V to 265V)

PRO

COMP

GND

GATE

RT7736

VDD

CBULK

DS7736-04 September 2014

RT7736

www.richtek.com

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should

obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot

assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be

accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

Outline Dimension

AA1

Dime nsions In Millimeters Dimensions In In che s

Symbol Min Max Min Max

A 0.889 1.295 0.031 0.051

A1 0.000 0.152 0.000 0.006

B 1.397 1.803 0.055 0.071

b 0.250 0.560 0.010 0.022

C 2.591 2.997 0.102 0.118

D 2.692 3.099 0.106 0.122

e 0.838 1.041 0.033 0.041

H 0.080 0.254 0.003 0.010

L 0.300 0.610 0.012 0.024

SOT-23-6 Surface Mount Package