DS1501/DS1511 Ra = B SEMICONDUCTOR Y2KC Watchdog Real Time Clock www.dalsemi.com FE ATURES BCD coded century, year, month, date, day, hours, minutes, and seconds with automatic leap year compensation valid up to the year 2100 Programmable watchdog timer and RTC alarm Century register; Y2K-compliant RTC +3.3 or +5-volt operation Precision power-on reset Power control circuitry supports system power-on from date/day/time alarm or key closure/modem detect signal 256 bytes user NV SRAM Burst mode for reading/writing successive addresses in NV SRAM Auxiliary battery input Accuracy of DS1511 is better than + 1 min./month @ 25C Day of week/date alarm register Crystal select bit allows RTC to operate with 6 pF or 12.5 pF crystal Battery voltage level indicator flags Available as chip (DS1501) or standalone module with embedded battery and crystal (DS1511) Optional industrial temperature range -40C to +85C (DS1501 only) ORDERING INFORMATION DS1501XXX blank commercial temp range N industrial temp range Blank 28-pin DIP E 28-pin TSOP Ss 28-pin SOIC Y 5 Volt operation WwW 3.3 Volt operation DS1S11X Dip Module Y 5 Volt operation Ww 3.3 Volt operation PIN ASSIGNMENT 7 PWR(71 28 [7 Voc x12 27 [7 WE _X2(713 26 [7] Vaaux RST 4 25 (7) Vast IRQ (75 241-4 KS A416 23 (7 sQw A3(7]7 22 [3 OE A218 21 [= GND Atc9 20 CE AO] 10 19 [5 DQ7 DQO (J 11 18 F Da6 DQ1 [7] 12 17 [Das DQ2 (77 13 16 [= Da4 GND (J 14 15 [J Das 3 als ERE BA Ao RRRE < 5 = ale < fs) a FI > Halx x 1 of 23 MM 2644130 00394038 28-Pin DIP, 28-Pin SOIC 28-Pin ENCAPSULATED PACKAGE (720-mil FLUSH) DONOOhWD = = =o amo hoh 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28-Pin TSOP 141 111699DS1501/DS1511 DESCRIPTION The DS1501/DS1511 is a full function, year 2000-compliant (Y2KC), real-time clock/calendar (RTC) with a RTC alarm, watchdog timer, power-on reset, battery monitors, and 256 bytes nonvolatile static RAM in a monolithic chip. User access to all registers within the DS1501 is accomplished with a bytewide interface as shown in Figure 1. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for day of month and leap year are made automatically. SIGNAL DESCRIPTION Vee - Supply Voltage A0-A4 - Address Inputs DQ0-DQ8 - Data VO CE - Chip Enable Input OE - Output Enable Input WE - Write Enable Input IRQ - Interrupt Output (Open Drain) PWR - Power-On Output (Open Drain) RST - Reset Output (Open Drain) KS - Kickstart Input SQW - Square Wave Output VBAT - Backup Battery Supply VBAUX - Auxiliary Battery Supply XI - Oscillator Input x2 - Oscillator Output GND - Ground NC - No Connection The RTC registers are double-buffered into an internal and external set. The user has direct access to the external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow the user to access static data. Assuming the internal oscillator is turned on, the internal set of registers are continuously updated; this occurs regardless of external registers settings to guarantee that accurate RTC information is always maintained. The DS1501/DS1511 contains its own power-fail circuitry which automatically deselects the device when the Vcc supply enters an out-of-tolerance condition. This feature provides a high degree of data security during unpredictable system operation brought on by low Vcc levels. The DS1501/DS1511 has interrupt (IRQ), wakeup (PWR ), and reset (RST ) outputs which can be used to control CPU activity. The IRQ interrupt output can be used to generate an external interrupt under several conditions. A Wakeup interrupt will be generated when the RTC register values match user programmed alarm values and Time of day/date Power Enable bit (TPE) (Bit 4), in register OFh is set to a logic 1. A Kickstart interrupt will be generated when a high to low transition occurs on the Kickstart (KS) pin while the Kickstart Interrupt Enable bit (KIE) (Bit 2), in register OFh is set to a logic 1. The interrupt is always available while the device is powered from the system supply. The PWR output can be programmed to occur when in the battery backed state to serve as a system wake-up. The PWR pin is under software control, so that when a task is complete, the system power can then be shut down. Either the IRQ or RST outputs can also be used as a CPU watchdog timer, CPU activity is monitored and an 2 of 23 M@@ 264130 0054035 815 aDS$1501/D81511 interrupt or reset output will be activated if the correct activity is not detected within programmed limits. The DS1501/DS1511 power-on reset can be used to detect a system power down or failure and hold the CPU in a safe reset state until normal power returns and stabilizes; the RST output is used for this function. The DS1501/DS1511 also incorporates a 32.768kHz output for sustaining power management activities. DS1501/DS1511 BLOCK DIAGRAM Figure 1 > IRQ [ ao SOW xt > CLOCK AND CONTROL CLOCK ALARM, AND e | Gays We WATCHDOG i REGISTERS 4 [ Gt Al) A4 pi <== D007 vec - Tita = Vaat POWER CONTROL < CE VBAUX e| WRITE PROTECTION, AND POWER-ON . WE GND > RESET KS > OE = AST o PWR DS1501/DS1511 OPERATING MODES Table 1 Vec ce | oe | WE Dor A0-A4 MODE POWER Vin xX x HIGH-Z xX DESELECT STANDBY Vit xX Vit Dn Aw WRITE ACTIVE IN TOLERANCE Vil Val Vm} Dor lo An READ ACTIVE Vir | Vor | Var | HIGH-Z Aw READ ACTIVE Vaat <Vcc < TOLERANCE 4 x x HIGH-Z ,4 DESELECT CMOS STANDBY Vcc < Veatr 4 >< xX HIGH-Z xX DATA RETENTION | BATTERY CURRENT DATA READ MODE The DS1501/DS1511 is in the read mode whenever CE (chip enable) is low and WE (write enable) is high. The device architecture allows ripple-through access to any valid address location. Valid data will be available at the DQ pins within ta, (address access) after the last address input is stable, providing that CE and OE access times are satisfied. If CE or OE access times are not met, valid data will be available at the latter of chip enable access (tcga) or at output enable access time (toga). The state of the data input/output pins (DQ) is controlled by CE and OE. If the outputs are activated before taa, the data lines are driven to an intermediate state until ta,. If the address inputs are changed while CE and OE remain valid, output data will remain valid for output data hold time (toy) but will then go indeterminate until the next address access. (See Table 1.) 3 of 23 BS 2614130 OO34040 S37 meDS1501/DS1511 DATA WRITE MODE The DS1501/DS1511 is in the write mode whenever WE and CE are in their active state. The start of a write is referenced to the latter occurring transition of WE or CE. The addresses must be held valid throughout the cycle. CE and WE must return inactive for a minimum of twe prior to the initiation of a subsequent read or write cycle. Data in must be valid tps (data setup) prior to the end of the write and remain valid for tpy (data hold) afterward. Ina typical application, the OE signal will be high during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to a high to low transition on WE, the data bus can become active with read data defined by the address inputs. A low transition on WE will then disable the outputs twez (WE data off time) after WE goes active. (See Table 1.) DATA RETENTION MODE The 5-volt device is fully accessible and data can be written and read only when Vcc is greater than Vpr. However, when Vcc falls below the power-fail point Vpg (point at which write protection occurs) the internal clock registers and SRAM are blocked from any access. While in the data retention mode, all inputs are dont cares and outputs go to a high-Z state. When Vcc falls below the greater of Vgar and Veaux; device power is switched from the Vcc pin to either the Vaar or Vaaux pin. RTC operation and SRAM data are maintained from the battery until Vcc is returned to nominal levels. The 3.3-volt device is fully accessible and data can be written and read only when Vcc is greater than Vpr. However, when Vcc falls below Vpp, access to the device is inhibited. If Vpr is less than Var and Veaux, the device power is switched from Vcc to the greater of Vgar and Vgaux when Vcc drops below Vpr. If Vpr is greater than Vpat and Vraux, the device power is switched from Vcc to the larger of Vgar and Vpaux when Vcc drops below the larger of Vaar and Vgaux. RTC operation and SRAM data are maintained from the battery until Vcc is returned to nominal levels. (See Table 1.) All control, data, and address signals must be powered down when Vcc is absent. AUXILIARY BATTERY The Vgaux input is provided to supply power from an auxiliary battery for the DS1501/DS1511 kickstart and SQW output features in the absence of Vcc. This power source must be available in order to use these auxiliary features when Vcc is not applied to the device. This auxiliary battery may be used as the primary backup power source for maintaining the clock/calendar and extended user RAM. This occurs if the Vgar pin is at a lower voltage than Vgaux. If the DS1501/DSI511 is to be backed-up using a single battery with the auxiliary features enabled, then Veaux Should be used and Vgar should be grounded. If Vgaux is not to be used, it should be grounded. POWER-ON RESET A temperature compensated comparator circuit monitors the level of Vcc. When Vcc falls to the write protection voltage, the RST signal (open drain) is pulled low. When Vcc returns to nominal levels, the RST signal continues to be pulled low for a period of 40 ms to 200 ms. The power-on reset function is independent of the RST oscillator and thus is operational whether or not the oscillator is enabled. 4 of 23 MH 2614130 OO3s404u1L 473 meDS1501/DS1511 DS1501/DS1511 REGISTER MAP Table 2 DATA BCD Address | _B7 B6 | BS | B4 B3. | B2 | Bil | Bo FUNCTION RANGE 00H 0 10 SECONDS SECONDS SECONDS 00-59 01H 0 10 MINUTES MINUTES MINUTES 00-59 02H 0 0 10 HOURS HOUR HOURS 00-23 03H 0 0 0 | oO o | DAY DAY 1-7 04H 0 0 10 DATE DATE DATE 00-31 OSH | Eosc | 32x | BB32 | 10MO MONTH MONTH 01-12 06H 10 YEAR YEAR YEAR 00-99 07H 0 0 | 10CENTURY CENTURY CENTURY 00-39 ALARM 08H AM1 10 SECONDS SECONDS SECONDS 00-59 ALARM 09H AM2 10 MINUTES MINUTES MINUTES 00-59 OAH | AM3 0 10 HOURS HOUR ALARMHOURS | 00-23 oBpH | AM4 | Dy/DT| 10DAY/DATE DAY/DATE AARNE a : I. OCH 0.1 SECOND 0.01 SECOND WATCHDOG 00-99 0DH 10 SECOND SECOND WATCHDOG 00-99 QOEH | VRTI | VRT2 [| PRS | PAB | TDF | KSF [| WDF | IROF CONTROL A OFH TE cs BME | TPE TIE KIE_| WDE | WDS CONTROL B 10H EXTENDED RAM ADDRESS RAM ADDR LSB | 00-FF 11H RESERVED 12H RESERVED 13H EXTENDED RAM DATA RAM DATA 00-FF 14H RESERVED 15H RESERVED 16H RESERVED 17H RESERVED 18H RESERVED 19H RESERVED 1AH RESERVED 1BH RESERVED 1CH RESERVED 1DH RESERVED 1EH RESERVED 1FH RESERVED TABLE 2 LEGEND (DS1501/DS1511 REGISTER MAP): 0=0 and is Read Only PRS=PAB Reset Select Bit BME=Burst Mode Enable Bit EOSC =Oscillator Start/Stop Bit PAB=Power Active Bar Control Bit TPE=Time of Day/Date Alarm Power Enable Bit 32K =Enable 32.768 kHz Output Bit TDF=Time of Day/Date Alarm Flag TIE=Time of Day/Date Alarm Interrupt Enable Bit BB32=Battery Backup 32 kHz Enable Bit KSF=Kickstart Flag AM1-AM4=Alarm Mask Bits WDF=Watchdog Flag KIE=Kickstart Interrupt Enable Bit DY/DT=Day/Date Bit IRQF=Interrupt Request Flag WDE=Watchdog Enable Bit VRT1=Valid RAM and Time Bit TE=Transfer Enable Bit WDS=Watchdog Steering Bit VRT2=Auxiliary Battery Low Bit CS=Crystal Select Bit NOTE: Unless otherwise specified, the state of the control/RTC/SRAM bits in the DS1501/DS1511 is not defined upon initial power application; the DS1501/DS1511 should be properly configured/defined during initial configuration. 5 of 23 MH -2b14130 OO34042 30TDS1501/DS1511 CLOCK OSCILLATOR CONTROL The Clock oscillator may be stopped at any time. To increase the shelf life of a backup lithium battery source, the oscillator can be turned off to minimize current drain from the battery. The EOSC bit is the MSB of the month register (B7 of 05h). Setting it to a 1 stops the oscillator, setting to a O starts the oscillator. READING THE CLOCK When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC registers. This puts the external registers into a static state allowing data to be read without register values changing during the read process. Normal updates to the internal registers continue while in this state. External updates are halted when a 0 is written into the read (TE) bit, B7, of Control register B (OFh). As long as a 0 remains in the Control register B (TE) bit, updating is halted. After a halt is issued, the registers reflect the RTC count (day, date, and time) that was current at the moment the halt command was issued. Normal updates to the external set of registers will resume within 1 second after the (TE) bit is settoa l. SETTING THE CLOCK It is also recommended to halt updates to the external set of double-buffered RTC registers when writing to the clock. The (TE) bit should be used as described above before loading the RTC registers with the desired RTC count (day, date, and time) in 24-hour BCD format. Setting the (TE) bit to a 1 then transfers the values written to the internal RTC registers and allows normal operation to resume. CLOCK ACCURACY A standard 32.768 kHz quartz crystal should be directly connected to the DS1501 X1 and X2 oscillator pins. The crystal selected for use should have a specified load capacitance (CL) of either 6 pF or 12.5 pF depending on crystal capacitance setting selected with the Crystal Select (CS) bit. For more information on crystal selection and crystal layout considerations, please consult Application Note 58, Crystal Considerations with Dallas Real Time Clocks. The DS1501 can also be driven by an external 32.768 kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated. Accuracy of DS1511 is better than +1 min./month @ 25C. USING THE CLOCK ALARM The alarm settings and control for the DS1501/DS1511 reside within registers 08h - OBh. Bit 7 of registers 08h to OBh contains an alarm mask bit: AM1 through AM4. The TIE (Time of Day/Date alarm Interrupt Enable bit, B3 of OFh) and Alarm Mask bits AM1-AM4 must be set as described below for the IRQ output to be activated for a matched alarm condition. The alarm can be programmed to activate on a specific day of the month, day of the week, or repeat every day, hour, minute, or second. It can also be programmed to go off while the DS1501/DS1511 is in the battery backed state of operation to serve as a system wake-up. Alarm Mask bits AM1-AM4 control the alarm mode. Table 3 shows the possible settings. Configurations not listed in the table default to the once per second mode to notify the user of an incorrect alarm setting. When the RTC register values match alarm register settings, the Time of Day/Date Alarm Flag TDF bit is set to logic 1. If TIE is also set to logic 1, the alarm condition activates the IRQ. NOTE: Please refer to Table 2 as required for the following functional descriptions. 6 of 23 MB 2634330 0034043 cub mmDS1501/DS1511 ALARM MASK BITS Table 3 DY/DT_| AM4 | AM3 | AM2 | AMI | ALARMRATE x 1 1 1 l ONCE PER SECOND Xx 1 1 1 0 WHEN SECONDS MATCH x 1 1 0 0 WHEN MINUTES AND SECONDS MATCH x 1 0 0 0 WHEN HOURS, MINUTES, AND SECONDS MATCH 0 0 0 0 0 WHEN DATE, HOURS, MINUTES, AND SECONDS MATCH 1 0 0 0 0 WHEN DAY, HOURS, MINUTES, AND SECONDS MATCH USING THE WATCHDOG TIMER The watchdog timer can be used to detect an out-of-control processor. The user programs the watchdog timer by setting the desired amount of time-out into the two BCD Watchdog Registers (Address 0Ch and ODh). (For example: writing 60h in the watchdog register 0Ch and 00h to watchdog register 0Dh will set the watchdog time-out to 60 milliseconds.) If the processor does not access the timer, with a read or write, within the specified period, the Watchdog Flag WDF will be set. The Interrupt Request Flag IRQF will be set and either IRQ or RST will go active at this time if the Watchdog Enable bit WDE is set to logic 1 (enabled). The Watchdog Steering Bit WDS determines which of the outputs, IRQ or RST , will go active when WDE is enabled and the watchdog times out. The watchdog will be reloaded and restarted whenever the watchdog times out. Bit 0 of register OFh is the Watchdog Steering Bit WDS. When set to a 0 and WDE? is set to logic 1, the watchdog will activate the IRQ output and the IRQF flag will be set when the watchdog times out. The WDF bit will be set to a logic 1 regardless of the state of WDE to serve as an indication to the processor that a watchdog time-out has occurred. When WDS is set to a 1 and WDE? is set to logic 1, the watchdog will output a negative pulse on the RST output for a duration of 40 ms to 200 ms and the IRQF flag will be set when the watchdog times out. The WDE bit will reset to a logic 0 immediately after RST goes active. The WDF bit will be set to a logic 1 regardless of the state of WDE? to serve as an indication to the processor that a watchdog time out has occurred. The watchdog timer is reloaded when the processor performs a read or write of the Watchdog register. The time-out period then starts over. The watchdog timer is disabled by writing a value of 00h to both watchdog registers. The watchdog function is automatically disabled upon power-up. The following summarizes the configurations in which the watchdog can be used. 1. WDE=0 and WDS=0: WDF will be set. 2. WDE=0 and WDS=1: WDF will be set. 3. *WDE=] and WDS=0: WDF and IRQF will be set, and the IRQ pin will be pulled low. 4, WDE=1 and WDS=1: WDF will be set, the RST pin will be pulled low for a duration of 40 ms to 200 ms, and WDE will be reset to 0. 7 of 23 Me 2634130 OOs404u4 162DS1501/DS1511 CLEARING IRQ AND FLAGS The alarm flag(s), watchdog flag, interrupt request flag, and the IRQ output are cleared by reading the Flags register (OEh) or writing 0 to the corresponding Flag as shown in Figures 2a and 2b. IRQ AND FLAG WAVEFORMS Figure 2a OE VL ge$ 15 ns MIN __> AQ-A4 V ADDRESS 0Eh x ACTIVE FLAG BIT(S) \ y Ro /\_ HIGH-z IRQ AND FLAG WAVEFORMS Figure 2b ees 15 1S MIN nmr tl f y A0-A4 ADDRESS 0Eh IN ACTIVE FLAG BIT(S) \ iRQ N HIGH-Z WAKE-UP/KICKSTART The DS1501/DS1511 incorporates a wake-up feature which can power-on at a predetermined date through activation of the PWR output pin. In addition, the kickstart feature can allow the system to be powered up in response to a low going transition on the KS pin, without operating voltage applied to the Vec pin. As a result, system power may be applied upon such events as key closure, or modem ring- detect signal. In order to use either the wake-up or the kickstart features, the DS1501/DS1511 must have a battery connected to the Vaux pin and the oscillator must be running. The wake-up feature is controlled through the Time of Day/Date Alarm Power Enable bit TPE in Control B register (B4 of OFh). Setting TPE to 1 enables the wake-up feature, clearing TPE to 0 disables it. Similarly, the kickstart feature is controlled through the Kickstart Interrupt Enable bit KIE in Control B register (B2 of OFh). A wake-up sequence will occur as follows: When wake-up is enabled via TPE = 1 while the system is powered down (no Vcc voltage), the clock/calendar will monitor the current day or date for a match condition with Day/Date Alarm register (OBh). In conjunction with the Day/Date Alarm register, the hours, minutes, and seconds alarm bytes in the clock calendar register map (02h, O1h, and 00h) are also monitored. Asa result, a wake-up will occur at the day or date and time specified by the day/date, hours, minutes, and seconds alarm register values. This additional alarm will occur regardless of the programming of the TIE bit (Time of Day/Date Alarm Interrupt Enable bit) (B3 of OFh). When the match 8 of 23 MB 26144130 0034045 015 aDS1501/DS1511 condition occurs, the PWR pin will automatically be driven low. This output can be used to turn on the main system power supply which provides Vcc voltage to the DS1501/DS1511 as well as the other major components in the system. Also, at this time, the Time of Day/Date Alarm Flag will be set, indicating that a wake-up condition has occurred. While the system is powered down and Vgavux is present, the KS input pin will be monitored for a low- going transition of minimum pulse width txspw. When such a transition is detected, the PWR line will be pulled low, as it is for a wake-up condition. Also at this time, the Kickstart Flag (KSF, register OEh) will be set, indicating that a kickstart condition has occurred. The KS input pin is always enabled and must not be allowed to float. The timing associated with both the wake-up and kickstarting sequences is illustrated in the Wake- Up/Kickstart Timing Diagram, Figure 9, in the Electrical Specifications section of this datasheet. The timing associated with these functions is divided into 5 intervals, labeled 1-5 on the diagram. The occurrence of either a kickstart or wake-up condition will cause the PWR pin to be driven low, as described above. During interval 1, if the supply voltage on the DS1501/DS1511 Vcc pin rises above the battery switch voltage (Vsw) before the power-on timeout period (tpoto) expires, then PWR will remain at the active low level. If Vcc does not rise above the battery switch voltage (Vsw) in time, then the PWR output pin will be turned off and will return to its high-impedance level. In this event, the IRQ pin will also remain tri-stated. The interrupt flag bit (either TDF or KSF) associated with the attempted power-on sequence will remain set until cleared by software during a subsequent system power-on. If Vcc is applied within the time-out period, then the system power-on sequence will continue as shown in intervals 2-5 in the timing diagram. During interval 2, PWR will remain active and IRQ will be driven to its active low level, indicating that either TDF or KSF was set in initiating the power-on. In the diagram KS is assumed to be pulled up to the Vpaux supply (logic high). Also at this time, the PAB bit will be automatically cleared to 0 in response to a successful power-on. The PWR line will remain active as long as the PAB remains cleared to 0. At the beginning of interval 3, the system processor has begun code execution and clears the interrupt condition of TDF and/or KSF by writing zeroes to both of these control bits. As long as no other interrupt within the DS1501 is pending, the IRQ line will be taken inactive once these bits are reset, and execution of the application software may proceed. During this time, both the wakeup and kickstart functions may be used to generate status and interrupts. TDF will be set in response to a day/date, hours, minutes, and seconds match condition. KSF will be set in response to a low going transition on KS. If the associated interrupt enable bit is set (TDE and/or KIE) then the IRQ line will be driven low in response to enabled event. In addition, the other possible interrupt sources within the DS1501/DS1511 may cause IRQ to be driven low. While system power is applied, the on chip logic will always attempt to drive the PWR pin active in response to the enabled kickstart or wake-up condition. This is true even if PWR was previously inactive as the result of power being applied by some means other than wake-up or kickstart. The system may be powered down under software control by setting the PAB bit to a 1. This causes the open-drain PWR pin to be placed in a high-impedance state, as shown at the beginning of interval 4 in the timing diagram. As Vcc voltage decays, the IRQ output pin will be placed in a high-impedance state when Vcc goes below Vpr. If the system is to be again powered on in response to a wake-up or kickstart, 9 of 23 MM 2ebb4130 OOS4O4R TSS MeDS1501/DS1511 then both the TDF and KSF flags should be cleared and TPE and/or KIE should be enabled prior to setting the PAB bit. During interval 5, the system is fully powered down. Battery backup of the clock calendar and nonvolatile RAM is in effect and IRQ is tri-stated, and monitoring of wake-up and kickstart takes place. If PRS=1, PWR stays active; otherwise if PRS=0, PWR is tri-stated. SQUARE WAVE OUTPUT The square wave output is enabled and disabled via the 'E32K' bit in the month register (B6 of 05h). If the square wave is enabled (E32K = 0) and the oscillator is enabled, then a 32.768 kHz square wave will be output on the SQW pin. If 32K = 0 and the Battery Backup 32 kHz enable bit BB32 is enabled (B5 of 05h) and volt-age is applied to Veaux, then the 32 kHz square wave signal will be output on the SQW pin in the absence of Vcc. BATTERY MONITOR Upon power-up, the DS1501/DS1511 checks the battery voltage of the back-up battery sources (Vpar and Veaux). The Battery Low Flag VRT1 and VRT2 bits of control A register (B7 and B6 of 0Eh) will be set to a logic 1 at power-up if the battery voltage on Vpar and Vpaux are less than 2.5V (typical), otherwise VRT1 and VRT2 bits will be logic 0. VRT1 monitors Vaart with VRT2 monitoring Vgaux. POWER-UP DEFAULT STATES These bits are set upon power-up: EOSC =0, E32K =0, TIE=0, KIE=0, WDE=0, and WDS=0. 256 X 8 EXTENDED RAM The DS1501/DS1511 provides 256 x 8 of on-chip SRAM which is controlled as nonvolatile data storage sustained from a lithium battery. On power-up, the RAM is taken out of write protect status by an internal signal. Access to the SRAM is controlled by two on-chip latch registers. One register is used to hold the SRAM address, and the other is used to hold read/write data. The SRAM address space is from 00h to FFh. The 8-bit address of the RAM location to be accessed must be loaded into the extended RAM address register located at 10h. Data in the addressed location may be read by performing a read operation from location 13h, or written to by performing a write operation to location 13h. Data in any addressed location may be read or written repeatedly without changing the address in location 10h. To read or write consecutive extended RAM locations, a burst mode feature can be enabled to increment the extended RAM address. To enable the burst mode feature, set the BME bit (B4 of control B register) to a logic 1. With burst mode enabled, write the extended RAM starting address location to register 10h. Then read or write the extended RAM data from/to register 13h. The extended RAM address locations are automatically incremented on the rising edge of OE, WE, or CE only when register 13h is being accessed. Refer to the Burst Mode Timing Waveform (Figure 6). 10 of 23 MB 2634130 0034047? 9451DS$1501/DS1511 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground -0.5V to +6.0V Operating Temperature, Commercial Range 0C to 70C Operating Temperature, Industrial Range -40C to +85C Storage Temperature, DS1501 -55C to +125C Storage Temperature, DS1511 -40C to +70C Soldering Temperature 260C for 10 seconds (See Note 8) * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (0C to 70C) PARAMETER SYMBOL MIN TYP MAX UNITS | NOTES Logic 1 Voltage All Inputs Vec =5V 110% Vin 2.2 Vec +0.3 Vv Vcc = 3.3V +10% Vin 2.0 Voc +0.3 Vv Logic 0 Voltage All Inputs Vec =5V +10% Vit -0.3 0.8 Vv 1 Vec =3.3V+10% Vit -0.3 0.6 Vv 1 Battery Voltage VAT 2.5 3.7 Vv 1 Auxiliary Battery Voltage Veaux 2.5 3.7 Vv 1 DC ELECTRICAL CHARACTERISTICS (0C to 70C; Vcc = 5.0V 410%) PARAMETER SYMBOL MIN TYP MAX | UNITS | NOTES Active Supply Current Icc Xx 15 mA 2 TTL Standby Current( CE = leet X 3 mA > Vin ) CMOS Standby Current I Xx (CE > Vec -0.2V) co 3 mA 2 Battery Current, Oscillator On Ipatt 1.0 HA Battery Current, Oscillator Off Ipat2 0.1 LA Input Leakage Current any input) ft | 1 HA Output Leakage Current (any output) lo. I 1 HA Output Logic 1 Voltage Tour = -1.0 mA) Vou 2.4 Vv 1 Output Logic 0 Voltage Jour = 2.1 mA, DQO-7 Outputs Vou 0.4 Vv I lour = 10.0 mA, IRQ, PWR, and lour = 10.0 mA, IRQ, PWR, an Vou 0.4 Vv 1,3 RST Outputs Power-fail Voltage VpF 4.25 4.37 4.50 Vv l Battery Switch-over Voltage Vso Veats V 1,4 VBAux 11 of 23 MM 2614130 OO34048 4ce6DC ELECTRICAL CHARACTERISTICS DS1501/DS81511 (0C to 70C; Vec = 3.3V 10%) PARAMETER SYMBOL MIN TYP MAX | UNITS | NOTES Active Supply Current lec xX 10 mA 2 TTL Standby Current(CE = lec xX > mA 2 Vin) CMOS Standby Current _ I x 2 mA 2 (CE > Voc -0.2V) ce Battery Current, Oscillator On Ipati 1.0 LA Battery Current, Oscillator Off Ipat2 0.1 LA Input Leakage Current (any input) I. rl +1 pA Output Leakage Current - + (any output) ToL I | HA Output Logic 1 Voltage V 2.4 Vv 1 (our = -1.0 mA) OH Output Logic 0 Voltage lout = -2.1 mA, DQO0-7 Outputs Vou 0.4 Vv 1 = 10.0 mA, IRQ, PWR our = 10.0 mA, IRQ, PWR,and | Vo, 0.4 1,3 RST Outputs Power-fail Voltage VpF 2.80 2.88 2.97 1 VBAT; Battery Switch-over Voltage Vso VBAUX, Vv 1,7 or VpF READ CYCLE, AC CHARACTERISTICS (0C to 70C; Vec = 5.0V +10%) MH 2634130 0034049 764 me PARAMETER SYMBOL MIN TYPE MAX UNITS | NOTES Read Cycle Time trc 70 ns Address Access Time tra 70 ns CE to DQ Low-Z tcEL 5 ns CE Access Time tcEA 70 ns CE Data Off Time tcez 25 ns OE to DQ Low-Z toEL 5 ns OE Access Time toga 35 ns OE Data Off Time tonz 25 ns Output Hold from Address tou 5 ns 12 of 23DS1501/DS1511 READ CYCLE, AC CHARACTERISTICS (0C to 70C; Veco = 3.3V +10%) PARAMETER SYMBOL MIN TYPE MAX UNITS | NOTES Read Cycle Time trc 120 ns Address Access Time tAA 120 ns CE to DQ Low-Z tcEL 5 ns CE Access Time tcEA 120 ns CE Data Off Time tcEz 40 ns OE to DQ Low-Z tort 5 ns OE Access Time toEA 100 ns OE Data Off Time toEz 35 ns Output Hold from Address tou 5 ns READ CYCLE TIMING Figure 3 <t tac Y Y A0-A4 /\ feet ton toez tcEA arr he ice. > tOEA beg - toez _ > OE \ \ oe DdQo-DO7 a VALID -__.. WRITE CYCLE, AC CHARACTERISTICS (OC to 70C; Vec= 5.0V +10%) WH 2624130 GO3I4O50 48h PARAMETER SYMBOL MIN TYPE MAX UNITS | NOTES Write Cycle Time twe 70 ns Address Step-up Time tas 0 ns WE Pulse Width twew 50 ns CE Pulse Width tcew 55 ns Data Setup Time tos 30 ns Data Hold Time toy 0 ns Address Hold Time tan 0 ns WE Data Off Time twez 25 ns Write Recovery Time twr 5 ns 13 of 23WRITE CYCLE, AC CHARACTERISTICS DS1501/DS1511 (0C to 70C; Vec= 3.3V 410%) PARAMETER SYMBOL MIN TYPE MAX UNITS | NOTES Write Cycle Time twe 120 ns Address Step-up Time tas 0 ns WE Pulse Width twew 100 ns CE Pulse Width tcew 110 ns Data Setup Time tps 80 ns Data Hold Time toy 0 ns Address Hold Time taH 0 ns WE Data Off Time twez 40 ns Write Recovery Time twr 10 ns WRITE CYCLE TIMING, WRITE ENABLE CONTROLLED Figure 4 a twe pa A0-A4 x VALID x VALID _-@-/ tas tan CE f \ <t o>! tas peep yyy a ty WE a cat twez t Ip ae| DQ0-DQ7 DATA OUTPUT ) DATA INPUT DATA INPUT 14 of 23 MS 2614130 CO34051 312DS1501/DS1511 WRITE CYCLE TIMING, CHIP ENABLE CONTROLLED Figure 5 << twe VALID < VAUD tas taH AOQ-A4 \ / a ea tcew > ep KR = |" r\ a tou DQO-DQ7 DATA INPUT DATA INPUT t (ps | BURST MODE TIMING CHARACTERISTICS (0C to 70C; Vec=5.0V+1 0%) PARAMETER SYMBOL | MIN | TYP | MAX | UNITS | NOTES Pulse Width OF, WE, or CE High PWuicu Xx nS Pulse Width OE, WE, or CE Low PWLow x nS BURST MODE TIMING CHARACTERISTICS _(0C to 70C; Veci=3.3V+10%) PARAMETER SYMBOL | MIN | TYP | MAX | UNITS | NOTES Pulse Width OE, WE, or CE High PWuicu X nS Pulse Width OE, WE, or CE Low PW iow X nS BURST MODE TIMING WAVEFORM Figure 6 Ao-Ad x 13h _ PW Low PW hisu OE 5 WE , or ; _| . | _ pavvaz >> > 15 of 23 MMH 2614130 0034052 255POWER UP/DOWN CHARACTERISTICS DS81501/DS1511 (0C to 70C; Vec= 5.0V +10%) PARAMETER SYMBOL MIN TYP MAX UNITS | NOTES CE or WE at Vi Before tp 0 Ls Power-Down Vcc Fall Time: VPF(max) to tr 300 ys VPF(min) Vcc Fall Time: Vermin) to Vso trB 10 [ls Vcc Rise Time: Vermin) to tr 0 Lis VpF(max) Vopr to RST High trEC 40 200 ms (Ts = 25C) PARAMETER SYMBOL MIN TYP MAX UNITS | NOTES Expected Data Retention tor 10 years 6 Time(QOscillator On) POWER-UP/DOWN WAVEFORM TIMING 5-VOLT DEVICE Figure 7 RST wows recoowan DON'T CARE Y, RECOGNIZED ey) \ y K HIGH-Z OUTPUTS VALID J - VALID 16 of 23 Me 2614130 OO34053 195DS1501/DS1511 POWER UP/DOWN CHARACTERISTICS (0C to 70C; Vec= 3.3V +10%) PARAMETER SYMBOL MIN TYP MAX UNITS | NOTES CE or WE at Vi Before tep 0 [is Power-Down Vcc Fall Time: VpF(max) to tf 300 Ls VF (min) Vcc Rise Time: Vpr(miny to tr 0 us VpF(max) Vopr to RST High trEc 40 200 ms POWER-UP/DOWN WAVEFORM TIMING 3.3-VOLT DEVICE Figure 8 thec / {recoonz ~~ ~ ~~ ves ) { reoeuzen ) y DONT CARE OUTPUTS VALID} CAPACITANCE PARAMETER SYMBOL | MIN TYP | MAX HIGH-Z VALID (Ta= 25C) UNITS | NOTES Cr 10 pF Cio 10 pF Capacitance on all input pins Capacitance on IRQ, PWR, RST ,and DQ pins 17 of 23 MB 2614150 0034054 02], meDS1501/DS1511 AC TEST CONDITIONS Output Load: 100 pF + 1TTL Gate Input Pulse Levels: 0.0 to 3.0 Volts Timing Measurement Reference Levels: Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5 ns WAKE-UP/KICKSTART TIMING Figure 9 CONDITION: Ver [ZA NL Ver < Vaart Mer | Vee ov +-e Eee Eee a CONDITION: Ver 42 oe NU Ver > Vea . WE/KF (INTERNAL) i \ 4 Mf 7 \ = ] 1 ow 2 4 ee 5 NOTE: Time intervals shown above are referenced in Wake-up/Kickstart section. *This condition can occur with the 3.3V device. 18 of 23 Me 2614130 0034055 The meDS1501/DS1511 WAKE-UP/KICKSTART TIMING (Ta= 25C) PARAMETER SYMBOL MIN TYP MAX UNITS | NOTES Kickstart Input Pulse Width tkspw 2 Us Wake-up/Kickstart Power-on tpoto 2 seconds 5 Timeout NOTE 1. Voltage referenced to ground. 2. Outputs are open. 3. The IRQ, PWR, and RST outputs are open drain. 4. Battery switch-over occurs at the battery terminal voltage level. 5. Wakeup kickstart timeout generated only when the oscillator is enabled and the countdown chain is not reset. 6. tpr is the amount of time that the internal battery can power the internal oscillator and internal registers of the DS1511. 7. If Vpris less than Vpar and Vpaux, the device power is switched from Vcc to the greater of Vgar and Vpaux When Vcc drops below Vpr. If Vpr is greater than Vgar and Vgaux, the device power is switched from Vcc to the larger of Vgar and Vpaux when Vcc drops below the larger of Var and VBAux- 8. Real-Time Clock Modules can be successfully processed through conventional wave-soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85C. Post-solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used. 19 of 23 MM 2644130 COS4OSb ITY mmDS1501/DS1511 DS1501 28-PIN DIP PKG 28-PIN DIM [| MIN | MAX B AIN. | 1.445 | 1.470 MM 36.70 | 37.34 | BIN. | 0.530 | 0.550 MM 13.46 | 13.97 lL A | CIN. [ 0.140 | 0.160 MM 3.56 4.06 DIN. [| 0.600 | 0.625 MM 15.24 | 15.88 EIN. | 0.015 | 0.040 MM 0.38 1.02 FIN. [ 0.120 | 0.145 MM 3.05 3.68 GIN. | 0.090 | 0.110 MM 2.29 2.79 HIN. [ 0.625 | 0.675 MM 15.88 | 17.15 JIN. [ 0.008 [| 0.012 MM 0.20 0.30 ; KIN. [ 0.015 [| 0.022 MM 0.38 0.56 h 4 20 of 23 M@ 2614130 0034057 830 meDS1501S 28-PiN SOIC DS$1501/DS1511 K G mi eds PKG 28-PIN DIM MIN MAX AIN. 0.697 0.728 MM 17.70 18.50 BIN. 0.324 0.350 MM 8.23 8.90 CIN. 0.087 0.118 MM 2.20 3.00 DIN. 0.016 0.050 MM 0.40 1.27 EIN. 0.002 0.014 MM 0.05 0.35 FIN. 0.100 0.120 7 MM 2.55 3.05 MM 1.27 +L it HIN. 0.453 0.500 E A MM 11.50 12.70 JIN. 0.006 0.013 MM 0.14 0.32 KIN. 0.014 0.020 MM 0.35 0.50 21 of 23 M8 2644130 OO3S4058 77?DS1501/DS1511 DS1501E 28-PIN TSOP a, NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS A DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL BUT ONE HALF OF ITS AREA MUST BE LOCATED WITHIN THE ZONE INDICATED SEE DETAIL A A 1 L DETAIL A PKG 28-PIN DIM MIN MAX A - 1.20 Al 0.05 - A2 0.91 1.02 b 0.18 0.27 c 0.15 0.20 D 13.20 13.60 D1 11.70 11.90 E 7.90 8.10 e 0.55 BSC L 0.30 0.70 l 0.80 BSC 22 of 23 MH 2614130 0034059 L035DS1501/DS1511 DS1511 28 PKG 28-PIN DIM MIN MAX AIN. 1.520 1.540 MM 38.61 39.12 BIN. 0.695 0.720 MM 17.65 18.29 CIN. 0.350 0.375 MM 8.89 9.52 DIN. 0.100 0.130 MM 2.54 3.30 EIN. 0.015 0.030 +r MM 0.38 0.76 CE FIN. 0.110 0.140 tt MM 2.79 3.56 J =-t GIN. [ 0.090 | 0.110 F MM 2.29 2.79 sh kK ape HIN. 0.590 0.630 13 EQUAL SPACES AT > MM 14.99 16.00 -100 4.010 TNA JIN. 0.008 0.012 . MM 0.20 0.30 KIN. 0.015 0.021 MM 0.38 0.53 NOTE: PINS 2, 3,21, AND 25 ARE MISSING BY 7 J DESIGN. he 4H oe 8 23 of 23 M@ 2614130 OO340b0 3cs