1. General description
74AHC1G125 and 74AHCT1G125 are high-speed Si-gate CMOS devices. They provide
one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by
the output enable input (OE). A HIGH at OE causes th e ou tp ut to assu m e a
high-impedance OFF-state.
The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V.
The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.
2. Features and benefits
Symmetrical output impedance
High noise immunity
Low power dissipation
Balanced propagation delays
Multiple package options
ESD protection:
HBM JESD22-A114F: exceeds 2000 V
MM JESD22-A115-A: exceeds 200 V
CDM JESD22-C101E: exceeds 1000 V
Specified from 40 C to +125 C
3. Ordering information
74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
Rev. 10 — 23 August 2012 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AHC1G125GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package;
5 leads; body width 1.25 mm SOT353-1
74AHCT1G125GW
74AHC1G125GV 40 C to +125 C SC-74A plastic surface-mounted package; 5 leads SOT753
74AHCT1G125GV
74AHC1G125GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no
leads; 6 terminals; body 1 1.45 0.5 mm SOT886
74AHCT1G125GM
74AHC1G125GF 40 C to +125 C XSON6 plastic extremely thin small outline package;
no leads; 6 terminals; body 1 10.5 mm SOT891
74AHCT1G125GF
74AHC_AHCT1G125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 23 August 2012 2 of 17
NXP Semiconductors 74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
6. Pinning information
6.1 Pinning
Table 2. Marking codes
Type number Marking[1]
74AHC1G125GW AM
74AHCT1G125GW CM
74AHC1G125GV A25
74AHCT1G125GV C25
74AHC1G125GM AM
74AHCT1G125GM CM
74AHC1G125GF AM
74AHCT1G125GF CM
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram
mna118
AY
2
1
4
OE
mna119
14
2
EN
mna120
AY
OE
Fig 4. Pin configuration
SOT353-1 and SOT753 Fig 5. Pin configuration SOT886 Fig 6. Pin configuration SOT891
74AHC1G125
74AHCT1G125
OE V
CC
A
GND Y
001aaf101
1
2
3
5
4
74AHC1G125
74AHCT1G125
A
001aaj971
OE
GND
n.c.
V
CC
Y
Transparent top view
2
3
1
5
4
6
74AHC1G125
74AHCT1G125
A
001aaj972
OE
GND
n.c.
VCC
Y
Transparent top view
2
3
1
5
4
6
74AHC_AHCT1G125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 23 August 2012 3 of 17
NXP Semiconductors 74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
6.2 Pin description
7. Functional description
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
Table 3. Pin description
Symbol Pin Description
SOT353-1/SOT753 SOT886/SOT891
OE 1 1 output enable input
A 2 2 data input
GND 3 3 ground (0 V)
Y 4 4 data output
n.c. - 5 not connected
VCC 5 6 supply voltage
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state
Inputs Output
OE A Y
LLL
LHH
HXZ
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7.0 V
VIinput voltage 0.5 +7.0 V
IIK input clamping current VI < 0.5 V [1] 20 - mA
IOK output clamping current VO < 0.5 V or VO>V
CC +0.5V [1] -20 mA
IOoutput current 0.5 V < VO <V
CC +0.5V - 25 mA
ICC supply current - 75 mA
IGND ground current 75 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C[2] - 250 mW
74AHC_AHCT1G125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 23 August 2012 4 of 17
NXP Semiconductors 74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
9. Recommended operating conditions
10. Static characteristics
Table 6. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 74AHC1G125 74AHCT1G125 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V
VIinput voltage 0 - 5.5 0 - 5.5 V
VOoutput voltage 0 - VCC 0-V
CC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise
and fall rate VCC = 3.3 V 0.3 V - - 100 - - - ns/V
VCC = 5.0 V 0.5 V - - 20 - - 20 ns/V
Table 7. Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74AHC1G125
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V
VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V
VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V
VIL LOW-level
input voltage VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V
VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V
VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V
VOH HIGH-level
output voltage VI= VIH or VIL
IO= 50 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO= 50 A; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V
IO= 50 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO= 4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V
IO= 8.0 mA; VCC = 4.5 V 3.94 - - 3.8 - 3.70 - V
VOL LOW-level
output voltage VI= VIH or VIL
IO= 50 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO= 50 A; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V
IO= 50 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO= 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V
IO= 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V
IOZ OFF-state
output current VI=V
CC or GND;
VCC =5.5V - - 0.25 - 2.5 - 10 A
IIinput leakage
current VI= 5.5 V or GND;
VCC =0Vto5.5V - - 0.1 - 1.0 - 2.0 A
ICC supply current VI=V
CC or GND; IO = 0 A;
VCC = 5.5 V - - 1.0 - 10 - 40 A
74AHC_AHCT1G125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 23 August 2012 5 of 17
NXP Semiconductors 74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
11. Dynamic characteristics
CIinput
capacitance - 1.5 10 - 10 - 10 pF
74AHCT1G125
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI= VIH or VIL; VCC = 4.5 V
IO= 50 A 4.4 4.5 - 4.4 - 4.4 - V
IO= 8.0 mA 3.94 - - 3.8 - 3.70 - V
VOL LOW-level
output voltage VI= VIH or VIL; VCC = 4.5 V
IO= 50 A - 0 0.1 - 0.1 - 0.1 V
IO= 8.0 mA - - 0.36 - 0.44 - 0.55 V
IOZ OFF-state
output current VI=V
CC or GND;
VCC =5.5V - - 0.25 - 2.5 - 10 A
IIinput leakage
current VI= 5.5 V or GND;
VCC =0Vto5.5V - - 0.1 - 1.0 - 2.0 A
ICC supply current VI=V
CC or GND; IO = 0 A;
VCC = 5.5 V - - 1.0 - 10 - 40 A
ICC additional
supply current per input pin; VI=3.4V;
other inputs at VCC or GND;
IO=0 A; V
CC = 5.5 V
- - 1.35 - 1.5 - 1.5 mA
CIinput
capacitance - 1.5 10 - 10 - 10 pF
Table 7. Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
Table 8. Dynamic characteristics
GND = 0 V; For test circuit see Figure 9.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74AHC1G125
tpd propagation
delay AtoY; see Figure 7 [1]
VCC = 3.0 V to 3.6 V [2]
CL= 15 pF - 4.7 8.0 1.0 9.5 1.0 11.5 ns
CL= 50 pF - 6.6 11.5 1.0 13.0 1.0 14.5 ns
VCC = 4.5 V to 5.5 V [3]
CL= 15 pF - 3.4 5.5 1.0 6.5 1.0 7.0 ns
CL= 50 pF - 4.8 7.5 1.0 8.5 1.0 9.5 ns
74AHC_AHCT1G125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 23 August 2012 6 of 17
NXP Semiconductors 74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
ten enable time OE to Y; see Figure 8 [1]
VCC = 3.0 V to 3.6 V [2]
CL= 15 pF - 5.0 8.0 1.0 9.5 1.0 11.5 ns
CL= 50 pF - 6.9 11.5 1.0 13.0 1.0 14.5 ns
VCC = 4.5 V to 5.5 V [3]
CL= 15 pF - 3.6 5.1 1.0 6.0 1.0 6.5 ns
CL= 50 pF - 4.9 7.5 1.0 8.5 1.0 9.5 ns
tdis disable time OE to Y; see Figure 8 [1]
VCC = 3.0 V to 3.6 V [2]
CL= 15 pF - 6.0 9.7 1.0 11.5 1.0 12.5 ns
CL= 50 pF - 8.3 13.2 1.0 15.0 1.0 16.5 ns
VCC = 4.5 V to 5.5 V [3]
CL= 15 pF - 4.1 6.8 1.0 8.0 1.0 8.5 ns
CL= 50 pF - 5.7 8.8 1.0 10.0 1.0 11.0 ns
CPD power
dissipation
capacitance
per buffer;
CL=50pF;f=1 MHz;
VI=GNDtoV
CC
[4] -9- - - - -pF
74AHCT1G125
tpd propagation
delay AtoY; see Figure 7 [1]
VCC = 4.5 V to 5.5 V [3]
CL= 15 pF - 3.4 5.5 1.0 6.5 1.0 7.0 ns
CL= 50 pF - 4.8 7.5 1.0 8.5 1.0 9.5 ns
ten enable time OE to Y; see Figure 8 [1]
VCC = 4.5 V to 5.5 V [3]
CL= 15 pF - 3.9 5.1 1.0 6.0 1.0 6.5 ns
CL= 50 pF - 5.1 7.5 1.0 8.5 1.0 9.5 ns
tdis disable time OE to Y; see Figure 8 [1]
VCC = 4.5 V to 5.5 V [3]
CL= 15 pF - 4.5 6.8 1.0 8.0 1.0 8.5 ns
CL= 50 pF - 6.1 8.8 1.0 10.0 1.0 11.0 ns
Table 8. Dynamic characteristics …continued
GND = 0 V; For test circuit see Figure 9.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74AHC_AHCT1G125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 23 August 2012 7 of 17
NXP Semiconductors 74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
[1] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[2] Typical values are measured at VCC = 3.3 V.
[3] Typical values are measured at VCC = 5.0 V.
[4] CPD is used to determine the dynamic power dissipation PD(W).
PD=C
PD VCC2fi+(CLVCC2fo)where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in Volts.
12. Waveforms
CPD power
dissipation
capacitance
per buffer;
CL=50pF;f=1 MHz;
VI=GNDtoV
CC
[4] -11- - - - - pF
Table 8. Dynamic characteristics …continu ed
GND = 0 V; For test circuit see Figure 9.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. Input (A) to output (Y) propagation delay s
mnb153
tPHL tPLH
VM
VM
A input
Y output
GND
VI
VOH
VOL
74AHC_AHCT1G125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 23 August 2012 8 of 17
NXP Semiconductors 74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. Enable an d disable times
mna644
t
PLZ
t
PHZ
outputs
disabled outputs
enabled
V
Y
V
X
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
OE input
V
I
V
OL
V
OH
V
CC
V
M
GND
GND
t
PZL
t
PZH
V
M
V
M
Table 9. Measurement point
Type Inputs Output
VIVMVMVXVY
74AHC1G125 GND to VCC 0.5VCC 0.5VCC VOL + 0.3 V VOH 0.3 V
74AHCT1G125 GND to 3.0 V 1.5 V 0.5VCC VOL + 0.3 V VOH 0.3 V
74AHC_AHCT1G125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 23 August 2012 9 of 17
NXP Semiconductors 74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
Test data is given in Table 10.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 9. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aad983
DUT
V
CC
V
CC
VIVO
RT
RLS1
CL
open
G
Table 10. Test data
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74AHC1G125 VCC 3 ns 15 pF, 50 pF 1 kopen GND VCC
74AHCT1G125 3 V 3 ns 15 pF, 50 pF 1 kopen GND VCC
74AHC_AHCT1G125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 23 August 2012 10 of 17
NXP Semiconductors 74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
13. Package outline
Fig 10. Package outline SOT353-1 (TSSOP5)
74AHC_AHCT1G125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 23 August 2012 11 of 17
NXP Semiconductors 74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
Fig 11. Package outline SOT753 (SC-74A)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT753 SC-74A
wBM
bp
D
e
A
A1
Lp
Q
detail X
HE
E
vMA
AB
y
0 1 2 mm
scale
c
X
132
45
Plastic surface-mounted package; 5 leads SOT753
UNIT A1bpcDEHELpQywv
mm 0.100
0.013 0.40
0.25 3.1
2.7
0.26
0.10 1.7
1.3
e
0.95 3.0
2.5 0.2 0.10.2
DIMENSIONS (mm are the original dimensions)
0.6
0.2 0.33
0.23
A
1.1
0.9
02-04-16
06-03-16
74AHC_AHCT1G125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 23 August 2012 12 of 17
NXP Semiconductors 74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
Fig 12. Package outline SOT886 (XSON6)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT886 MO-252
sot886_po
04-07-22
12-01-05
Unit
mm max
nom
min
0.5 0.04 1.50
1.45
1.40
1.05
1.00
0.95
0.35
0.30
0.27
0.40
0.35
0.32
0.6
A(1)
Dimensions (mm are the original dimensions)
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886
A1b
0.25
0.20
0.17
DEee
1
0.5
LL
1
terminal 1
index area
D
E
e1
e
A1
b
L
L1
e1
0 1 2 mm
scale
1
6
2
5
3
4
6x
(2)
4x
(2)
A
74AHC_AHCT1G125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 23 August 2012 13 of 17
NXP Semiconductors 74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
Fig 13. Package outline SOT891 (XSON6)
terminal 1
index area
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT891
SOT891
05-04-06
07-05-15
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
D
E
e1
e
A1
b
L
L1
e1
0 1 2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm 0.20
0.12 1.05
0.95 0.35
0.27
A1
max b E
1.05
0.95
Dee
1L
0.40
0.32
L1
0.350.55
A
max
0.5 0.04
1
6
2
5
3
4
A
6×
(1)
4×
(1)
Note
1. Can be visible in some manufacturing processes.
74AHC_AHCT1G125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 23 August 2012 14 of 17
NXP Semiconductors 74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
14. Abbreviations
15. Revision history
Table 11. Abbreviation s
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
CDM Charged Device Mo del
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 12. Revision history
Document ID Release date Data sheet status Change
notice Supersedes
74AHC_AHCT1G12 5 v10 20120823 Product data sheet - 74AHC_AHCT1G125 v.9
Modifications: •Package outline drawing of SOT886 (Figure 12) modified.
74AHC_AHCT1G12 5 v.9 20090622 Product data sheet - 74AHC_AHCT1G125 v.8
74AHC_AHCT1G12 5 v.8 20090409 Product data sheet - 74AHC_AHCT1G125 v.7
74AHC_AHCT1G12 5 v.7 20070707 Product data sheet - 74AHC_AHCT1G125 v.6
74AHC_AHCT1G12 5 v.6 20020606 Product specification - 74AHC_AHCT1G125 v.5
74AHC_AHCT1G12 5 v.5 20020322 Product specification - 74AHC_AHCT1G125 v.4
74AHC_AHCT1G12 5 v.4 20010222 Product specification - 74AHC_AHCT1G125 v.3
74AHC_AHCT1G12 5 v.3 19990615 Product specification - 74AHC_AHCT1G125_N v.2
74AHC_AHCT1G12 5_N v.2 19981207 Preliminary specification - 74AHC_AHCT1G125_N v.1
74AHC_AHCT1G12 5_N v.1 19981125 Preliminary specification - -
74AHC_AHCT1G125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 23 August 2012 15 of 17
NXP Semiconductors 74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full informatio n see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificatio n — The information and data provided in a Product
data sheet shall define the specification of the product as agr eed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggreg ate and cumulative l iability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors pro duct can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with t heir
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessa ry
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by cust omer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property right s.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data fro m the objective specification fo r product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74AHC_AHCT1G125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 23 August 2012 16 of 17
NXP Semiconductors 74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for aut omo tive use. It i s neit her qua lif ied nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applicati ons.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting f rom customer design an d
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 23 August 2012
Document identifier: 74AHC_AHCT1G125
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 3
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
9 Recommended operating conditions. . . . . . . . 4
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
17 Contact information. . . . . . . . . . . . . . . . . . . . . 16
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17