8543BGI www.icst.com/products/hiperclocks.html REV. C JANUARY 5, 2004
1
Integrated
Circuit
Systems, Inc.
ICS8543I
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
GENERAL DESCRIPTION
The ICS8543I is a low skew, high performance
1-to-4 Differential-to-LVDS Clock Fanout Buffer
and a member of the HiPerClockS™ family of
High Performance Clock Solutions from ICS.
Utilizing Low Voltage Differential Signaling
(LVDS) the ICS8543I provides a low power, low noise, solu-
tion for distributing clock signals over controlled impedances
of 100Ω. The ICS8543I has two selectable clock inputs. The
CLK, nCLK pair can accept most standard differential input
levels. The PCLK, nPCLK pair can accept LVPECL, CML, or
SSTL input levels. The clock enable is internally synchronized
to eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8543I ideal for those applications demanding
well defined performance and repeatability.
FEATURES
•4 differential LVDS outputs
•Selectable differential CLK, nCLK or LVPECL clock inputs
•CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
•PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
•Maximum output frequency: 650MHz
•Translates any single ended input signal to LVDS levels
with resistor bias on nCLK input
•Output skew: 40ps (maximum)
• Part-to-part skew: 600ps (maximum)
•Propagation delay: 2.6ns (maximum)
•3.3V operating supply
•-40°C to 85°C ambient operating temperature
BLOCK DIAGRAM PIN ASSIGNMENT
ICS8543I
20-Lead TSSOP
4.4mm x 6.5mm x 0.92mm body package
G Package
Top View
GND
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
OE
GND
VDD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
VDD
Q1
nQ1
Q2
nQ2
GND
Q3
nQ3
HiPerClockS™
ICS
OE
CLK
nCLK
PCLK
nPCLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
0
1
CLK_EN
CLK_SEL
D
Q
LE
8543BGI www.icst.com/products/hiperclocks.html REV. C JANUARY 5, 2004
2
Integrated
Circuit
Systems, Inc.
ICS8543I
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
TABLE 2. PIN CHARACTERISTICS
TABLE 1. PIN DESCRIPTIONS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
R
PULLUP
rotsiseRpulluPtupnI 15KΩ
R
NWODLLUP
rotsiseRnwodlluPtupnI 15KΩ
rebmuNemaNepyTnoitpircseD
31,9,1DNGrewoP.dnuorgylppusrewoP
2NE_KLCtupnIpulluP
kcolcswollofstuptuokcolc,HGIHnehW.e
lbanekcolcgnizinorhcnyS
decroferastuptuoQn,woldecroferastuptuoQ,WOLnehW.tupni
.slevelecafretniLTTVL/SOMCVL.hgih
3LES_KLCtupnInwodlluP
.stupniKLCPn,KLCPstceles,HGIHnehW.tupnitceleskcolC
.stupniKLCn,KLCstcelesWOL
nehW
.slevelecafretniLTTVL/SOMCVL
4KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN
5KLCntupnIpulluP.tupnikc
olclaitnereffidgnitrevnI
6KLCPtupnInwodlluP.tupnikcolcLCEPVLlaitnereffidgnitrevni-noN
7KLCPntupnIpulluP.tupnikc
olcLCEPVLlaitnereffidgnitrevnI
8EOtupnIpulluP 0Qn,0QstuptuofognilbasiddnagnilbaneslortnoC.elbanetuptuO
.3Qn
,3Qhguorht
81,01V
DD
rewoP.snipylppusevitisoP
21,113Q,3QntuptuO.slevelecafretniSDVL.riaptuptuolaitnereffiD
51,412Q,2QntuptuO.slevel
ecafretniSDVL.riaptuptuolaitnereffiD
71,611Q,1QntuptuO.slevelecafretniSDVL.riaptuptuolaitnereffiD
02,910Q,0
QntuptuO.slevelecafretniSDVL.riaptuptuolaitnereffiD
:ETON
pulluP
dna
wodlluP
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefern
8543BGI www.icst.com/products/hiperclocks.html REV. C JANUARY 5, 2004
3
Integrated
Circuit
Systems, Inc.
ICS8543I
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
TABLE 3B. CLOCK INPUT FUNCTION TABLE
TABLE 3A. CONTROL INPUT FUNCTION TABLE
stupnIstuptuO
EONE_KLCLES_KLCecruoSdetceleS3Q:0Q3Qn:0Qn
0XX ZiHZiH
10 0 KLCn,KLCwoL;delbasiDhgiH;delbasiD
10 1 KLCPn,KLCPwoL;delb
asiDhgiH;delbasiD
110 KLCn,KLCdelbanEdelbanE
111 KLCPn,KLCPdelbanEdelbanE
nwohssaegdekcolctupnignillafdnagnisiragniwo
llofdelbanerodelbasiderastuptuokcolceht,sehctiwsNE_KLCretfA
ni
.1erugiF
nidebircsedsastupniKLCPn,KLCPdnaKLCn,KLCehtfonoitcnufaerastuptuoehtfoetatseht,edomevitcaehtnI
.B3elbaT
stupnIstuptuO edoMtuptuOottupnIytiraloP
KLCP,KLCKLCPn,KLCn3Q:0Q3Qn:0Qn
01 WOLHGIHlaitnereffiDotlaitnereffiDgnitrevn
InoN
10 HGIHWOLlaitnereffiDotlaitnereffiDgnitrevnInoN
01ETON;desaiBWOLHGIHlaitnereffiDotdednEelgniSgnitrevnInoN
11ET
ON;desaiBHGIHWOLlaitnereffiDotdednEelgniSgnitrevnInoN
1ETON;desaiB0HGIHWOLlaitnereffiDotdednEelgniSgnitrevnI
1ET
ON;desaiB1WOLHGIHlaitnereffiDotdednEelgniSgnitrevnI
."sleveLdednEelgniStpeccAottupnIlaitnereffiDehtgniriW"n
oitcesnoitamrofnInoitacilppAehtotreferesaelP:1ETON
Enabled
Disabled
FIGURE 1. CLK_EN TIMING DIAGRAM
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ0:nQ3
Q0:Q3
8543BGI www.icst.com/products/hiperclocks.html REV. C JANUARY 5, 2004
4
Integrated
Circuit
Systems, Inc.
ICS8543I
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSevitisoP531.33.3564.3V
I
DD
tnerruCylppuSrewoP 05Am
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnIEO,LES_KLC,NE_KLC2V
DD
3.0-V
V
LI
egatloVwoLtupnIEO,LES_KLC,NE_KLC3.0-8.0V
I
HI
tnerruChgiHtupnI EO,NE_KLC 5Aµ
LES_KLC 051Aµ
I
LI
tnerruCwoLtupnI EO,NE_KLC051-Aµ
LES_KLC5-Aµ
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
tnerruChgiHtupnI KLCV
DD
V=
NI
V564.3=051Aµ
KLCnV
DD
V=
NI
V564.3=5Aµ
I
LI
tnerruCwoLtupnI KLCV
DD
V,V564.3=
NI
V0=5-Aµ
KLCnV
DD
V,V564.3=
NI
V0=051-Aµ
V
PP
egatloVtupnIkaeP-ot-kaeP 51.03.1V
V
RMC
2,1ETON;egatloVtupnIedoMnommoC 5.0V
DD
58.0-V
VsadenifedsiegatlovedomnommoC:1ETON
HI
.
VsiKLCn,KLCrofegatlovtupnimumixameht,snoitacilppadedneelgnisroF:2ETON
DD
.V3.0+
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD 4.6V
Inputs, VI-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current 10mA
Surge Current 15mA
Package Thermal Impedance, θ
JA 73.2°C/W (0 lfpm)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
8543BGI www.icst.com/products/hiperclocks.html REV. C JANUARY 5, 2004
5
Integrated
Circuit
Systems, Inc.
ICS8543I
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
ycneuqerFtuptuomumixaM 056zHM
t
DP
1ETON;yaleDnoitagaporPf≤zHM0565.16.2sn
t
)o(ks4,2ETON;wekStuptuO 04sp
t
)pp(ks4,3ETON;wekStraP-ot-traP 006sp
t
R
emiTesiRtuptuOzHM05@%08ot%02051054sp
t
F
emiTllaFtuptuOzHM05@%08ot%02051054sp
cdoelcyCytuDtuptuO540555%
.esiwrehtodetonsselnu,zHM005taderusaemsretemarapl
lA
.tniopgnissorctuptuolaitnereffidehtottniopgnissorctupnilaitnereffidehtmorfderusaeM:1ETON
.snoitidnoc
daollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON
.stniopssorclaitnereffidtuptuo
ehtderusaeM
segatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON
derusae
merastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqehtiwdna
.stniopssorclaitnereffi
dehtta
.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON
TABLE 4D. LVPECL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
tnerruChgiHtupnI KLCPV
DD
V=
NI
V564.3=051Aµ
KLCPnV
DD
V=
NI
V564.3=5Aµ
I
LI
tnerruCwoLtupnI KLCPV
DD
V,V564.3=
NI
V0=5-Aµ
KLCPnV
DD
V,V564.3=
NI
V0=051-Aµ
V
PP
egatloVtupnIkaeP-ot-kaeP 3.01V
V
RMC
2,1ETON;egatloVtupnIedoMnommoC 5.1V
DD
V
VsadenifedsiegatlovedomnommoC:1ETON
HI
.
VsiKLCPndnaKLCProfegatlovtupnimumixameht,snoitacilppadedneelgnisroF:2ETON
DD
.V3.0+
TABLE 4E. LVDS DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DO
egatloVtuptuOlaitnereffiD002082063Vm
∆V
DO
egnahCedutingaMDOV 004Vm
V
SO
egatloVtesffO521.152.1573.1V
∆V
SO
egnahCedutingaMSOV 552Vm
I
ZO
tnerruCegakaeLecnadepmIhgiH01-01+Aµ
I
FFO
egakaeLffOrewoP02-1±02+Aµ
I
DSO
tnerruCtiucriCtrohStuptuOlaitnereffiD 5.3-5-Am
I
SO
tnerruCtiucriCtrohStuptuO 5.3-5-Am
V
HO
hgiHegatloVtuptuO 43.16.1V
V
LO
woLegatloVtuptuO9.060.1V
8543BGI www.icst.com/products/hiperclocks.html REV. C JANUARY 5, 2004
6
Integrated
Circuit
Systems, Inc.
ICS8543I
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
DIFFERENTIAL INPUT LEVEL3.3V OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
nQx
LVD S
3.3V±5%
Power Supply
+-
Float GND
3.3V
DIFFERENTIAL OUTPUT LEVEL
V
CMR
Cross Points
V
PP
GND
CLK,
PCLK
nCLK,
nPCLK
VDD
PART-TO-PART SKEW
PROPAGATION DELAY
OUTPUT RISE/FALL TIME
Clock
Outputs 20%
80% 80%
20%
t
R
t
F
V
OD
t
sk(o)
Qx
Qy
OUTPUT SKEW
t
sk(pp)
PART 1
PART 2
CLK,
PCLK
t
PD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
Pulse Width
tPERIOD
tPW
tPERIOD
odc =
Q0:Q3
nCLK,
nPCLK
nQx
nQy
Qx
Qy
nQx
nQy
nQ0:nQ3
Q0:Q3
nQ0:nQ3
V
OS
Cross Points
V
OD
GND
Q0:Q3
nQ0:nQ3
VDD
8543BGI www.icst.com/products/hiperclocks.html REV. C JANUARY 5, 2004
7
Integrated
Circuit
Systems, Inc.
ICS8543I
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
DIFFERENTIAL OUTPUT VOLTAGE SETUPOFFSET VOLTAGE SETUP
HIGH IMPEDANCE LEAKAGE CURRENT SETUP
OUTPUT SHORT CIRCUIT CURRENT SETUP POWER OFF LEAKAGE SETUP
DIFFERENTIAL OUTPUT SHORT CIRCUIT SETUP
out
out
LVDS
DC Input
➤
➤
➤
V
OS
/∆ V
OS
V
DD
➤
➤
➤
100
out
out
LVDS
DC Input V
OD
/∆ V
OD
V
DD
out
out
LVDS
DC Input
➤
I
OSD
V
DD
out
LVDS
DC Input
➤
IOS
➤
IOSB
VDD
out
LVDS
➤
I
OFF
V
DD
out
out
LVDS
DC Input
➤
➤
3.3V±5% POWER SUPPLY
Float GND
+_
IOZ
IOZ
8543BGI www.icst.com/products/hiperclocks.html REV. C JANUARY 5, 2004
8
Integrated
Circuit
Systems, Inc.
ICS8543I
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
APPLICATION INFORMATION
Figure 2
shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
R2
1K
VDD
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
8543BGI www.icst.com/products/hiperclocks.html REV. C JANUARY 5, 2004
9
Integrated
Circuit
Systems, Inc.
ICS8543I
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in
Figure 3A,
the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
8543BGI www.icst.com/products/hiperclocks.html REV. C JANUARY 5, 2004
10
Integrated
Circuit
Systems, Inc.
ICS8543I
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP
and VCMR input requirements.
Figures 4A to 4D
show inter-
face examples for the HiPerClockS PCLK/nPCLK input driven
by the most common driver types. The input interfaces sug-
gested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please con-
sult with the vendor of the driver component to confirm the
driver termination requirements.
FIGURE 4A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A CML DRIVER
FIGURE 4B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY AN SSTL DRIVER
FIGURE 4C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
PCLK/nPCLK
2.5V
Zo = 60 Ohm
SSTL
HiPerClockS
PCLK
nPCLK
R2
120
3.3V
R3
120
Zo = 60 Ohm
R1
120
R4
120
2.5V
FIGURE 4E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
HiPerClockS
PCLK
nPCLK
PCLK/nPCLK
3.3V
R2
50
R1
50
3.3V
Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
3.3V
HiPerClockS
PCLK
nPCLK
R2
84
R3
125
Input
Zo = 50 Ohm
R4
125
R1
84
LVPECL
3.3V
3.3V
Zo = 50 Ohm
C2
R2
1K
R5
100
Zo = 50 Ohm
3.3V
3.3V
C1
R3
1K
LVDS
R4
1K
HiPerClockS
PCLK
nPCLK
R1
1K
Zo = 50 Ohm
3.3V
PCLK/nPCLK
3.3V
R5
100 - 200
3.3V
3.3V
HiPerClockS
PCLK
nPCLK
R1
125
PCLK/nPCLK
R2
125
R3
84
C1
C2
Zo = 50 Ohm
R4
84
Zo = 50 Ohm
R6
100 - 200
3.3V LVPECL
8543BGI www.icst.com/products/hiperclocks.html REV. C JANUARY 5, 2004
11
Integrated
Circuit
Systems, Inc.
ICS8543I
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS8543I is: 636
TABLE 6. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
3.3V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω differ-
ential transmission line environment, LVDS drivers require a
matched load termination of 100Ω across near the receiver in-
FIGURE 5. TYPICAL LVDS DRIVER TERMINATION
put. For a multiple LVDS outputs buffer, if only partial outputs
are used, it is recommended to terminate the un-used outputs.
100 Ohm Differiential Transmission Line
R1
100
3.3V
+
-
LVDS_Driv er
3.3V
100ΩΩ
ΩΩ
Ω Differential Transmission Line
8543BGI www.icst.com/products/hiperclocks.html REV. C JANUARY 5, 2004
12
Integrated
Circuit
Systems, Inc.
ICS8543I
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MO-153
lobmyS sretemilliM
muminiMmumixaM
N02
A--02.1
1A50.051.0
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b91.003.0
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8543BGI www.icst.com/products/hiperclocks.html REV. C JANUARY 5, 2004
13
Integrated
Circuit
Systems, Inc.
ICS8543I
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
TABLE 8. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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8543BGI www.icst.com/products/hiperclocks.html REV. C JANUARY 5, 2004
14
Integrated
Circuit
Systems, Inc.
ICS8543I
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
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