September 2011
© 2000 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7SZ57 • NC7SZ58 • Rev. 1.0.4
NC7SZ57 / NC7SZ58 — TinyLogic® UHS Universal Configuration Two-Input Logic Gates
NC7SZ57 / NC7SZ58
TinyLogic® UHS Universal Configurable Two-Input
Logic Gates
Features
Ultra High Speed
Capable of Implementing any Two-Input Logic
Functions
Typical Usage Replaces Two (2) TinyLogic® Gate
Devices
Reduces Part Counts in Inventory
Broad VCC Operating Range: 1.65V to 5.5V
Power Down High Impedance Input/Output
Over-Voltage Tolerant Inputs Facilitate 5V to 3V
Translation
Proprietary Noise/EMI Reduction Circuitry
Implemented
Description
The NC7SZ57 and NC7SZ58 are universal configurable
two-input logic gates. Each device is capable of being
configured for 1 of 5 unique two-input logic functions.
Any possible two-input combinatorial logic function can
be implemented, as shown in the Function Selection
Table. Device functionality is selected by how the device
is wired at the board level. Figures 4 through 13
illustrate how to connect the NC7SZ57 and NC7SZ58,
respectively, for the desired logic function. All inputs
have been implemented with hysteresis.
The device is fabricated with advanced CMOS
technology to achieve ultra high speed with high output
drive while maintaining low static power dissipation over
a broad VCC operating range. The device is specified to
operate over the 1.65V to 5.5V VCC operating range.
The input and output are high impedance when VCC is
0V. Inputs tolerate voltages up to 5.5V independent of
VCC operating range.
Ordering Information
Part Number Top Mark Package Packing Method
NC7SZ57P6X Z57 6-Lead SC70, EIAJ SC-88a, 1.25mm Wide 3000 Units on Tape & Reel
NC7SZ57L6X KK 6-Lead Micropak™, 1.0mm Wide 5000 Units on Tape & Reel
NC7SZ57FHX KK 6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch
NC7SZ58P6X Z58 6-Lead SC70, EIAJ SC-88a, 1.25mm Wide 3000 Units on Tape & Reel
NC7SZ58L6X LL 6-Lead Micropak™, 1.0mm Wide 5000 Units on Tape & Reel
NC7SZ58FHX LL 6-Lead, MicroPak2™ , 1x1mm Body, .35mm Pitch
© 2000 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7SZ57 • NC7SZ58 • Rev. 1.0.4 2
NC7SZ57 / NC7SZ58 — TinyLogic
®
UHS Universal Configuration Two-Input Logic Gates
Pin Configurations
Figure 1. SC70 (Top View) Figure 2. MicroPak™ (Top Through View)
Figure 3. Pin 1 Orientation
Notes:
1. AAA represents product code top mark (see Ordering Information).
2. Orientation of top mark determines pin one location.
3. Reading the top mark left to right, pin one is the lower left pin.
Pin Definitions
Pin # SC70 Pin # MicroPak™ Name Description
1 1 I1 Data Input
2 2 GND Ground
3 3 I0 Data Input
4 4 Y Output
5 5 VCC Supply Voltage
6 6 I2 Data Input
© 2000 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7SZ57 • NC7SZ58 • Rev. 1.0.4 3
NC7SZ57 / NC7SZ58 — TinyLogic
®
UHS Universal Configuration Two-Input Logic Gates
Function Table
Inputs NC7SZ57 NC7SZ58
I2 I
1 I
0 Y = (I0) • (I2) + (I1) • (I 2) Y = (I0) • (I2) + (I1) • (I2)
L L L H L
L L H L H
L H L H L
L H H L H
H L L L H
H L H L H
H H L H L
H H H H L
H = HIGH Logic Level
L = LOW Logic Level
Function Selection Table
2-Input Logic Function Device Selection Connection Configuration
2-Input AND NC7SZ57 Figure 4
2-Input AND with Inverted Input NC7SZ58 Figure 10, Figure 11
2-Input AND with Both Inputs Inverted NC7SZ57 Figure 7
2-Input NAND NC7SZ58 Figure 9
2-Input NAND with Inverted Input NC7SZ57 Figure 5, Figure 6
2-Input NAND with Both Inputs Inverted NC7SZ58 F igure 12
2-Input OR NC7SZ58 F igure 12
2-Input OR with Inverted Input NC7SZ57 Figure 5, Figure 6
2-Input OR with Both Inputs Inverted NC7SZ58 Figure 9
2-Input NOR NC7SZ57 Figure 7
2-Input NOR with Inverted Input NC7SZ58 Figure 9, Figure 10
2-Input NOR with Both Inputs Inverted NC7SZ57 Figure 4
2-Input XOR NC7SZ58 Figure 13
2-Input XNOR NC7SZ57 Figure 8
© 2000 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7SZ57 • NC7SZ58 • Rev. 1.0.4 4
NC7SZ57 / NC7SZ58 — TinyLogic
®
UHS Universal Configuration Two-Input Logic Gates
NC7SZ57 Logic Configurations
Figure 4 through Figure 8 show the logical functions that
can be implemented using the NC7SZ57. The diagrams
show the DeMorgan’s equivalent logic duals for a given
two-input function. The logical implementation is next to
the board-level physical implementation of how the pins
of the function should be connected.
Figure 4. 2-Input AND Gate Figure 5. 2-Input NAND with Inverted A Input
Figure 6. 2-Input NAND with Inverted B Input Figure 7. 2-Input NOR Gate
Figure 8. 2-Input XNOR Gate
© 2000 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7SZ57 • NC7SZ58 • Rev. 1.0.4 5
NC7SZ57 / NC7SZ58 — TinyLogic
®
UHS Universal Configuration Two-Input Logic Gates
NC7SZ58 Logic Configurations
Figure 9 through Figure 13 show the logical functions
that can be implemented using the NC7SZ58. The
diagrams show the DeMorgan’s equivalent logic duals
for a given two-input function. The logical
implementation is next to the board-level physical
implementation of how the pins of the function should be
connected.
Figure 9. 2-Input NAND Gate Figure 10. 2-Input AND with Inverted A Input
Figure 11. 2-Input AND with Inverted B Input Figure 12. 2-Input OR Gate
Figure 13. 2-Input XOR Gate
© 2000 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7SZ57 • NC7SZ58 • Rev. 1.0.4 6
NC7SZ57 / NC7SZ58 — TinyLogic
®
UHS Universal Configuration Two-Input Logic Gates
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol Parameter Min. Max. Units
VCC Supply Voltage -0.5 7.0 V
VIN DC Input Voltage -0.5 7.0 V
VOUT DC Output Voltage -0.5 7.0 V
IIK DC Input Diode Current VIN < 0.5V -50 mA
IOK DC Output Diode Current VOUT < -0.5V -50 mA
IOUT DC Output Source / Sink Current ±50 mA
ICC or IGND DC VCC or Ground Current ±50 mA
TSTG Storage Temperature Range -65 +150 °C
TJ Maximum Junction Temperature under Bias +150 °C
TL Lead Temperature, Soldering 10 Seconds +260 °C
PD Power Dissipation at +85°C MicroPak™-6 130
mW SC70-6 180
MicroPak2™-6 120
ESD Human Body Model, JEDEC:JESD22-A114 4000 V
Charged Device Model, JEDEC:JESD22-C101 2000
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol Parameter Conditions Min. Max. Units
VCC Supply Voltage Operating 1.65 5.5 V
Supply Voltage Data Retention 1.5 5.5
VIN Input Voltage 0 5.5 V
VOUT Output Voltage 0 VCC V
TA Operating Temperature -40 +85 °C
JAThermal Resistance SC70-6 350
°C/W
MicroPak™-6 500
MicroPak2™-6 560
© 2000 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7SZ57 • NC7SZ58 • Rev. 1.0.4 7
NC7SZ57 / NC7SZ58 — TinyLogic
®
UHS Universal Configuration Two-Input Logic Gates
DC Electrical Characteristics
Symbo
l Parameter VCC Conditions TA=+25°C TA=-40 to +85°C Units
Min. Typ. Max. Min. Max.
VP Positive
Threshold
Voltage
1.65
0.60 0.99 1.40 0.60 1.40
V
2.30 1.00 1.39 1.80 1.00 1.80
3.00 1.30 1.77 2.20 1.30 2.20
4.50 1.90 2.49 3.10 1.90 3.10
5.50 2.20 2.95 3.60 2.20 3.60
VN Negative
Threshold
Voltage
1.65
0.20 0.50 0.90 0.20 0.90
V
2.30 0.40 0.75 1.15 0.40 1.15
3.00 0.60 0.99 1.50 0.60 1.50
4.50 1.00 1.43 2.00 1.00 2.00
5.50 1.20 1.70 2.30 1.20 2.30
VH Hysteresis
Voltage
1.65
0.15 0.48 0.90 0.15 0.90
V
2.30 0.25 0.64 1.10 0.25 1.10
3.00 0.40 0.78 1.20 0.40 1.20
4.50 0.60 1.06 1.50 0.60 1.50
5.50 0.70 1.25 1.70 0.70 1.70
VOH HIGH Level
Output Voltage
1.65
VIN=VIH or VIL
IOH= -100µA
1.55 1.65 1.55
V
2.30 2.20 2.30
2.20
3.00 2.90 3.00
2.90
4.50 4.40 4.50
4.40
1.65
VIN=VIH
or VIL
IOH= -4mA 1.29 1.52 1.29
2.30 IOH= -8mA 1.90 2.15 1.90
3.00 IOH= -16mA 2.40 2.80 2.40
3.00 IOH= -24mA 2.30 2.68 2.30
4.50 IOH= -32mA 3.80 4.20 3.80
Continued on the following page…
© 2000 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7SZ57 • NC7SZ58 • Rev. 1.0.4 8
NC7SZ57 / NC7SZ58 — TinyLogic
®
UHS Universal Configuration Two-Input Logic Gates
DC Electrical Characteristics (Continued)
Symbol Parameter VCC Conditions TA=+25°C TA=-40 to +85°C Units
Min. Typ. Max. Min. Max.
VOL LOW Level
Output Voltage
1.65
VIN=VIH or VIL
IOL=100µA
0.10 0.10
V
2.30 0.10 0.10
3.00 0.10 0.10
4.50 0.10 0.10
1.65
VIN=VIH or
VIL
IOL=4mA 0.08 0.24 0.24
2.30 IOL=8mA 0.10 0.30 0.30
3.00 IOL=16mA 0.15 0.40 0.40
3.00 IOL=24mA 0.22 0.55 0.55
4.50 IOL=32mA 0.22 0.55 0.55
IIN Input Leakage
Current 0 to
5.50 VIN 5.5V, GND ±0.1 ±1.0 µA
IOFF Power Off
Leakage
Current 0 VIN or VOUT 5.5V 1 10 µA
ICC Quiescent
Supply Current 1.65 to
5.5 VIN 5.5V, GND 1 10 µA
AC Electrical Characteristics
Symbol Parameter VCC Conditions
TA=25°C TA=-40 to 85°C Units Figure
Min. Typ. Max. Min. Max.
tPHL, tPLH Propagation
Delay In to Y
1.8 ± 0.15
CL=15pF, RL=1M
3.0 8.0 14.0 3.0 14.5
ns Figure 14
Figure 16
2.5 ± 0.2 1.5 4.9 8.0 1.5 8.5
3.3 ± 0.3 1.2 3.7 5.3 1.2 5.7
5.0 ± 0.5 0.8 2.8 4.3 0.8 4.6
3.3 ± 0.3 CL=50pF,
RL=500 1.5 4.2 6.0 1.5 6.5
5.0 ± 0.5 1.0 3.4 4.9 1.0 5.3
CIN Input
Capacitance 0 2 pF
CPD Power
Dissipation
Capacitance
3.3 Note 4 14 pF Figure 15
5.0 17
Note:
4. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating
current consumption (ICCD) at no output loading and operating at 50% duty cycle. (See Figure 12) CPD is related
to ICCD dynamic operatic current by the expression: ICCD = (CPD)(VCC)(fin) + (ICCstatic).
© 2000 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7SZ57 • NC7SZ58 • Rev. 1.0.4 9
NC7SZ57 / NC7SZ58 — TinyLogic
®
UHS Universal Configuration Two-Input Logic Gates
AC Loadings and Waveforms
Note:
5. CL includes load and stray capacitance.
6. Input PRR = 1.0MHz, tW = 500ns. Figure 14. AC Test Circuit
Note:
7. Input = AC waveforms.
8. PRR = Variable; Duty Cycle = 50%. Figure 15. ICCD Test Circuit
Figure 16. AC Waveforms
© 2000 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7SZ57 • NC7SZ58 • Rev. 1.0.4 10
NC7SZ57 / NC7SZ58 — TinyLogic
®
UHS Universal Configuration Two-Input Logic Gates
Physical Dimensions
DETAIL A
SCALE: 60X
B
1.90
2.00±0.20
0.50 MIN
1.00
0.80
1.10
0.80
0.10 C
0.25
0.10
0.46
0.26
0.20
GAGE
PLANE (R0.10)
30°
0°
SEATING
PLANE
C0.10
0.00
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO EIAJ
SC-88, 1996.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH.
D) DRAWING FILENAME: MKT-MAA06AREV6
2.10±0.30
0.10 AB
0.65
1.30
(0.25) 0.30
0.15
1
1.25±0.10
3
1.30 0.40 MIN
SEE DETAIL A
LAND PATTERN RECOMMENDATION
6
A
4
C
0.65 L
SYMM
PIN ONE
Figure 17. 6-Lead, SC70, EIAJ SC-88a, 1.25mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specifications
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/products/analog/pdf/sc70-6_tr.pdf
Package Designator Tape Section Cavity Number Cavity Status Cover Type Status
P6X Leader (Start End) 125 (Typical) Empty Sealed
Carrier 3000 Filled Sealed
Trailer (Hub End) 75 (Typical) Empty Sealed
© 2000 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7SZ57 • NC7SZ58 • Rev. 1.0.4 11
NC7SZ57 / NC7SZ58 — TinyLogic
®
UHS Universal Configuration Two-Input Logic Gates
Physical Dimensions
2. DIMENSIONS ARE IN MILLIMETERS
1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD
4. FILENAME AND REVISION: MAC06AREV4
Notes:
3. DRAWING CONFORMS TO ASME Y14. 5M- 1994
TOP VIEW
RECOMMENED
LAND PATTERN
BOTTOM VIEW
1.45
1.00
A
B
0.05 C
0.05 C
2X
2X
0.55MAX
0.05 C
(0.49)
(1)
(0.75)
(0.52)
(0.30)
6X
1X
6X
PIN 1
DETAIL A
0.075 X 45
CHAMFER
0.25
0.15
0.35
0.25
0.40
0.30
0.5
(0.05)
1.0
5X
DETAIL A
PIN 1 TERMINAL
0.40
0.30
0.45
0.35
0.10
0.00
0.10 CBA
0.05 C
C0.05 C
0.05
0.00
5X
5X
6X (0.13)
4X
6X
PIN 1 IDENTIFIER
(0.254)
5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY
5
OTHER LINE IN THE MARK CODE LAYOUT.
Figure 18. 6-Lead, MicroPak™, 1.0mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specifications
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.
Package Designator Tape Section Cavity Number Cavity Status Cover Type Status
L6X Leader (Start End) 125 (Typical) Empty Sealed
Carrier 5000 Filled Sealed
Trailer (Hub End) 75 (Typical) Empty Sealed
© 2000 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7SZ57 • NC7SZ58 • Rev. 1.0.4 12
NC7SZ57 / NC7SZ58 — TinyLogic
®
UHS Universal Configuration Two-Input Logic Gates
Physical Dimensions
1.00
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994
NOTES:
A. COMPLIES TO JEDEC MO-252 STANDARD
0.05 CA
B
0.55MAX
0.05 C
C
0.35
0.09
0.19
123
0.35
0.25
5X
6X
DETAIL A
0.60
(0.08)
4X
(0.05) 6X
0.40
0.30
0.075X45°
CHAMFER
5X 0.40
0.35
1X 0.45
6X 0.19
TOP VIEW
BOTTOM VIEW
0.66
0.10 CBA
.05 C
0.89
PIN 1
0.05 C
2X
2X 1.00
D. LANDPATTERN RECOMMENDATION IS BASED ON FSC
E. DRAWING FILENAME AND REVISION: MGF06AREV3
0.52
0.73
0.57
0.20 6X
1X
5X
RECOMMENDED LAND PATTERN
FOR SPACE CONSTRAINED PCB
DETAIL A
PIN 1 LEAD SCALE: 2X
ALTERNATIVE LAND PATTERN
FOR UNIVERSAL APPLI CATION
DESIGN.
0.90
MIN 250uM
654
0.35
(0.08) 4X
SIDE VIEW
Figure 19. 6-L ead , MicroPak2™, 1x1mm Body, .35mm Pitch
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specifications
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf.
Package Designator Tape Section Cavity Number Cavity Status Cover Type Status
FHX Leader (Start End) 125 (Typical) Empty Sealed
Carrier 5000 Filled Sealed
Trailer (Hub End) 75 (Typical) Empty Sealed
© 2000 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7SZ57 • NC7SZ58 • Rev. 1.0.4 13
NC7SZ57 / NC7SZ58 — TinyLogic
®
UHS Universal Configuration Two-Input Logic Gates
