74VHC138MTCX - FAIRCHILD SEMICONDUCTOR

November 1992

Revised April 1999

74VHC138 3-to-8 Decoder/Demultiplexer

74VHC138

3-to-8 Decoder/Demultiplexer

General Descript ion

The VHC138 is an advanced high speed CMOS 3-to-8

decoder/demultiplexer fabricated with silicon gate CMOS

technolo gy. It achie ves the high sp eed opera tion similar to

equivalent Bipolar Schottky TTL while maintaining the

CMOS low power dissipation.

When the de vice is enabled , 3 binary select i nputs (A0, A1

and A2) determine which one of the outputs (O0–O7) will go

LOW. When enable input E3 is held LOW or either E1 or E2

is held HIGH, de coding fun ction is inhib ited and all outputs

go HIGH. E3, E1 and E2 inputs are provided to ease cas-

cade connection and for use as an address decoder for

memory systems. An input protection circuit ensures that

0V to 7V can be app lied to the inpu t pins without re gard to

the supply voltage. This device can be used to interface 5V

to 3V systems and two supply systems such as battery

back up. This circuit prevents device destruction due to

mismatched supply and input voltages.

Features

■High Speed: tPD = 5.7n s (typ) at TA = 25°C

■Low power dissipation: ICC = 4 µA (max.) at TA = 25°C

■High noise immunity: VNIH = VNIL = 28% VCC (min.)

■Power down protection provided on all inputs

■Pin and function compatible with 74HC138

Ordering Code:

Surface m ount pa c k ages are als o availa ble on Tape and Reel. Specify by appendi ng the suffix let te r “X” to the ordering co de.

Logic Symbols

IEEE/IEC

Connection Diagram

Pin Descripti ons

Order Number Package Number Package Description

74VHC138M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

74VHC138SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC138MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74VHC138N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Pin Names Description

A0–A2Address Inputs

E1–E2Enable Inputs

E3Enable Input

O0–O7Outputs

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74VHC138

Truth Table

H = HIGH Voltage Le ve l

L = LOW Voltage Level

X = Immaterial

Inputs Outputs

E1E2E3A0A1A2O0O1O2O3O4O5O6O7

HXXXXXHHHHHHHH

XHXXXXHHHHHHHH

XXLXXXHHHHHHHH

LLHLLLLHHHHHHH

LLHHLLHLHHHHHH

LLHLHLHHLHHHHH

LLHHHLHHHLHHHH

LLHLLHHHHHLHHH

LLHHLHHHHHHLHH

LLHLHHHHHHHHLH

LLHHHHHHHHHHHL

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74VHC138

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions (Note 2)

Note 1: Absolute Maximum Ratings are values beyond which the device

may be da maged or ha ve its useful life impaire d. The datab ook specific a-

tions should be met, without exception, to ensure that the system design is

reliable over its pow er supply, temperatu re, and out put/input loa ding vari-

ables. Fairchild does not recommend operation outside databook specifica-

tions.

Note 2: Unused inputs must be held HIGH or LOW. They may not float.

DC Electrical Characteristics

Supply Voltage (VCC)−0.5V to +7.0V

DC Input Voltage (VIN)−0.5V to +7.0V

DC Output V oltage (VOUT)−0.5V to VCC + 0.5V

Input Diode Current (IIK)−20 mA

Output Diode Current (IOK)±20 mA

DC Output Current (IOUT)±25 mA

DC VCC/GND Current (ICC)±75 mA

Stora ge Temperature (TSTG)−65°C to +150°C

Lead Temperat ure (TL)

(Soldering, 10 seconds) 260°C

Supply Voltage (VCC)2.0V to +5.5V

Input Voltage (VIN)0V to +5.5V

Output Voltage (VOUT)0V to V

Operating Temperature (TOPR)−40°C to +85°C

Input Rise and Fall Time (tr, tf)

VCC = 3.3V ± 0.3V 0 ∼ 100 ns/V

VCC = 5.0V ± 0.5V 0 ∼ 20 ns/V

Symbol Parameter VCC

(V)

TA = 25°CT

A = −40°C to +85°CUnits Conditions

Min Typ Max Min Max

VIH HIGH Level Input V oltag e 2.0 1.50 1.50 V

3.0 − 5.5 0.7 VCC 0.7 VCC

VIL LOW Level Input Voltage 2.0 0.50 0.50 V

3.0 − 5.5 0.3 VCC 0.3 VCC

VOH HIGH Level Output Voltage 2.0 1.9 2.0 1.9 VIN = VIH IOH = −50 µA

3.0 2.9 3.0 2.9 V or VIL

4.5 4.4 4.5 4.4

3.0 2.58 2.48 VIOH = −4 mA

4.5 3.94 3.80 IOH = −8 mA

VOL LOW Level Output Voltage 2.0 0.0 0.1 0.1 VIN = VIH IOL = 50 µA

3.0 0.0 0.1 0.1 V or VIL

4.5 0.0 0.1 0.1

3.0 0.36 0.44 VIOL = 4 mA

4.5 0.36 0.44 IOL = 8 mA

IIN Input Leakage Current 0 − 5.5 ±0.1 ±1.0 µAV

IN = 5.5V or GND

ICC Quiescent Supply Current 5.5 4.0 40.0 µAV

IN = VCC or GND

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74VHC138

AC Electrical Characteristics

Note 3: CPD is defined as th e v alue of th e interna l equivalent capacitance which is calculated fro m t he operating cur rent cons umptio n w it hout loa d. Av erage

operat ing cur rent can be obt ained by th e equat ion: ICC (opr.) = CPD * VCC * fIN + ICC.

Symbol Parameter VCC

(V)

TA = 25°CT

A = −40°C to +85°CUnits Conditions

Min Typ Max Min Max

tPLH Propagati on Delay 3.3 ± 0.3 8.2 1 1.4 1.0 13.5 ns CL = 15 pF

tPHL An to On10.0 15.8 1.0 18.0 CL = 50 pF

5.0 ± 0.5 5.7 8.1 1.0 9.5 ns CL = 15 pF

7.2 10.1 1.0 11.5 CL = 50 pF

tPLH Propagati on Delay 3.3 ± 0.3 8.1 12.8 1.0 15.0 ns CL = 15 pF

tPHL E3 to On10.6 16.3 1.0 18.5 CL = 50 pF

5.0 ± 0.5 5.6 8.1 1.0 9.5 ns CL = 15 pF

7.1 10.1 1.0 11.5 CL = 50 pF

tPLH Propagati on Delay 3.3 ± 0.3 8.2 1 1.4 1.0 13.5 ns CL = 15 pF

tPHL E1 or E2 to On10.7 14.9 1.0 17.0 CL = 50 pF

5.0 ± 0.5 5.8 8.1 1.0 9.5 ns CL = 15 pF

7.3 10.1 1.0 11.5 CL = 50 pF

CIN Input Capacitance 4 10 10 pF VCC = Open

CPD Power Dissipation 34 pF (Note 3)

Capacitance

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74VHC138

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

Package Number M16A

16-Lead Sma ll Outline Packa ge (SOP) EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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74VHC138

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC16

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

74VHC138 3-to-8 Decoder/Dem ultiplexer

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the labe l ing, can be re a-

sonably expected to result in a significant injury to the

user.

2. A criti cal com ponen t in any compo nent o f a l ife supp ort

device or system whose failure to perform can be rea-

sonabl y e xpec ted to c ause th e fa i lure of the li fe s upp or t

device or system, or to affect its safety or effectiveness.

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N16E