1
LTC1293/LTC1294/LTC1296
Single Chip 12-Bit
Data Acquisition System
The LTC1293/4/6 is a family of data acquisition systems
which contain a serial I/O successive approximation A/D
converter. It uses LTCMOSTM switched capacitor technol-
ogy to perform either 12-bit unipolar, or 11-bit plus sign
bipolar A/D conversions. The input multiplexer can be
configured for either single ended or differential inputs (or
combinations thereof). An on-chip sample and hold is
included for all single ended input channels. When the
LTC1293/4/6 is idle it can be powered down in applica-
tions where low power consumption is desired. The
LTC1296 includes a System Shutdown Output pin which
can be used to power down external circuitry, such as
signal conditioning circuitry prior to the input mux.
The serial I/O is designed to communicate without external
hardware to most MPU serial ports and all MPU parallel
I/O ports allowing up to eight channels of data to be
transmitted over as few as three wires.
D
U
ESCRIPTIO
S
FEATURE
■
Software Programmable Features
Unipolar/Bipolar Conversion
Differential/Single Ended Inputs
MSB-First or MSB/LSB Data Sequence
Power Shutdown
■
Built-In Sample and Hold
■
Single Supply 5V or ±5V Operation
■
Direct 4-Wire Interface to Most MPU Serial
Ports and All MPU Parallel Ports
■
46.5kHz Maximum Throughput Rate
■
System Shutdown Output (LTC1296)
■
Resolution ..................................................... 12 Bits
■
Fast Conversion Time ............ 12µs Max Over Temp.
■
Low Supply Current........................................ 6.0mA
KEY SPECIFICATIO S
U
U
A
O
PPLICATITYPICAL
12-Bit Data Acquisition System with Power Shutdown
LTCMOS
TM
is a trademark of Linear Technology Corporation
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DGND
–
+
R
B
5.1k
R2
1.2M
R1
10k 1/4 LT1014
R2
1.2M
C2
1µF
350Ω STRAIN
GAUGE BRIDGE
+5V
47µF
1N4148
MPU
LTC1296
V
CC
SSO
CLK
CS
D
OUT
D
IN
REF
+
REF
–
AGND
V
–
THREE ADDITIONAL STRAIN GAUGE INPUTS
CAN BE ACCOMMODATED USING THE OTHER
AMPLIFIERS IN THE LT1014
LTC1293 TA01
2N3906
74HC04
2
LTC1293/LTC1294/LTC1296
A
U
G
W
A
W
U
W
ARBSOLUTEXI T
I
S
Supply Voltage (V
CC
) to GND or V
–
................................................... 12V
Negative Supply Voltage (V
–
) ..................... –6V to GND
Voltage
Analog and Reference
Inputs............................ (V
–
) –0.3V to V
CC
+ 0.3V
Digital Inputs .........................................–0.3V to 12V
Digital Outputs........................... –0.3V to V
CC
+ 0.3V
Power Dissipation............................................. 500mW
Operating Temperature Range
LTC1293/4/6BC, LTC1293/4/6CC,
LTC1293/4/6DC ....................................... 0°C to 70°C
LTC1293/4/6BI, LTC1293/4/6CI,
LTC1293/4/6DI ....................................–40°C to 85°C
LTC1293/4/6BM, LTC1293/4/6CM,
LTC1293/4/6DM ............................... –55°C to 125°C
Storage Temperature Range ..................–65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................ 300°C
(Note 1 and 2)
WU
U
PACKAGE/ORDER I FOR ATIO
LTC1293BCS
LTC1293CCS
LTC1293DCS
ORDER PART
NUMBER ORDER PART
NUMBER
LTC1293BMJ
LTC1293CMJ
LTC1293DMJ
LTC1293BIJ
LTC1293CIJ
LTC1293DIJ
LTC1293BIN
LTC1293CIN
LTC1293DIN
LTC1293BCN
LTC1293CCN
LTC1293DCN
LTC1294BCS
LTC1294CCS
LTC1294DCS
LTC1296BCS
LTC1296CCS
LTC1296DCS
LTC1294BIN
LTC1294CIN
LTC1294DIN
LTC1294BCN
LTC1294CCN
LTC1294DCN
LTC1294BMJ
LTC1294CMJ
LTC1294DMJ
LTC1294BIJ
LTC1294CIJ
LTC1294DIJ
LTC1296BIN
LTC1296CIN
LTC1296DIN
LTC1296BCN
LTC1296CCN
LTC1296DCN
LTC1296BMJ
LTC1296CMJ
LTC1296DMJ
LTC1296BIJ
LTC1296CIJ
LTC1296DIJ
1
2
3
4
5
6
7
8
9
10
TOP VIEW
S PACKAGE
20-LEAD PLASTIC SO
20
19
18
17
16
15
14
13
12
11
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DGND
DV
CC
AV
CC
CLK
CS
D
OUT
D
IN
REF
+
REF
–
AGND
V
–
1
2
3
4
5
6
7
8
TOP VIEW
S PACKAGE
16-LEAD PLASTIC SOL
16
15
14
13
12
11
10
9
CH0
CH1
CH2
CH3
CH4
CH5
COM
DGND
V
CC
CLK
CS
D
OUT
D
IN
V
REF
AGND
V
–
1
2
3
4
5
6
7
8
TOP VIEW
J PACKAGE
16-LEAD CERAMIC DIP N PACKAGE
16-LEAD PLASTIC DIP
16
15
14
13
12
11
10
9
CH0
CH1
CH2
CH3
CH4
CH5
COM
DGND
V
CC
CLK
CS
D
OUT
D
IN
V
REF
AGND
V
–
1
2
3
4
5
6
7
8
9
10
TOP VIEW
J PACKAGE
20-LEAD CERAMIC DIP N PACKAGE
20-LEAD PLASTIC DIP
20
19
18
17
16
15
14
13
12
11
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DGND
V
CC
SSO
CLK
CS
D
OUT
D
IN
REF+
REF–
AGND
V–
1
2
3
4
5
6
7
8
9
10
TOP VIEW
S PACKAGE
20-LEAD PLASTIC SO
20
19
18
17
16
15
14
13
12
11
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DGND
V
CC
SSO
CLK
CS
D
OUT
D
IN
REF
+
REF
–
AGND
V
–
1
2
3
4
5
6
7
8
9
10
TOP VIEW
J PACKAGE
20-LEAD CERAMIC DIP N PACKAGE
20-LEAD PLASTIC DIP
20
19
18
17
16
15
14
13
12
11
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DGND
DV
CC
AV
CC
CLK
CS
D
OUT
D
IN
REF
+
REF
–
AGND
V
–
3
LTC1293/LTC1294/LTC1296
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
Offset Error (Note 4) ●±3.0 ±3.0 ±3.0 LSB
Linearity Error (INL) (Notes 4, 5) ●±0.5 ±0.5 ±0.75 LSB
Gain Error (Note 4) ●±0.5 ±1.0 ±4.0 LSB
Minimum Resolution for which No ●12 12 12 Bits
Missing Codes are Guaranteed
Analog and REF Input Range (Note 7) (V
–
)–0.05V to V
CC
+ 0.05V V
On Channel Leakage Current (Note 8) On Channel = 5V ●±1±1±1µA
Off Channel = 0V
On Channel = 0V ●±1±1±1µA
Off Channel = 5V
Off Channel Lekage Current (Note 8) On Channel = 5V ●±1±1±1µA
Off Channel = 0V
On Channel = 0V ●±1±1±1µA
Off Channel = 5V
(Note 3)
CO VERTER A D ULTIPLEXER CHARACTERISTICS
UU W
LTC1293/4/6C LTC1293/4/6D
LTC1293/4/6B
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
CLK
Clock Frequency V
CC
= 5V (Note 6) 0.1 1.0 MHz
t
SMPL
Analog Input Sample Time See Operating Sequence 2.5 CLK Cycles
t
CONV
Conversion Time See Operating Sequence 12 CLK Cycles
t
CYC
Total Cycle Time See Operating Sequence (Note 6) 21 CLK Cycles
+500ns
t
dDO
Delay Time, CLK↓ to D
OUT
Data Valid See Test Circuits ●160 300 ns
t
dis
Delay Time, CS↑ to D
OUT
Hi-Z See Test Circuits ●80 150 ns
t
en
Delay Time, CLK↓ to D
OUT
Enabled See Test Circuits ●80 200 ns
t
hDI
Hold Time, D
IN
after CLK↑V
CC
= 5V (Note 6) 50 ns
t
hDO
Time Output Data Remains Valid After CLK↓130 ns
t
f
D
OUT
Fall Time See Test Circuits ●65 130 ns
t
r
D
OUT
Rise Time See Test Circuits ●25 50 ns
t
WHCLK
CLK High Time V
CC
= 5V (Note 6) 300 ns
t
WLCLK
CLK Low Time V
CC
= 5V (Note 6) 400 ns
t
suDI
Set-up Time, D
IN
Stable Before CLK↑V
CC
= 5V (Note 6) 50 ns
t
suCS
Set-up Time, CS↓ before CLK↑V
CC
= 5V (Note 6) 50 ns
t
wHCS
CS High Time During Conversion V
CC
= 5V (Note 6) 500 ns
t
wLCS
CS Low Time During Data Transfer V
CC
= 5V (Note 6) 21 CLK Cycles
t
enSSO
Delay Time, CLK↓ to SSO↓See Test Circuits ●750 1500 ns
t
disSSO
Delay Time, CS↓ to SSO↑See Test Circuits ●250 500 ns
C
IN
Input Capacitance Analog Inputs On Channel 100 pF
Analog Inputs Off Channel 5
Digital Inputs 5
LTC1293/4/6B
LTC1293/4/6C
LTC1293/4/6D
AC CHARACTERISTICS (Note 3)
4
LTC1293/LTC1294/LTC1296
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IH
High Level Input Voltage V
CC
= 5.25V ●2.0 V
V
IL
Low Level Input Voltage V
CC
= 4.75V ●0.8 V
I
IH
High Level Input Current V
IN
= V
CC
●2.5 µA
I
IL
Low Level Input Current V
IN
= 0V ●–2.5 µA
V
OH
High Level Output Voltage V
CC
= 4.75V, I
O
= –10mA 4.7 V
I
O
= 360µA●2.4 4.0
V
OL
Low Level Output Voltage V
CC
= 4.75V, I
O
= 1.6mA ●0.4 V
I
OZ
High Z Output Leakage V
OUT =
V
CC
,
CS High ●3µA
V
OUT
= 0V, CS High ●–3
I
SOURCE
Output Source Current V
OUT
= 0V –20 mA
I
SINK
Output Sink Current V
OUT
= V
CC
20 mA
I
CC
Positive Supply Current CS High ●612 mA
I
CC
Positive Supply Current CS High, LTC1294BC, LTC1294CC, ●510 µA
Power LTC1294DC, LTC1294BI,
Shutdown LTC1294CI, LTC1294DI,
CLK Off LTC1294BM, LTC1294CM, ●515 µA
LTC1294DM
I
REF
Reference Current CS High ●10 50 µA
I
–
Negative Supply Current CS High ●150 µA
I
SOURCEs
SSO Source Current V
SSO
= 0V ●0.8 1.5 mA
I
SINKs
SSO Sink Current V
SSO
= V
CC
●0.5 1.0 mA
ELECTRICAL C CHARA TER STICS
DIGITAL AD
U
I
DC
(Note 3)
LTC1293/4/6B
LTC1293/4/6C
LTC1293/4/6D
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to DGND, AGND and REF
–
wired
together (unless otherwise noted).
Note 3: V
CC
= 5V, V
REF
+ = 5V, V
REF
– = 0V, V
–
= 0V for unipolar mode and
–5V for bipolar mode, CLK = 1.0MHz unless otherwise specified. The ●
denotes specifications which apply over the full operating temperature
range; all other limits and typicals T
A
= 25°C.
Note 4: These specs apply for both unipolar and bipolar modes. In bipolar
mode, one LSB is equal to the bipolar input span (2V
REF
) divided by 4096.
For example, when V
REF
= 5V, 1LSB (bipolar) = 2 (5V)/4096 = 2.44mV.
Note 5: Linearity error is specified between the actual end points of the
A/D transfer curve. The deviation is measured from the center of the
quantization band.
Note 6: Recommended operating conditions.
Note 7: Two on-chip diodes are tied to each reference and analog input
which will conduct for reference or analog input voltages one diode drop
below V
–
or one diode drop above V
CC
. Be careful during testing at low
V
CC
levels (4.5V), as high level reference or analog inputs (5V) can cause
this input diode to conduct, especially at elevated temperatures, and cause
errors for inputs near full scale. This spec allows 50mV forward bias of
either diode. This means that as long as the reference or analog input
does not exceed the supply voltage by more than 50mV, the output code
will be correct. To achieve an absolute 0V to 5V input voltage range will
therefore require a minimum supply voltage of 4.950V over initial
tolerance, temperature variations and loading.
Note 8: Channel leakage current is measured after the channel selection.
5
LTC1293/LTC1294/LTC1296
Supply Current vs Temperature
CCHARA TERISTICS
UW
AT
Y
P
I
CALPER
F
O
RC
E
Supply Current vs Supply Voltage
SUPPLY VOLTAGE (V)
4
SUPPLY CURRENT (mA)
4
6
6
LTC1293 G01
2
05
10
8
CLK = 1MHz
T
A
= 25°C
AMBIENT TEMPERATURE (°C)
–50
SUPPLY CURRENT (mA)
7
8
9
30 70
LTC1293 G02
6
5
–30 –10 50 90 110
4
3
10
10 130
CLK = 1MHz
VCC = 5V
REFERENCE VOLTAGE (V)
1
0.5
0.6
5
LTC1293 G03
0.4
0.3
0.1 234
0.2
0.9
0.8
OFFSET (LSB = 1/4096 × V
REF
)
0.7
V
OS
= 0.125mV
V
CC
= 5V
V
OS
= 0.250mV
Unadjusted Offset Voltage vs
Reference Voltage
Change in Linearity vs Reference
Voltage
REFERENCE VOLTAGE (V)
0
CHANGE IN LINEARITY (LSB = 1/4096 × V
REF
)
0.75
1.00
1.25
4
LTC1293 G04
0.50
0.25
01235
Change in Gain vs Reference
Voltage
REFERENCE VOLTAGE (V)
0
–1.2
CHANGE IN GAIN (LSB = 1/4096 × VREF)
–1.0
–0.8
–0.6
–0.4
–0.2
0
1234
LTC1293 G05
5
VCC = 5V
LTC1294/6
LTC1293
Change in Offset vs Temperature
AMBIENT TEMPERATURE (°C)
–50
MAGNITUDE OF OFFSET CHANGE (LSB)
0.3
0.4
0.5
50
LTC1293 G06
0.2
0.1
0–25 025 75 125100
V
CC
= 5V
V
REF
= 5V
CLK = 1MHz
Change in Linearity vs
Temperature Change in Gain vs Temperature Minimum Clock Rate for 0.1LSB
Error
* AS THE CLK FREQUENCY IS DECREASED FROM 1MHz, MINIMUM CLK FREQUENCY (∆ERROR ≤ 0.1LSB) REPRESENTS
THE FREQUENCY AT WHICH A 0.1LSB SHIFT IN ANY CODE TRANSITION FROM ITS 1MHz VALUE IS FIRST DETECTED.
AMBIENT TEMPERATURE (°C)
–50
MAGNITUDE OF LINEARITY CHANGE (LSB)
0.3
0.4
0.5
50
LTC1293 G07
0.2
0.1
0–25 025 75 125100
V
CC
= 5V
V
REF
= 5V
CLK = 1MHz
AMBIENT TEMPERATURE (°C)
–50
MAGNITUDE OF GAIN CHANGE (LSB)
0.3
0.4
0.5
50
LTC1293 G08
0.2
0.1
0–25 025 75 125100
V
CC
= 5V
V
REF
= 5V
CLK = 1MHz
AMBIENT TEMPERATURE (°C)
–50
MINIMUM CLK FREQUENCY* (MHz)
0.15
0.20
0.25
50
LTC1293 G09
0.10
0.05
–25 025 75 125100
V
CC
= 5V
6
LTC1293/LTC1294/LTC1296
LTC1296 SSO Source Current vs
VCC – VSSO
CCHARA TERISTICS
UW
AT
Y
P
I
CALPER
F
O
RC
E
Maximum Clock Rate vs Source
ResistanceDOUT Delay Time vs Temperature
CYCLE TIME (µs)
10
MAXIMUM R
FILTER
** (Ω)
100
1k
10k
10 1k 10k
LTC1293 G12
1100
+
–
+V
IN
C
FILTER
≥1µF
R
FILTER
Maximum Filter Resistor vs Cycle
Time
Sample and Hold Acquisition
Time vs Source Resistance
R
SOURCE
+ (Ω)
100
1
S & H AQUISITION TIME TO 0.02% (µs)
10
100
1000 10000
LTC1292 G13
+
–
V
IN
R
SOURCE
+
V
REF
= 5V
V
CC
= 5V
T
A
= 25°C
0V TO 5V INPUT STEP
Input Channel leakage Current vs
Temperature
AMBIENT TEMPERATURE (°C)
–50
0
INPUT CHANNEL LEAKAGE CURRENT (nA)
100
300
400
500
1000
700
–10 30 50 130
LTC1293 G14
200
800
900
600
–30 10 70 90 110
ON CHANNEL
OFF CHANNEL
GUARANTEED
Noise Error vs Reference Voltage
REFERENCE VOLTAGE (V)
0
0
PEAK-TO-PEAK NOISE ERROR (LSB)
0.25
0.75
1.00
1.25
245
2.25
0.50
13
1.50
1.75
2.00
LTC1293 G15
LTC1293/4/6 NOISE = 200µV
p-p
LTC1296 SSO Sink Current vs
VSSO
100
0.2
MAXIMUM CLK FREQUENCY* (MHz)
0.4
0.6
0.8
1.0
1k 10k 100k
LTC1293 G11
0
V
CC
= 5V
V
REF
= 5V
CLK = 1MHz
R
SOURCE–
(Ω)
+
–
+IN
–IN
+V
IN
R
SOURCE
–
* MAXIMUM CLK FREQUENCY REPRESENTS THE CLK
FREQUENCY AT WHICH A 0.1LSB SHIFT IN THE ERROR
AT ANY CODE TRANSITION FROM ITS 1MHz VALUE IS
FIRST DETECTED.
** MAXIMUM R
FILTER
REPRESENTS THE FILTER RESISTOR
VALUE AT WHICH A 0.1LSB CHANGE IN FULL SCALE ERROR
FROM ITS VALUE AT R
FILTER
= 0Ω IS FIRST DETECTED.
0
I
SINK
(µA)
300
400
500
0.8
LTC1293 G17
200
100
00.2 0.4 0.6 1.0
V
CC
= 5V
V
SSO
VOLTAGE (V)
0
I
SOURCE
(µA)
300
400
500
0.4
LTC1293 G16
200
00.1 0.2 0.3 0.5 0.70.6
V
CC
= 5V
100
V
CC
– V
SSO
VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
–50
D
OUT
DELAY TIME FROM CLK↓ (ns)
150
200
250
50
LTC1293 G10
100
0–25 025 75 125100
V
CC
= 5V
50
MSB FIRST DATA
LSB FIRST DATA
7
LTC1293/LTC1294/LTC1296
PI FU CTIO S
U
UU
# PIN FUNCTION DESCRIPTION
1 – 6 CH0 – CH5 Analog Inputs The analog inputs must be free of noise with respect to AGND.
7 COM Common The common pin defines the zero reference point for all single ended inputs. It must be free of noise and is
usually tied to the analog ground plane.
8 DGND Digital Ground This is the ground for the internal logic. Tie to the ground plane.
9V
–
Negative Supply Tie V
–
to most negative potential in the circuit (Ground in single supply applications).
10 AGND Analog Ground AGND should be tied directly to the analog ground plane.
11 V
REF
Ref. Input The reference inputs must be kept free of noise with respect to AGND.
12 D
IN
Data Input The A/D configuration word is shifted into this input.
13 D
OUT
Digital Data Output The A/D conversion result is shifted out of this output.
14 CS Chip Select Input A logic low on this input enables data transfer.
15 CLK Clock This clock synchronizes the serial data transfer and controls A/D conversion rate.
16 V
CC
Positive supply This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane.
LTC1293
# PIN FUNCTION DESCRIPTION
1 –8 CH0 – CH7 Analog Inputs The analog inputs must be free of noise with respect to AGND.
9 COM Common The common pin defines the zero reference point for all single ended inputs. It must be free of noise and is
usually tied to the analog ground plane.
10 DGND Digital Ground This is the ground for the internal logic. Tie to the ground plane.
11 V
–
Negative Supply Tie V
–
to most negative potential in the circuit (Ground in single supply applications).
12 AGND Analog Ground AGND should be tied directly to the analog ground plane.
13, 14 REF
–
, REF
+
Ref. Inputs The reference inputs must be kept free of noise with respect to AGND. The A/D sees a reference voltage equal
to the difference between REF
+
and REF
–
.
15 D
IN
Data Input The A/D configuration word is shifted into this input.
16 D
OUT
Digital Data Output The A/D conversion result is shifted out of this output.
17 CS Chip Select Input A logic low on this input enables data transfer.
18 CLK Clock This clock synchronizes the serial data transfer and controls A/D converion rate.
19, 20 AV
CC,
DV
CC
Positive Supplies These supplies must be kept free of noise and ripple by bypassing directly to the analog ground plane. AV
CC
and DV
CC
must be tied together.
LTC1294
# PIN FUNCTION DESCRIPTION
1 –8 CH0 – CH7 Analog Inputs The analog inputs must be free of noise with respect to AGND.
9 COM Common The common pin defines the zero reference point for all single ended inputs. It must be free of noise and is
usually tied to the analog ground plane.
10 DGND Digital Ground This is the ground for the internal logic. Tie to the ground plane.
11 V
–
Negative Supply Tie V
–
to most negative potential in the circuit (Ground in single supply applications).
12 AGND Analog Ground AGND should be tied directly to the analog ground plane.
13, 14 REF
–
, REF
+
Ref. Inputs The reference inputs must be kept free of noise with respect to AGND. The A/D sees a reference voltage equal
to the difference between REF
+
and REF
–
.
15 D
IN
Data Input The A/D configuration word is shifted into this input.
16 D
OUT
Digital Data Output The A/D conversion result is shifted out of this output.
17 CS Chip Select Input A logic low on this input enables data transfer.
18 CLK Clock This clock synchronizes the serial data transfer and controls A/D conversion rate.
19 SSO System Shutdown System Shutdown Output pin will go low when power shutdown is requested.
Output
20 V
CC
Positive Supply This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane.
LTC1296
8
LTC1293/LTC1294/LTC1296
W
IDAGRA
B
L
O
C
K
(Pin numbers refer to LTC1294)
Load Circuit for tdDO, tr and tfLoad Circuit for tenSSO and tdisSSO
DOUT
1.4V
3kΩ
100pF
TEST POINT
LTC1293 TC02
1.4V
3kΩ
100pF
TEST POINT
LTC1293 TC08
SSO
LT1296
TEST CIRCUITS
On and Off Channel Leakage Current
D
OUT
3k
100pF
TEST POINT
5V t
dis
WAVEFORM 2, t
en
t
dis
WAVEFORM 1
LTC1293 TC05
Load Circuit for tdis and ten
INPUT
SHIFT
REGISTER
SAMPLE
AND
HOLD
12-BIT
CAPACITIVE
DAC
DV
CC
20
ANALOG
INPUT MUX
1
2
3
4
5
6
7
8
9
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
D
OUT
16
CLK
18
CONTROL
AND
TIMING
17 CS
LTC1293 BD
19
15
REF
+
14
DGND
10
V
–
11
AGND
12
REF
–
13
COMP
12-BIT
SAR
OUTPUT
SHIFT
REGISTER
D
IN
AV
CC
5V
A
A
I
OFF
I
ON
POLARITY
OFF
CHANNELS
ON CHANNEL
LTC1293 TC1
9
LTC1293/LTC1294/LTC1296
TEST CIRCUITS
Voltage Waveforms for ten
CS
B11
D
OUT
t
en
0.8V
CLK
LTC1293 TC07
START
78
456
3
2
1
D
IN
Voltage Waveform for DOUT Rise and Fall Times, tr, tf
D
OUT
0.4V
2.4V
t
r
t
f
LTC1293 TC04
Voltage Waveform for tdis
Voltage Waveform for DOUT Delay Time, tdDO
CLK
D
OUT
0.8V
t
dDO
0.4V
2.4V
LTC1293 TC03
Voltage Waveform for for tenSSO
CLK 0.8V
0.8V
LTC1293 TC09
SSO
t
en
SSO
Voltage Waveform for tdisSSO
D
OUT
WAVEFORM 1
(SEE NOTE 1)
2.0V
t
dis
90%
10%
D
OUT
WAVEFORM 2
(SEE NOTE 2)
CS
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
LTC1293 TC06
0.8V
2.4V
LTC1293 TC10
SSO
t
dis
SSO
CS
10
LTC1293/LTC1294/LTC1296
Start Bit
The first "logical one" clocked into the D
IN
input after CS
goes low is the start bit. The start bit initiates the data
transfer and all leading zeroes which precede this logical
one will be ignored. After the start bit is received the
remaining bits of the input word will be clocked in. Further
inputs on the D
IN
pin are then ignored until the next CS
cycle.
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The LTC 1293/4/6 is a data acquisition component which
contains the following functional blocks:
1. 12-bit successive approximation capacitive A/D
converter
2. Analog multiplexer (MUX)
3. Sample and hold (S/H)
4. Synchronous, half duplex serial interface
5. Control and timing logic
DIGITAL CONSIDERATIONS
Serial Interface
The LTC1293/4/6 communicates with microprocessors
and other external circuitry via a synchronous, half duplex,
four-wire serial interface (see Operating Sequence). The
clock (CLK) synchronizes the data transfer with each bit
being transmitted on the falling CLK edge and captured on
the rising CLK edge in both transmitting and receiving
systems. The input data is first received and then the A/D
conversion result is transmitted (half duplex). Because of
INPUT DATA WORD
The LTC1293/4/6 seven-bit data word is clocked into the
D
IN
input on the rising edge of the clock after chip select
goes low and the start bit has been recognized. Further
inputs on the D
IN
pin are then ignored until the next CS
cycle. The input word is defined as follows:
the half duplex operation D
IN
and D
OUT
may be tied
together allowing transmission over just 3 wired: CS, CLK
and DATA (D
IN
/D
OUT
). Data transfer is initiated by a falling
chip select (CS) signal. After CS falls the LTC1293/4/6
looks for a start bit. After the start bit is received a 7-bit
input word is shifted into the D
IN
input which configures
the LTC1293/4/6 and starts the conversion. After one null
bit, the result of the conversion is output on the D
OUT
line.
With the half duplex serial interface the D
OUT
data is from
the current conversion. After the end of the data exchange
CS should be brought high. This resets the LTC1293/4/6
in preparation for the next data exchange.
CS
D
IN
1 D
IN
2
D
OUT
2
D
OUT
1
SHIFT MUX
ADDRESS IN
1 NULL
BIT
SHIFT A/D CONVERSION
RESULT OUT
LTC1293 AI01
MUX Address
The four bits of the input word following the START BIT
assign the MUX configuration for the requested conver-
sion. For a given channel selection, the converter will
measure the voltage between the two channels indicated
by the + and – signs in the selected row of the following
table. Note that in differential mode (SGL/DIFF = 0) mea-
surements are limited to four adjacent input pairs with
either polarity. In single ended mode, all input channels
are measured with respect to COM. Only the +inputs have
sample and holds. Signals applied at the –inputs must not
change more than the required accuracy during the con-
version.
START SGL/
DIFF ODD/
SIGN SELECT
1SELECT
0UNI MSBF PS
MUX ADDRESS MSB FIRST/
LSB FIRST
UNIPOLAR/
BIPOLAR POWER
SHUTDOWN
LTC1293 AI02
11
LTC1293/LTC1294/LTC1296
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MUX ADDRESS
SGL/
DIFF
DIFFERENTIAL CHANNEL SELECTION
00 00 +–
00 01 +–
00 10 +–
00 11 + –
01 00 –+
01 01 –+
01 10 –+
01 11 – +
0 1 2 3 4 5 6 7
Table 1a. LTC1294/6 Multiplexer Channel Selection
MUX ADDRESS SINGLE-ENDED CHANNEL SELECTION
0 1 2 3 4 5 6 7 COM
00 00 + –
00 01 + –
00 10 + –
00 11
01 00 – +
01 01 – +
01 10 – +
01 11
Table 1b. LTC1293 Channel Selection
0 1 2 3 4 5
MUX ADDRESS
Not Used
Not Used Not Used
Not Used
Unipolar/Bipolar (UNI)
The UNI bit determines whether the conversion will be
unipolar or bipolar. When UNI is a logical one, a unipolar
conversion will be performed on the selected input volt-
age. When UNI is a logical zero, a bipolar conversion will
result. The input span and code assignment for each
conversion type are shown in the figures below:
Unipolar Output Code (UNI = 1)
ODD
SIGN SELECT
1 0 SGL/
DIFF SELECT
1 0
ODD
SIGN
10 00+ –
10 01 + –
10 10 + –
10 11 + –
11 00 + –
11 01 + –
11 10 + –
11 11 + –
DIFFERENTIAL CHANNEL SELECTION SINGLE-ENDED CHANNEL SELECTIONMUX ADDRESS
SGL/
DIFF ODD
SIGN SELECT
1 0 SGL/
DIFF ODD
SIGN SELECT
1 0 0 1 2 3 4 5 COM
10 00 + –
10 01 + –
10 10 + –
10 11
11 00 + –
11 01 + –
11 10 + –
11 11
0V
1LSB
V
REF
–2LSB
V
REF
–1LSB
V
REF
V
IN
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
•
•
•
LTC1293 AI03b
OUTPUT CODE
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
•
•
•
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
INPUT VOLTAGE
V
REF
– 1LSB
V
REF
– 2LSB
•
•
•
1LSB
0V
INPUT VOLTAGE
(VREF = 5V)
4.9988V
4.9976V
•
•
•
0.0012V
0V
LTC1293 AI03a
Unipolar Transfer Curve (UNI = 1)
12
LTC1293/LTC1294/LTC1296
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Bipolar Transfer Curve (UNI = 0)
OUTPUT CODE
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
•
•
•
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0 0 0 0 0
INPUT VOLTAGE
–1LSB
–2LSB
•
•
•
–(V
REF
) + 1LSB
– (V
REF
)
INPUT VOLTAGE
(V
REF
= 5V)
–0.0024V
–0.0048V
•
•
•
–4.9976V
–5.00000V
OUTPUT CODE
0 1 1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 0
•
•
•
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
INPUT VOLTAGE
V
REF
– 1LSB
V
REF
– 2LSB
•
•
•
1LSB
0V
INPUT VOLTAGE
(V
REF
= 5V)
4.9976V
4.9851V
•
•
•
0.0024V
0V
LTC1293 AI04a
Bipolar Output Code (UNI = 0)
INPUT
CONFIGURATION UNIPOLAR MODE BIPOLAR MODE
Single-Ended Lower Value COM –(REF
+
– REF
–
) + COM
Upper Value (REF
+
– REF
–
) + COM (REF
+
– REF
–
) + COM
Differential Lower Value IN
–
–(REF
+
– REF
–
) + IN
–
Upper Value (REF
+
– REF
–
) + IN
–
(REF
+
– REF
–
) + IN
–
The following discussion will demonstrate how the two
reference pins are to be used in conjunction with the
analog input multiplexer. In unipolar mode the input span
of the A/D is set by the difference in voltage on the REF
+
pin
and the REF
–
pin. In the bipolar mode the input span is
twice the difference in voltage on the REF
+
pin and the
REF
–
pin. In the unipolar mode the lower value of the input
span is set by the voltage on the COM pin for single-ended
inputs and by the voltage on the minus input pin for
differential inputs. For the bipolar mode of operation the
voltage on the COM pin or the minus input pin set the
center of the input span.
The upper and lower value of the input span can now be
summarized in the following table:
The reference voltages REF
+
and REF
–
can fall between
V
CC
and V
–
, but the difference (REF
+
– REF
–
) must be less
than or equal to V
CC
. The input voltages must be less than
or equal to V
CC
and greater than or equal to V
–
. For the
LTC1293 REF
–
= 0V.
The following examples are for a single-ended input con-
figuration.
Example 1: Let V
CC
= 5V, V
–
= 0V, REF
+
= 4V, REF
–
= 1V
and COM = 0V. Unipolar mode of operation. The resulting
input span is 0V ≤ IN
+
≤ 3V.
1LSB
V
REF
–2LSB
V
REF
–1LSB
V
REF
V
IN
1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1 1 1 0
0 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
•
•
•
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0 0 0 0 0
–1LSB
–2LSB
–V
REF
–V
REF
+ 1LSB
•
•
•
LTC1293 AI04b
13
LTC1293/LTC1294/LTC1296
MSB-First/LSB-First (MSBF)
The output data of the LTC1293/4/6 is programmed for
MSB-first or LSB-first sequence using the MSB bit. When
the MSBF bit is a logical one, data will appear on the D
OUT
line in MSB-first format. Logical zeroes will be filled in
indefinitely following the last data bit to accommodate
longer word lengths required by some microprocessors.
When the MSBF bit is a logical zero, LSB first data will
follow the normal MSB first data on the D
OUT
line. In the
bipolar mode the sign bit will fill in after the MSB bit for
MSBF = 0 (see Operating Sequence).
Power Shutdowns (PS)
The power shutdown feature of the LTC1293/4/6 is acti-
vated by making the PS bit a logical zero. If CS remains low
after the PS bit has been received, a 12-bit D
OUT
word with
Example 2: The same conditions as Example 1 except
COM = 1V. The resulting input span is 1V ≤ IN
+
≤ 4V. Note
if IN
+
≥ 4V the resulting D
OUT
word is all 1’s. If IN
+
≤ 1V
then the resulting D
OUT
word is all 0’s.
Example 3: Let V
CC
= 5V, V
–
= –5V, REF
+
= 4V, REF
–
= 1V
and COM = 1V. Bipolar mode of operation. The resulting
input span is –2V ≤ IN
+
≤ 4V.
For differential input configurations with the same condi-
tions as in the above three examples the resulting input
spans are as follows:
Example 1 (Diff.): IN
–
≤ IN
+
≤ IN
–
+ 3V.
Example 2 (Diff.): IN
–
≤ IN
+
≤ IN
–
+ 3V.
Example 3 (Diff.): IN
–
– 3V ≤ IN
+
≤ IN
–
+ 3V.
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Operating Sequence
Example: Differential Inputs (CH4+, CH5–), Unipolar Mode
LTC1293 AI05
MSB-FIRST DATA (MSBF = 0)
MSB-FIRST DATA (MSBF = 1)
t
CYC
CS
D
IN
D
OUT
START SEL1 UNI PS
SGL/
DIFF ODD/
SIGN
MSBF
t
CONV
t
SMPL
SEL0
HI-Z FILLED WITH ZEROES
DON'T CARE
CLK DON'T
CARE
B0B1
B11
CLK DON'T
CARE
t
CYC
CS
D
IN
START SEL1 UNI PS
SGL/
DIFF ODD/
SIGN MSBFSEL0
DON'T CARE
D
OUT
t
CONV
t
SMPL
HI-Z B11 B1 B0 B1 B11 FILLED WITH
ZEROES
14
LTC1293/LTC1294/LTC1296
PART NUMBER TYPE OF INTERFACE
Motorola
MC6805S2, S3 SPI
MC68HC11 SPI
MC68HC05 SPI
RCA CDP68HC05 SPI
HitachiHD6305 SCI Synchronous
HD6301 SCI Synchronous
HD63701 SCI Synchronous
HD6303 SCI Synchronous
HD64180 SCI Synchronous
National Semiconductor
COP400 Family MICROWIRE†
COP800 Family MCROWIRE/PLUS†
NS8050U MICROWIRE/PLUS
HPC16000 Family MICROWIRE/PLUS
Texas Instruments
TMS7002 Serial Port
TMS7042 Serial Port
TMS70C02 Serial Port
TMS70C42 Serial Port
TMS32011* Serial Port
TMS32020* Serial Port
TMS370C050 SPI
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Power Shutdown Operating Sequence
Example: Differential Inputs (CH4+, CH5–), Unipolar Mode and MSB-First Data
all logical ones will be shifted out followed by logical
zeroes till CS goes high. Then the D
OUT
line will go into its
high impedance state. The LTC 1293/4/6 will remain in the
shutdown mode till the next CS cycle. There is no warm-
up or wait period required after coming out of the power
shutdown cycle so a conversion can commence after CS
goes low (see Power Shutdown Operating Sequence). The
LTC1296 has a System Shutdown Output pin (SSO) which
will go low when power shutdown is activated. The pin will
stay low till next CS cycle.
Microprocessor Interfaces
The LTC1293/4/6 can interface directly (without external
hardware) to most popular microprocessors (MPU) syn-
chronous serial formats (see Table 1). If an MPU without
a dedicated serial port is used, then three of the MPU’s
parallel port lines can be programmed to form the serial
link to the LTC1293/4/6. Included here are one serial
interface example and one example showing a parallel
port programmed to form the serial interface.
Microprocessor Interfaces
The LTC1293/4/6 can interface directly (without external
hardware) to most popular microprocessors (MPU) syn-
chronous serial formats (see Table 1). If an MPU without
a dedicated serial port is used, then three of the MPU’s
parallel port lines can be programmed to form the serial
link to the LTC1293/4/6.
* Requires external hardware
** Contact factory for interface information for processors not on this list
†MICROWIRE and MICROWIRE/PLUS are trademarks of National
Semiconductor Corp.
Table 1. Microprocessor with Hardware Serial Interfaces Compat-
ible with the LTC1293/4/6**
D
IN
LTC1293 AI06
SHUTDOWN*
REQUEST POWER SHUTDOWN NEW CONVERSION BEGINS
PS
MSBF
UNI
SEL0
ODD/
SIGN
SEL1/
DIFF
SEL1
START
DON'T CARE
PSUNI
SEL0
ODD/
SIGN
SEL1/
DIFF
SEL1
START
MSBF B0
B11
• • • • • • • • • •
HI-Z
D
OUT
FILLED
WITH
ZEROES
HI-Z
CLK
CS
*STOPPING THE CLOCK WILL HELP REDUCE POWER CONSUMPTION.
CS CAN BE BROUGHT HIGH ONCE THE DIN WORD HAS BEEN CLOCKED IN.
15
LTC1293/LTC1294/LTC1296
Interfacing to the Parallel Port of the Intel 8051 Family
The Intel 8051 has been chosen to show the interface
between the LTC1293/4/6 and parallel port microproces-
sors. Usually the signals CS, D
IN
and CLK are generated
on three port lines and the D
OUT
signal is read on a fourth
port line. This works very well. One can save a line by tying
the D
IN
and D
OUT
lines together. The 8051 first sends the
start bit and D
IN
to the LTC1294 over the line connected to
P1.2. Then P1.2 is reconfigured as an input and the 8051
reads back the 12-bit A/D result over the same data line.
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Data Exchange Between LTC1294 and MC68HC11
Motorola SPI (MC68HC11)
The MC68HC11 has been chosen as an example of an MPU
with a dedicated serial port. This MPU transfers data MSB-
first and in 8-bit increments. The D
IN
word sent to the data
register starts the SPI process. With three 8-bit transfers,
the A/D result is read into the MPU. The second 8-bit
transfer clocks B11 through B8 of the A/D conversion
result into the processor. The third 8-bit transfer clocks
the remaining bits B7 through B0 into the MPU. The data
is right justified in the two memory locations. ANDing the
second byte with 0D
HEX
clears the four most significant
bits. This operation was not included in the code. It can be
inserted in the data gathering loop or outside the loop
when the data is processed.
Hardware and Software Interface to Motorola MC68HC11
CS
CLK
D
OUT
MPU
RECEIVED
WORD
LTC1293 TD01
UNI
SGL/
DIFF ODD/
EVEN SEL
1SEL
0
START MSBF PS
B3B7 B6 B5 B4 B2 B0
B1
B11 B10 B9 B8
D
IN
MPU
TRANSMIT
WORD
BYTE 3 (DUMMY)
BYTE 2
SGL
0ODD SEL
0
SEL
1
BYTE 1
XUNI MSBF PS XXX
X
001
START
XXX
XX
XX
X
BYTE 3
BYTE 2
?
???
?
BYTE 1
B11? ??0B10 B8
B9
??? B7 B6 B4
B5 B3 B2 B0
B1
DON'T CARE
LTC1293 TD01a
CLK
D
OUT
LTC1294
CS
ANALOG
INPUTS
DO
SCK
MISO
MC68HC11
D
IN
MOSI
B2 B1 B0
B3
B4
B6
B7 B5
BYTE 1
B10 B9 B8B11
OO
OO
D
OUT FROM LTC1294 STORED ON MC68HC11 RAM
BYTE 2
LSB
MSB
#62
#63
16
LTC1293/LTC1294/LTC1296
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STAA $102A LOAD DIN INTO SPI, START SCK
WAIT2 LDAA $1029 CHECK SPI STATUS REG
BPL WAIT2 CHECK IF TRANSFER IS DONE
LDAA $102A LOAD LTC1294 MSBs INTO ACC A
STAA $62 STORE MSBs IN $62
LDAA $52 LOAD DUMMY DIN INTO ACC A FROM
$52
STAA $102A LOAD DUMMY DIN INTO SPI, START
SCK
WAIT3 LDAA $1029 CHECK SPI STATUS REG
BPL WAIT3 CHECK IF TRANSFER IS DONE
BSET $08,X,$01 D0 GOES HIGH (CS GOES HIGH)
LDAA $102A LOAD LTC1294 LSBs IN ACC
STAA $63 STORE LSBs IN $63
JMP LOOP START NEXT CONVERSION
LABEL MNEMONIC OPERAND COMMENTS
LDAA #$50 CONFIGURATION DATA FOR SPCR
STAA $1028 LOAD DATA INTO SPCR ($1028)
LDAA #$1B CONFIG. DATA FOR PORT D DDR
STAA $1009 LOAD DATA INTO PORT D DDR
LDAA #$10 LOAD DIN WORD INTO ACC A
STAA $50 LOAD DIN DATA INTO $50
LDAA #$E0 LOAD DIN WORD INTO ACC A
STAA $51 LOAD DIN DATA INTO $51
LDAA #$00 LOAD DUMMY DIN WORD INTO ACC A
STAA $52 LOAD DUMMY DIN DATA INTO $52
LDX #$1000 LOAD INDEX REGISTER X WITH $1000
LOOP BCLR $08,X,$01 D0 GOES LOW (CS GOES LOW)
LDAA $50 LOAD DIN INTO ACC A FROM $50
STAA $102A LOAD DIN INTO SPI, START SCK
LDAA $1029 CHECK SPI STATUS REG
WAIT1 BPL WAIT1 CHECK IF TRANSFER IS DONE
LDAA $51 LOAD DIN INTO ACC A FROM $51
MC68HC11 CODE
LABEL MNEMONIC OPERAND COMMENTS
Hardware and Software Interface to Intel 8051
CS
CLK
DATA
(D
IN
/D
OUT
)
LTC1293 TD02
12346
57
8
PS BIT LATCHED
INTO LTC1294
8051 P1.2 OUTPUT DATA
TO LTC1294
8051 P1.2 RECONFIGURED
AS INPUT AFTER THE 8TH RISING
CLK BEFORE THE 8TH FALLING CLK
LTC1294 SEND A/D RESULT
BACK TO 8051 P1.2
LTC1294 TAKES CONTROL OF DATA
LINE ON 8TH FALLING CLK
START B11
SGL/
DIFF ODD/
SIGN SEL
1SEL
0UNI MSB PS B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Hardware and Software Interface to Intel 8051
LTC1293 TD02a
DOUT FROM LTC1294 STORED IN 8051 RAM
00
0
0
B0
B2
B3 B1
B10
B11
LSB
MSB
R2
R3
B9 B8 B7 B6 B5 B4
CLK
D
OUT
CS
ANALOG
INPUTS
P1.4
P1.3
8051
D
IN
P1.2
MUX ADDRESS
A/D RESULT
LTC1294
17
LTC1293/LTC1294/LTC1296
Sharing the Serial Interface
The LTC1293/4/6 can share the same 3-wire serial inter-
face with other peripheral components or other LTC1293/
4/6’s (Figure 3). Now, the CS signals decide which LTC1293/
4/6 is being addressed by the MPU.
ANALOG CONSIDERATIONS
Grounding
The LTC1293/4/6 should be used with an analog ground
plane and single point grounding techniques. Do not use
wire wrapping techniques to breadboard and evaluate the
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CLR P1.3 CLK GOES LOW
CLR A CLEAR ACC
RLC A ROTATE DATA BIT (B3) INTO ACC
MOV C,P1.2 READ DATA BIT INTO CARRY
RLC A ROTATE DATA BIT (B2) INTO ACC
SETB P1.3 CLK GOES HIGH
CLR P1.3 CLK GOES LOW
MOV C,P1.2 READ DATA BIT INTO CARRY
RLC A ROTATE DATA BIT (B1) INTO ACC
SETB P1.3 CLK GOES HIGH
CLR P1.3 CLK GOES LOW
MOV C,P1.2 READ DATA BIT INTO CARRY
SETB P1.4 CS GOES HIGH
RRC A ROTATE DATA BIT (B0) INTO ACC
RRC A ROTATE RIGHT INTO ACC
RRC A ROTATE RIGHT INTO ACC
RRC A ROTATE RIGHT INTO ACC
MOV R3,A STORE LSBs IN R3
AJMP CONT START NEXT CONVERSION
LABEL MNEMONIC OPERAND COMMENTS
SETB P1.4 CS GOES HIGH
CONT MOV A,#87H DIN WORD FOR LTC1294
CLR P1.4 CS GOES LOW
MOV R4,#08H LOAD COUNTER
LOOP1 RLC A ROTATE DIN BIT INTO CARRY
CLR P1.3 CLK GOES LOW
MOV P1.2,C OUTPUT DIN BIT TO LTC1294
SETB P1.3 CLK GOES HIGH
DJNZ R4,LOOP1 NEXT DIN BIT
MOV P1,#04H P1.2 BECOMES AN INPUT
CLR P1.3 CLK GOES LOW
MOV R4,#09H LOAD COUNTER
LOOP MOV C,P1.2 READ DATA BIT INTO CARRY
RLC A ROTATE DATA BIT (B3) INTO ACC
SETB P1.3 CLK GOES HIGH
CLR P1.3 CLK GOES LOW
DJNZ R4,LOOP NEXT DOUT BIT
MOV R2,A STORE MSBs IN R2
MOV C,P1.2 READ DATA BIT INTO CARRY
SETB P1.3 CLK GOES HIGH
LABEL MNEMONIC OPERAND COMMENTS
8051 CODE
8 CHANNELS 8 CHANNELS
8 CHANNELS
3
3
33
3-WIRE SERIAL
INTERFACE TO OTHER
PERIPHERALS OR LTC1293/4/6s
210
OUTPUT PORT
SERIAL DATA
MPU
LTC1293 F03
LTC1294
CS
LTC1294
CS LTC1294
CS
Figure 3. Several LTC1294 Sharing One 3-Wire Serial Interface
device. To achieve the optimum performance use a PC
board. The analog ground pin (AGND) should be tied
directly to the ground plane with minimum lead length (a
low profile socket is fine). The digital ground pin (DGND)
also can be tied directly to this ground pin because
minimal digital noise is generated within the chip itself.
V
CC
should be bypassed to the ground plane with a 22µF
(minimum value) tantalum with leads as short as possible
and as close as possible to the pin. A 0.1µF ceramic disk
also should be placed in parallel with the 22µF and again
with leads as short as possible and as close to V
CC
as
possible. AV
CC
and DV
CC
should be tied together on the
18
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LTC1294. Figure 4 shows an example of an ideal LTC1293/
4/6 ground plane design for a two sided board. Of course
this much ground plane will not always be possible, but
users should strive to get as close to this ideal as possible.
Bypassing
For good performance, V
CC
must be free of noise and
ripple. Any changes in the V
CC
voltage with respect to
ground during a conversion cycle can induce errors or
noise in the output code. V
CC
noise and ripple can be kept
below 0.5mV by bypassing the V
CC
pin directly to the
analog ground plane with a minimum of 22µF tantalum
capacitor and with leads as short as possible. The lead
from the device to the V
CC
supply also should be kept to a
minimum and the V
CC
supply should have a low output
impedance such as obtained from a voltage regulator
(e.g., LT323A). For high frequency bypassing a 0.1µF
ceramic disk placed in parallel with the 22µF is recom-
mended. Again the leads should be kept to a minimum.
Figure 5 and 6 show the effects of good and poor V
CC
bypassing.
HORIZONTAL: 10µs/DIV
VERTICAL: 0.5mV/DIV
VERTICAL: 0.5mV/DIV
HORIZONTAL: 10µs/DIV
Figure 5. Poor VCC Bypassing.
Noise and Ripple Can Cause A/D Errors.
Figure 6. Good VCC Bypassing Keeps Noise
and Ripple on VCC Below 1mV
CS
V
CC
Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1293/4/6
have capacitive switching input current spikes. These
current spikes settle quickly and do not cause a problem.
If large source resistances are used or if slow settling op
amps drive the inputs, take care to insure the transients
caused by the current spikes settle completely before the
conversion begins.
Figure 4. Ground Plane for the LTC1293/4/6
Figure 7. Analog Input Equivalent Circuit
6TH CLK↑
R
ON
= 500Ω
8TH CLK↓C
IN
=
100pF
LTC1293/4/6
“+”
INPUT
R
SOURCE
+
V
IN
+
C1
“–”
INPUT
R
SOURCE
–
V
IN
–
C2
LTC1293 F07
V
–
22µF
TANTALUM
V
CC
LTC1293 F04
0.1µF
CERAMIC
DISK
ANALOG
GROUND
PLANE
0.1µF
CERAMIC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
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Source Resistance
The analog inputs of the LTC1293/4/6 look like a 100pF
capacitor (C
IN
) in series with a 500Ω resistor (R
ON
). C
IN
gets switched between (+) and (–) inputs once during each
conversion cycle. Large external source resistors and
capacitances will slow the settling of the inputs. It is
important that the overall RC time constant is short
enough to allow the analog inputs to settle completely
within the allowed time.
“+” Input Settling
The input capacitor is switched onto the “+” input during
the sample phase (t
SMPL
, see Figure 8). The sample period
2 1/2 CLK cycles before a conversion starts. The voltage on
the “+” input must settle completely within the sample
period. Minimizing R
SOURCE
+ and C1 will improve the
settling time. If large “+” input source resistance must be
used, the sample time can be increased by using a slower
CLK frequency. With the minimum possible sample time
of 2.5µs R
SOURCE
+ < 1.5kΩ and C1 < 20pF will provide
adequate settling time.
“–” Input Settling
At the end of the sample phase the input capacitor switches
to the “-” input and the conversion starts (see Figure 8).
During the conversion, the “+” input voltage is effectively
“held” by the sample and hold and will not affect the
conversion result. It is critical that the “–” input voltage be
free of noise and settle completely during the first CLK
cycle of the conversion. Minimizing R
SOURCE
– and C2 will
improve settling time. If large “–” input source resistance
must be used the time can be extended by using a slower
CLK frequency. At the maximum CLK frequency of 1MHz,
R
SOURCE
– < 250Ω and C2 < 20pF will provide adequate
settling.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settles within the allowed time
(see Figure 8). Again the “+” and “–” input sampling times
can be extended as described above to accommodate
slower op amps. Most op amps including the LT1006 and
LT1013 single supply op amps can be made to settle
Figure 8. “+” and “–” Input Settling Windows
D
IN
CLK
START
HI-Z
LTC1293 F08
CS
1ST BIT TEST (–) INPUT MUST
SETTLE DURING THIS TIME
t
SMPL
(+) INPUT MUST SETTLE DURING THIS TIME
(+) INPUT
(–) INPUT
SGL/
DIFF MSBF PS
D
OUT
B11
SAMPLE HOLD
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Figure 11. RC Input Filtering
R
FILTER
V
IN
–
C
FILTER
LTC1293 F11
LTC1293/4/6
"+"
"–"
I
IDC
within the minimum settling windows of 2.5µs (“+” input)
and 1µs(“–” input) that occurs at the maximum clock rate
of 1MHz. Figures 9 and 10 show examples of adequate
and poor op amp settling.
RC Input Filtering
It is possible to filter the inputs with an RC network as
shown in Figure 11. For large values of C
F
(e.g., 1µF) the
capacitive input switching currents are averaged into a net
DC current. A filter should be chosen with a small resistor
and large capacitor to prevent DC drops across the resis-
tor. The magnitude of the DC current is approximately I
DC
= 100pF × V
IN
/t
CYC
and is roughly proportional to V
IN
.
When running at the minimum cycle time of 21.5µs, the
input current equals 23µA at V
IN
= 5V. Here a filter resistor
of 5Ω will cause 0.1LSB of full-scale error. If a larger filter
resistor must be used, errors can be reduced by increasing
the cycle time as shown in the typical performance char-
acteristic curve Maximum Filter Resistor vs Cycle Time.
Input Leakage Current
Input leakage currents also can create errors if the source
resistance gets too large. For example, the maximum input
leakage specification of 1µA (at 125°C) flowing through a
source resistance of 1kΩ will cause a voltage drop of 1mV
or 0.8LSB. This error will be much reduced at lower
temperatures because leakage drops rapidly (see typical
performance characteristic curve Input Channel Leakage
Current vs Temperature).
SAMPLE AND HOLD
Single-Ended Input
The LTC1293/4/6 provides a built-in sample and hold
(S&H) function for all signals acquired in the single-ended
mode (COM pin grounded). The sample and hold allows
the LTC1293/4/6 to convert rapidly varying signals (see
typical performance characteristic curve of S&H Acquisi-
tion Time vs Source Resistance). The input voltage is
sampled during the t
SMPL
time as shown in Figure 8. The
sampling interval begins as the bit preceding the MSBF bit
is shifted in and continues until the falling edge of the PS
bit is received. On this falling edge the S&H goes into the
hold mode and the conversion begins.
Differential Input
With a differential input the A/D no longer converts a
single voltage but converts the difference between two
voltages. The voltage on the selected “+” input is sampled
and held and can be rapidly time varying. The voltage on
the “–” pin must remain constant and be free of noise and
ripple throughout the conversion time. Otherwise the
differencing operation will not be done accurately. The
conversion time is 12 CLK cycles. Therefore a change in
the –IN input voltage during this interval can cause con-
version errors. For a sinusoidal voltage on the –IN input
this error would be:
VfV
f
ERROR MAX PEAK CLK
() (–)
=π
()
212
Where f
(–)
is the frequency of the “–” input voltage, V
PEAK
is its peak amplitude and f
CLK
is the frequency of the CLK.
HORIZONTAL: 20µs/DIV
HORIZONTAL: 500ns/DIV
Figure 9. Adequate Settling of Op Amp Driving Analog Input
Figure 10. Poor Op Amp Settling Can Cause A/D Errors
VERTICAL: 5mV/DIV
VERTICAL: 5mV/DIV
21
LTC1293/LTC1294/LTC1296
Usually V
ERROR
will not be significant. For a 60Hz signal
on the “–” input to generate a 0.25LSB error (300µV) with
the converter running at CLK = 1MHz, its peak value would
have to be 66mV. Rearranging the above equation the
maximum sinusoidal signal that can be digitized to a given
accuracy is given as:
fV
V
f
MAX ERROR MAX
PEAK
CLK
(–) ()
=π
212
For 0.25LSB error (300µV) the maximum input sinusoid
with a 5V peak amplitude that can be digitized is 0.8Hz.
Unused inputs should be tied to the ground plane.
Reference Input
The voltage on the reference input of the LTC1293/4/6
determines the voltage span of the A/D converter. The
reference input has transient capacitive switching cur-
rents due to the switched capacitor conversion technique
(see Figure 12). During each bit test of the conversion
(every CLK cycle) a capacitive current spike will be gener-
ated on the reference pin by the A/D. These current spikes
settle quickly and do not cause a problem. If slow settling
circuitry is used to drive the reference input, take care to
insure that transients caused by these current spikes settle
completely during each bit test of the conversion.
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Figure 13 and 14 show examples of both adequate and
poor settling. Using a slower CLK will allow more time for
the reference to settle. Even at the maximum CLK rate of
1MHz most references and op amps can be made to settle
within the 1µs bit time. For example the LT1027 will settle
adequately or with a 10µF bypass capacitor at V
REF
the
LT1021 also can be used.
VERTICAL: 0.5mV/DIVVERTICAL: 0.5mV/DIV
Figure 14. Poor Reference Settling Can Cause A/D Errors
HORIZONTAL: 1µs/DIV
HORIZONTAL: 1µs/DIV
Figure 13. Adequate Reference Settling (LT1027)
Figure 12. Reference Input Equivalent Circuit
R
ON
8pF – 40pF
LTC1293/4/6
REF+
R
OUT
V
REF
EVERY CLK CYCLE
14
13
REF–
LTC 1293 F12
Reduced Reference Operation
The effective resolution of the LTC1293/4/6 can be in-
creased by reducing the input span of the converter. The
LTC1293/4/6 exhibits good linearity over a range of refer-
ence voltages (see typical performance characteristics
curves of Change in Linearity vs Reference Voltage and
Change in Gain Error vs Reference Voltage). Care must be
taken when operating at low values of V
REF
because of the
reduced LSB step size and the resulting higher accuracy
requirement placed on the converter. Offset and Noise are
factors that must be considered when operating at low
V
REF
values. For the LTC1293 REF
–
has been tied to the
AGND pin. Any voltage drop from the AGND pin to the
ground plane will cause a gain error.
Offset with Reduced V
REF
The offset of the LTC1293/4/6 has a larger effect on the
output code when the A/D is operated with a reduced
reference voltage. The offset (which is typically a fixed
voltage) becomes a larger fraction of an LSB as the size of
the LSB is reduced. The typical performance characteris-
tic curve of Unadjusted Offset Error vs Reference Voltage
shows how offset in LSB’s is related to reference voltage
for a typical value of V
OS
. For example a V
OS
of 0.1mV,
which is 0.1LSB with a 5V reference becomes 0.4LSB with
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a 1.25 reference. If this offset is unacceptable, it can be
corrected digitally by the receiving system or by offsetting
the “–” input to the LTC1293/4/6.
Noise with Reduced V
REF
The total input referred noise of the LTC1293/4/6 can be
reduced to approximately 200µV peak-to-peak using a
ground plane, good bypassing, good layout techniques
and minimizing noise on the reference inputs. This noise
is insignificant with a 5V reference input but will become
a larger fraction of an LSB as the size of the LSB is reduced.
The typical performance characteristic curve of Noise
Error vs Reference Voltage shows the LSB contribution of
this 200µV of noise.
For operation with a 5V reference, the 200µV noise is only
0.16LSB peak-to-peak. Here the LTC1293/4/6 noise will
contribute virtually no uncertainty to the output code. For
reduced references, the noise may become a significant
fraction of an LSB and cause undesirable jitter in the
output code. For example, with a 1.25V reference, this
200µV noise is 0.64LSB peak-to-peak. This will reduce
the range of input voltages over which a stable output code
can be achieved by 0.64LSB. Now averaging readings may
be necessary.
This noise data was taken in a very clean test fixture. Any
setup induced noise (noise or ripple on V
CC
, V
REF
or V
IN
)
will add to the internal noise. The lower the reference
voltage used, the more critical it becomes to have a noise-
free setup.
Gain Error due to Reduced V
REF
The gain error of the LTC1294/6 is very good over a wide
range of reference voltages. The error component that is
seen in the typical performance characteristics curve
Change in Gain Error vs Reference Voltage for the LTC1293
is due the voltage drop on the AGND pin from the device
to the ground plane. To minimize this error the LTC1293
should be soldered directly onto the PC board. The internal
reference point for V
REF
is tied to AGND. Any voltage drop
in the AGND pin will make the reference voltage, internal
to the device, less than what is applied externally (Figure
15). This drop is typically 400µV due to the product of the
pin resistance (R
PIN
) and the LTC1293 supply current. For
example, with V
REF
= 1.25V this will result in a gain error
change of –1.0LSB from the gain error measured with
V
REF
= 5V.
Figure 15. Parasitic Pin Resistance (RPIN)
LTC1293
REF
+
R
PIN
I
CC
DAC
REF
–
V
REF
AGND
LTC1293 F15
±
REFERENCE
VOLTAGE
LTC1293/4/6 AC Characteristics
Two commonly used figures of merit for specifying the
dynamic performance of the A/Ds in digital signal process-
ing applications are the Signal-to-Noise Ratio (SNR) and
the “effective number of bits”(ENOB). SNR is the ratio of
the RMS magnitude of the fundamental to the RMS
magnitude of all the non-fundamental signals up to the
Nyquist frequency (half the sampling frequency). The
theoretical maximum SNR for a sine wave input is given
by:
SNR = (6.02N + 1.76dB)
where N is the number of bits. Thus the SNR depends on
the resolution of the A/D. For an ideal 12-bit A/D the SNR
is equal to 74dB. A Fast Fourier Transform (FFT) plot of the
output spectrum of the LTC1294 is shown in Figures 16a
and 16b. The input (f
IN
) frequencies are 1kHz and 22kHz
with the sampling frequency (f
S
) at 45.4kHz. The SNR
obtained from the plot are 72.7dB and 72.5dB.
Rewriting the SNR expression it is possible to obtain the
equivalent resolution based on the SNR measurement.
NSNR dB
=
–.
.
176
602
This is the so-called effective number of bits (ENOB). For
the example shown in Figures 16a and 16b, N = 11.8 bits.
Figure 17 shows a plot of ENOB as a function of input
frequency. The top curve shows the A/D’s ENOB remains
at 11.8 for input frequencies up to f
S
/2 with ±5V supplies.
23
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FREQUENCY (kHz)
0
EFFECTIVE NUMBER OF BITS
9.5
10.0
10.5
60 100
LT1293 F17
9.0
8.5
8.0 20 40 80
11.0
11.5
12.0
fS = 45.4kHz
±5V SUPPLIES
+5V SUPPLY
For +5V supplies the ENOB decreases more rapidly. This
is due predominantly to the 2nd harmonic distortion term.
Figure 18 shows a FFT plot of the output spectrum for two
tones applied to the input of the A/D. Nonlinearities in the
A/D will cause distortion products at the sum and differ-
ence frequencies of the fundamentals and products of the
fundamentals. This is classically referred to as
intermodulation distortion (IMD).
Overvoltage Protection
Applying signals to the LTC1293/4/6’s analog inputs that
exceed the positive supply or that go below V
–
will
degrade the accuracy of the A/D and possibly damage the
device. For example this condition would occur if a signal
is applied to the analog inputs before power is applied to
the LTC1293/4/6. Another example is the input source is
operating from different supplies of larger value than the
LTC1293/4/6. These conditions should be prevented ei-
ther with proper supply sequencing or by use of external
circuitry to clamp or current limit the input source. There
are two ways to protect the inputs. In Figure 19 diode
clamps from the inputs to V
CC
and V
–
are used. The
second method is to put resistors in series with the analog
inputs for current limiting. As shown in Figure 20a, a 1kΩ
resistor is enough to stand off ±15V (15mA for only one
channel). If more than one channel exceeds the supplies
than the following guidelines can be used. Limit the
current to 7mA per channel and 28mA for all channels.
FREQUENCY (kHz)
0
MAGNITUDE (dB)
–40
–20
0
15
1293 F16a
–60
–80
20
–100
–120
–140 2510
5
FREQUENCY (kHz)
0
MAGNITUDE (dB)
–40
–20
0
15
1293 F16b
–60
–80
20
–100
–120
–140 2510
5
FREQUENCY (kHz)
0
MAGNITUDE (dB)
–40
–20
0
15
1293 F8
–60
–80
20
–100
–120
–140 2510
5
Figure 16b. LTC1294 FFT Plot
fIN = 22kHz, fS = 45.4kHz,
SNR = 72.5dB with ±5V Supplies
Figure 16a. LTC1294 FFT Plot
fIN = 1kHz, fS = 45.4kHz,
SNR = 72.7dB with ±5V Supplies
Figure 17. LTC1294 ENOB vs Input Frequency
Figure 18. LTC1294 FFT Plot
fIN1 = 5.1kHz, fIN2 = 5.6kHz, fS = 45.4kHz
with ±5V Supplies
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This means four channels can handle 7mA of input current
each. Reducing CLK frequency from a maximum of 1MHz
(See typical performance characteristics curves Maxi-
mum CLK Frequency vs Source Resistance and Sample
and Hold Acquisition Time vs Source Resistance) allows
the use of larger current limiting resistors. The “+” input
can accept a resistor value of 1kΩ but the “–” input cannot
accept more than 250Ω when the maximum clock fre-
quency of 1MHz is used. If the LTC1293/4/6 is clocked at
the maximum clock frequency and 250Ω is not enough to
current limit the “–” input source then the clamp diodes
are recommended (Figures 20a and 20b). The reason for
the limit on the resistor value is the MSB bit test is affected
by the value of the resistor placed at the “–” input (see
discussion on Analog Inputs and the typical performance
characteristics curve Maximum CLK Frequency vs Source
Resistance).
If V
CC
and V
REF
are not tied together, then V
CC
should be
turned on first, then V
REF
. If this sequence cannot be met
connecting a diode from V
REF
to V
CC
is recommended (see
Figure 21).
For dual supplies (bipolar mode) placing two Schottky
diodes from V
CC
and V
–
to ground (Figure 22) will prevent
Figure 20a. Overvoltage Protection for Inputs
Figure 19. Overvoltage Protection for Inputs
Figure 22. Power Supply Reversal
Figure 21
power supply reversal from occuring when an input source
is applied to the analog MUX before power is applied to the
device. Power supply reversal occurs, for example, if the
input is pulled below V
–
. V
CC
will then pull a diode drop
below ground which could cause the device not to power
up properly. Likewise, if the input is pulled above V
CC
, V
–
will be pulled a diode drop above ground. If no inputs are
present on the MUX, the Schottky diodes are not required
if V
–
is applied first then V
CC
.
Because a unique input protection structure is used on the
digital input pins, the signal levels on these pins can
exceed the device V
CC
without damaging the device.
Figure 20b. Overvoltage Protection for Inputs
+5V
LTC1293 F19
DGND V
–
AGND
V
CC
1N4148 DIODES
LTC1293/4/6
–5V
+5V
LTC1293 F20a
+
DGND V
–
AGND
V
CC
–
250Ω
1k
LTC1293/4/6
–5V
+5V
LTC1293 F20b
+
DGND V
–
AGND
V
CC
–
LTC1293/4/6
1N4148 DIODES
1k
–5V
+5V
LTC1293 F22
DGND
AGND
VCC
LTC1293/4/6
1N5817
–5V
V–
1N5817
+5V
LTC1293 F21
DGND
AGND
VCC
LTC1293/4/6
1N4148
+5V
REF+
25
LTC1293/LTC1294/LTC1296
Unipolar conversion is requested and the data is output
MSB first. CS is driven at 1/64 the clock rate by the CD4520
and D
OUT
outputs the data. The output data from the D
OUT
pin can be viewed on an oscilloscope that is set up to
trigger on the falling edge of CS (Figure 24).
VERTICAL: 5V/DIV
HORIZONTAL: 2µs/DIV
CLK
FILLS
ZEROES
LSB
(B0)
NULL
BIT MSB
(B11)
Figure 24. Scope Trace of the
LTC1294/6 “Quick Look” Circuit
Showing A/D Output
101010101010 (AAAHEX)
LTC1293 TA03
1k
22µF
TANTALUM
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DGND
DVCC
AVCC
CLK
CS
DOUT
DIN
REF+
REF–
AGND
V–
LTC1294
–
+
TO/FROM
68HC11
PROCESSOR
+15V
A2
LT1006
30.1k**
1µF
3.92M**
500k
ZERO°C TRIM
+15V
–
+A1
LT1101
A=10
+15V
5VOUT
10µF
500k
400°C TRIM
12.5k*
12k*
1k*
+
Rplat.
* TRW-IRC MAR-6 RESISTOR – 0.1%
** 1% FILM RESISTOR
Rplat. = 1kΩ AT 0°C – ROSEMOUNT #118MF
LT1027
Digitally Linearized Platinum RTD Signal Conditioner
TO
OSCILLOSCOPE
LTC1293 F23
CLK
EN
Q1
Q2
Q3
Q4
RESET
V
SS
V
DD
RESET
Q4
Q3
Q2
Q1
EN
CLK
V
IN
f/64
+5V
CLOCK IN
1MHz MAX
22µF CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DGND
DV
CC
AV
CC
CLK
CS
D
OUT
D
IN
REF+
REF
–
AGND
V
–
LTC1294
f
CD4520
Figure 23. “Quick Look” Circuit for the LTC1294/6
U
SA
O
PPLICATITYPICAL
A “Quick Look” Circuit for the LTC1294/6
Users can get a quick look at the function and timing of the
LTC1294/6 by using the following simple circuit (Figure
23). V
REF
is tied to V
CC
. D
IN
is tied high which means V
IN
should be applied to the CH7 with respect to COM. A
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
CS
DOUT
26
LTC1293/LTC1294/LTC1296
U
SA
O
PPLICATITYPICAL
Micropower, 5000V Opto-Isolated, Multichannel,12-Bit Data
Acquisition System is Accessed Once Every Two Seconds
LT1027
5V
MISO
MOSI
C0
SCK
C1
10k
10k
9V
ISOLATION
BARRIER
4N28s
51k
51k
51k
51k
300Ω
5.1k
(3)
2N3906
5V
5V
5V
5V
51k
5.1k
10k
10k
10k
10k
150Ω
150Ω
150Ω
150Ω
4N28
TO ADDITIONAL
LTC1294s
NC
4N28
*SOLID TANTALUM
10µF*
8
ANALOG
INPUTS
0–5V RANGE
2N3904
2N3906
TO
68HC11
10k
LT1292 TA02
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DGND
DV
CC
AV
CC
CLK
CS
D
OUT
D
IN
REF
+
REF
–
AGND
V
–
LTC1294
27
LTC1293/LTC1294/LTC1296
PACKAGE DESCRIPTIO
U
Dimensions in inches (millimeters) unless otherwise noted.
0.290 - 0.320
(7.366 - 8.128)
GLASS
SEALANT
0° – 15°
0.008 – 0.018
(0.203 – 0.457)
0.385 ± 0.025
(9.779 ± 0.635)
11
37
20 16 15
56 10
9
17 14 13 12
142
19
8
18
0.005
(0.127)
0.025
(0.635)
RAD TYP
0.220 - 0.310
(5.588 - 7.874)
1.060
(26.924)
MAX
0.015 – 0.060
(0.381 – 1.524)
0.160
(4.064)
MAX
0.125
(3.175)
MIN 0.080
(2.032)
MAX
0.014 – 0.026
(0.356 – 0.660)
0.100 ± 0.010
(2.540 ± 0.254)
0.200
(5.080)
MAX
0.038 – 0.068
(0.965 – 1.727)
J20 12/91
J Package
16-Lead Ceramic DIP
123456
7
8
0.220 – 0.310
(5.588 – 7.874)
0.840
(21.336)
MAX
0.005
(0.127)
MIN
16 13 91011121415
0.025
(0.635)
RAD TYP
J16 1291
0.290 – 0.320
(7.366 – 8.128)
0.008 – 0.018
(0.203 – 0.460) 0° – 15°
0.385 ± 0.025
(9.779 ± 0.635)
0.015 – 0.060
(0.380 – 1.520)
GLASS
SEALANT
0.080
(2.030)
MAX
0.100 ± 0.010
(2.540 ± 0.254)
0.014 – 0.026
(0.360 – 0.660)
0.038 – 0.068
(0.965 – 1.727)
0.200
(5.080)
MAX
0.160
(4.064)
MAX
0.125
(3.175)
MIN
J Package
20-Lead Ceramic DIP
T
JMAX
θ
JA
150°C80°C/W
T
JMAX
θ
JA
150°C80°C/W
N Package
16-Lead Plastic DIP
N16 1291
0.260 ± 0.010
(6.604 ± 0.254)
0.770
(19.558)
16
1234567
8
910
11
12
1314
15
0.009 - 0.015
(0.229 - 0.381)
0.300 – 0.325
(7.620 – 8.255)
0.325 +0.025
–0.015
+0.635
–0.381
8.255
()
0.015
(0.381)
MIN
0.125
(3.175)
MIN
0.130 ± 0.005
(3.302 ± 0.127)
0.065
(1.651)
TYP
0.045 – 0.065
(1.143 – 1.651)
0.018 ± 0.003
(0.457 ± 0.076)
0.045 ± 0.015
(1.143 ± 0.381)
0.100 ± 0.010
(2.540 ± 0.254)
T
JMAX
θ
JA
110°C 100°C/W
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of circuits as described herein will not infringe on existing patent rights.
28
LTC1293/LTC1294/LTC1296
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900
●
FAX
: (408) 434-0507
●
TELEX
: 499-3977
LINEAR TECHNOLOGY CORPORATION 1992
LT/GP 0392 10K REV 0
PACKAGE DESCRIPTIO
U
Dimensions in inches (millimeters) unless otherwise noted.
N Package
20-Lead Plastic DIP
T
JMAX
θ
JA
110°C 100°C/W
T
JMAX
θ
JA
110°C 150°C/W
T
JMAX
θ
JA
110°C 150°C/W
S Package
16-Lead Plastic SOL
0.037 – 0.045
(0.940 – 1.143)
0.004 – 0.012
(0.102 – 0.305)
0.093 – 0.104
(2.362 – 2.642)
0.050
(1.270)
TYP 0.014 – 0.019
(0.356 – 0.483)
TYP
0° – 8° TYP
SEE NOTE
0.005
(0.127)
RAD MIN
0.009 – 0.013
(0.229 – 0.330)
0.016 – 0.050
(0.406 – 1.270)
0.291 – 0.299
(7.391 – 7.595)
× 45°
0.010 – 0.029
(0.254 – 0.737)
SOL16 12/91
NOTE:
PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
SEE NOTE
0.398 – 0.413
(10.109 – 10.490)
16 15 14 13 12 11 10 9
12345678
0.394 – 0.419
(10.008 – 10.643)
S Package
20-Lead Plastic SOL
0° – 8° TYP
SEE NOTE
0.005
(0.127)
RAD MIN
0.009 – 0.013
(0.229 – 0.330)
0.016 – 0.050
(0.406 – 1.270)
0.291 – 0.299
(7.391 – 7.595)
× 45°
0.010 – 0.029
(0.254 – 0.737)
SOL20 12/91
NOTE:
PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
SEE NOTE
0.496 – 0.512
(12.598 – 13.995)
20 19 18 17 16 15 14 13
12345678
0.394 – 0.419
(10.008 – 10.643)
910
1112
0.037 – 0.045
(0.940 – 1.143)
0.004 – 0.012
(0.102 – 0.305)
0.093 – 0.104
(2.362 – 2.642)
0.050
(1.270)
TYP 0.014 – 0.019
(0.356 – 0.483)
TYP
N20 0192
0.009 – 0.015
(0.229 – 0.381)
0.300 – 0.325
(7.620 – 8.255)
0.325 +0.025
–0.015
+0.635
–0.381
8.255
()
0.015
(0.381)
MIN
0.125
(3.175)
MIN
0.130 ± 0.005
(3.302 ± 0.127)
0.045 – 0.065
(1.143 – 1.651)
0.018 ± 0.003
(0.457 ± 0.076)
0.065 ± 0.015
(1.651 ± 0.381)
0.100 ± 0.010
(2.540 ± 0.254)
0.065
(1.651)
TYP
17 16 1215 14 13 11
18
19
20
12345678910
1.040
(26.416)
MAX
0.260 ± 0.010
(6.604 ± 0.254)
