Micron Serial NOR Flash Memory
3V, 2Mb Page Erasable with Byte Alterability
M45PE20
Features
SPI bus-compatible serial interface
75 MHz clock frequency (MAX)
2.7–3.6V single supply voltage
2Mb of page-erasable Flash memory
Page size: 256 bytes
Page write: 11ms (TYP)
Page program: 0.8ms (TYP)
Page erase: 10ms (TYP)
Sector erase: 64KB
Hardware write protection of the bottom memory
area 64KB
Electronic signature
JEDEC-standard, 2-byte signature (4012h)
Deep power-down mode: 1µA (TYP)
WRITE cycles per sector: >100,000
Years of data retention: >20
Packages (RoHS-compliant)
VFQFPN8 (MP) 6mm x 5mm
SO8N (MN) 150 mil
75MHz, Serial Peripheral Interface Flash Memory
Features
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© 2011 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Contents
Functional Description ..................................................................................................................................... 5
Signal Descriptions ........................................................................................................................................... 7
Configuration and Memory Map ....................................................................................................................... 8
Memory Configuration and Block Diagram .................................................................................................... 8
Memory Map – 2Mb Density ............................................................................................................................. 9
Operating Features Overview .......................................................................................................................... 10
Sharing the Overhead of Modifying Data ..................................................................................................... 10
Easy Method to Modify Data ....................................................................................................................... 10
Fast Method to Modify Data ........................................................................................................................ 10
Polling During a WRITE, PROGRAM, or ERASE Cycle ................................................................................... 11
Reset .......................................................................................................................................................... 11
Active Power, Standby Power, and Deep Power-Down .................................................................................. 11
Status Register ............................................................................................................................................ 11
Protection Modes ....................................................................................................................................... 11
Serial Peripheral Interface Modes .................................................................................................................... 13
Command Set Overview ................................................................................................................................. 15
WRITE ENABLE .............................................................................................................................................. 17
WRITE DISABLE ............................................................................................................................................. 18
READ IDENTIFICATION ................................................................................................................................. 19
READ STATUS REGISTER ................................................................................................................................ 20
WIP Bit ...................................................................................................................................................... 21
WEL Bit ...................................................................................................................................................... 21
READ DATA BYTES ......................................................................................................................................... 22
READ DATA BYTES at HIGHER SPEED ............................................................................................................ 23
PAGE WRITE .................................................................................................................................................. 24
PAGE PROGRAM ............................................................................................................................................ 25
PAGE ERASE ................................................................................................................................................... 26
SECTOR ERASE .............................................................................................................................................. 27
DEEP POWER-DOWN ..................................................................................................................................... 28
RELEASE from DEEP POWER-DOWN .............................................................................................................. 29
Electrical Characteristics ................................................................................................................................ 30
Maximum Ratings and Operating Conditions .................................................................................................. 31
AC Characteristics .......................................................................................................................................... 32
Package Information ...................................................................................................................................... 38
Device Ordering Information .......................................................................................................................... 40
Standard Parts ............................................................................................................................................ 40
Revision History ............................................................................................................................................. 41
Rev. B – 03/14 ............................................................................................................................................. 41
Rev. A – 05/13 ............................................................................................................................................. 41
75MHz, Serial Peripheral Interface Flash Memory
Features
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List of Figures
Figure 1: Logic Diagram ................................................................................................................................... 5
Figure 2: Pin Connections: VFQFPN and SO ..................................................................................................... 6
Figure 3: Block Diagram .................................................................................................................................. 8
Figure 4: Bus Master and Memory Devices on the SPI Bus ............................................................................... 14
Figure 5: SPI Modes ....................................................................................................................................... 14
Figure 6: WRITE ENABLE Command Sequence .............................................................................................. 17
Figure 7: WRITE DISABLE Command Sequence ............................................................................................. 18
Figure 8: READ IDENTIFICATION Command Sequence ................................................................................. 20
Figure 9: READ STATUS REGISTER Command Sequence ................................................................................ 20
Figure 10: Status Register Format ................................................................................................................... 21
Figure 11: READ DATA BYTES Command Sequence ........................................................................................ 22
Figure 12: READ DATA BYTES at HIGHER SPEED Command Sequence ........................................................... 23
Figure 13: PAGE WRITE Command Sequence ................................................................................................. 24
Figure 14: PAGE PROGRAM Command Sequence ........................................................................................... 25
Figure 15: SECTOR ERASE Command Sequence ............................................................................................. 26
Figure 16: SECTOR ERASE Command Sequence ............................................................................................. 27
Figure 17: DEEP POWER-DOWN Command Sequence ................................................................................... 28
Figure 18: RELEASE from DEEP POWER-DOWN Command Sequence ............................................................. 29
Figure 19: AC Measurement I/O Waveform ..................................................................................................... 32
Figure 20: Serial Input Timing ........................................................................................................................ 36
Figure 21: Write Protect Setup and Hold Timing ............................................................................................. 36
Figure 22: Output Timing .............................................................................................................................. 37
Figure 23: Reset AC Waveforms ...................................................................................................................... 37
Figure 24: VFQFPN8 (MLP8) 6mm x 5mm ...................................................................................................... 38
Figure 25: SO8N 150 mils Body Width ............................................................................................................ 39
75MHz, Serial Peripheral Interface Flash Memory
Features
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List of Tables
Table 1: Signal Names ...................................................................................................................................... 5
Table 2: Signal Descriptions ............................................................................................................................. 7
Table 3: Sectors[3:0] ........................................................................................................................................ 9
Table 4: SPI Modes ........................................................................................................................................ 13
Table 5: Command Set Codes ........................................................................................................................ 16
Table 6: READ IDENTIFICATION Data-Out Sequence ..................................................................................... 19
Table 7: DC Current Specifications ................................................................................................................. 30
Table 8: DC Voltage Specifications ................................................................................................................. 30
Table 9: Absolute Maximum Ratings .............................................................................................................. 31
Table 10: Operating Conditions ...................................................................................................................... 31
Table 11: AC Measurement Conditions ........................................................................................................... 32
Table 12: Capacitance .................................................................................................................................... 32
Table 13: AC Specifications (50 MHz Operation) ............................................................................................. 33
Table 14: AC Specifications (75MHz) .............................................................................................................. 34
Table 15: Reset Specifications ........................................................................................................................ 35
Table 16: Part Number Information Scheme ................................................................................................... 40
75MHz, Serial Peripheral Interface Flash Memory
Features
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Functional Description
The M45PE20 is a 2Mb (256Kb x 8) serial Flash memory device accessed by a high-
speed, SPI-compatible bus.
The memory can be written or programmed 1 to 256 bytes at a time using the PAGE
WRITE or PAGE PROGRAM command. The PAGE WRITE command consists of an inte-
grated PAGE ERASE cycle followed by a PAGE PROGRAM cycle.
The memory is organized as 16 sectors, each containing 256 pages. Each page is 256
bytes wide. The entire memory can be viewed as consisting of 1024 pages, or 262,144
bytes.
The memory can be erased one page at a time using the PAGE ERASE command or one
sector at a time using the SECTOR ERASE command.
To meet environmental requirements, Micron offers the device in RoHS-compliant
packages, which are also lead-free.
Figure 1: Logic Diagram
S#
VCC
RESET#
VSS
DQ1
C
DQ0
W#
Table 1: Signal Names
Signal Name Function Direction
C Serial clock Input
DQ0 Serial data input Input
DQ1 Serial data output Output
S# Chip select Input
W# Write protect Input
RESET# Reset Input
VCC Supply voltage
VSS Ground
75MHz, Serial Peripheral Interface Flash Memory
Functional Description
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Figure 2: Pin Connections: VFQFPN and SO
1
2
3
4
DQ1
5
6
7
8
C
S#
DQ0
W#
VSS
VCC
RESET#
There is an exposed central pad on the underside of the VFQFPN package that is pulled
internally to VSS and must not be connected to any other voltage or signal line on the
PCB. The Package Information section provides details about package dimensions and
how to identify pin 1.
75MHz, Serial Peripheral Interface Flash Memory
Functional Description
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Signal Descriptions
Table 2: Signal Descriptions
Signal Type Description
DQ0 Input Serial data: Transfers data serially into the device. DQ0 receives commands, address-
es, and data to be programmed. Values are latched on the rising edge of serial clock
(C).
C Input Clock: Provides timing for the serial interface. Commands, addresses, or data present
at serial data input (DQ0) is latched on the rising edge of serial clock (C). Data on DQ1
changes after the falling edge of C.
S# Input Chip select: When S# is HIGH, the device is deselected and DQ1 is High-Z. Unless an
internal READ, PROGRAM, ERASE, or WRITE cycle is in progress, the device will be in
the standby power mode (not deep power-down mode). Driving S# LOW enables the
device, placing it in the active power mode. After power-up, a falling edge on S# is
required prior to the start of any command.
RESET# Input Reset: Provides a hardware reset for the memory. When RESET# is driven HIGH, the
device is in the normal operating mode. When RESET# is driven LOW, the device en-
ters the reset mode. In reset mode, the output is High-Z. Driving RESET# LOW while an
internal operation is in progress affects the WRITE, PROGRAM, or ERASE cycle, and da-
ta may be lost.
W# Input Write protect: Places the device in hardware protected mode when connected to VSS,
causing the first 256 pages of memory to become read-only, protected from WRITE,
PROGRAM, and ERASE operations. When W# is connected to VCC, the first 256 pages
of memory behave like the other pages.
DQ1 Output Serial data: Transfers data serially out of the device. Data is shifted out on the falling
edge of the serial clock (C).
VCC Supply Supply voltage: 2.7–3.6V
VSS Supply Ground: Reference for VCC.
75MHz, Serial Peripheral Interface Flash Memory
Signal Descriptions
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Configuration and Memory Map
Memory Configuration and Block Diagram
Each page of memory can be individually programmed; bits are programmed from 1 to
0 and when written to are changed to either 0 or 1. The device is sector- and page-erasa-
ble; bits are erased from 0 to 1. The memory is configured as follows:
262,144 bytes (8 bits each)
4 sectors (512Kb, 65KB each)
1024 pages (256 bytes each)
Figure 3: Block Diagram
RESET#
S#
W# Control Logic
High Voltage
Generator
I/O Shift Register
Address Register
and Counter
256 Byte
Data Buffer
256 bytes (page size)
X Decoder
Y Decoder
C
DQ0
DQ1
Status
Register
00000h
10000h
3FFFFh
000FFh
(Note 1)
75MHz, Serial Peripheral Interface Flash Memory
Configuration and Memory Map
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Memory Map – 2Mb Density
Table 3: Sectors[3:0]
Sector
Address Range
Start End
3 0003 0000h 0003 FFFFh
2 0002 0000h 0002 FFFFh
1 0001 0000h 0001 FFFFh
0 0000 0000h 0000 FFFFh
75MHz, Serial Peripheral Interface Flash Memory
Memory Map – 2Mb Density
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Operating Features Overview
Sharing the Overhead of Modifying Data
To write or program 1 or more data bytes, two commands are required: WRITE ENABLE
which is 1 byte, and a PAGE WRITE or PAGE PROGRAM command sequence, which
consists of 4 bytes plus data. This is followed by the internal cycle of duration tPW or tPP.
To share this overhead, the PAGE WRITE or PAGE PROGRAM command allows up to 256
bytes to be programmed (changing bits from 1 to 0) or written (changing bits to 0 or 1)
at a time, provided that they lie in consecutive addresses on the same page of memory.
Easy Method to Modify Data
The PAGE WRITE command provides a convenient way of modifying data (up to 256
contiguous bytes at a time) and requires the start address and the new data in the in-
struction sequence.
The PAGE WRITE command is entered by driving chip select (S#) LOW, and then trans-
mitting the instruction byte, 3 address bytes A[23:0] and at least 1 data byte, and then
driving S# HIGH. While S# is being held LOW, the data bytes are written to the data buf-
fer, starting at the address given in the third address byte A[7:0]. When S# is driven
HIGH, the WRITE cycle starts. The remaining unchanged bytes of the data buffer are
automatically loaded with the values of the corresponding bytes of the addressed mem-
ory page. The addressed memory page is then automatically put into an ERASE cycle.
Finally, the addressed memory page is programmed with the contents of the data buf-
fer.
All of this buffer management is handled internally, and is transparent to the user. The
user may alter the contents of the memory on a byte-by-byte basis. For optimized tim-
ings, it is recommended to use the PAGE WRITE command to write all consecutive tar-
geted bytes in a single sequence versus using several PAGE WRITE sequences with each
containing only a few bytes.
Fast Method to Modify Data
The PAGE PROGRAM command provides a fast way of modifying data (up to 256 con-
tiguous bytes at a time), provided that it only involves resetting bits to 0 that had previ-
ously been set to 1.
This might be:
When the designer is programming the device for the first time.
When the designer knows that the page has already been erased by an earlier PAGE
ERASE or SECTOR ERASE command. This is useful, for example, when storing a fast
stream of data, having first performed the erase cycle when time was available.
When the designer knows that the only changes involve resetting bits to 0 that are still
set to 1. When this method is possible, it has the additional advantage of minimizing
the number of unnecessary ERASE operations and the extra stress incurred by each
page.
For optimized timings, it is recommended to use the PAGE PROGRAM command to
program all consecutive targeted bytes in a single sequence versus using several PAGE
PROGRAM sequences with each containing only a few bytes.
75MHz, Serial Peripheral Interface Flash Memory
Operating Features Overview
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Polling During a WRITE, PROGRAM, or ERASE Cycle
The following commands can be completed faster by not waiting for the worst-case de-
lay (tW, tPP, tPE, tBE, or tSE).
The write in progress (WIP) bit is provided in the status register so that the application
program can monitor this bit in the status register, polling it to establish when the pre-
vious WRITE, PROGRAM, or ERASE cycle is complete.
Reset
An internal power-on reset circuit helps protect against inadvertent data writes. Addi-
tional protection is provided by driving RESET# LOW during the power-on process, and
driving it HIGH only when VCC has reached the correct voltage level, VCC,min.
Active Power, Standby Power, and Deep Power-Down
When chip select (S#) is LOW, the device is selected and in the active power mode.
When S# is HIGH, the device is deselected, but could remain in the active power mode
until all internal cycles have completed (PROGRAM, ERASE, WRITE). The device then
goes in to the standby power mode, and power consumption drops to ICC1.
The deep power-down mode is entered when the DEEP POWER-DOWN command is
executed. The device power consumption drops further to ICC2. The device remains in
this mode until the RELEASE FROM DEEP POWER-DOWN command is executed. While
in the deep power-down mode, the device ignores all WRITE, PROGRAM, and ERASE
commands. This provides an extra software protection mechanism when the device is
not in active use, by protecting the device from inadvertent WRITE, PROGRAM, or
ERASE operations. For further information, see the DEEP POWER-DOWN section.
Status Register
The status register contains a number of status bits that can be read by the READ STA-
TUS REGISTER (RDSR) command. For a detailed description of the status register bits,
see the READ STATUS REGISTER section.
Protection Modes
Nonvolatile memory is used in environments that can include excessive noise. The fol-
lowing capabilities help protect data in these noisy environments.
Power-on reset and an internal timer (tPUW) can provide protection against inadver-
tent changes while the power supply is outside the operating specification.
WRITE, PROGRAM, and ERASE commands are checked before they are accepted for ex-
ecution to ensure they consist of a number of clock pulses that is a multiple of eight.
All commands that modify data must be preceded by a WRITE ENABLE command to set
the write enable latch (WEL) bit. This bit is returned to its reset state by the following
events.
Power-up
Reset (RESET#) driven LOW
WRITE DISABLE command completion
PAGE WRITE command completion
PAGE PROGRAM command completion
75MHz, Serial Peripheral Interface Flash Memory
Operating Features Overview
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PAGE ERASE command completion
SECTOR EASE command completion
The hardware-protected mode is entered when W# is driven LOW, causing the first 256
pages of memory to become read-only. When W# is driven HIGH, the first 256 pages of
memory behave like the other pages of memory. The RESET# signal can be driven LOW
to freeze and reset the internal logic.
In addition to the low power-consumption feature, deep power-down mode offers extra
software protection from inadvertent WRITE, PROGRAM, and ERASE commands while
the device is not in active use.
75MHz, Serial Peripheral Interface Flash Memory
Operating Features Overview
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Serial Peripheral Interface Modes
The device can be driven by a microcontroller while its serial peripheral interface is in
either of the two modes shown in the following table. The difference between the two
modes is the clock polarity when the bus master is in standby mode and not transfer-
ring data. Input data is latched in on the rising edge of the clock, and output data is
available from the falling edge of the clock.
Table 4: SPI Modes
Note 1 applies to the entire table
SPI Modes Clock Polarity
CPOL = 0, CPHA = 0 C remains at 0 for (CPOL = 0, CPHA = 0)
CPOL = 1, CPHA = 1 C remains at 1 for (CPOL = 1, CPHA = 1)
Note: 1. The listed SPI modes are supported in extended, dual, and quad SPI protocols.
The following figures show an example of three memory devices in extended SPI proto-
col in a simple connection to an MCU on a SPI bus. Because only one device is selected
at a time, that one device drives DQ1, while the other devices are High-Z.
Resistors ensure that the device is not selected if the bus master leaves chip select (S#)
High-Z. The bus master might enter a state in which all input/output is High-Z simulta-
neously, such as when the bus master is reset. Therefore, the serial clock must be con-
nected to an external pull-down resistor so that S# is pulled HIGH while the serial clock
is pulled LOW. This ensures that S# and the serial clock are not HIGH simultaneously
and that tSHCH is met. The typical resistor value of 100kΩ, assuming that the time con-
stant R × Cp (Cp = parasitic capacitance of the bus line), is shorter than the time the bus
master leaves the SPI bus in High-Z.
Example: Cp = 50 pF, that is R × Cp = 5μs. The application must ensure that the bus
master never leaves the SPI bus High-Z for a time period shorter than 5μs. W# and
HOLD# should be driven either HIGH or LOW, as appropriate.
75MHz, Serial Peripheral Interface Flash Memory
Serial Peripheral Interface Modes
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Figure 4: Bus Master and Memory Devices on the SPI Bus
SPI bus master
SPI memory
device
SDO
SDI
SCK
C
DQ1 DQ0
S#
SPI memory
device
C
DQ1 DQ0
S#
SPI memory
device
C
DQ1 DQ0
S#
CS3 CS2 CS1
SPI interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
W# RESET# RESET# W# RESET#
R R R
VCC VCC
VSS VSS
R
W#
VSS
VCC
VCC
VSS
Figure 5: SPI Modes
C
C
DQ0
DQ1
CPHA
0
1
CPOL
0
1
MSB
MSB
75MHz, Serial Peripheral Interface Flash Memory
Serial Peripheral Interface Modes
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Command Set Overview
All commands, addresses, and data are shifted in and out of the device, most significant
bit first.
Serial data inputs DQ0 and DQ1 are sampled on the first rising edge of serial clock (C)
after chip select (S#) is driven LOW. Then, the 1-byte command code must be shifted
into the device, most significant bit first, on DQ0 and DQ1, with each bit latched on the
rising edges of C.
Every command sequence starts with a 1-byte command code. Depending on the com-
mand, this command code might be followed by address or data bytes, by address and
data bytes, or by neither address nor data bytes. For the following commands, the shif-
ted-in command sequence is followed by a data-out sequence. S# can be driven HIGH
after any bit of the data-out sequence is being shifted out.
READ DATA BYTES (READ)
READ DATA BYTES at HIGHER SPEED
READ STATUS REGISTER
For the following commands, S# must be driven HIGH exactly at a byte boundary. That
is, after an exact multiple of eight clock pulses following S# being driven LOW, S# must
be driven HIGH. Otherwise, the command is rejected and not executed.
PAGE WRITE
PAGE PROGRAM
PAGE ERASE
SECTOR ERASE
WRITE ENABLE
WRITE DISABLE
DEEP POWER-DOWN
RELEASE FROM DEEP POWER-DOWN
All attempts to access the memory array are ignored during a WRITE STATUS REGIS-
TER, PROGRAM, or ERASE command cycle. In addition, the internal cycle for each of
these commands continues unaffected.
75MHz, Serial Peripheral Interface Flash Memory
Command Set Overview
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Table 5: Command Set Codes
Command Name
1-Byte
Command Code
Bytes
Address Dummy Data
WRITE ENABLE 0000
0110
06h 0 0 0
WRITE DISABLE 0000
0100
04h 0 0 0
READ IDENTIFICATION 1001
1111
9Fh 0 0 1 to 20
READ STATUS REGISTER 0000
0101
05h 0 0 1 to
READ DATA BYTES 0000
0011
03h 3 0 1 to
READ DATA BYTES at HIGHER SPEED 0000
1011
0Bh 3 1 1 to
PAGE WRITE 0000
1010
0Ah 3 0 1 to 256
PAGE PROGRAM 0000
0010
02h 3 0 1 to 256
PAGE ERASE 1101
1011
DBh 3 0 0
SECTOR ERASE 1101
1000
D8h 3 0 0
DEEP POWER-DOWN 1011
1001
B9h 0 0 0
RELEASE from DEEP POWER-DOWN 1010
1011
ABh 0 0 0
75MHz, Serial Peripheral Interface Flash Memory
Command Set Overview
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WRITE ENABLE
The WRITE ENABLE command sets the write enable latch (WEL) bit.
The WEL bit must be set before execution of every PAGE WRITE, PAGE PROGRAM,
PAGE ERASE, and SECTOR ERASE command.
The WRITE ENABLE command is entered by driving chip select (S#) LOW, sending the
command code, and then driving S# HIGH.
Figure 6: WRITE ENABLE Command Sequence
Don’t Care
DQ[0]
01 2 4 53 76
C
High-Z
DQ1
MSB
LSB
0 0 0 0 0 011
Command bits
S#
75MHz, Serial Peripheral Interface Flash Memory
WRITE ENABLE
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WRITE DISABLE
The WRITE DISABLE command resets the write enable latch (WEL) bit.
The WRITE DISABLE command is entered by driving chip select (S#) LOW, sending the
command code, and then driving S# HIGH.
The WEL bit is reset under the following conditions:
Power-up
Completion of WRITE DISABLE operation
Completion of PAGE WRITE operation
Completion of PAGE PROGRAM operation
Completion of PAGE ERASE operation
Completion of SECTOR ERASE operation
Figure 7: WRITE DISABLE Command Sequence
Don’t Care
DQ[0]
01 2 4 53 76
C
High-Z
DQ1
MSB
LSB
0 0 0 0 0 001
Command bits
S#
75MHz, Serial Peripheral Interface Flash Memory
WRITE DISABLE
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READ IDENTIFICATION
The READ IDENTIFICATION command reads the following device identification data:
Manufacturer identification (1 byte): This is assigned by JEDEC.
Device identification (2 bytes): This is assigned by device manufacturer; the first byte
indicates memory type, and the second byte indicates device memory capacity.
A unique ID code (UID) (17 bytes, 16 available upon customer request): The first byte
contains the length of the data to follow; the remaining 16 bytes contain optional cus-
tomized factory data (CFD) content.
Table 6: READ IDENTIFICATION Data-Out Sequence
Manufacturer
Identification
Device Identification UID
Memory Type Memory Capacity CFD Length CFD Content
20h 40h 12h 10h 16 bytes
Note: 1. The CFD bytes are read-only and can be programmed with customer data upon demand.
If customers do not make requests, the devices are shipped with all the CFD bytes pro-
grammed to 0.
A READ IDENTIFICATION command is not decoded while an ERASE or PROGRAM cy-
cle is in progress and has no effect on a cycle in progress.
The device is first selected by driving chip select (S#) LOW. Then, the 8-bit command
code is shifted in, and content is shifted out on serial data output (DQ1) as follows: the
24-bit device identification stored in memory, then the 8-bit CFD length, followed by 16
bytes of CFD content. Each bit is shifted out during the falling edge of the serial clock
(C).
The READ IDENTIFICATION command is terminated by driving S# HIGH at any time
during data output. When S# is driven HIGH, the device is put in the standby power
mode and waits to be selected so that it can receive, decode, and execute commands.
75MHz, Serial Peripheral Interface Flash Memory
READ IDENTIFICATION
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Figure 8: READ IDENTIFICATION Command Sequence
UIDDevice
identification
Manufacturer
identification
High-Z
DQ1
MSB MSB
DOUT DOUT DOUT DOUT
LSB
LSB
7 8 15 16 32
31
0
C
MSB
DQ0
LSB
Command
MSB
DOUT DOUT
LSB
Don’t Care
READ STATUS REGISTER
The READ STATUS REGISTER command allows the status register to be read. The status
register may be read at any time, even while a PROGRAM, ERASE, or WRITE STATUS
REGISTER cycle is in progress. When one of these cycles is in progress, it is recommen-
ded to check the write in progress (WIP) bit before sending a new command to the de-
vice. It is also possible to read the status register continuously.
Figure 9: READ STATUS REGISTER Command Sequence
High-Z
DQ1
7 8 9 10 11 12 13 14 15
0
C
MSB
DQ0
LSB
Command
MSB
DOUT DOUT DOUT DOUT DOUT
LSB
DOUT DOUT DOUT DOUT
Don’t Care
75MHz, Serial Peripheral Interface Flash Memory
READ STATUS REGISTER
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Figure 10: Status Register Format
WIP Bit
The write in progress (WIP) bit is a volatile read-only bit that indicates whether the
memory is busy with a WRITE, a PROGRAM, or ERASE cycle. When the WIP bit is set to
1, a cycle is in progress; when the WIP bit is set to 0, a cycle is not in progress. WIP is set
and reset automatically by the internal logic of the device.
WEL Bit
The write enable latch (WEL) bit is a volatile read-only bit that indicates the status of
the internal write enable latch. When the WEL bit is set to 1, the internal write enable
latch is set; when the WEL bit is set to 0, the internal write enable latch is reset and no
WRITE , PROGRAM, or ERASE command is accepted. The WEL bit is set and reset by
specific commands.
75MHz, Serial Peripheral Interface Flash Memory
READ STATUS REGISTER
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© 2011 Micron Technology, Inc. All rights reserved.
READ DATA BYTES
The device is first selected by driving chip select (S#) LOW. The command code for
READ DATA BYTES is followed by a 3-byte address A[23:0], with each bit latched in dur-
ing the rising edge of the serial clock (C). The memory contents at that address are then
shifted out on a serial data output (DQ1), with each bit shifted out at a maximum fre-
quency fR during the falling edge of C.
The first byte addressed can be at any location. The address is automatically incremen-
ted to the next-higher address after each byte of data is shifted out. Therefore, the entire
memory can be read with a single READ DATA BYTES command. When the highest ad-
dress is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The READ DATA BYTES command is terminated by driving S# HIGH. S# can be driven
HIGH at any time during data output. Any READ DATA BYTES command issued while
an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without any effect on
the cycle that is in progress.
Figure 11: READ DATA BYTES Command Sequence
Don’t Care
MSB
DQ[0]
LSB
Command
A[MAX]
A[MIN]
7 8 Cx
0
C
High-Z
DQ1
MSB
DOUT DOUT DOUT DOUT DOUT
LSB
DOUT DOUT DOUT DOUT
Notes: 1. Cx= 7 + (A[MAX] + 1).
2. Address bits A[23:18] are "Don't Care" in the M25PE20.
75MHz, Serial Peripheral Interface Flash Memory
READ DATA BYTES
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© 2011 Micron Technology, Inc. All rights reserved.
READ DATA BYTES at HIGHER SPEED
The device is first selected by driving chip select (S#) LOW. The command code for the
READ DATA BYTES at HIGHER SPEED command is followed by a 3-byte address A[23:0]
and a dummy byte, with each bit latched in during the rising edge of the serial clock (C).
The memory contents at that address are then shifted out on a serial data output (DQ1)
at a maximum frequency fC, during the falling edge of C.
The first byte addressed can be at any location. The address is automatically incremen-
ted to the next-higher address after each byte of data is shifted out. Therefore, the entire
memory can be read with a single READ DATA BYTES at HIGHER SPEED command.
When the highest address is reached, the address counter rolls over to 000000h, allow-
ing the read sequence to be continued indefinitely.
The READ DATA BYTES at HIGHER SPEED command is terminated by driving S# HIGH.
S# can be driven HIGH at any time during data output. Any READ DATA BYTES at
HIGHER SPEED command issued while an ERASE, PROGRAM, or WRITE cycle is in
progress is rejected without any effect on the cycle that is in progress.
Figure 12: READ DATA BYTES at HIGHER SPEED Command Sequence
7 8 Cx
0
C
MSB
DQ0
LSB
Command
A[MAX]
A[MIN]
MSB
DOUT DOUT DOUT DOUT DOUT
LSB
DOUT DOUT DOUT DOUT
Dummy cycles
DQ1 High-Z
Don’t Care
Notes: 1. Cx= 7 + (A[MAX] + 1).
2. Address bits A[23:18] are "Don't Care" in the M25PE20.
75MHz, Serial Peripheral Interface Flash Memory
READ DATA BYTES at HIGHER SPEED
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© 2011 Micron Technology, Inc. All rights reserved.
PAGE WRITE
The PAGE WRITE command allows bytes in the memory to be programmed. Before a
PAGE WRITE command can be accepted, a WRITE ENABLE command must be execu-
ted. After the WRITE ENABLE command has been decoded, the device sets the write en-
able latch (WEL) bit.
The PAGE WRITE command is entered by driving chip select (S#) LOW, followed by the
command code, 3 address bytes, and at least 1 data byte on a serial data input (DQ0).
The reset of the page remains unchanged if no power failure occurs during this WRITE
cycle. The PAGE WRITE command performs a PAGE ERASE cycle even if only 1 byte is
updated.
If the eight least-significant address bits A[7:0] are not all 0, all transmitted data that
goes beyond the end of the current page is programmed from the start address of the
same page; that is, from the address whose eight least-significant bits A[7:0] are all 0. S#
must be driven LOW for the entire duration of the sequence.
If more than 256 bytes are sent to the device, previously latched data is discarded, and
the last 256 data bytes are guaranteed to be programmed correctly within the same
page. If fewer than 256 data bytes are sent to device, they are correctly programmed at
the requested addresses without any effect on the other bytes of the same page.
For optimized timings, it is recommended to use the PAGE WRITE command to pro-
gram all consecutive targeted bytes in a single sequence rather than to use several PAGE
WRITE command sequences, each containing only a few bytes.
S# must be driven HIGH after the eighth bit of the last data byte has been latched in;
otherwise, the PAGE WRITE command is not executed.
As soon as S# is driven HIGH, the self-timed PAGE WRITE cycle is initiated. While the
PAGE WRITE cycle is in progress, the status register may be read to check the value of
the write in progress (WIP) bit. The WIP bit is 1 during the self-timed PAGE WRITE cycle
and 0 when the cycle is completed. At some unspecified time before the cycle is com-
pleted, the write enable latch (WEL) bit is reset.
A PAGE WRITE command is not executed if it applies to a page that is hardware-protec-
ted. Any PAGE WRITE command while an ERASE, PROGRAM, or WRITE cycle is in pro-
gress is rejected without having any effect on the cycle that is in progress.
Figure 13: PAGE WRITE Command Sequence
7 8 Cx
0
C
MSB
DQ[0]
LSB
Command
A[MAX]
A[MIN]
MSB
DIN DIN DIN DIN DIN
LSB
DIN DIN DIN DIN
Notes: 1. Cx= 7 + (A[MAX] + 1).
2. Address bits A[23:18] are "Don't Care" in the M25PE20.
3. 1 <n<256.
75MHz, Serial Peripheral Interface Flash Memory
PAGE WRITE
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© 2011 Micron Technology, Inc. All rights reserved.
PAGE PROGRAM
The PAGE PROGRAM command allows bytes in the memory to be programmed, which
means the bits are changed from 1 to 0. Before a PAGE PROGRAM command can be ac-
cepted, a WRITE ENABLE command must be executed. After the WRITE ENABLE com-
mand has been decoded, the device sets the write enable latch (WEL) bit.
The PAGE PROGRAM command is entered by driving chip select (S#) LOW, followed by
the command code, 3 address bytes, and at least 1 data byte on a serial data input
(DQ0).
If the eight least-significant address bits A[7:0] are not all 0, all transmitted data that
goes beyond the end of the current page is programmed from the start address of the
same page, that is, from the address whose eight least-significant bits A[7:0] are all 0. S#
must be driven LOW for the entire duration of the sequence.
If more than 256 bytes are sent to the device, previously latched data is discarded, and
the last 256 data bytes are guaranteed to be programmed correctly within the same
page. If fewer than 256 data bytes are sent to device, they are correctly programmed at
the requested addresses without any effect on the other bytes of the same page.
For optimized timings, it is recommended to use the PAGE PROGRAM command to
program all consecutive targeted bytes in a single sequence rather than to use several
PAGE PROGRAM sequences, each containing only a few bytes.
S# must be driven HIGH after the eighth bit of the last data byte has been latched in;
otherwise, the PAGE PROGRAM command is not executed.
As soon as S# is driven HIGH, the self-timed PAGE PROGRAM cycle is initiated; the cy-
cles's duration is tPP. While the PAGE PROGRAM cycle is in progress, the status register
may be read to check the value of the write in progress (WIP) bit. The WIP bit is 1 during
the self-timed PAGE PROGRAM cycle and 0 when the cycle is completed. At some un-
specified time before the cycle is completed, the write enable latch (WEL) bit is reset.
A PAGE PROGRAM command is not executed if it applies to a page protected by all the
block-protect bits.
Figure 14: PAGE PROGRAM Command Sequence
7 8 Cx
0
C
MSB
DQ[0]
LSB
Command
A[MAX]
A[MIN]
MSB
DIN DIN DIN DIN DIN
LSB
DIN DIN DIN DIN
Notes: 1. Cx = 7 + (A[MAX] + 1).
2. Address bits A[23:18] are "Don't Care" in the M25PE20.
75MHz, Serial Peripheral Interface Flash Memory
PAGE PROGRAM
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PAGE ERASE
The PAGE ERASE command sets to 1 (FFh) all bits inside the designated page. Before
the PAGE ERASE command can be accepted, a WRITE ENABLE command must have
been executed previously. After the WRITE ENABLE command has been decoded, the
device sets the write enable latch (WEL) bit.
The PAGE ERASE command is entered by driving chip select (S#) LOW, followed by the
command code and 3 address bytes on a serial data input (DQ0). Any address inside the
sector is a valid address for the PAGE ERASE command. S# must be driven LOW for the
entire duration of the sequence.
S# must be driven HIGH after the eighth bit of the last address byte has been latched in;
otherwise, the PAGE ERASE command is not executed. As soon as S# is driven HIGH,
the self-timed PAGE ERASE cycle is initiated; the cycle's duration is tPE. While the PAGE
ERASE cycle is in progress, the status register may be read to check the value of the write
in progress (WIP) bit. The WIP bit is 1 during the self-timed PAGE ERASE cycle and 0
when the cycle is completed. At some unspecified time before the cycle is completed,
the WEL bit is reset.
A PAGE ERASE command is not executed if it applies to a page that is protected by the
block-protect bits BP1 and BP0.
A PAGE ERASE command issued while an ERASE, PROGRAM, or WRITE cycle is in pro-
gress is rejected without having any effect on the cycle that is in progress.
Figure 15: SECTOR ERASE Command Sequence
7 8 Cx
0
C
MSB
DQ0
LSB
Command
A[MAX]
A[MIN]
Notes: 1. Cx= 7 + (A[MAX] + 1).
2. Address bits A[23:18] are "Don't Care" in the M25PE20.
75MHz, Serial Peripheral Interface Flash Memory
PAGE ERASE
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© 2011 Micron Technology, Inc. All rights reserved.
SECTOR ERASE
The SECTOR ERASE command sets all bits inside the chosen sector to 1 (FFh). Before
the SECTOR ERASE command can be accepted, a WRITE ENABLE command must have
been executed previously. After the WRITE ENABLE command has been decoded, the
device sets the write enable latch (WEL) bit.
The SECTOR ERASE command is entered by driving chip select (S#) LOW, followed by
the command code and 3 address bytes on a serial data input (DQ0). Any address inside
the sector is a valid address for the SECTOR ERASE command. S# must be driven LOW
for the entire duration of the sequence.
S# must be driven HIGH after the eighth bit of the last address byte has been latched in;
otherwise, the SECTOR ERASE command is not executed. As soon as S# is driven HIGH,
the self-timed SECTOR ERASE cycle is initiated; the cycle's duration is tSE. While the
SECTOR ERASE cycle is in progress, the status register may be read to check the value of
the write in progress (WIP) bit. The WIP bit is 1 during the self-timed SECTOR ERASE
cycle and 0 when the cycle is completed. At some unspecified time before the cycle is
completed, the WEL bit is reset.
A SECTOR ERASE command applied to a sector that contains a page that is hardware
protected is not executed.
Any SECTOR ERASE command issued while an ERASE, PROGRAM, or WRITE cycle is in
progress is rejected without having any effects on the cycle that is in progress.
Figure 16: SECTOR ERASE Command Sequence
7 8 Cx
0
C
MSB
DQ0
LSB
Command
A[MAX]
A[MIN]
Notes: 1. Cx= 7 + (A[MAX] + 1).
2. Address bits A[23:18] are "Don't Care" in the M25PE20.
75MHz, Serial Peripheral Interface Flash Memory
SECTOR ERASE
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DEEP POWER-DOWN
Executing the DEEP POWER-DOWN command is the only way to put the device in the
lowest power-consumption mode, the deep power-down mode. The DEEP POWER-
DOWN command can also be used as a software-protection mechanism while the de-
vice is not in active use because in the deep power-down mode the device ignores all
WRITE, PROGRAM, and ERASE commands.
Driving chip select (S#) HIGH deselects the device and puts it in standby power mode if
there is no internal cycle currently in progress. After entering standby power mode, the
deep power-down mode can be entered by executing the DEEP POWER-DOWN com-
mand, subsequently reducing the standby current from ICC1 to ICC2.
To take the device out of deep power-down mode, the RELEASE from DEEP POWER-
DOWN command must be issued. Other commands must not be issued while the de-
vice is in deep power-down mode. The deep power-down mode stops automatically at
power-down. The device always powers up in standby power mode.
The DEEP POWER-DOWN command is entered by driving S# LOW, followed by the
command code on a serial data input (DQ0). S# must be driven LOW for the entire du-
ration of the sequence.
S# must be driven HIGH after the eighth bit of the command code has been latched in;
otherwise, the DEEP POWER-DOWN command is not executed. As soon as S# is driven
HIGH, a delay of tDP is required before the supply current is reduced to ICC2, and deep
power-down mode is entered.
Any DEEP POWER-DOWN command issued while an ERASE, PROGRAM, or WRITE cy-
cle is in progress is rejected without any effect on the cycle that is in progress.
Figure 17: DEEP POWER-DOWN Command Sequence
7
0
C
MSB
DQ0
LSB tDP
Command
Don’t Care
Deep Power-Down ModeStandby Mode
75MHz, Serial Peripheral Interface Flash Memory
DEEP POWER-DOWN
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© 2011 Micron Technology, Inc. All rights reserved.
RELEASE from DEEP POWER-DOWN
After the device has entered deep power-down mode, all commands are ignored except
RELEASE from DEEP POWER-DOWN. Executing this command takes the device out of
deep power-down mode.
The RELEASE from DEEP POWER-DOWN command is entered by driving chip select
(S#) LOW, followed by the command code on a serial data input (DQ0). S# must be driv-
en LOW for the entire duration of the sequence.
The RELEASE from DEEP POWER-DOWN command is terminated by driving S# HIGH.
Sending additional clock cycles on the serial clock (C) while S# is driven LOW causes the
command to be rejected and not executed.
After S# has been driven HIGH, followed by a delay, tRDP, the device is put in the stand-
by mode. S# must remain HIGH at least until this period is over. The device waits to be
selected so that it can receive, decode, and execute commands.
Any RELEASE from DEEP POWER-DOWN command issued while an ERASE, PRO-
GRAM, or WRITE cycle is in progress is rejected without any effect on the cycle that is in
progress.
Figure 18: RELEASE from DEEP POWER-DOWN Command Sequence
High-Z
DQ1
7
0
C
MSB
DQ0
LSB tRDP
Command
Don’t Care
Deep Power-Down Mode Standby Mode
75MHz, Serial Peripheral Interface Flash Memory
RELEASE from DEEP POWER-DOWN
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© 2011 Micron Technology, Inc. All rights reserved.
Electrical Characteristics
Table 7: DC Current Specifications
Parameter Symbol Test Conditions Min Max Units
Input leakage current ILI ±2 µA
Output leakage current ILO ±2 µA
Standby current (standby and re-
set modes)
ICC1 S# = VCC, VIN = VSS, or VCC 50 µA
Deep power-down current ICC2 S# = VCC, VIN = VSS, or VCC 10 µA
Operating current (READ) ICC3 C = 0.1 × VCC / 0.9 × VCC at 75 MHz, DQ1
= open
12 mA
C = 0.1 × VCC / 0.9VCC at 33 MHz, DQ1 =
open
4 mA
Operating current
(PAGE PROGRAM)
ICC4 S# = VCC 15 mA
Operating current
(SECTOR ERASE)
ICC5 S# = VCC 15 mA
Table 8: DC Voltage Specifications
Symbol Parameter Test Conditions Min Max Units
VIL Input LOW voltage –0.5 0.3 × VCC V
VIH Input HIGH voltage 0.7 ×
VCC
VCC + 0.4 V
VOL Output LOW voltage IOL = 1.6mA 0.4 V
VOH Output HIGH voltage IOH = –100µA VCC - 0.2 V
75MHz, Serial Peripheral Interface Flash Memory
Electrical Characteristics
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© 2011 Micron Technology, Inc. All rights reserved.
Maximum Ratings and Operating Conditions
Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. These are stress ratings only, and operation of
the device at these or any other conditions beyond those indicated in the Operating
sections of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Table 9: Absolute Maximum Ratings
Symbol Parameter Min. Max. Unit Notes
TSTG Storage temperature –65 150 °C
TLEAD Lead temperature during soldering See note °C 1
VIO Input and output voltage (with respect to
ground)
–0.6 VCC + 0.6 V
VCC Supply voltage –0.6 4.0 V
VESD Electrostatic discharge voltage (human body
model)
–2000 2000 V 2
Notes: 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly) and the Eu-
ropean directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
Table 10: Operating Conditions
Symbol Parameter Min. Max. Unit
VCC Supply voltage 2.7 3.6 V
TAAmbient operating temperature –40 85 °C
75MHz, Serial Peripheral Interface Flash Memory
Maximum Ratings and Operating Conditions
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© 2011 Micron Technology, Inc. All rights reserved.
AC Characteristics
In the following AC specifications, output HIGH-Z is defined as the point where data
out is no longer driven.
Table 11: AC Measurement Conditions
Parameter Symbol Min Max Unit
Load capacitance CL30 30 pF
Input rise and fall times 5 ns
Input pulse voltages 0.2 × VCC 0.8 × VCC V
Input and output timing reference voltages 0.3 × VCC 0.7 × VCC V
Figure 19: AC Measurement I/O Waveform
Input and output
timing reference levels
Input levels
0.8VCC
0.2VCC
0.7VCC
0.3VCC
0.5VCC
Table 12: Capacitance
Parameter Symbol Test condition Min Max Unit Notes
Output capacitance (DQ1) COUT VOUT = 0V 8 pF 1
Input capacitance (other pins) CIN VIN = 0V 6 pF
Note: 1. Values are sampled only, not 100% tested, at TA = 25°C and a frequency of 33 MHz.
75MHz, Serial Peripheral Interface Flash Memory
AC Characteristics
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© 2011 Micron Technology, Inc. All rights reserved.
Table 13: AC Specifications (50 MHz Operation)
Parameter Symbol Alt Min Typ Max Unit Notes
Clock frequency for commands (see note) fCfCDC 50 MHz 1
Clock frequency for READ command fR DC 33 MHz
Clock HIGH time tCH tCLH 9 ns 2
Clock LOW time tCL tCLL 9 ns 2
Clock rise time (peak-to-peak, expressed as a slew rate) tCLCH 0.1 V/ns 3
S# active setup time (relative to C) tSLCH tCSS 5 ns
S# not active hold time (relative to C) tCHSL 5 ns
Data In setup time tDVCH tDSU 2 ns
Data In hold time tCHDX tDH 5 ns
S# active hold time (relative to C) tCHSH 5 ns
S# not active setup time (relative to C) tSHCH 5 ns
S# deselect time tSHSL tCSH 100 ns
Output disable time tSHQZ tDIS 8 ns 3
Clock LOW to output valid tCLQV tV 8 ns
Output hold time tCLQX tHO 0 ns
WRITE PROTECT setup time tWHSL 50 ns
WRITE PROTECT hold time tSHWL 100 ns
S# to deep power-down mode tDP 3 μs 3
S# HIGH to standby mode tRDP 30 μs 3
Reset pulse width tRLRH 10 ns 3
Reset recovery time tRHSL 3 ns
Chip deselected before RESET# is asserted tSHRH 10 ns
PAGE WRITE cycle time (256 bytes) tPW 11 23 ms 4
PAGE PROGRAM cycle time (256 bytes) tPP 0.8 3 ms 4
PAGE PROGRAM cycle time (n bytes) tPP int(n/8)
× 0.025
3 ms 4
PAGE ERASE cycle time tPE 10 20 ms
SECTOR ERASE cycle time tSE 1 5 s
Notes: 1. WRITE ENABLE/DISABLE, READ DATA BYTES at HIGHER SPEED, PAGE WRITE, PAGE PRO-
GRAM, PAGE ERASE, SECTOR ERASE, DEEP POWER-DOWN, RELEASE from DEEP POWER-
DOWN, READ STATUS REGISTER
2. The tCH and tCL signal values must be greater than or equal to 1/fC.
3. Signal values are guaranteed by characterization; not 100% tested in production.
4. n = number of bytes to program. int(A) corresponds to the upper integer part of A. For
example, int(1/8) = 1, int(16/8) = 2, int(17/8) = 3.
75MHz, Serial Peripheral Interface Flash Memory
AC Characteristics
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© 2011 Micron Technology, Inc. All rights reserved.
Table 14: AC Specifications (75MHz)
Parameter Symbol Alt. Min Typ Max Unit Notes
Clock frequency for all commands (except READ) fCfCDC 75 MHz 1
Clock frequency for READ command fR DC 33 MHz
Clock HIGH time tCH tCLH 6 ns 2
Clock LOW time tCL tCLL 6 ns 2
Clock rise time (peak-to-peak, expressed as a slew rate) tCLCH 0.1 V/ns 3
S# active setup time (relative to C) tSLCH tCSS 5 ns
S# not active hold time (relative to C) tCHSL 5 ns
Data In setup time tDVCH tDSU 2 ns
Data In hold time tCHDX tDH 5 ns
S# active hold time (relative to C) tCHSH 5 ns
S# not active setup time (relative to C) tSHCH 5 ns
S# deselect time tSHSL tCSH 100 ns
Output disable time tSHQZ tDIS 8 ns 3
Clock LOW to output valid tCLQV tV 8 ns
Output hold time tCLQX tHO 0 ns
WRITE PROTECT setup time tWHSL 20 ns 4
WRITE PROTECT hold time tSHWL 100 ns 4
S# HIGH to deep power-down mode tDP 3 μs 3
S# HIGH to standby mode tRDP 30 μs 3
PAGE WRITE cycle time (256 bytes) tPW 11 23 ms 5
PAGE PROGRAM cycle time (256 bytes) tPP 0.8 3 ms 5
PAGE PROGRAM cycle time (n bytes) tPP int(n/8)
× 0.025
3 ms 5, 6
PAGE ERASE cycle time tPE 10 20 ms
SECTOR ERASE cycle time tSE 1.5 5 s
Notes: 1. WRITE ENABLE/DISABLE, READ DATA BYTES at HIGHER SPEED, PAGE WRITE, PAGE PRO-
GRAM, PAGE ERASE, SECTOR ERASE, DEEP POWER-DOWN, RELEASE from DEEP POWER-
DOWN, READ STATUS REGISTER, READ IDENTIFICATION
2. ThetCH and tCL signal values must be greater than or equal to 1/fC.
3. Signal values are guaranteed by characterization; not 100% tested in production.
4. Only applicable as a constraint for a WRITE STATUS REGISTER command when SRWD is 1.
5. When using PAGE WRITE and PAGE PROGRAM commands to update consecutive bytes,
optimized timings are obtained with one sequence including all the bytes versus several
sequences of only a few bytes (1 256).
6. int(A) corresponds to the upper integer part of A. For example, int(12/8) = 2, int(32/8) =
4.
75MHz, Serial Peripheral Interface Flash Memory
AC Characteristics
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Table 15: Reset Specifications
Parameter Symbol Alt Conditions Min Typ Max Unit Notes
Reset pulse width tRLRH tRST 10 μs 1
Chip select HIGH
to Reset HIGH
tSHRH Chip should have been deselected
before RESET# is de-asserted
10 ns
Reset recovery
time
tRHSL tREC Clock frequency for commands (see
note)
30 μs 2, 1, 3
Under completion of ERASE or PRO-
GRAM cycle for commands (see
note)
300 μs 1
Device deselected (S# HIGH) and in
standby
0 μs 1
Notes: 1. Value guaranteed by characterization; not 100% tested in production.
2. WRITE ENABLE/DISABLE, READ DATA BYTES, READ DATA BYTES at HIGHER SPEED, PAGE
WRITE, PAGE PROGRAM, PAGE ERASE, SECTOR ERASE, DEEP POWER-DOWN, RELEASE
from DEEP POWER-DOWN, READ STATUS REGISTER, READ IDENTIFICATION
3. S# remains LOW while RESET# is LOW.
4. PAGE WRITE, PAGE PROGRAM, PAGE ERASE, SECTOR ERASE
75MHz, Serial Peripheral Interface Flash Memory
AC Characteristics
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© 2011 Micron Technology, Inc. All rights reserved.
Figure 20: Serial Input Timing
C
DQ0
S#
MSB IN
DQ1
tDVCH
high impedance
LSB IN
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
Figure 21: Write Protect Setup and Hold Timing
C
DQ0
S#
DQ1
high impedance
W#/VPP
tWHSL tSHWL
75MHz, Serial Peripheral Interface Flash Memory
AC Characteristics
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Figure 22: Output Timing
C
DQ1
S#
LSB OUT
DQ0 ADDRESS
LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCLQX
tCLQV
tCLQX
tCLQV
Figure 23: Reset AC Waveforms
tSHRH
tRLRH
tRHSL
S#
RESET#
Don’t Care
75MHz, Serial Peripheral Interface Flash Memory
AC Characteristics
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Package Information
Figure 24: VFQFPN8 (MLP8) 6mm x 5mm
12°
0.20 TYP
0 MIN/
0.05 MAX
5.75 TYP
Pin one
indicator 1.27
TYP
4 +0.30
-0.20
0.60 +0.15
-0.10
0.85 +0.15
-0.05
0.40 +0.08
-0.05
3.40 ±0.20
θ
0.10 MAX/
0 MIN
C
A
B
M
2x
6 TYP
4.75 TYP
0.05
5 TYP
0.65 TYP
0.10 C B
0.10 C A
0.15 C B
0.10 C A B
0.15 C A
Note: 1. Drawing is not to scale.
75MHz, Serial Peripheral Interface Flash Memory
Package Information
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Figure 25: SO8N 150 mils Body Width
8
1
0.25mm
Gauge plane
0.10 MIN/
0.25 MAX 0.40 MIN/
1.27 MAX
0o MIN/
8o MAX
0.28 MIN/
0.48 MAX
0.17 MIN/
0.23 MAX
x 45°
0.25 MIN/
0.50 MAX
0.10 MAX
1.75 MAX/
1.27 TYP
1.04 TYP
1.25 MIN
3.90 ±0.10
6.00 ±0.20
4.90 ±0.10
Note: 1. Drawing is not to scale.
75MHz, Serial Peripheral Interface Flash Memory
Package Information
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Device Ordering Information
Standard Parts
Micron Serial NOR Flash memory is available in different configurations and densities.
Verify valid part numbers using Micron’s part catalog search at micron.com.
To compare features and specifications by device type, visit micron.com/products.
Contact the factory for any devices not found.
For more information on how to identify products and top-side marking by process
identification letter, refer to technical note TN-12-24, "Serial Flash Memory Device
Marking for the M25P, M25PE, M25PX, and N25Q Product Families."
Table 16: Part Number Information Scheme
Part Number
Category Category Details
Device type M45PE = Page-erasable serial Flash memory
Density 20 = 2Mb (256Kb x 8)
Security – = No extra security
Operating voltage V = VCC = 2.7–3.6V
Package MP = VDFPN8 6mm x 5mm (MLP8)
MN = SO8N (150 mil width)
Device grade 6 = Industrial temperature range: –40°C to 85°C; device tested with standard test flow
Packing option – = Standard packing
T = Tape and reel packing
Plating technology P or G = RoHS-compliant
75MHz, Serial Peripheral Interface Flash Memory
Device Ordering Information
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Revision History
Rev. B – 03/14
In PAGE ERASE, revised the first sentence to say "designated page" instead of "sec-
tor."
Rev. A – 05/13
Micron rebrand
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
75MHz, Serial Peripheral Interface Flash Memory
Revision History
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m45pe20.pdf - Rev. B 03/14 EN 41 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.