0.1 GHz to 33 GHz,1 dB LSB, 5-Bit,
GaAs Digital Attenuator
Data Sheet HMC939ALP4E
Rev. D Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2018 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Attenuation range: 1 dB LSB steps to 31 dB
Insertion loss: 6 dB typical at 33 GHz
Attenuation accuracy: ±0.5 dB typical
Input linearity
0.1 dB compression (P0.1dB): 24 dBm typical
Third-order intercept (IP3): 40 dBm typical
Power handling: 27 dBm
Dual-supply operation: ±5 V
CMOS-/TTL-compatible parallel control
24-lead, 4 mm × 4 mm LFCSP package
APPLICATIONS
Test instrumentation
Microwave radios and very small aperture terminals (VSATs)
Military radios, radars, electronic counter measures (ECMs)
Broadband telecommunications systems
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
GENERAL DESCRIPTION
The HMC939ALP4E is a 5-bit digital attenuator with a 31 dB
attenuation control range in 1 dB steps.
The HMC939ALP4E offers optimum insertion loss, attenuation
accuracy, and input linearity over the specified frequency range
from 100 MHz to 33 GHz.
The HMC939ALP4E requires dual supply voltages, VDD = +5 V
and VSS = −5 V, and provides CMOS-/TTL-compatible parallel
control interface by incorporating an on-chip driver.
The HMC939ALP4E comes in a RoHS compliant, compact,
4 mm × 4 mm LFCSP package. See HMC939A-DIE for the die
version of HMC939ALP4E.
PACKAGE
BASE
NI
C
P4
P3
P2
P1
P0
NIC
NIC
NIC
NIC
NIC
NIC
NIC
RF2
NIC
NIC
NIC
VDD
NIC
NIC = NO INTERNA L CONNECTI ON
RF1
NIC
NIC
NIC
VSS
24 23 22 21 20
7
1
2
3
4
5
6
18
17
16
15
14
13
89101112
DRIVER
2dB 4dB 8dB 16dB
19
13920-001
GND
HMC939ALP4E Data Sheet
Rev. D | Page 2 of 11
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Interface Schematics..................................................................... 5
Typical Performance Characteristics ............................................. 6
Insertion Loss, Return Loss, State Error, Step Error, and
Relative Phase ................................................................................6
Input Power Compression and Third-Order Intercept ............8
Theory of Operation .........................................................................9
Power Supply ..................................................................................9
RF Input and Output ....................................................................9
Applications Information .............................................................. 10
Evaluation Board ........................................................................ 10
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 11
REVISION HISTORY
5/2018—Rev. C to Rev. D
Changed + 27 V to 27 dBm in Rating Column, Table 2 .............. 4
Change to Ordering Guide ............................................................ 11
8/2017—Rev. 02.0417 to Rev. C
This Hittite Microwave Products data sheet has been reformatted to
meet the styles and standards of Analog Devices, Inc.
Changed N/C to NIC ............................................................ Throughout
Changes to Features Section, Applications Section, and General
Description Section ................................................................................... 1
Changes to Table 1 ..................................................................................... 3
Changes to Table 2 and Added Thermal Resistance Section ............ 4
Added Table 3; Renumbered Sequentially ............................................ 4
Changes to Table 4 ..................................................................................... 5
Changes to Figure 5 Caption through Figure 10 Caption ................. 6
Changes to Figure 11 Caption through Figure 14 Caption ............... 7
Changes to Figure 15 Caption through Figure 20 Caption ............... 8
Added Theory of Operation Section, RF Input and Output Section,
and Power Supply Section ........................................................................ 9
Changes to Figure 22 ............................................................................... 10
Changes to Ordering Guide ................................................................... 11
Data Sheet HMC939ALP4E
Rev. D | Page 3 of 11
SPECIFICATIONS
VDD = 5 V, VSS = −5 V, VCTL = 0 V or VDD, TCASE = 25°C, 50 Ω system, unless otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
FREQUENCY RANGE 0.1 33 GHz
INSERTION LOSS 0.1 GHz to 18 GHz 4.5 5.5 dB
18 GHz to 26.5 GHz 5.5 7.0 dB
26.5 GHz to 33 GHz 6.0 8.0 dB
ATTENUATION
Range Between minimum and maximum
attenuation states, 0.1 GHz to
33 GHz
31 dB
Step Size Between any successive
attenuation states, 0.1 GHz to
33 GHz
1 dB
Step Error
Between any successive
attenuation states, 0.1 GHz to
33 GHz
0.5
dB
State Error Referenced to insertion loss state
1 dB to 15 dB attenuation states,
0.1 GHz to 33 GHz
−(0.5 + 5% of
attenuation state)
+(0.5 + 5% of
attenuation state)
dB
16 dB to 31 dB attenuation states,
0.1 GHz to 20 GHz
−(0.5 + 5% of
attenuation state)
+(0.5 + 5% of
attenuation state)
dB
16 dB to 31 dB attenuation states,
20 GHz to 33 GHz
−(0.6 + 8% of
attenuation state)
+(0.6 + 8% of
attenuation state)
dB
RETURN LOSS RF1 and RF2 pins, all attenuation
states, 0.1 GHz to 33 GHz
10 dB
RELATIVE PHASE Between minimum and maximum
attenuation states
0.1 GHz to 18 GHz 45 Degrees
18 GHz to 26.5 GHz 60 Degrees
26.5 GHz to 33 GHz 80 Degrees
SWITCHING CHARACTERISTICS
Between all attenuation states
Rise and Fall Time tRISE, tFALL 10% to 90% of RF output 45 ns
On and Off Time tON, tOFF 50% VCTL to 90% of RF output 60 ns
INPUT LINEARITY All attenuation states
0.1 dB Compression
P0.1dB
0.1 GHz to 0.5 GHz
20
dBm
0.5 GHz to 33 GHz 24 dBm
Third-Order Intercept IP3 8 dBm per tone, 1 MHz spacing
0.1 GHz to 0.5 GHz 43 dBm
0.5 GHz to 33 GHz 40 dBm
SUPPLY CURRENT
Positive IDD 2.5 4.5 6.5 mA
Negative ISS −7.0 −5.5 −3.0 mA
DIGITAL CONTROL INPUTS P0 to P5 pins
Voltage
Low VINL 0 0.8 V
High VINH 2.0 5.0 V
Current
Low and High IINL, IINH <1 µA
HMC939ALP4E Data Sheet
Rev. D | Page 4 of 11
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage
Positive
+7 V
Negative −7 V
Digital Control Input Voltage VDD + 0.5 V
RF Input Power (All Attenuation States,
f = 0.1 GHz to 33 GHz, TCASE = 85°C)
27 dBm
Continuous Power Dissipation, PDISS
(TCASE = 85°C)
0.453 W
Temperature
Junction, TJ 150°C
Storage −65°C to +150°C
Reflow1 ((Moisture Sensitivity Level 3
(MSL3) Rating)
260°C
ESD Sensitivity
Human Body Model (HBM) 250 V (Class 1A)
1 See the Ordering Guide for more information.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any one time.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJC is the junction to case thermal resistance.
Table 3. Thermal Resistance
Package Type θJC Unit
CP-24-161 143.52 °C/W
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with nine thermal vias. See JEDEC JESD51.
2 The device is set to maximum attenuation state.
ESD CAUTION
Data Sheet HMC939ALP4E
Rev. D | Page 5 of 11
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 VSS Negative Supply Voltage.
2 to 4, 6 to
13, 15 to 17,
19
NIC These pins are not internally connected; however, all data shown herein was measured when these pins
connected to the RF/DC ground of evaluation board.
5 RF1 This pin can be used as RF input or output of attenuator. This pin is dc-coupled to 0 V and ac matched to
50 Ω. No dc blocking capacitor is necessary when the RF line potential is equal to 0 V dc.
14 RF2 This pin can be used as RF input or output of attenuator. This pin is dc-coupled to 0 V and ac matched to
50 Ω. No dc blocking capacitor is necessary when the RF line potential is equal to 0 V dc.
18 VDD Positive Supply Voltage.
20 to 24 P4 to P0 Parallel Control Voltage Inputs. These pins select the required attenuation (see Table 6). There is no
internal pull-up or pull-down resistor on these pins; therefore, they must always be kept at a valid logic
level (VIH or VIL) and not be left floating.
EPAD Exposed Pad. The exposed pad must be connected to ground for proper operation.
INTERFACE SCHEMATICS
Figure 3. RF1, RF2 Interface Schematic
Figure 4. Digital Control Input Interface
HMC939ALP4E
TOP VIEW
(No t t o Scal e)
13920-002
PACKAGE
BASE
NIC
P4
P3
P2
P1
P0
NIC
NIC
NIC
NIC
NIC
NIC
NIC
RF2
NIC
NIC
NIC
VDD
NIC
RF1
NIC
NIC
NIC
VSS
24 23 22 21 20 19
7
1
2
3
4
5
6
18
17
16
15
14
13
8 9 10 1112
GND
NOTES
1. NI C = NO I NTERNAL CONNECTION
2. T HE E X P OSE D P AD M US T BE CO NNE CTED TO GRO UND FO R
PROP E R OPE RATION.
RF1
RF2
13920-003
P0 TO P4 500
VDD
VDD
13920-004
HMC939ALP4E Data Sheet
Rev. D | Page 6 of 11
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, RETURN LOSS, STATE ERROR, STEP ERROR, AND RELATIVE PHASE
Figure 5. Insertion Loss vs. Frequency over Temperature
Figure 6. RF1 Return Loss vs. Frequency over Major Attenuation States
Figure 7. State Error vs. Attenuation State over Frequency
Figure 8. Normalized Attenuation vs. Frequency over Major Attenuation
States
Figure 9. RF2 Return Loss vs. Frequency over Major Attenuation States
Figure 10. State Error vs. Frequency over Major Attenuation States
0
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0 5 10 15 20 25 30 35 40
INSERTION LOSS (dB)
FREQUENCY ( GHz)
+85°C
+25°C
–40°C
13920-005
0
–50
–40
–30
–20
–10
0 5 10 15 20 25 30 35 40
RET URN LOS S ( dB)
FRE QUENCY ( GHz)
31dB
13920-006
16dB
8dB
4dB
2dB
1dB
0dB
2.0
–2.0
–1.0
0
–1.5
0.5
–0.5
1.0
1.5
0 4 8 12 16 20 24 28 32
ST ATE ERROR (dB)
ATTENUATION STATE (dB)
13920-007
5GHz
10GHz
18GHz
26.5GHz
33GHz
0
–35
–30
–25
–20
–15
–10
–5
0 5 10 15 20 25 30 35 40
NORM ALIZED ATTE NUATI ON (d B)
FRE QUENCY ( GHz)
13920-008
31dB
16dB
8dB
4dB
2dB
1dB
0dB
0
–50
–40
–30
–20
–10
0 5 10 15 20 25 30 35 40
RET URN LOS S ( dB)
FRE QUENCY ( GHz)
13920-009
31dB
16dB
8dB
4dB
2dB
1dB
0dB
2.0
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
0 5 10 15 20 25 30 35 40
ST ATE ERROR (dB)
FRE QUENCY ( GHz)
13920-010
31dB
16dB
8dB
4dB
2dB
1dB
0dB
Data Sheet HMC939ALP4E
Rev. D | Page 7 of 11
Figure 11. Step Error vs. Attenuation State over Frequency
Figure 12. Relative Phase vs. Attenuation State over Frequency
Figure 13. Step Error vs. Frequency over Major Attenuation States
Figure 14. Relative Phase vs. Frequency over Major Attenuation States
1.5
–1.5
–0.5
–1.0
0
0.5
1.0
0 4 8 12 16 20 24 28 32
STEP ERROR (dB)
ATTENUATION STATE (dB)
13920-011
5GHz
10GHz
18GHz
26.5GHz
33GHz
100
–20
20
40
0
60
80
0 4 812 16 20 24 28 32
REL ATIV E P HAS E ( Degrees)
ATTENUATION STATE (dB)
13920-012
5GHz
10GHz
18GHz
26.5GHz
33GHz
1.5
–1.5
–1.0
–0.5
0
0.5
1.0
0 5 10 15 20 25 30 35 40
STEP ERROR (dB)
FRE QUENCY ( GHz)
13920-013
31dB
16dB
8dB
4dB
2dB
1dB
0dB
100
–20
20
40
0
60
80
0 5 10 15 20 25 30 35 40
REL ATIV E P HAS E ( Degrees)
FRE QUENCY ( GHz)
13920-014
31dB
16dB
8dB
4dB
2dB
1dB
0dB
HMC939ALP4E Data Sheet
Rev. D | Page 8 of 11
INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT
Figure 15. Input P0.1dB vs. Frequency at Minimum Attenuation State
over Temperature
Figure 16. Input P0.1dB vs. Frequency at Minimum Attenuation State over
Temperature (Low Frequency Detail)
Figure 17. Input P0.1dB vs. Frequency over Major Attenuation States
Figure 18. Input IP3 vs. Frequency at Minimum Attenuation State over
Temperature
Figure 19. Input IP3 vs. Frequency at Minimum Attenuation State over
Temperature (Low Frequency Detail)
Figure 20. Input IP3 vs. Frequency over Major Attenuation States
35
10
15
20
25
30
0 5 10 15 20 25 30
P0.1dB (dBm)
FREQUENCY ( GHz)
+85°C
+25°C
–40°C
13920-015
35
10
15
20
25
30
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
P0. 1dB (d Bm)
FRE QUENCY ( GHz)
+85°C
+25°C
–40°C
13920-016
35
10
15
20
25
30
0 5 10 15 20 25 30
P0.1dB (dBm)
FREQUENCY ( GHz)
13920-017
4dB
8dB
16dB
0dB
1dB
2dB
70
20
30
40
50
60
0 5 10 15 20 25 30
IP3 (dBm)
FREQUENCY ( GHz)
+85°C
+25°C
–40°C
13920-018
70
20
30
40
50
60
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
IP 3 ( dBm)
FRE QUENCY ( GHz)
+85°C
+25°C
–40°C
13920-019
70
20
30
40
50
60
0 5 10 15 20 25 30
IP3 ( dBm)
FREQUENCY ( GHz)
13920-020
4dB
8dB
16dB
0dB
1dB
2dB
Data Sheet HMC939ALP4E
Rev. D | Page 9 of 11
THEORY OF OPERATION
The HMC939ALP4E incorporates a 5-bit attenuator die that
offers an attenuation range of 31 dB in 1 dB steps and a driver
for CMOS-/TTL-compatible parallel control of the 5-bit
attenuator. See Table 5 for the truth table.
Table 5. P4 to P0 Truth Table
Digital Control Input1 Attenuation
P4 P3 P2 P1 P0 State (dB)
High High High High High 0 dB (reference)
High High High High Low 1 dB
High High High Low High 2 dB
High High Low High High 4 dB
High
Low
High
High
High
8 dB
Low High High High High 16 dB
Low Low Low Low Low 31 dB
1 Any combination of the control voltage input states shown in Table 5
provides an attenuation equal to the sum of the bits selected.
POWER SUPPLY
The HMC939ALP4E requires dual supply voltages, VDD = +5 V
and VSS = −5 V, and CMOS/TTL-compatible control voltages
applied to the P0 to P4 pins. The ideal power-up sequence is as
follows:
1. Connect the ground reference.
2. Power up VDD and VSS. The relative order is not
important.
3. Apply the digital control inputs. The relative order of the
digital control inputs is not important.
4. Apply an RF input signal to RF1 or RF2.
The power-down sequence is the reverse of the power-up
sequence.
RF INPUT AND OUTPUT
The HMC939ALP4E is bidirectional. The RF1 and RF2 pins are
internally matched to 50 Ω and dc-coupled to 0 V; therefore,
they do not require external matching components and dc
blocking capacitors when the RF line potential is equal to 0 V.
HMC939ALP4E Data Sheet
Rev. D | Page 10 of 11
APPLICATIONS INFORMATION
EVALUATION BOARD
The HMC939ALP4E uses a 4-layer evaluation board. The
copper thickness is 0.5 oz (0.7 mil) on each layer. The top
dielectric material is 10 mil Rogers RO4350 for optimal high
frequency performance. The middle and bottom dielectric
materials are FR-4 type materials to achieve an overall board
thickness of 62 mil. RF traces are routed on the top copper layer
and the bottom layer is grounded plane that provide a solid
ground for the RF transmission lines. The RF transmission lines
are designed using a coplanar waveguide (CPWG) model with a
width of 16 mil and ground spacing of 13 mil to have a
characteristic impedance of 50 Ω. For enhanced RF and thermal
grounding, as many plated through vias as possible are arranged
around transmission lines and under the exposed pad of the
package.
Figure 21 shows the top view of the populated HMC939ALP4E
evaluation board, available from Analog Devices, Inc., upon
request (see the Ordering Guide section).
Figure 21. Populated Evaluation Board—Top View
The evaluation board is grounded from the 2 × 5-pin header, J3.
All the supply and digital control pins are also connected to the
J3. A 1 nF decoupling capacitors are placed on the supply traces
to filter high frequency noise.
The RF1 and RF2 ports are connected through 50 Ω transmission
lines to the RF connectors, J1 and J2, respectively. A thru
calibration line connects J4 and J5; this transmission line is used
to estimate the loss of the PCB over the environmental conditions
being evaluated.
Figure 22 and Table 6 show the evaluation board schematic and
bill of materials, respectively.
Figure 22. Evaluation Board Schematic
Table 6. List of Materials for EV1HMC939ALP4
Item Description
J1, J2 PCB mount, 2.9 mm RF connector
J3, 2 × 5-pin header
J4, J5
PCB mount, 2.9 mm RF connector, do not insert
C1, C2 1 nF capacitor, 0402 package
U1 HMC939ALP4E digital attenuator
PCB 131909-1 evaluation PCB
13920-021
U1
C1 C2
J3
J2
J4 J5
J1
131909-1
THRU CAL
RF1 RF2
VSS
VDD
P0
P1
P2
P3
P4
GND
GND
939A
XXXX
HMC939ALP4E
U1
THRU CAL
J4
J1 RF1
C1
1NF
1
2
3
4
5
6
18
17
16
15
14
13
7
8
9
10
11
12
24
23
22
21
20
19
J3
VDDVSS
C2
1NF
J2
RF2
J6
NIC
NIC
NIC
NIC
NIC
NIC
NIC
RF1
NIC
NIC
NIC
VSS
NIC
P4
P3
P2
P1
P0
NIC
RF2
NIC
NIC
NIC
NIC = NO INTERNAL CONNECTION
VDD
13920-022
Data Sheet HMC939ALP4E
Rev. D | Page 11 of 11
OUTLINE DIMENSIONS
Figure 23. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.85 mm Package Height
(CP-24-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range MSL Rating2 Package Description Package Option
HMC939ALP4E −40°C to +85°C MSL3 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-16
HMC939ALP4ETR −40°C to +85°C MSL3 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-16
EV1HMC939ALP4 Evaluation Board
1 All models are RoHS compliant.
2 See the Absolute Maximum Ratings section.
0.50
BSC
0.50
0.40
0.30
COMPLIANT
TO
JEDE C S TANDARD S MO - 2 20 - VGGD-8
BOTTO M VIEWTOP VIEW
4.10
4.00 S Q
3.90
0.90
0.85
0.80 0.05 M AX
0.02 NOM
0.20 REF
COPLANARITY
0.08
PIN 1
INDICATOR
1
24
712
13
18
19
6
FOR PROPER CONNECTI ON OF
THE EXPOSED PAD, REFER TO
THE PIN C ONF IG U RATI ON AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
12-12-2017-C
0.30
0.25
0.18
0.20 MI N
2.80
2.70 S Q
2.60
EXPOSED
PAD
PKG-004926/004942
SEATING
PLANE
PIN 1
INDICATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95 )
©2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13920-0-5/18(D)
