TSS461F-TDRA-9 - Atmel Corporation

Features

•Fully Compliant to VAN Specification ISO/11519.3

•Handles All Specified Module Types

•Handles All Specified Message Types

•Handles Retransmission of Frames on Contention and Erro rs

•3 Separate Line Input s with Automatic Diagnosis and Selection

•1 Mbit/s Maximum Transfer Rate

•Normal or Pulsed (O ptical and Radio Mo de) Coding

•Intel®, NEC®, Texas Instruments® and Motorola® Compatible 8-bit Microprocessor

Interface

•Multiplexed Address and Data Bus

•Idle and Sleep Modes

•128 Bytes of General-purpose RAM

•DMA Capabilities for Message Handling

•14 Identifier Registers with All Bits Individually Maskable

•6-source Maskable Interrupt Inclu ding an Interrupt-on-reset to Detect Glitches on the

Reset Pin

•Integrated Crystal or Resonator Oscillator with Internal Baud Rate Generator and

Buffered Clock Output

•Single +5V Power Supply

•0.5 mm CMOS Technology

•SOP 24 Packaging

Description

Cost optimization in car manufactur ing is of extreme importance today. Solutions to

this problem often implies the use of more advanced and intelligent electronic circuits.

The TSS461F is a circuit which allows the transfer of all the status information neede d

in a car or truck over a single low-cost wire pair, thereby, minimizing the electrical wire

usage.

It can be used to interconnect powerful functions (ABS, dashboard, power train con-

trol) and to control and interface car body electronics (lights, wipers, power window,

etc.).

The TSS461F is fully compliant with the ISO standard 11519-3. This standard sup-

ports a wide range of applications such as low-cost remote control switches, typically

used for lamp control; complex, highly-aut onomous, distributed systems like engine

controls, which re qu ire fas t and sec ur e data transfe rs .

The TSS461F is a microprocessor-interfaced line controller for mid-to-high complexity

bus-masters and listeners like injection/ignition control calculators, dashboard control-

lers and car stereo or mobile telephone CPUs.

The microprocessor interface consists of a 256-bytes of RAM and the register area is

divided into 11 control registers, 14 channel register sets and 128 bytes of g eneral

purpose RAM, used as a message storage area, and a 6-source maskable interrup t.

The circuit operates in RAM using DMA techniq ues, controlled by the channel and

control registers. This allows virtually any microproc essor to interface with ease to the

TSS461F, and to use the free RAM as a scr at ch pad.

Messages are encode d in enhanced Manche ster code, and an optional pulsed code

for use with an optical or radio link, at a maximum bit ra te of 1 Mbit/s. The TSS461F

analyzes the messages received or transmitted according to 6 different criteria includ-

ing some higher level checks.

In addition, the bus interface has three separate inputs with automatic source diagno-

sis and selection, allowing for multibus listening or the automatic selection of the most

reliable source at any time if several line receivers are connected to the same bus.

VAN Data Link

Controller

TSS461F

7615A–AUTO–02/06

27615A–AUTO–02/06

TSS461F

Figure 1. Block Diagram

Message ID registers

RAM

128 bytes

buffer

Protocol controller

state machine and

Data serializer and

deserializer

Clock generator and

line synchronization

logic

Multiplexing logic Status and

control

registers

Reception logic

CRC generator

and checker

Transmission logic

Source diagnosis

and selection logi

AD[7:0] ALE

control bus

data bus

address bus

INT

XTAL1 XTAL2 CKOUT TxD

status bus

RxD0 RxD1 RxD2

RESET TEST VCC GND

Address and Data Bus

7615A–AUTO–02/06

TSS461F

Pin Configuration

The names in parenthesis refer to the functionalities in Motorola mode.

1 24

2 23

3 22

4 21

5 20

6 19

7 18

8 17

AD4

AD5

AD6

AD7

VCC

INT

(E) CS

XTAL1

TOP VIEW

9 16

10 15

11 14

12 13

ALE

XTAL2

TEST/VSS

CKOUT

AD3

AD2

AD1

AD0

VSS

RESET

RXD0

RXD2

TXD

RXD1

WR (R/W)

RD (VSS)

24 Pin SOP

I/O Type Pin Name Pin Number Pin Function

I/O TTL AD0 21 Multiplexed address and

data bus. The address is

latched on the falling

address of ALE.

AD1 22

AD2 23

AD3 24

AD4 1

AD5 2

AD6 3

AD7 4

I Trigger TTL ALE 7 Address Latch Enable

RD (VSS) 13 Read Command

WR (R/W) 14 Write Command

CS(E) 8 Chip Select (active high)

Open-drain INT 6 Interrupt

I Trigger CMOS Pull-down RESET 19 Asynchronous general

reset glitch filtered

(12 ns)

47615A–AUTO–02/06

TSS461F

I CMOS Pull-down RXD0 17 VAN bus Inputs

RXD1 15

RXD2 16

3-state TXD 18 VAN bus Output

IXTAL1 9 Crystal oscillator or clock

input pins

0XTAL2 10

0CKOUT 12 Buffered clockout output

enabled if no reset

Ground TEST/VSS 11 Oscillator Ground

Power VCC 5 +5V Power Supply

Ground VSS 20

I/O Type Pin Name Pin Number Pin Function

7615A–AUTO–02/06

TSS461F

Operation The TSS461F is a microprocessor-controlled line co ntroller for the VAN bus. It can interface to

virtually any microprocessor, but the I/O signals of the circuit have been optimized for use with

the TSC51/TSC251 series of microcontrollers.

It features a multiplexed address and data bus, controlled by an address strobe pin ALE and

separated read RD and write WR command pins. The address is latched on the falling edge of

ALE.

The circuit also features one single interrupt pin. This pin can be treated as level or edge sensi-

tive, For example, if there is a pendin g interru pt inside th e ci rcuit when another inter rupt is reset,

the INT pin will emit a high pulse with the same pulse width as the internal write strobe (typically

20 ns).

Figure 2. Typical Application

Remaining Pins

TSS461F

Microcontroller

Series

P3.6/WR

P3.7/RD

ALE

P0.7

P0.6

P0.5

P0.4

P0.3

P0.2

P0.1

P0.0

ALE

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

XTAL1 XTAL2

TXD

RXD0

RXD1

RXD2

VAN

DLC

INT CKOUT RESETRESET XTAL 1 IN T VCC

33 pF

GND GND

VREF

DATA

Differential

DATA

VAN Bus

VAN Line Driver

& Receivers

General I/O

67615A–AUTO–02/06

TSS461F

Microprocessor

Interface The processor controls the TSS461F by reading and writing the internal registers of the circuit.

These registers appear to the processor as regular memory locations.

Interface Modes The TSS461F must be plugged in an Intel or Motorola environment with an 8-bit address/data

bus multiplexed.

Table 1. Access Mode Logic

In Intel environment, access operations need CS active, a read one with RD active, a write one

with WR active. If TSS461F is the sin gle periphera l in the process or space, CS ca n be wired to

VCC.

In Motorola environment, the RD pin is wired to VSS and the access operations are driven by

CS (E). Contrary to Intel mode, CS (E) must never be wired to Vcc even if the TSS46 1F is alone.

To switch on-the-fly from one mode to th e other, CS must be inactive.

Intel Mode The Intel mode inte rface consists of 13 pins. 8 pins ar e the multiplexed addres s and data bus,

and the rest are the addr ess strobe, the re ad an d write commands, the chip select and the inter-

rupt request pins.

To access the memory locations in Intel mode, the processor mu st first assert a valid address on

the multiplexed address and data bus and drive the address strobe pin high. When the required

set up time has passed, the processor must drive the address strobe low, and keep the address

valid for the required hold time.

The processor m ust then either as sert the data to be writt en on the address an d data bus, if a

write is intended, o r float th e data bu s for a re ad. The next step is to drive e ither the write or read

command pins low, a ccording to the function requir ed, and at the same time drive the chip select

pin high.

The TSS461F access cycle is then terminated by driving the chip select and co mman d pins low.

Note: that the chip select pin may be driven high fo r the entire access cycle, and may also remain high

during and after the termination of th e cycle.

CS (E) RD WR (R/W)Operation Mode

0No operation

10 0

Write Operation in Motorola mode

10 1

Read operation in both modes

11 0

Write operation in Intel mode

11 1

No operation

7615A–AUTO–02/06

TSS461F

Figure 3. Intel Read and Write Cycles

Motorola Mode In Motorola mode, the WR pin becomes the R/W command, the RD pin must be connected to

ground and the CS pin becomes the E strobe. There is no separate chip select input. For exam-

ple, if some external decoder is used, this decoder should not drive the E input high unless the

processors E output is high as well.

See Figure 4 for the Motorola read and write cycles. The main difference between Intel and

Motorola mode is that the timing in Intel mode is referenced to the command signals (RD and

WR), but in Motorola mode the reference is the E signal.

Figure 4. Motorola Read and Write Cycles

Interrupts If an event occurs in the TSS461F, that needs the attention of the processor, this will be sig-

nalled on the active low, open-drain interrupt request pin. The events that create this request is

controlled by the internal registers.

Every time the microprocessor accesses any of the interrupt registers (addresses 0x08 to 0x0B),

the INT pin will be released momentarily. This enables the TSS461F to work with processors

that have either edge or level sensitive interrupt inputs.

ALE

AD[7:0]

ADDRESS DATA TO BE

WRITTEN ADDRESS DATA

READ

WRITE CYCLE READ CYCLE

ALE

AD[7:0]

VSS (RD)

R/W (WR)

E (CS)

ADDRESS DATA TO BE

WRITTEN ADDRESS DATA

READ

WRITE CYCLE READ CYCLE

87615A–AUTO–02/06

TSS461F

Reset The reset is applied asynchronously regarding XTAL clock. It can be done either by the RESET

pin or by software. The RESET pin is a CMOS trigger input with a pull-down resistor (110 k Ω).

An external 1 µF capacitor to VCC provides to RESET pin an efficient behavior.

The software reset is made through the GRES command bit of the Command Register (0x03).

The two resets are ored, filtered and gauged. T

he internal reset, always asserted asynchronously, enables the internal oscillator. Then it waits

for eight clock periods the oscillator stability.

The different blocks of the TSS461F need to be turned on synchronously. So the release of the

internal reset is synchronous and a loose of clock can let the TSS461F in permanent reset after

applying Reset.

7615A–AUTO–02/06

TSS461F

Oscillator An oscillator is integrated in the TSS461F, and consists of an inverting amplifier which the input

is XTAL1 and the output XTAL2.

A parallel resonance quartz crystal or ceramic resonator must be connected to these pins. As

shown in Figure 2, two ca pacitors have to be co nnected fr om the crysta l pins to gr ound. The val-

ues of C1 depend on the frequency chosen and can be selected using the graphic given in

Figure 34.

If the oscillator is not used, then a clock signal must be fed to the circuit via the XTAL1 input.

Note, that this pin will behave as a CMOS level compatible Schmitt trigger input.

In this case, the XTAL2 output should be left unconnected. The oscillator also features a buff-

ered clock outp ut pin CKOUT. The signal on this pin is directly buffere d from the XTAL1 inpu t,

without inversion.

There is one more pin used for the oscillator. The TEST/VSS pin is in fact its ground, and unless

this pin is firmly connected to ground, with decoupling capacitors, the oscillator will not operate

correctly.

The test mode itself, i.e., when the TEST/VSS pin is held high, is only intended for factory use,

and the functionality of this mode is not specified in any way.

Furthermore, it is subje ct to change without notice, the only exception being for incoming inspec-

tion tests using the test program.

The clock signal is then fed to the clock generator generate all the necessary timing signals for

the operation of the circuit. The clock gene rator is controlled by a 4-bit code called the clock

divider.

FTSCLK FXTAL1

n16×

------------------

10 7615A–AUTO–02/06

TSS461F

Table 2. Clock Divider

Clock

Divider Divide by

8 MHz 6 MHz 4 MHz 2 MHz

KTS/s Kbits/s KTS/s Kbits/s KTS/s Kbits/s KTS/s Kbits/s

0000 1 500 400 375 300 250 200 125 100

0001 2 250 200 187.50 150 125 100 62.50 50

0010 4 125 100 93.75 75 62.50 50 31.25 25

0011 8 62.5 50 46.875+ 37.5 31.25 25 15.625 12.5

0100 16 31.25 25 23.438 18.75 15.625 12.5 7.813 6.25

0101 32 15.625 12.5 11.718 9.375 7.813 6.25 3.906 3.125

0110 64 7.813 6.25 5.859 4.688 3.906 3.125 1.953 1.562

0111 128 3.906 3.125 500 400 1.953 1.562 166.666 133.333

1000 1.5 333.333 266.666 250 200 166.666 133.333 83.333 66.666

1001 3 166.666 133.333 125 100 83.333 66.666 41.666 33.333

1010 6 83.333 66.666 62.50 50 41.666 33.333 20.833 16.666

1011 12 41.666 33.333 31.25 25 20.833 16.666 10.416 8.333

1100 24 20.833 16.666 15.625 12.50 10.416 8.333 5.208 4.166

1101 48 10.416 8.333 7.813 6.25 5.208 4.166 2.604 2.083

1110 96 5.208 4.166 3.906 3.125 2.604 2.083 1.302 1.042

1111 192 2.604 2.083 1.953 1.5625 1.302 1.042 0.651 0.521

7615A–AUTO–02/06

TSS461F

VAN Protocol

Line Interface There are three line inputs and one line out put available on the TSS461F. Each of the three

inputs to use is either pr og rammed by softwar e o r a utomatically selected by a dia gnosis syste m.

The diagnosis system continuously monitors the d ata received through the three inputs, and

compares them and the selected bitrate. It then chooses the most reliable input according to the

results.

The data on the line is en coded according to the VAN standar d ISO/11519-3. This means that

the TSS461F is using a two-level signal having a recessive (1) and a domina nt (0) state. Fur-

thermore, due to the simple medium used, all data transmitted on the bus is also received

simultaneously.

Consequently, the VAN protocol is a CSMA/CD (Carrier Sense Multiple Access/Collision Detec-

tion) protocol, allowing for continuous bitwise arbitration of the bus, an d non-destru ctive (for the

higher priority message) collision detection.

Figure 5. CSMA/CD Arbitration

In addition to the VAN specification there is also a pulsed coding of the dominant and recessive

states. This mode is intended to be used with an optical or radio link. In this mode, the dominant

state for the transmitter is a low pulse, (2x prescaled clocks at the beginning of the bit) and the

recessive state is just a high level.

When receiving in this mode, it is not the state of the signal which is decoded, but the edges.

Also, reception is imposed on the RxD0 input, and the diagnosis system does not ope rate

correctly.

In addition, in this mode there is an internal loopback in the circuit since optical transceivers are

not able to receive the signal that they transmit.

Node a: TxD Node a loses the arbitration

Node a releases the bus

Node b wins the arbitration

Node c loses the arbitration

Node c releases the bus

Node b: TxD R

Node c: TxD R

On Bus: DATA R

Arbitration field

R: Recessive level D: Dominant level

12 7615A–AUTO–02/06

TSS461F

Figure 6. State Encoding

In Figure 6 the pulsed waveforms are shown. In Figure 9 through Figure 15 the low "timeslots"

(i.e. blocks of 16 prescaled clocks) should be replaced by the dominant waveform showed in

Figure 6, if the correct representations for pulsed coding is desired.

VAN Frame Figure 7. VAN Bus Frame

The VAN bus supports three different module (unit) types:

1. The Autonomous module, which is a bus master. It can transmit Start Of Frame (SOF)

sequences, it can initiate data transfers and can receive messages.

2. The Synchronous access module. It cannot transmit SOF sequences, but it can initiate

data transfers and can receive messages.

3. The Slave module, which can only transmit using an in-frame mechanism and can

receive messages.

Figure 8. Hierarchical Access Methods

VAN BUS

SEQUENCE

VAN BUS

SEQUENCE

VAN BUS

SEQUENCE

NUMBER OF

PRESCALED

CLOCKS

NORMAL OR PULSED RECESSIVE STATE

NORMAL DOMINANT STATE

PUSED DOMINANT STATE

0481216

2 6 10 14

SOF Identifier

Field

Command Data

Field

Frame

Check

Sum EOD ACK EOF

EXT RAK R/W RTR

SOF ID COM DATA ACK EOF

EOD

Autonomous

ank 0

ID COM DATA FCS ACK EOF

EOD

Synchronous

ank 1

DATA FCS ACK EOFEOD

Slave

ank 16

RTR

FCS

7615A–AUTO–02/06

TSS461F

Figure 7 shows a normal VAN bus fram e. It is initiated with a Start of Frame (SOF) sequence

shown in Figure 9. The SOF can only be transmitted by an autonomou s module . Dur ing the pr e-

amble, the TSS461F will synchronize its bit rate clock to the data received.

Figure 9. Framing Sequences

When the complete SOF sequence has been transmitted or received, the circuit will start the

transmission or reception of the identifier field.

All data on the VAN bus, including the identifier and Frame Check Sum (FCS), are transmitted

using enhanced Manchester code.

In enhanced Manchester code, three NRZ bits are transmitted first followed by one Manchester

bit, then three more NRZ bits followed by one Mancheste r bit and so on.

Since the high state is recessive and the low state is dominant, the bus arbitration can be done.

If a module wants access to the bus, it must first listen to the bus during one full End of Frame

(EOF) and one full Inter Frame Spacing (IFS) p eriod, to determine whether the bus is free or not

(i.e.,no dom ina nt stat es re ce ive d) .

Figure 10. Data Encoding

The IFS is defined to be a minimum of 64 prescaled clocks periods. The TSS461F, accepts an

IFS of zero prescaled clocks for the reception only of a SOF sequence.

VAN BUS

SEQUENCE

VAN BUS

SEQUENCE

NUMBER OF

PRESCALED

CLOCKS

PREAMBLE

START OF FRAME

START

SYNC

END OF

DATA ACK END OF FRAME

0 16 32 48 64 80 96 112 128 144 160 176 192

VAN BUS

SEQUENCE

VAN BUS

SEQUENCE

VAN BUS

SEQUENCE

NUMBER OF

PRESCALED

CLOCKS

NRZ 0  NRZ 1

MANCHESTER 0

MANCHESTER 1

0 8 16 24 32

14 7615A–AUTO–02/06

TSS461F

Once the bus is free, the module must now, if it is an autonomous module emits a SOF

sequence or, if it is a synchronous access module, wait until it detects a preamble sequence.

Up till this point there can be several modules transmitting on the bus, and there is no possibility

of knowing if this is the case or not. Therefore, the first field in which arbitration can be per-

formed is the identifier field. Since the logical zeroes on the bus are dominant, and all data is

transmitted with the most significant bit (MSB) first, the first module to transmit a logical zero on

the bus will be the prioritized module, i.e., the message that is tag ged with the lowest identifier

will have priority over the other messages.

However it is possible that two messages tr ansmitted on the bus will have the same identifier.

The TSS461F therefore, continues the arbitration of the bus throughout the whole frame. In

addition, if the identifier in transmission has been programmed for reception as well, it transmits

and receives messages simultaneously, right up till the Frame Check Sequence (FCS). Only

then, if the TSS461F has transmitted the whole message. It discards the message received.

Arbitration loss in the FCS field is considered as a CRC error during transmission.

This feature is called full data field ar bitration, and it enables the user to extend the identifie r. For

instance, it can be used to transmit the emitting modules address in the first bytes of the data

field, thus enabling the identifier to specify the contents of the frame and the data field to specify

the source of the information.

The identifier field of the VAN bus frame is always 12 bits long, and it is always followed by the

4-bit command field:

• The first bit of the command is the extension bit (EXT). This bit is defined by the user on

transmission and is re ceived and retaine d by the TSS461F. To conform with the standard, it

should be set to 1 (recessive) by the user, else the frame is ignored without any IT

generation.

• The second bit is the request ACKno wledge bit (RAK). If this bit is a logical one, the

receiving module must acknowledge the transfer with an in-frame acknowledgement in the

ACK field. If it is set to logical zero, then the ACK field must contain an acknowledge absent

sequence.

• The third bit is the Read/Write bit (R/W). This bit indicates the direction of the data in a

frame.

• If set to zero it is a "write" message, i.e. data transmitted by one module to be received by

another module. If it is set to one it implies a "read" message, i.e., a request that another

module should transmit data to be received by the one that requested the data (reply

request message).

• Last in the command field is the Remote Transmission Reque st bit (RTR). This bit is a

logical zero if the fr ame conta ins data an d a logical one if the frame does not contain data. In

order to conform with the standard a received frame included the combination R/W. RTR =

01 is ignored without any IT generation.

All the bits in the comm a nd fie l d ar e a utom a tica lly ha nd le d b y the TSS 46 1F , so the user doesn’t

need to be concer ned for the encoding and de coding of these. The command bits transmitted on

the VAN bus are calculated from the current status of the active message.

After the command field comes the data field. This is just a sequence of bytes transmitted, MSB

first. In the VAN standard the maximum message length is set to 28 bytes, but the TSS461F

handles messages up to 30 bytes.

The next field is the FCS field. This field is a 15 bit CRC ch ecksum defined by the following gen-

erator polynomial g(x) of order 15:

g(x) = x15 + x11 + x10 + x9 + x8 + x7 + x4 + x3 + x2 + 1

7615A–AUTO–02/06

TSS461F

The division is done with a rest initialized to 0x7FFF, and an inversion of the CRC bits is per-

formed before transmission.

However, since the CRC is calculated automatically from the identifier, command and data fields

by the TSS461F, the user should not be concerned with the circuit. When the frame check

sequence has b een transmitted, the transmitting module must transmit an End Of Data (EOD)

sequence, followed by the ACKnowledge field (ACK) and the End of Frame sequence (EOF) to

terminate th e tra ns fe r.

Figure 11. Acknowledge Sequences

Frame Examples The frames transmitted on the VAN bus are generated by several modules, each supplying dif-

ferent parts of the message. Figure 12 through Figure 15 show the four frame types specified in

the VAN standard, and what module is generating the different fields.

• The most straigh tforward frame is the normal data frame in Figure 13. Like all other frames it

is initiated with a SOF sequence. This sequence is generated by a bus master (not shown in

figure).

• During this frame, there is basically only one module transmitting wi th th e ex cep tio n bein g

the acknowledgement, generated by the receiving module if requested in the RAK bit.

• The reply request frame with immed iate repl y in Figure 13 is the only frame in which a slave

module can transmit data by filling it into the appropriate field.

• The difference for the frame on the bus is that the R/W bit has changed state compared to

the normal frame.

• This is a highly intera ctiv e fra m e wh er e a bus maste r ge n er ates th e SOF an d the initia to r

generates the identifier, the three first bits of the command, and the acknowledge. The RTR

bit, the data field, the frame check, the EOD and the EOF are all generated by the r eplying

module.

• The reply request frame with deferred reply in Figure 14 is the same frame as the reply

request frame with immediate reply. But since the requested module does not generate the

RTR bit, the requesting module will continue with the frame check, the EOD and the EOF.

• During this frame, the requested module will only generate the acknowledge, and only if this

was requested by the initiator through the RAK bit.

• Finally, the deferred reply frame in Figure 16 which is sent when a module has prepared a

reply for a reply request that has been received earlier.

This frame is similar to the normal data frame with the exception being the R/W bit that has

changed state.

VAN BUS

SEQUENCE

VAN BUS

SEQUENCE

NUMBER OF

PRESCALED

CLOCKS

POSITIVE ACKNOWLEDGE

ABSENT ACKNOWLEDGE

0 8 16 24 32

16 7615A–AUTO–02/06

TSS461F

Figure 12. Normal Data Frame

FRAME

on bus

TRANSMITTING

FRAME

on bus

TRANSMITTING

module CRC

CRC

SOF

IDENTIFIER

DATA

EOF

module

RECEIVING

module

RECEIVING

module

: Positive from Receiver because RAK is Recessive

RAK

EXT

R/W

RTR

ACK

: Recessive for acknowledge from Transmitter

: Recessive from Transmitter

: Dominant from Transmitter

 (*) Manchester bit

With acknowlegment

Without acknowlegment

: Absent from Transmitter and from Receiver because RAK is Dominant

RAK

EXT

R/W

RTR

ACK

: Dominant for no acknowledge from Transmitter

: Recessive from Transmitter

: Dominant from Transmitter

 (*) Manchester bit

EXT

RAK

R/W

RTR

(*)

EXT

RAK

R/W

RTR

(*)

EXT

RAK

R/W

RTR

(*)

EXT

RAK

R/W

RTR

(*)

EOD

ACKACK

EOD

ACK

EOD

ACK

EOD

ACK

7615A–AUTO–02/06

TSS461F

Figure 13. Reply Request Frame with Immediate Reply

Figure 14. Reply Request Frame with Deferred Reply

(*)

SOF IDENTIFIER

RTR

FRAME

module

REQUESTED

module

REQUESTING

(*)

CRC

SOF IDENTIFIER DATA

DATA EOF

EOF

on bus

: Absent from Requestee and Positive from Requestor because RAK is Recessive

RAK

EXT

R/W

RTR

ACK

: Recessive for acknowledge from Requestor

: Recessive from Requestor

: Recessive from Requestor and Dominant from Requestee

 (*) Manchester bit

EXT

RAK

R/W

RTR

(*)

EOD

ACK ACK

EXT

RAK

R/W

RTR

EOD

ACK

SOF

RTR

IDENTIFIER

FRAME

on Bus

REQUESTING

(*)

CRC

SOF IDENTIFIER

EOF

Module

REQUESTED

Module

: Absent from Requestor and Positive from Requestee because RAK is Recessive

RAK

EXT

R/W

RTR

ACK

: Recessive for acknowledge from Requestor

: Recessive from Requestor

: Recessive from Requestor - (*) Manchester bit

EXT

RAK

R/W

EOD

ACK

EOD

ACK ACK

RTR

EXT

RAK

R/W

(*)

18 7615A–AUTO–02/06

TSS461F

Figure 15. Deferred Reply Frame

FRAME

on bus

module

REPLYING

CRC

CRCSOF

SOF

IDENTIFIER

IDENTIFIER DATA

DATA EOF

EOF

RECEIVING

module

: Absent from Replyer and Positive from Receiver because RAK is Recessive

RAK

EXT

R/W

RTR

ACK

: Recessive for acknowledge from Replyer

: Recessive from Replyer

: Dominant from Replyer  (*) Manchester bit

EXT

RAK

R/W

EOD

ACK

EOD

ACK ACK

EXT

RAK

R/W

(*) (*)

RTRRTR

7615A–AUTO–02/06

TSS461F

Diagnosis

System The purpose of the diagnosis system is to detect any short or open circuits on either the DATA

or DATA lines and to permit, if it is possible, to carry the comm unications on the non-defective

line.

The diagnosis system is based on the assumption that three separate line receivers are con-

nected to the VAN bus (see Figure 3):

• One of the line receivers is connected in differential mode, sensing both DATA and DATA

signals, and is connected to the RxD0 input.

• The other two line receivers are operating in single wire mode and are sensing only one of

the two VAN bus signals:

– The line receiver sensing DATA is connected to RxD1

– The line receiver sensing DATA is connected to RxD2

The diagnosis system analyzes and compares the data sent over both VAN lines. So, the diag-

nosis system executes a digital filtering and transition analyses. In order to perform its

investigation, three internal signals are generated, RI (Return to Idle), SDC (Synchronous Diag-

nosis Clock) and TIP (Transmission In Progress).

One of four operating modes can be chosen to manage the results of the diagnosis system.

Diagnosis States If the diagnosis system finds a failure on either of the VAN bus signals, it changes from nominal

to degraded mode, and connects the line receiver not coupled to the failing signal to the recep-

tion logic.

When the diagnosis system finds that the failing signal is working again, it returns to nominal

mode and re-connects the diffe rential line receiver to the reception logic.

A major error occurs when both the VAN bus signals fail.

Figure 16. Diagnosis States

Status bits give permanent information on the diagnosis performed, wha tever the programmed

operating mode. This is encoded over three bits: Sa, Sb a nd Sc. Sa a nd Sb bits in dicate th e four

possible states of the VAN bus.

NONIMAL

MAJOR

ERROR DEGRATED

DATA

DEGRATED

DATA

- Failure during the frame.

- Default of transitions on the valid input between 2 consecutive SDC rising edges.

- Protocol fault

- In specified selection mode, every RI pulse when an EOF is detected or through an active SDC.

- In automatic selection mode and SDC active, no failure sampled by 2 consecutive SDC rising edges.

- General reset

20 7615A–AUTO–02/06

TSS461F

Table 3. Status Bits Sa and Sb

Notes: 1. Sc bit sets to 1 as soon as one of the three inputs (RXD2, RXD1, RXD0) differs from the others

in the input comparison analysis performed by the diagnosis system, S2 is set.

2. The only way to reset this status bit is through the RI signal or a genera l reset.

Internal

Operations

Digital Filtering If several spurious pulses occur during one bit, the diagnosis for defective conductor may be

corrupted. To avoid such errors, digital filters are implemented.

Filtering operation is based on sampling of the comp arator output signals. A transition is taken

into account only if it is observed over five samples (1/16th of timeslot).

Transition Analyses These analyses are continuously done on the effective edges on comparators after digital

filtering.

• Asynchronous diagnosis:

The asynchronous diagnosis is done by comparing the number of edges on DATA and

DATA.

If four edges are detected on one input and no edges on the other during the same period,

the second input is considered faulty and the diagnosis mode will change to one of the

degraded modes.

• Synchronous diagnosis:

The synchronous diagnosis counts the number of edges on the data input connected to the

reception logic during one SDC period.

If there are less than four edges during one SDC period, the diagnosis mode will change to

the major error mode.

• Transmission diagnosis:

The transmission compares RxD1 and RxD2 inputs (through the input comparators and the

Sa Sb Communication

0 0 Mode nominal

Fault no fault on VAN bus

Status differential communication DATA and DATA

0 1 Mode degraded on DATA

Fault fault on DATA

Status communication on DATA

1 0 Mode degraded on DATA

Fault fault on DATA

Status communication on DATA

1 1 Mode major error

Fault fault on DATA and DATA

Status no communication on DATA and DATA (attempt to

communicate alternatively on DATA then DATA every

SDC period.

7615A–AUTO–02/06

TSS461F

filters) with the data transmitted on TxD output.

At a time when the transmission logic generates a dominant (recessive transition ), the inputs

can give different values. Taking into account the filtering delay, the bus line seen as

dominant is assumed to be correct, the other one, recessive, is considered faulty. The

diagnosis mode is changed to reflect that.

• Protocol fault:

The protoco l fau lt is det ec ted by co un tin g th e nu mb e r of consecutive dom ina nt time slo ts.

If eight consecutive timeslots are dominant, the diagnosis mode will change to the major

error mode.

Generation of

Internal Signals

RI Signal (Return to

Idle) This signal is used to return to nominal mode in the three specified selection modes (see

section “Diagnosis States” and se ction “Programming Modes”). The RI signal is disabled in auto-

matic selection mode.

The RI signal is a pulse generated when an EOF is detected. So, at the end of each frame, the

user, regarding the diagnosis status bit Sa, Sb & Sc, can select its own choice.

SDC Signal

(Synchronous

Diagnosis Clock)

This time base is used by diagnosis system in automatic selection mode (see

section “Programming Modes”) when no event is recorded on the bu s.

The SDC is generated either by a special SDC divider connected to the timeslot clock, or manu-

ally. The SDC clock period must be longer compared to the timeslot duration.

A typical SDC period should be greater than the maximum frame length appearing on the VAN

network.

TIP Signal

(Transmission In

Progress)

This signal must be enabled to allow the transmission diagnosis (see section “Transition

Analyses”).

The TIP turns on synchronously at the beginning of the transmission:

• For asynchronous bus access, the beg inning of SOF,

• For synchronous bus access, the beginning of the identifier field,

• For a request of in frame reply, the RTR bit of the command field.

The TIP turns off synchronously at the end of the transmission:

•after EOF

• after a losing of arbitration or a code violation detection

• for a requester of in frame reply, when the arbitration is lost on RTR the bit.

This signal is not generated when the transmission logic only sends an ACK.

22 7615A–AUTO–02/06

TSS461F

Programming

Modes Four programm ing modes determine the way for using three different inputs and the diagnosis

system.

• 3 specified selection modes

• 1 automatic selection mode

Table 4. Programming Modes

Ma Mb Operating Mode

0 0 Differential communication

0 1 Degraded communication on RxD2 (DATA)

1 0 Degraded communication on RxD1 (DATA)

1 1 Automatic selection according to the diagnosis status

7615A–AUTO–02/06

TSS461F

Registers The TSS461F memory map consists of three different areas, the Control & Status registers, the

Channel Register s and th e Me ssa g e Data (o r Ma ilb ox) .

Mapping

Figure 17. Memory Map

Notes: 1. All the non-specified addresses between 0x00 and 0x7F are considered as absent.

2. (r) means read only register.

(w) means write only register.

(r/w) means read/write register.

3. Value after RESET is found after register name. If no value is given, the register is not initialized at RESET.

0x70 to 0x77 (r/w)

Reserved

0x7C & 0x7D Reserved

Channel 90x58 to 0x5F (r/w)

Channel 100x60 to 0x67 (r/w)

0x17 (r/w)

Channel 20x20 to 0x27 (r/w) 0x10 (r/w)

0x28 to 0x2F (r/w)

Channel 5

0x78 (r/w)

0x79 (r/w)

0x7A (r/w)

0x7B (r/w)

Channel 13

0x78 to 0x7F (r/w)

0x38 to 0x3F (r/w) ID_Mask [11..4]

ID_TAG [11..4]

ID_Mask [3..0]

0x11 (r/w)

0x12 (r/w)

0x13 (r/w)

0x14 & 0x15

0x16 (r/w)

Line Control (0x00)

0x01 (r/w) Transmit Contr ol ( 0x02) 0x81 Data Byte 1

Diagnosis Control (0x00)

Command (0x00)

Line Status ( 0bx01xxx00)

Transmit Status ( 0x00)

Last Message Status (0x00)

Last Error Status (0x00)

Reserved

Interrupt Status (0x80)

Interrupt Enable (0 x80)

0x00 (r/w)

0x02 (r/w)

0x03 (w)

0x04 (r)

0x05 (r)

0x06 (r)

0x07 (r)

0x08

0x09 (r)

0x0B (w) Interrupt Reset

0x0A (r/w)

0xFF Data Byte 127

0x80

0x82

0x83

0x84

0x85

0x86

0x87

0x88

0x89

0x8A

0x8B

0x8C

Data Byte 0

Data Byte 2

Data Byte 3

Data Byte 4

Data Byte 5

Data Byte 6

Data Byte 7

Data Byte 8

Data Byte 9

Data Byte 10

Data Byte 11

Data Byte 12

Channel 4

Channel 8

Channel 6

Channel 12

Channel 1

Channel 11

Channel 7

Reserved

0x10 to 0x17 (r/w)

0x30 to 0x37 (r/w)

0x50 to 0x57 (r/w)

0x40 to 0x47 (r/w)

0x18 to 0x1F (r/w)

0x68 to 0x6F (r/w)

0x48 to 0x4F (r/w)

0x0C to 0x0F

ID_TAG [3..0] + COM

DRAK + Message Address

Message Lengt h + Status

Reserved

Channel 0 Registers

Channel 0

ID_TAG (lsb) + COM

ID_TAG (msb)

DRAK + Message Address

Message Lengt h + Status

0x7E (r/w)

Channel 13 Registers

ID_Mask [11..4]

0x7F (r/w) ID_Mask [3..0]

ID_Mask [11..4]

Channel 3

Channel 13

Channel 2

0x17 (r/w)

24 7615A–AUTO–02/06

TSS461F

Control and Status Registers

Line Control Register

(0x00)

• Read/write register.

• Default value af ter reset: 0y00

• reserved: Bit 2, this bit cannot be set by the user; a 0 must always be written to this bit.

CD[3:0] Clock Divider They control the VAN Bus rate through a Baud Rate generator according to the formula below:

PC Pulsed CodeOne The TSS461F will transmit and receive data using the pulsed coding mode (i.e optical or radio

link mode). The use of this mode implies communication via the RXD0 input and the non-func-

tionality of the diagnosis system.

Zero: (default at reset) The TSS461F will transmit and receive data using the Enhanced

Manchester code (RXD0, RXD1, RXD2).

IVTX Invert TXD output.

IVRX Invert RXD inputs.The user can invert the logical levels used on either the TXD output or the

RXD inputs in order to adapt to different line drivers and receivers.

One: A one on either of these bits will invert the respective signals.

Zero: (default at reset). The TSS461F will set TXD to recessive state in Idle mode and consider

the bus free (recessive states on RXD inputs).

Transmit Control

• Read/Write register

• Default value af ter reset: 0x02

76543210

MR3 MR2 MR1 MR0 VER2 VER1 VER0 MT

FTSCLK FXTAL1

n16×

------------------

76543210

MR3 MR2 MR1 MR0 VER2 VER1 VER0 MT

7615A–AUTO–02/06

TSS461F

MR[3:0]: Maximum

Retries These bits allow the user to control the amount of retries the circuit will perform if any errors

occurred during transmission.

Table 5. Retries

Note: Bus contention is not regarded as an error and that an infinite number of transmission attempts

will be performed if bus contention occurs continuously.

VER[2:0]: DLC Version

After Reset • 000: TSS461A & B

• 001: TSS461C and TSS461F

These bits cannot be set by user; 001 must always be written to these bits.

MT: Module Type The three differe nt module types are supported (see section “VAN Frame”):

One: The TSS461F is an autonomous module (Rank 0), an synchronous access module (Rank

1) or a slave module (Rank 16).

Zero: The TSS461F is an synchronous access module (Rank 1) or a slave module (Rank 16).

MR [3:0] Max Number of Retries Max Number of Transmits

0000 0 1

0001 1 2

0010 2 3

0011 3 4

0100 4 5

0101 5 6

0110 6 7

0111 7 8

1000 8 9

1001 9 10

1010 10 11

1011 11 12

1100 12 13

1101 13 14

1110 14 15

1111 15 16+

26 7615A–AUTO–02/06

TSS461F

Diagnosis Control

• Read/Write register

• Default value af ter reset: 0x00.

The diagnosis is discussed in detail in section “Diagnosis States”.

• In its four high order bits the user can program the SDC rate SDC [3:0]

• In its two medium order bits the diagnosis system mode is controlled: M1, M0

• In the two low order bits, the user controls if the SDC and TIP are to be generated

automatically ETIP, ESDC

SDC [3:0]: SDC divider The input clock is the times lot clock.

Table 6. System Diagnosis Clock Divider

76543210

SDC3 SDC2 SDC1 SDC0 Ma Mb ETIP ESDC

SDC Divider SDC [3:0] Divide By

0000 64

0001 128

0010 256

0011 512

0100 1024

0101 2048

0110 4096

0111 8192

1000 16384

1001 32768

1010 65536

1011 131072

1100 262144

1101 524288

1110 1048576

1111 2097152

7615A–AUTO–02/06

TSS461F

Ma, Mb: Operating

mode command bits Table 7. Diagnosis System Command Bits

ETIP: Enable

Transmission In

Progress

One: Enable TIP generation

Zero: Disable TIP generation.

• The Transmission In Progress (TIP) tells the diagnostic system to enable transmission

diagnosis.

ESDC: Enable System

Diagnosis Clock One: Enable SDC divider.

Zero: Disable SDC divider.

-The Synchronous Diagnosis Clock (SDC) controls the cycle time of the synchronous diagnosis.

Command Register

(0x03)

• Write only register.

• Reserved: Bit 1, 2 these bit cannot be set by the user; a zero must always be written to

these bit.

• If the circuit is operating at low bit rates there mig ht be a considerable delay between the

writing of this register and the performing of the actual command (worst case 6 timeslots).

The user must verify, by reading the Line Status Register (0x04) that the commands have

been performed.

GRES: General Reset The Reset circuit command bit performs, if set, exactly as if the external reset pin was asserted.

This command bit has its own auto-reset circuitry.

One: Reset active

Zero: Reset inactive

SLEEP: Sleep

Command If the user sets the Sleep bit, the circuit will enter sleep mode. When the circuit is in sleep mode,

all non-user registers are setup to minimize power co nsumption and the oscillator is stopped. To

exit from this mode, the user must set either the idle or activate commands.

One: Sleep active

Zero: Sleep inactive

Ma Mb

0 0 Forces the Communication on RxD0 (differential)

0 1 Forces the Communication on RxD2 (DATA)

1 0 Forces the Communication on RxD1 (DATA)

1 1 Automatic selection

76543210

GRES SLEEP IDLE ACTI REAR 0 0 MSDC

28 7615A–AUTO–02/06

TSS461F

IDLE: Idle Command If the user sets the Idle bit, the circuit will enter idle mode. In idle mode the oscillator will oper-

ate, but the TSS461F will not transmit or receive anything on the bus, and the TXD output will

be in three-state

One: Idle active

Zero: Idle inactive

ACTI: Activate

Command The Activate command will put the circuit in the active mode, i.e it will transmit and receive nor-

mally on the bus. When the circuit is in activate mode the TXD three-state output is enabled.

One: Activate active

Zero: Activate inactive

REAR: Re-Arbitrate

Command This command will, after the current attempt, reset the retry counter and re-arbitrate the mes-

sages to be transmitted in order to find the highest priority message to transmit.

One: Re-arbitrate active

Zero: Re-arbitrate inactive

MSDC: Manual System

Diagnosis Clock Rather than using the SDC divider described in section “Diagnosis Control Register (0x02)”, the

user can use the manual SDC co mmand to generate a SDC pulse for the di agnosis system.

This MSDC pulse should be high at least two timeslot clock.

Line Status Register

(0x04)

Read only register.

• Default value after reset: 0bx01xxx00.

• This register reports the operation mode of the TSS461F in the Sleep an Idle bits

(Command Register located at address 0y03) as well as th e diagnosis system st atus bits S2

to S0 discussed in section “Diagnosis System”.

SPG: Sleeping

IDG: Idling Default mode at reset

Sa, Sb and Sc Diagnosis system status bits

• Sa and Sb

76543210

xSPGIDGScSbSaTXGRXG

7615A–AUTO–02/06

TSS461F

Table 8. Diagnosis System Status Bits

• Sc: As soon as one of the three inputs (RXD2, RXD1, RXD0) differs from the others in the

input comparison analy sis pe rf or m by the diagnosis syste m, S2 is set.

The only way to reset this status bit is through the RI signal or a general reset.

TXG: Transmitting If this status bit is active, it indi cates that th e TSS461F has ch osen an ide ntifier to tran smit, and

it will continue to make transmission attempts for this mess age until it succeeds or the retry

count is exceeded.

RXG: Receiving The receiving indicates that there is activity on the bus.

Note: For safe modification of active channel registers both bits should be inactive (except "abort"

command).

Transmission Status Register (0x05)

• Read only regist er.

• Default value af ter reset: 0x00.

• The transmission S tatus register contains the number of retries made up-to-date, according

to Table 3, and the channel currently in transmission.

NRT [3:0]: Number of

Retries Done in

Transmission

IDT [3:0]: Channel

Number Currently in

Transmission

Last Message Status Register (0x06)

• Read only regist er.

• Default value af ter reset: 0x00.

• This register is the same as the transmission status register. It contains the last identifier

number that was successfully transmitted, received or exceeded its retry count.

If it was a successful transmission, the number of retries performed can be seen in this

Sb Sa Communication Indication

0 0 Nominal mode, differential communication

0 1 Degraded over DATA, fault on DATA

1 0 Degraded over DATA, fault on DATA

1 1 Major error, fault on DATA and DATA

76543210

NRT3 NRT2 NRT1 NRT0 IDT3 IDT2 IDT1 IDT0

76543210

NRTR3 NRTR2 NRTR1 NRTR0 IDTR3 IDTR2 IDTR1 IDTR0

30 7615A–AUTO–02/06

TSS461F

NRTR [3:0]: Number of retries done successfully in transmission. In case of reception NRTR[3:0] is

undefined.

IDTR [3:0]: Channel number that was successfully transmitted, received or exceeded its retry count.

Last Error Status Register (0x07)

• Read only regist er.

• Default value af ter reset: 0×00.

• The Last Error Status Register contains the error code for the last transmission or r ecep tion

attempt. It is updated af ter each attempt, i.e. several erro r codes can be r eported during one

single transmission (with several retries).

BOC: Buffer Occupied • When one channel configured in “Reply request” mode has its “received” bit set when it

attempts to transmit its request.

• BOC with the link capability between two channels sharing the same received buffer is set

when one channel has already set its “received” bit in its “Message length and sta tus

Channel register” and a receive is attempted on the other one.

BOV: Buffer Overflow BOV indicates that the buffer length setup in the Channel Status Register was shorter than the

number of bytes received plus 1, therefore, some data got lost.

One: BOV active

Zero: BOV inactive

FCSE: Framing Check

Sequence Error FCSE indicates a mismatch between the FCS received and the FCS calculated

One: FCSE active

Zero: FCSE inactive

ACKE: Acknowledge

Error ACKE indicates a physical violation or collis ion on ACK field of the frame when the TSS463 is

produced.

One: ACKE active

Zero: ACKE inactive

76543210

x BOC BOV x FCSE ACKE CV FV

7615A–AUTO–02/06

TSS461F

Figure 18. ACKE Status Bit

CV: Code Violation CV indicates:

• either a Manchester code violation (2 identical TS on Manchester bit), or a physical violation

(transmitted bit “dominant”, received bit “recessive”), on fields ID, COM, DATA and CRC, or

• a physical violation or collision on field “preamble” and the “recessive” bit of the “Star Sync”

field.

One: CV active

Zero: CV inactive

RAK* = 1

*RAK: bit of the frame COMMAND field

ACKE = 0

ACKE = 1

ACKE = 0

ACKE = 1

EOD field ACK field

expected

received

expected

received

DLC: Producer

RAK = 0

32 7615A–AUTO–02/06

TSS461F

FV: Frame Violation FV indicates a physical violation or collision on ACK field of the frame when the TSS463 is

consumed.

One: FV active

Zero: FV inactive

Figure 19. FV Status Bit

Interrupt Status Register (0x09)

• Read only re gist er.

• Default value af ter reset: 0×80

RST: Reset interrupt RE indicates that the circuit has detected a valid reset command via the RESET pin or the reset

command bit GRES. This interrupt cannot be disabled, since its enable bit is set when a reset is

detected.

TE: Transmit Error

Status Flag (or

Exceeded Retry)

This flag is set only when the Max number of transmission (1+MR [3:0]) is reached with error of

transmission.

Figure 20. Exceeded retry with MR[3.0] = 3

FV = 0

FV = 1

FV = 0

FV = 1

EOD field ACK field

expected

received

expected

received

DLC: Consumer

76543210

RST 0 0 TE TOK RE ROK RNOK

1st TX 2nd TX 3rd TX set TE

set CHER

set CHTx

7615A–AUTO–02/06

TSS461F

TOK: Transmit OK

Status Flag

RE: Receive Error

Status Flag

ROK: Receive “with

RAK (RAK=1)” OK

Status Flag

RNOK: Receive “with no

RAK (RAK=0)” OK

Status Flag

One: Status flag activated

Zero: No status flag.

Interrupt Enable Register (0x0A)

• Read/write register

• Default valu e re se t: 0x 80

Note: On reset the Reset Interrupt Enable bit is set to 1 instead of 0, as the general rule.

TEE: Transmit Error

Enable

TOKE: T ransmission OK

Enable

REE: Reception Error

Enable

ROKE: Reception “with

RAK” OK Enable

RNOKE: Reception

“with no RAK” OK

Enable

One: IT enabled.

Zero: IT disabled.

Interrupt Reset Register (0x0B)

• Write only register.

• Reserved bit: 5 and 6. This bit cannot be set by user; a zero must always be written to this

bit.

76543210

1 0 0 TEE TOKE REE ROKE RNOKE

76543210

RSTR 0 0 TER TOKR RER ROKR RNOKR

34 7615A–AUTO–02/06

TSS461F

RSTR: Reset Interr upt

Reset

TER: Transmit Error

Status Flag Reset

TOKR: Transmit OK

Status Flag Reset

RER: Receive Error

Status Flag Reset

ROKR: Receive “with

RAK” OK Status Flag

Reset

RNOKR: Receive “with

no RAK” OK Status Flag

Reset

One: Status flag reset

Zero: Status flag unchanged

Figure 21. Update of the Status Register

Channel Registers There is a total of 14 channel register sets, each occupying 8 bytes for addressing simplicity,

integrated into the circuit. Each set contains two 2 x 8-bit registers for the indentifier tag, indenti-

fier mask and command fields plus two 1 x 8-bit reg ister s fo r DMA poin te rs and me ssa ge status.

The base_address of each set is: (0x10 + [0x08 * channel_number]).

When the TSS461F is reset either via the external reset pin or the general reset command, the

channel registers ar e not affected. For exam ple, on power-up o f the circuit, all the channel r egis-

ters start with random values.

Due to this fact, the user should take care to initialize all the channel registers before exiting

from idle mode. The easie st way to disable a channel register is to se t the received and transm it-

ted bits to 1 in the Message Length & Status Register.

Reset RXG, TXG

Line Status Register (0x04)

4 TS

Set RXG

Set TXG

4 TS 1 to 2 TS 6 TS

SOF ID+COM+DATA+CRC

EOD

ACK

BUS

INT

Write “IT Status Register”

Write “Last Error Register”

Write “Last Message Register”

Write “Message Length & Status Register”Write “Message Status”

7615A–AUTO–02/06

TSS461F

Table 9. Channel Register Sets Map

Table 10. Channel Register Set Structure

Identifier Tag and

Command Registers The identifier tag and command registers is located at the base_ addre ss and ba se_addr ess + 1.

It allows the user to specify the full 12-bit identifier field of the ISO standard and the 4-bit

command.

• Read/Write registers.

Channel Number From To Ch annel Number From To

6 0x40 0x47 13 0x78 0x7F

5 0x38 0x3F 12 0x70 0x77

4 0x30 0x37 11 0x68 0x6F

3 0x28 0x2F 10 0x60 0x67

2 0x20 0x27 9 0x58 0x5F

1 0x18 0x1F 8 0x50 0x57

0 0x10 0x17 7 0x48 0x4F

Reg. Name Offset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ID_MASK0x07 ID_M [3:0] xxxx

ID_MASK 0x06 ID_M [11:4]

(no register)0x05x xxxxxxx

(no register)0x04x xxxxxxx

MESS_L/

STA 0x03 M_L [4:0] CHER CHTx CHRx

MESS_PTR 0x02 DRACK M_P [6:0]

ID_TAG/

CMD 0x01 ID_T [3: 0] EXT RAK RNW RTR

ID_TAG 0x00 ID_T [11:4]

76543210

ID_T 3 ID_T 2 ID_T 1 ID_T 0 EXT RAK RNW RTR base_address

+ 0x01

76543210

ID_T 11 ID_T 10 ID_T 9 ID_T 8 ID_T 7 ID_T 6 ID_T 5 ID_T 4 base_address

+ 0x00

36 7615A–AUTO–02/06

TSS461F

ID_T [11:0]: Identifier

Tag Upon a reception hit (i.e, a go od comparison between the iden tifier received and an identifier

specified, taking the co mpa rison ma sk into acco u nt, as well as a statu s an d comman d indicating

a message to be received, the identifier tag bits value will be rewritten with the identifier bits

actually received.

EXT, RAK, RNW &

RTR: (S ee

section “Retries,

Rearbitrate and Abort”)

No comparison will be done on the command bits, except on EXT bit. The RAK, RNW and RTR

bits will be written into the first byte of the Message upon a reception hit.

The RNW and RTR bit s, as we ll as th e stat us bits in the length a nd st atus r egister , mus t be in a

valid position for reception or transmission. If not, the message corresponding to this identifier is

considered as inactive or invalid.

The way of knowing if an acknowledge sequence was requested or not is to check the first byte

of the Message.

Message Pointer

where, in the Message DATA RAM area, the message buffer is located.

• Read/Write register

DRAK: Disable RAK

(Used in 'Spy Mode') In reception: whatever is the RAK bit of the incoming valid frame, no ACK answer will be set. If

the message was successfully received, an IT is set (ROK or RNOK).

In transmission: no action.

One: disable active, 'spy' mode.

Zero: disable inactive, normal operation.

M_P [6:0]: Message

Pointer Since the Message DATA RAM area base add ress is 0x80 , th e value in this reg ister is the o ffset

from that address. If the message buffer length value is illegal (i.e. zero), this register is rede-

fined as being a link pointer, thus containing the channel number of the chann el that contains the

actual message pointer, message length and received status. However, the ide ntifier, mask,

error and transmitted status used will be the originally matched channel. In any case, if a link is

intended, the three high bits of M_P [6:0] should be set to 0.

This allows several channels to use the same actual reception buffer in Message DATA RAM,

thus diminishing the memory usage.

Note that only 1 level of link is supported.

76543210

DRAK M_P 6 M_P 5 M_P 4 M_P 3 M_P 2 M_P 1 M_P 0 base_address

+ 0x02

7615A–AUTO–02/06

TSS461F

Message Length And

Statu s Re gi st er The message length and status register at address (base_address + 0x03) is also 8 bits wide. It

indicates the length reserved for the message in the Message DATA RAM area.

• Read/Write register.

M_L [4:0]: Message

Length The 5 high bits of this register allow the user to specify either the length of the message to be

transmitted, or the maximum length of a message receivable in the pointed reception buffer.

Note, that the first byte in this register does not contain data, but the length of the message

received. This implies that the length value has to be equal to or greater than the maximum

length of a message to be received in this buffer (or the length of a message to be transmitted)

plus 1. Thus allowing a maximum length of 30 bytes and a minimum length of 0 byte.

If the value of this field is "illegal" (i.e 0x00) then this message pointer is defined as being a link

(see section “Message Pointer Register” and section “Linked Channels”).

CHER: Channel Error

Status and Abort

Command

As status, this bit is set by the TSS461F whe n error occurs in transmission or on a received

frame. The user must reset it.

To abort the transmission defined in the channel, this bit can be set to1 by the user (see

section “Retries, Rearbitrate and Abort” and section “Abort”).

CHTx: Channel

Transmitted and

Transmit Enable

Command

76543210

M_L 4 M_L 3 M_L 2 M_L 1 M_L 0 CHER CHTx CHRx base_address

+ 0x03

M_L [4:0] = 0x00 Linked channel

M_L [4:0] = 0x01 Frame with no DATA field (*)

M_L [4:0] = 0x02 Frame with 1 DATA byte

- - - - - - - - - - - - - - - - - - - - - - - - - - - - -

M_L [4:0] = 0x1D Frame with 28 DATA bytes

M_L [4:0] = 0x1E Frame with 29 DATA bytes

M_L [4:0] = 0x1F Frame with 30 DATA bytes

(*) Different of a reply request frame with no in-frame reply (deferred reply).

38 7615A–AUTO–02/06

TSS461F

CHRx: Channel

Received and Receive

Enable Command

The two low order bits of this register contain the message status. Together with the RNW and

RTR bits of the command register (base_address + 0x01), they define the message type of this

channel (seesection “Messages Types”). As a general rule (see section “Abort”), the status bits

are only set by the TSS461F, so the user must reset them to perform a transmission (CHTx)

or/and a reception (CHRx). The received and transmitted bits are only set if the corresponding

frame is without errors or if the retry count has been exceeded.

Identifier Mask

Registers The Identifier Mask registers (base_address + 0x06 and base_address + 0x07) allow bitwise

masking of the comparison between the identifier received and the identifier specified.

• Read/Write registers

ID_M [11:0]: Identifier

Mask A value of 1 indicates comparison enabled.

A value of 0 indicates comparison disabled.

76543210

ID_M 3ID_M 2ID_M 1ID_M 0 x x x x

76543210

ID_M 11 ID_M 10 ID_M 9 ID_M 8 ID_M 7 ID_M 6 ID_M 5 ID_M 4

7615A–AUTO–02/06

TSS461F

Mailbox The mailbox contains all the messa ges received or to be transm itted. Each messages is link to a

channel. The Mailbox RAM area has 128 bytes and is mapped from 0x80 to 0xFF (see

section “Mapping”).

The message (or message buffer) is composed of:

• 1 byte of message status (only used in receiving)

• Bytes of data. These data are the bytes of the DATA field of the frame with the same

organization.

The message is pointed by the Message Pointer Register of the channel, the length of the mes-

sage is given by the Message Length & Status Register of the channel (section “Message

Pointer Register” and section “Message Length And Status Register”). This area is a pure RAM,

it contains a random value after reset.

Figure 22. Message Buffer Structure for Reception

Note: Received DATA Frame, immediate or deffered reply

CHER CHTx CHRx Message Pointer Register

DRAK M_P [6..0]

Message Length & Status Register

M_L [4..0]

RTRRNWRAK M_L [4..0] = n+1

receivedreceivedreceived received

DATA 0

Message

RTR

RNW

ID [11..0]

EXT

SOF DATA 0 DATA n FCS

EOD

ACK

EOF

received

DATA nreceived M_P + 0x80 + n + 2

( M_L >= n + 2 )

M_P + 0x80

RAK

40 7615A–AUTO–02/06

TSS461F

Figure 23. Message Buffer Structure for Transmission

Message Status (Pointed by: Message Pointer Register)

(no significant value in case of message to be transmitted )

RRAK: Received RAK

Bit This bit is the RAK bit coming from the COM field of the received frame.

RRNW: Received RNW

Bit This bit is the RNW bit coming from the COM field of the received frame.

RRTR: Received RTR

Bit This bit is the RTR bit coming from the COM field of the received frame.

RM_L[4:0]: Message

Length of the Rece ived

Frame

If the DATA field of the received frame included DATA0 to DATAn, RM_L[4:0] = n+1, even if the

reserved length (Message Length & Status Register) is larger.

CHER CHTx CHRx Message Pointer Register

DRAK M_P [6..0]

essage Length & Status Register

M_L [4..0]

DA TA 0

Message

RTR

RNW

RAK

ID [11..0]

EXT

SOF DATA 0 DATA n FCS

EOD

ACK

EOF

Transmitted DAT A Frame

Transmitted

DATA n

Transmitted M_P + 0x80 + n + 2

( M_L >= n + 2 )

M_P + 0x80

(Nothing)

76543210

RRAK RRNW RRTR RM_L4 RM_L3 RM_L2 RM_L1 RM_L0

7615A–AUTO–02/06

TSS461F

Figure 24. Message Status Updating

Message Data (String Pointed by: Message Pointer Register + 1)

DATA0 is the first received (or transmitted) byte, DATAn is the last one.

Notes: 1. If the length reserved (in the message length & status register) for an incoming frame is 2

bytes greater or more, the TSS461F will write the 2 bytes of the CRC field in the message

string just after DATAn.

Because the VAN frame does not contain a message length, the only way for the component

to know the length of the DATA field is either the message length register value, or the EOD

field detection. When the reserved length is too large, at the moment when it detects the EOD,

the TSS461F has already written the 2 bytes of the CRC field, considering these bytes as nor-

mal DATA.

2. The Mailbox RAM area is a circular buffer. The next location after 0xFF is 0x80.

76543210

DATAn

- - - - - - - - - - - - - - - - - - -- - - - - -

DATA0

Data Frame

Immediate

I, P C

Frame Type

Node x Message Status on Node A after IT(*)

Commu- Node A

RAK RNW RTR length

value

I, C P

RAK

RNW RTR

Deferred

Reply previous

value

I, C P

RAK RNW RTR

Data Frame I, PC

Immediate

I, CP

RAK RNW RTR length

Deferred

I, CP

RAK RNW RTR length

previous values

P: Producer I: Initiator C: Consumer

(*) After IT ROK or RNOK. In case of IT RE, the values can be erroneous.

nication

42 7615A–AUTO–02/06

TSS461F

Messages

Types There are 5 basic message types defined in the TSS461F. Two of them (transmit and receive

message types) correspond to the normal fra me, and the rest correspond to the different ver-

sions of reply frames.

To transmit a normal data frame on the VAN bus, the user must program an identifier as a

Transmit Message. The TSS461F will then transmit this message on the bus until it has suc-

ceeded or the retry count is exceeded.

The opposite of the transmit message type is the Receive Message type. Thi s message type will

not generate any frames on the bus. Instead, it will listen to the bus until a frame passes that

matches its identifier, with the mask taken into account, and then receive the data in that frame.

The data received will be stored in the message buffer and the length of the message received

is stored in the first byte of the message buffer.

The actual identifier received is stored in the identifier register itself. This identifier may differ

from the identifier specified in the register due to the effect of the mask register.

Normally, this s hould no t interf ere wit h t he next id entif ier co mpariso n sinc e the bits th at ma y dif-

fer are masked via the mask register.

The Reply Request Message type is a demand to transmit on the VAN bus a reply request.

When this message type is pro grammed, three things can happen.

First, no other modules on the bus responded with an in-frame reply, in this case the TSS461F

will set the message type to the after transmission state. When this message type is pro-

grammed, the TSS461F will listen on the bus for a deferred reply frame matching this identifier,

without transmitting the reply request.

Transmit Message

RNW RTR CHTx CHRx

Initial Setup 0 0 0 Don’t Care

After Transmission 0 0 1 Unchanged

Receive Message

RNW RTR CHTx CHRx

Initial Setup 0 1 Don’t Care 0

After Transmission 0 1 Unchanged 1

Reply Request Message

RNW RTR CHTx CHRx

Initial Setup 1 1 0 0

After Transmission

(Waiting for reply) 11 1 0

After Reception

(of reply) 11 1 1

7615A–AUTO–02/06

TSS461F

Second, another module on the bus replies with an in-frame reply. In this case the message type

will pass immediately into the after reception state, without passing the after transmission state.

Third, the TSS461F has not yet started to transmit the reply request, when another module

either requests a reply, and gets it, or transmits a deferred reply. Warning! This should be

avoided as it may result in an illegal message type (Illegal reply Request).

The immediate Reply Message will attempt to transmit an in-frame reply, using the data in the

message buffer. A deferred Reply Message is shown below.

This message type will immediately transmit a deferred reply frame.

Finally, there is the Reply Request Detector Message type. Its purpose is to receive a reply

request frame and notify the processor, without transmitting an in-frame reply.

The table above shows all inactive messages types. The last combination will transmit a reply

request, but will not receive the reply since its buffer is tagged as occupied.

Reply Request Message Without Transmission

RNW RTR CHTx CHRx

Initial Setup 1 1 Don’t Care 0

After Reception 1 1 Unchanged 1

Immediate Reply Message

RNW RTR CHTx CHRx

Initial Setup 1 0 0 0

After Transmission 1 0 1 1

Deferred Reply Message

RNW RTR CHTx CHRx

Initial Setup 1 0 0 1

After Reception

(of Reply Request) 10 1 1

Reply Request Detection Message

RNW RTR CHTx CHRx

Initial Setup 1 0 1 0

After Reception 1 0 1 1

Inactive Message

RNW RTR CHTx CHRx

Recommended Don’t Care Don’t Care 1 1

After Transmission 0 0 1 Don’t care

After Reception 0 1 Don’t Care 1

Illegal Reply Request 1 1 0 1

44 7615A–AUTO–02/06

TSS461F

Priority Among

the Different

Channels

The priority handling on the VAN bus is already explained in the Line Interface section. The pri-

orities for the messages in the TSS461F is, however, slightly different.

For instance, it's possible that an ide ntifier matches two or more of the identifiers progr ammed

into the registers. In this case, it is the lowest identifier number that has priority. i.e., if both iden-

tifier 5 and 10 match the identifier received, it is the identifier 5 that will receive the message.

However, since the identifier 5 will become an inactive message when it has received the frame,

the next time the same identifier is seen on the bus, the corresponding data will be received by

identifier 10.

The same is valid for messages to be transmitted, i.e., if two or more messages are ready to be

transmitted, it is the one with the lowest identifier number that will get priority.

7615A–AUTO–02/06

TSS461F

Retries,

Rearbitrate and

Abort

Retries and rearbitrate commands are located, in the Transmit Control Register and in th e Com-

mand Register, respectively. An abort command is located in each channel register set, in the

Message Length & Status Register (base_address + 0x03). These three commands are avail-

able only when the TSS461F is producer.

Figure 25. Transmit Function

Retries The purpose of retries feature is to provide, the capability of retrying a transmit request in case

of failure, w hen a node trie s to re ach an other node, either on norm al DATA fr ame or on REP LY

REQUEST frame.

The maximum of retries is programmable through MR[3:0] of the Transmit Control Register

(0x01). When a channel is enable – bit CHTx= 0 of Message Length & Status Register, a 4-bit

counter is loaded with MR[3:0]. At each attempt, this counter will be countdown. To 0, an IT TE

is set in the Interrupt Status Register (0x09), and the transmission is stopped.

MR[3:0] = 1 indicates 1 retry, hence 2 transmission attempts will be performed (see Table 4).

The number of retries performed, as well as the current channel number associated, can be

read in the Transmission Status Register (0x05).

The Last Error Status Register (0x07) informs about the trouble encountered:

Activate

Ch. Enabled in

Xmit Mode? no

Select the lowest

Ch. number and

load”Max - retries”

yes

Abort activated

on current Ch.?

yes

Disable of

current Ch.

Wait for bus free

(EOF+IFS= 12 Timeslots)

Retry needed?

abort

Abort required

rearbitrate?

on current Ch. rearbitrate

yes

Transmit frame

and wait for the end

Decrement

retry counter

46 7615A–AUTO–02/06

TSS461F

• Failure cases:- Code viol (CV error bit)

– Acknowledge error (ACKE error bit)

– CRC error (FCSE error bit)

• It should be noticed that contention is considered as normal CSMA/CD protocol and,

therefore, is not taken into account in failure cases. So, an 'infinite' number of atte m pts can

be performed if bus co nte n tion occurs continuou sly.

There is only one retries counter for all channels. When the user writes the Max_Retries value,

all channels start their transmission with this parameter.

Rearbitrate The purpose of rearbitrate feature is to postpone a channel already in transmission in order to

authorize an h ighe r prior ity ( see section “Priority Among the Different Chan nels” ) messag e to be

transmit.

Typical Example • Max_retries = 1 (2 transmissions attempts).

• If Ch 8 is in a the retry loop and the user wants to transmit the Ch 5 without waiting the end

of the loop, the user can use the rearbitrate command.

• Then, the TSS461F will wait the end of the current transmission, reload the retries counter

and enable the Ch 5 to transmit.

• At the end of this transmission Ch5, either when the attempt is successful or either when the

exceeded retry count is reached , the retries counter is reloaded and the transmission is

activated for the Ch 8 again.

Figure 26. Rearbitrate Example

First attempt

Xmit Ch5

Ex: FCS Error

Rearbitrate

EOF+IFS

(Activate Ch5)

Delay

Set CHTx/Ch5 & IT ROK

Xmit Ch8 (Load Max-retries)

(Load Max-retries)

* (not seen by application)

(Load Max-retries)

Ex: FCS Error

(not seen by application)

stand-by

First attempt

Xmit Ch8

econd attempt

Xmit Ch8

(Retries - 1)

Delay

Set CHER & CHTx /Ch

Ex: set FSCE status b

and set IT TE

Delay

Viol Viol Viol

EOF+IFS: 8 + 4 Timeslots

Delay Viol: 12 Timeslots

* (not seen by application means no IT generation)

7615A–AUTO–02/06

TSS461F

Figure 27. Idle and Rearbitrate Example

If the user sets the idle bit anywhere (after rearbitrate), the idle mode is entered only at the end

of all the transmit attempts (for more information about id le command, see section “Activate, Idle

and Sleep Modes”.

Disable Channel After

Rearbitrate

Figure 28. Disable Channel After Rearbitrate Example

Note: In this case, the TSS461F completes the current attempt (Ch8) and lets the transmi ssion go to the

new channel (Ch5 if validated); otherwise, it stops all attempts on the current channel.

Abort An abort command is dedicated to channels already enabled in transmission or in-frame

response. For example, this command can be used to break the retry procedure on one

channel.

First attempt

Xmit Ch5

Ex: FCS Error

Rearbitrate

EOF+IFS

(Activate Ch5)

Set CHTx/Ch5 & IT ROK

Xmit Ch8 (Load Max-retries)

(Load Max-retries)

Ex: FCS Error

(not seen by application)

First attempt

Xmit Ch8

econd attempt

Xmit Ch8

(Retries - 1)

Idle command

Idle

Set CHER & CHTx /Ch

Ex: set FSCE status b

and set IT TE

Delay Delay

Delay

Viol Viol Viol

EOF+IFS: 8 + 4 Timeslot

Delay Viol: 12 Timeslots

* (not seen by application)

* (not seen by application means no IT generation)

irst attempt

Xmit Ch5

Ex: FCS Error

Rearbitrate

EOF+IFS

(Activate Ch5)

Delay

Set CHTx/Ch5 & IT

Xmit Ch8 (Load Max-retries)

(Load Max-retries)

* (not seen by application)

(Load Max-retries)

Ex: FCS Error

(not seen by application)

stand-by

irst attempt

Xmit Ch8

ond attempt

mit Ch8

(

Retries - 1)

Delay

Set CHER & CHTx

Ex: set FSCE stat

and set IT TE

Delay Viol Viol

EOF+IFS: 8 + 4 Timeslots

Delay Viol: 12 Timeslots

Viol

48 7615A–AUTO–02/06

TSS461F

Abort channel is done by setting the Error bit (CHER) in the Message Length & Status Register

(base_address + 0x02). This command is taken into account if the channel aborted is not trans-

mitted. When this abort command is really done, the TSS461F set to 1 the Transmitted bit

(CHTx) of the Message Length & Status Register.

The abort mechanism is integrated into the transmit function. This means, abort, priority and

retries live together in the transmit function.

Figure 29. Abort Example

Reset

Ch’s initialization

Activate

Abort Ch0 (before Xmit)

Set CHTx/Ch0

Abort Ch13 (before Xmit)

Abort Ch4 (during Xmit)

Set CHTx/Ch4 &IT ROK

Set CHTx/Ch6 & IT ROK

if success

Set CHTx/Ch6 & IT ROK

if success

/Ch6 &

Set CHTx/Ch13

Xmit Ch6

Xmit Ch4

12 Timeslots

f previously fail

Xmit Ch6

f previously fail

IT ROK

or IT RE

Set CHTx

or CHER

7615A–AUTO–02/06

TSS461F

Activate, Idle

and Sleep

Modes

Sleep, idle and activate commands are located in the Command Register (0x03). These three

commands are general commands for the TSS461F.

Idle and Activate

Commands After reset, the TSS461F starts in idle mode . In this mode, the oscillator operates (CKOUT pin

active) but the circuit cannot transmit or receive anything on the VAN bus. The TxD output (pin

18) is in three-state mode, a pull-up resistor must be provided externally or by the line driver to

avoid floating state on the VAN bus.

To activate the TSS461F, the user must set the activate bit (ACTI) and reset the idle bit (IDLE).

Figure 30. Idle and Activate Timings

In both cases, the idle state can be verified by reading the Line Status register (0x04).

Sleep Command If the user sets the sleep bit (SLEEP), the TSS461F enters in sleep mode, whatever are the val-

ues of activate and idle bits. All non-user registers are set-up to reduce the p ower consump tion

and the internal oscillator is immediately stopped. However, all user regis ters (accessible by µP

bus) are always available by the user

To exit from this mode, the user must set either the idle bit or the activate bit.

In a typical application (Figure 12) using the CKOUT feature (pin 12), if the TSS461F is put in

sleep mode, the clock provided to the microcontroller is stopped. So, the system does not run

and the only way to awake this application is an external reset.

(max)

RxD

TxD

fter reset

Idle mode Activate mode

Activate command

3 TS 8 TS

12 TS TS: Timeslot period

SOF

Idle command

FCS

EOD

ACK

5 TS4 TS

RxD

INT

Idle modeActivate mode

50 7615A–AUTO–02/06

TSS461F

Linked

Channels The linkage feature allows two channels to share the same Message area, the message pointer

and the message length assumes the following property:

• Zero value as message length (M_L [4:0] - base_address + 0x03) declares the channel

linked to another channel.

• The number of this other channel is defined in the message pointer field (M_P [6:0] -

base_address + 0x02).

• The pointer and the len gth values for the Message area are defined only once time, in the

Only one level of linkage can be created. For example, (see Figure 30) a Channel k can be

linked to the Channel i but not to Channel j, already defined as linked to Channel i.

All the others can be different between the two ch annels, for example the ID_Tag.

Figure 31. Linkage Mechanism

This Message Area sharing permits either optimizing the allocation of the 128 bytes of DATA,

performing some special communica tions between the different nodes of the network.

ID_Tag j (msb)

ID_Tag j (lsb) EXT RAK RNW RTR

DRAK i

0x00 CHRx

Message Status

DATA 0

--- Channel i ---

ID_Tag i (msb)

ID_Tag i (lsb) EXT RAK RNW

DRAK Mess_Ptr

Mess_Len = n+2CHERCHTx CHRx

ID_Mask i (lsb)

--- Channel j ---

DATA n

The Channel j linked

to the Channel i

. . . .

Length = n+2

--- Message for Channels i & j ---

Channel i and j

share the same

Message area

ID_Mask i (msb)

RTR

CHERCHTx

ID_Mask j (msb)

ID_Mask j (lsb)

7615A–AUTO–02/06

TSS461F

Electrical Characteristics

Absolute Maximum Ratings

Characteristics TA = -40°C to 125°C; VCC = 5 V + 10%; VSS = 0 V

Ambient temperature under Bias:

A = Automotive............... ................. ... ... ...........-40°C to 125°C

Storage Temperature........................................-65°C to 150°C

Voltage on VCC to VSS.........................................-0.5 to +7.0 V

Voltage on any Pin to VSS......................-0.5 V to VCC + 0.5 V

Note: Stresses at or above those listed under "Absolute

Maximum Ratings" may cause permanent damage to

the device. This is a stress rating only a nd functional

operation of the device at these or any other condi-

tions exceeding those indicated in the operational

sections of this specification is not implied. Exp osure

to absolute maximum rating conditions may affect

device reliability.

Symbol Parameter Min Max Type Test Conditions

VIL Input Low Voltage (except RESET and

XTAL1) -0.5 0.8 V

VIH Input High Voltage (except RESET and

XTAL1) 2.0 VCC+0.5 V

VIL1 Input Low Voltage (RESET and XTAL1) -0.5 0.3·VCC V See Figure 2

VIH1 Input High Voltage (RESET and XTAL1) 0.7 VCC VCC+0.5 V

VOL Output Low Voltage 0.4 V IOL = 3.2 mA, Vcc min

VOH Output High Voltage 2.4 IOH = -3.2 mA, Vcc min

IL Input Leakage Current +5μA0 < V

IN < VCC

RPD Input Pull-down Resistor 110 kΩ0 < VIN < VCC

CIO I/O Buffer Capacitance 10 pF Not tested

ICCSB Power Supply Current

Sleep Mode 50 μA (Note 1)

ICCOP Power Supply Current

Idle or Active Mode 4

15 mA

mA (Notes 2, 4)

(Notes 3, 4)

Notes: 1. Sleep Mode ICCSB is measured according to Figure 40 with a VSS Clock Signal.

2. Active mode ICCOP is measured at: XTAL = 1 MHz clock, VAN speed rate = 62.5 KTS/s.

3. Active mode ICCOP is measured at: XTAL = 16 MHz clock, VAN speed rate = 250 KTS/s.

4. ICC is a function of the Clock Frequency. Figure 8 displa ys a graph showing ICC versus Clock frequency.

5. RESET, RxD0, RxD1, RxD2 inputs.

52 7615A–AUTO–02/06

TSS461F

Figure 32. ICC

Figure 33. ICC Versus Clock Frequency at 250 KTimeslot/s

LOCK SIGNAL

N.C.

Icc

TXD

8.5

7.5

7615A–AUTO–02/06

TSS461F

AC Characteristics

Microprocessor

Interface

TA = -40°C to 125°C; VCC = 5V + 10%; VSS = 0V

Symbol Characteristic Min Max Unit

TRESET RESET High Pulse Width (For Power-up Reset) 15 ns

LHLL ALE High Pulse Width 10 ns

AVLL Address Valid to ALE Low Setup Time 10 ns

LLAX ALE Low to Address Invalid Hold Time 10 ns

AVWL Address Valid to Command Active Time 20 ns

DVWH Data Valid to Write Inactive Setup Time 10 ns

6TWHDX Write Inactive to Data Invalid Hold Time 12 ns

WHLH Write Inactive to ALE High Recovery Time 20 ns

RLDV Read Active to Data Valid Access Time 110 ns

RHDZ Read Inactive to Data Float Time 20 ns

10 TWHRLIZ Write Inactive or Read Active to IRQ Float Time 90 ns

11 TIZIL IRQ Float Pulse Width 2 20 ns

54 7615A–AUTO–02/06

TSS461F

Oscillator

Characteristics Figure 34. C2 Versus Frequency

Note: C1 (no capacitance needed) see Figure 2.

External Clock

Drive

Characteristics

(XTAL1)

200

100

12 48

MHz

Symbol Parameter Min Max Unit

TCHCH Oscillator Period 120 ns

TCHCX High Time 20 ns

TCLCX Low Time 20 ns

TCLCH Rise Time 20 ns

TCHCL Fall Time 20 ns

tCHCX tCLCX

tCHCH

TAL1 VIH

VIL

tCLCH

tCHCL

VIH VIH

VIL

7615A–AUTO–02/06

TSS461F

Packaging Information 24

SO MM INCH

A 2.35 2.65 0.093 0.104

A1 0.10 0.30 0.004 0.012

B 0.35 0.49 0.014 0.019

C 0.23 0.32 0.009 0.013

D 15.20 15.60 0.599 0.614

E 7.40 7.60 0.291 0.299

e 1.27 BSC 0.050 BSC

H 10.00 10.65 0.394 0.419

h 0.25 0.75 0.010 0.029

L 0.40 1.27 0.016 0.050

N24 24

a0° 0°

56 7615A–AUTO–02/06

TSS461F

Ordering Information

Note: 1. These products are available in ROHS version.

Part Number Supply Voltage Temperature Range Package Packing

TSS461F-TDSA-9 5V +10% -40°C to +125°C SO24 Tube

TSS461F-TDRA-9 5V +10% -40°C to +125°C SO24 Tape & Reel

TSS461F-TDRZ-9(1) 5V +10% -40°C to +125°C SO24 Tape & Reel

Printed on recycled paper.

7615A–AUTO–02/06

are the trademarks of Atmel Corporation or its subsidiaries. Other ter ms and product names may be trademarks of other s.

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