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© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3111 • Rev. 1.6
January 2015
FAN3111 — Single 1A High-Speed, Low-Side Gate Driver
FAN3111 — Single 1A High-Speed, Low-Side
Gate Driver
Features
1.4 A Peak Sink / Source at VDD = 12 V
1.1 A Sink / 0.9 A Source at VOUT = 6 V
4.5 to 18 V Operating Range
FAN3111C Compatible with FAN3100C Footprint
Two Input Configurations:
Dual CMOS Inputs Allow Configuration as
Non-Inverting or Inverting with Enable Function
Single Non-Inverting, Low-Voltage Input for
Compatibility with Low-Voltage Controllers
Small Footprint Facilitates Distributed Drivers for
Parallel Power Devices
15 ns Typical Delay Times
9 ns Typical Rise / 8 ns Typical Fall times with
470 pF Load
5-Pin SOT23 Package
Rated from –40°C to 125°C Ambient
Applications
Switch-Mode Power Supplies
Synchronous Rectifier Circuits
Pulse Transformer Driver
Logic to Power Buffer
Motor Control
Description
The FAN3111 1A gate driver is designed to drive an N-
channel enhancement-mode MOSFET in low-side
switching applications.
Two input options are offered: FAN3111C has dual
CMOS inputs with thresholds referenced to VDD for use
with PWM controllers and other input-signal sources
that operate from the same supply voltage as the driver.
For use with low-voltage controllers and other input-
signal sources that operate from a lower supply voltage
than the driver, that supply voltage may also be used as
the reference for the input thresholds of the FAN3111E.
This driver has a single, non-inverting, low-voltage input
plus a DC input VXREF for an external reference voltage
in the range 2 to 5 V.
The FAN3111 is available in a lead-free finish industry-
standard 5-pin SOT23.
IN+
VDD OUT
GND
1
2
3 4
5
IN−
Figure 1. FAN3111C (Top View)
IN+
VDD OUT
GND
1
2
3 4
5
XREF
Figure 2. FAN3111E (Top View)
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3111 • Rev. 1.6 2
FAN3111 — Single 1A High-Speed, Low-Side Gate Driver
Ordering Information
Part Number
Input
Threshold
Package
Packing Method
Quantity per
Reel
FAN3111CSX
CMOS
5-Pin SOT23
Tape & Reel
3,000
FAN3111ESX
External
5-Pin SOT23
Tape & Reel
3,000
Thermal Characteristics(1)
Package
JL(2)
JT(3)
JA(4)
JB(5)
JT(6)
Units
5-Pin SOT23
58
102
161
53
6
°C/W
Notes:
1. Estimates derived from thermal simulation; actual values depend on the application.
2. Theta_JL (JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads
(including any thermal pad) that are typically soldered to a PCB.
3. Theta_JT (JT): Thermal resistance between the semiconductor junction and the top surface of the package,
assuming it is held at a uniform temperature by a top-side heatsink.
4. Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking,
and airflow. The value given is for natural convection with no heatsink using a 2S2P board,, as specified in
JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate.
5. Psi_JB (JB): Thermal characterization parameter providing correlation between semiconductor junction
temperature and an application circuit board reference point for the thermal environment defined in Note 4. For
the MLP-8 package, the board reference is defined as the PCB copper connected to the thermal pad and
protruding from either end of the package. For the SOIC-8 package, the board reference is defined as the PCB
copper adjacent to pin 6.
6. Psi_JT (JT): Thermal characterization parameter providing correlation between the semiconductor junction
temperature and the center of the top of the package for the thermal environment defined in Note 4.
Pin Definitions
Pin #
Name
Description
1
VDD
Supply Voltage. Provides power to the IC.
2
GND
Ground. Common ground reference for input and output circuits.
3
IN+
Non-Inverting Input. Connect to VDD to enable output.
4
IN–
FAN3111C Inverting Input. Connect to GND to enable output.
XREF
FAN3111E External Reference Voltage. Reference for input thresholds, 2 V to 5 V.
5
OUT
Gate Drive Output. Held low unless required inputs are present.
Output Logic with Dual-Input Configuration
IN+
IN−
OUT
0(7)
0
0
0(7)
1(7)
0
1
0
1
1
1(7)
0
Note:
7. Default input signal if no external connection is made.
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3111 • Rev. 1.6 3
FAN3111 — Single 1A High-Speed, Low-Side Gate Driver
Block Diagrams
1VDD
5OUT
2GND
IN+ 3
4
VDD 100kΩ
100kΩ
100kΩ
IN-
Figure 3. FAN3111C Simplified Block Diagram
1VDD
5OUT
2GND
IN+ 3
4
100k
100k
XREF
Figure 4. FAN3111E Simplified Block Diagram
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3111 • Rev. 1.6 4
FAN3111 — Single 1A High-Speed, Low-Side Gate Driver
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VDD
VDD to GND
-0.3
20.0
V
VIN
Voltage on IN to GND
FAN3111C
-0.3
VDD + 0.3
V
FAN3111E
-0.3
VXREF+0.3
V
VXREF
Voltage on XREF to GND
FAN3111E
-0.3
5.5
V
VOUT
Voltage on OUT to GND
-0.3
VDD+0.3
V
TL
Lead Soldering Temperature (10 Seconds)
+260
ºC
TJ
Junction Temperature
+150
ºC
TSTG
Storage Temperature
-65
+150
ºC
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Unit
VDD
Supply Voltage Range
4.5
18.0
V
VIN
Input Voltage IN
FAN3111C
0
VDD
V
FAN3111E
0
VXREF
V
VXREF
External Reference Voltage XREF
FAN3111E
2.0
5.0
V
TA
Operating Ambient Temperature
-40
+125
ºC
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3111 • Rev. 1.6 5
FAN3111 — Single 1A High-Speed, Low-Side Gate Driver
Electrical Characteristics
Unless otherwise noted, VDD = 12 V, VXREF = 3.3 V, TJ = -40°C to +125°C. Currents are defined as positive into the
device and negative out of the device.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Supply
VDD
Operating Range
4.5
18.0
V
IDD
Static Supply Current
Inputs Not Connected
5
10
µA
Inputs (FAN3111C)
VIL_C
IN Logic, Low-Voltage Threshold
30
38
%VDD
VIH_C
IN Logic, High-Voltage Threshold
55
70
%VDD
IINL
IN Current, Low
IN from 0 to VDD
-1
175
µA
IINH
IN Current, High
IN from 0 to VDD
-175
1
µA
VHYS_C
Input Hysteresis Voltage
17
%VDD
Inputs (FAN3111E)
VIL_E
IN Logic, Low-Voltage Threshold
25
30
%VXREF
VIH_E
IN Logic, High-Voltage Threshold
50
60
%VXREF
IINL
IN Current, Low
IN from 0 to VXREF
-1
50
µA
IINH
IN Current, High
IN from 0 to VXREF
-50
1
µA
VHYS_E
Input Hysteresis Voltage
20
%VXREF
Output
ISINK
OUT Current, Mid-Voltage, Sinking(8)
OUT at VDD/2,
CLOAD = 47nF, f = 1KHz
1.1
A
ISOURCE
OUT Current, Mid-Voltage, Sourcing(8)
OUT at VDD/2,
CLOAD = 47nF, f = 1KHz
-0.9
A
IPK_SINK
OUT Current, Peak, Sinking(8)
CLOAD = 47nF, f = 1KHz
1.4
A
IPK_SOURCE
OUT Current, Peak, Sourcing(8)
CLOAD = 47nF, f = 1KHz
-1.4
A
tRISE
Output Rise Time(9)
CLOAD = 470pF
9
18
ns
tFALL
Output Fall Time(9)
CLOAD = 470pF
8
17
ns
tD1, tD2
Output Prop. Delay(9)
FAN3111C: 0 - 12VIN,
1V/ns Slew Rate
15
30
ns
FAN3111E: 0 - 3.3VIN,
1V/ns Slew Rate
IRVS
Output Reverse Current Withstand(8)
250
mA
Notes:
8. Not tested in production.
9. See Timing diagrams.
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3111 • Rev. 1.6 6
FAN3111 — Single 1A High-Speed, Low-Side Gate Driver
Timing Diagrams
90%
10%
Output
IN+
tD1 tD2
tRISE tFALL
VINL
VINH
90%
10%
Output
tD1 tD2
tFALL tRISE
VINL
VINH
IN -
Figure 5. Non-Inverting Waveforms
Figure 6. Inverting Waveforms
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3111 • Rev. 1.6 7
FAN3111 — Single 1A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
Typical characteristics are provided at 25°C, VDD = 12 V, and VXREF = 3.3 V unless otherwise noted.
0.0
0.5
1.0
1.5
2.0
2.5
4 6 8 10 12 14 16 18
Supply Voltage (V)
IDD (μA)
FAN3111C
Inputs Floating, OutputLow
0.0
0.5
1.0
1.5
2.0
2.5
4 6 8 10 12 14 16 18
Supply Voltage (V)
IDD (μA)
FAN3111E
Inputs Floating, OutputLow
Figure 7. IDD (Static) vs. Supply Voltage
Figure 8. IDD (Static) vs. Supply Voltage
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
02004006008001000
Switching Frequency (kHz)
IDD (mA)
FAN3111C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
02004006008001000
Switching Frequency (kHz)
IDD (mA)
VDD =15V
VDD =12V
VDD = 8V
V
VDD = 4.5V
FAN3111C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
02004006008001000
Switching Frequency (kHz)
IDD (mA)
FAN3111E
VDD =15V
VDD =12V
VDD = 8V
VDD = 4.5V
Figure 9. IDD (No-Load) vs. Frequency
Figure 10. IDD (No-Load) vs. Frequency
0
1
2
3
4
5
6
7
8
9
02004006008001000
Switching Frequency (kHz)
IDD (mA)
FAN3111C
VDD =15V
VDD =12V
VDD = 8V
VDD = 4.5V
0
1
2
3
4
5
6
7
8
9
02004006008001000
Switching Frequency (kHz)
IDD (mA)
FAN3111E
VDD =15 V
VDD =12 V
VDD = 8 V
VDD = 4.5 V
Figure 11. IDD (470pF Load) vs. Frequency
Figure 12. IDD (470pF Load) vs. Frequency
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3111 • Rev. 1.6 8
FAN3111 — Single 1A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
Typical characteristics are provided at 25°C, VDD = 12 V, and VXREF = 3.3 V unless otherwise noted.
0
1
2
3
-50 -25 0 25 50 75 100125
Temperature (°C)
IDD (μA)
FAN3111C
Inputs Floating, OutputLow
0
1
2
3
-50 -25 0 25 50 75 100125
Temperature (°C)
IDD (μA)
FAN3111E
Inputs Floating, OutputLow
Figure 13. IDD (Static) vs. Temperature
Figure 14. IDD (Static) vs. Temperature
0
1
2
3
4
5
6
7
8
9
10
4 6 8 10 12 14 16 18
Supply Voltage (V)
InputThresholds (V)
FAN3111C
VIL
VIH
0.5
1.0
1.5
2.0
2.5
2.5 3.0 3.5 4.0 4.5 5.0
XREF (V)
InputThresholds (V)
FAN3111E
VIH
VIL
Figure 15. Input Thresholds vs. Supply Voltage
Figure 16. Input Threshold vs. XREF Voltage
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
4 6 8 10 12 14 16 18
Supply Voltage (V)
InputThresholds (% of V DD)
FAN3111C
VIL
VIH
4.0
4.5
5.0
5.5
6.0
6.5
7.0
-50 -25 0 25 50 75 100125
Temperature (°C)
InputThresholds (V)
FAN3111C
VIL
VIH
Figure 17. Input Thresholds % vs. Supply Voltage
Figure 18. Input Threshold vs. Temperature
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3111 • Rev. 1.6 9
FAN3111 — Single 1A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
Typical characteristics are provided at 25°C, VDD = 12 V, and VXREF = 3.3 V unless otherwise noted.
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-50 -25 0 25 50 75 100125
Temperature (°C)
InputThresholds (V)
FAN3111E
VIL
VIH
0
10
20
30
40
50
60
70
4 6 8 10 12 14 16 18
Supply Voltage (V)
Propagation Delays (ns)
IN rise to OUT fall
IN fall to OUT
FAN3111C Inverting Input
Figure 19. Input Threshold vs. Temperature
Figure 20. Propagation Delay vs. Supply Voltage
0
10
20
30
40
50
60
70
80
4 6 8 10 12 14 16 18
Supply Voltage (V)
Propagation Delays (ns)
FAN3111C Non-Inverting Input
IN Fall to OUT Fall
IN Rise to OUT Rise
0
10
20
30
40
50
60
70
80
90
4 6 8 10 12 14 16 18
Supply Voltage (V)
Propagation Delays (ns)
FAN3111E
IN Fall to OUT Fall
IN Rise to OUT Rise
Figure 21. Propagation Delay vs. Supply Voltage
Figure 22. Propagation Delay vs. Supply Voltage
10
12
14
16
18
20
22
24
-50 -25 0 25 50 75 100125
Temperature (°C)
Propagation Delays (ns)
INFall to OUT Fall
INRise to OUT Rise
FAN3111C Non-Inverting Input
8
10
12
14
16
18
20
-50 -25 0 25 50 75 100125
Temperature (°C)
Propagation Delays (ns)
INFall to OUT Fall
INRise to OUT Rise
FAN3111E
Figure 23. Propagation Delay vs. Temperature
Figure 24. Propagation Delays vs. Temperature
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3111 • Rev. 1.6 10
FAN3111 — Single 1A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
Typical characteristics are provided at 25°C, VDD = 12 V, and VXREF = 3.3 V unless otherwise noted.
10
12
14
16
18
20
22
-50 -25 0 25 50 75 100125
Temperature (°C)
Propagation Delays (ns)
INRise to OUT Fall
INFall to OUT Rise
FAN3111C Inverting Input
0
20
40
60
80
100
120
0 5 10 15 20
Supply Voltage (V)
Fall Time (ns)
CL=4.7nF
CL=2.2nF
CL=1.0nF
CL=470pF
Figure 25. Propagation Delays vs. Temperature
Figure 26. Fall Time vs. Supply Voltage
0
20
40
60
80
100
120
140
0 5 10 15 20
Supply Voltage (V)
Rise Time (ns)
CL=4.7nF
CL=2.2nF
CL=1.0nF
CL=470pF
7
8
9
10
11
12
-50 -25 0 25 50 75 100125
Temperature (°C)
Rise and Fall Times (ns)
Rise Time
Fall Time
CL=470pF
Figure 27. Rise Time vs. Supply Voltage
Figure 28. Rise and Fall Time vs. Temperature
t = 20ns/div
tFALL = 8 ns
tRISE = 9 ns
VIN (5V/div)
(CMOS Input)
VDD = 12V
CL = 470 pF
VOUT (5V/div)
t = 100ns / div
IOUT (0.5A /div)
VIN (2V/div)
(3.3V Input)
VOUT (5V / div)
CLOAD = 47 nF
Figure 29. Rise and Fall Waveforms (470pF)
Figure 30. Quasi-Static Source Current (VDD=12V)
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3111 • Rev. 1.6 11
FAN3111 — Single 1A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
Typical characteristics are provided at 25°C, VDD = 12 V, and VXREF = 3.3 V unless otherwise noted.
t = 100ns / div
IOUT (0.5A /div)
VIN (2V/div)
(3.3V Input)
VOUT (5V / div)
CLOAD = 47 nF
t = 100ns / div
IOUT (0.5A /div)
VIN (2V/div)
(3.3V Input)
VOUT (5V / div)
CLOAD = 47 nF
Figure 31. Quasi-Static Sink Current (VDD=12V)
Figure 32. Quasi-Static Source Current (VDD=8V)
t = 100ns / div
IOUT (0.5A /div)
VIN (2V/div)
(3.3V Input)
VOUT (5V / div)
CLOAD = 47 nF
470µF
Al. El.
VDD
VOUT
1µF
Ceramic
4.7µF
Ceramic
CLOAD
47nF
IOUT
IN
1kHz
Current Probe
LECROY AP015
FAN3111
Figure 33. Quasi-Static Sink Current (VDD=8V)
Figure 34. Quasi-Static IOUT / VOUT Test Circuit
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3111 • Rev. 1.6 12
FAN3111 — Single 1A High-Speed, Low-Side Gate Driver
Applications Information
The FAN3111 offers CMOS- or logic-level-compatible
input thresholds. In the FAN3111C, the logic input
thresholds are dependent on the VDD level and, with VDD
of 12 V, the logic rising-edge threshold is approximately
55% of VDD and the input falling-edge threshold is
approximately 38% of VDD. The CMOS input
configuration offers a hysteresis voltage of
approximately 17% of VDD. The CMOS inputs can be
used with relatively slow edges (approaching DC) if
good decoupling and bypas s techniques are
incorporated in the system design to prevent noise from
violating the input-voltage hysteresis window. This
allows setting precise timing intervals by fitting an R-C
circuit between the controlling signal and the IN pin of
the driver. The slow rising edge at the IN pin of the
driver introduces a delay between the controlling signal
and the OUT pin of the driver.
In the FAN3111E, the input thresholds are dependent
on the VXREF voltage that typically is chosen between 2V
and 5 V. This range of VXREF allows compatibility with
TTL and other logic levels up to 5 V by connecting the
XREF pin to the same source as the logic circuit that
drives the FAN3111E input stage. The logic rising edge
threshold is approximately 50% of VXREF and the input
falling-edge threshold is approximately 30% of VXREF.
The TTL-like input configuration offers a hysteresis
voltage of approximately 20% of VXREF.
Startup Operation
The FAN3111 internal logic is optimized to drive ground
referenced N-channel MOSFETs as VDD supply voltage
rises during startup operation. As VDD rises from 0V to
approximately 2 V, the OUT pin is held LOW by an
internal resistor, regardless of the state of the input
pins. When the internal circuitry becomes active at
approximately 2 V, the output assumes the state
commanded by the inputs.
Figure 35 illustrates FAN3111C startup operation with
VDD increasing from 0 to 12 V, with the output
commanded to the low level (IN+ and IN- tied to
ground). Note that OUT is held LOW to maintain an N-
channel MOSFET in the OFF state.
OUT @ 5 V/Div
VDD @ 5 V/Div
t = 200 us/Div
VDD
OUT
FAN3111C
Figure 35. FAN3111C Startup Operation
Figure 36 illustrates startup operation as VDD increases
from 0 to 12 V with the output commanded to the high
level (IN+ tied to VDD, IN- tied to GND). This
configuration might not be suitable for driving high-side
P-channel MOSFETs because the low output voltage of
the driver would attempt to turn the P-channel MOSFET
on with low VDD levels.
OUT @ 5 V/Div
VDD @ 5 V/Div
VDD
OUT
FAN3111C
t = 200 us/Div
Figure 36. Startup Operation as VDD Increases
Figure 37 illustrates FAN3111E startup operation with the
output commanded to the low level (IN+ tied to ground)
and the voltage on XREF ramped from 0 to 3.3 V.
t = 50 us/Div
OUT @ 2 V/Div
VXREF @ 2 V/Div
VDD @ 5 V/Div
VDD
OUT
FAN3111E
XREF
Figure 37. FAN3111E Startup Operation
MillerDrive™ Gate Drive Technology
FAN3111 drivers incorporate the MillerDrive
architecture shown in Figure 38 for the output stage, a
combination of bipolar and MOS devices capable of
providing large currents over a wide range of supply-
voltage and temperature variations. The bipolar devices
carry the bulk of the current as OUT swings between
1/3 to 2/3 VDD and the MOS devices pull the output to
the high or low rail.
The purpose of the MillerDrive architecture is to speed
up switching by providing the highest current during the
Miller plateau region when the gate-drain capacitance of
the MOSFET is being charged or discharged as part of
the turn-on / turn-off process. For applications with zero
voltage switching during the MOSFET turn-on or turn-off
interval, the driver supplies high peak current for fast
switching even though the Miller plateau is not present.
This situation often occurs in synchronous rectifier
applications because the body diode is generally
conducting before the MOSFET is switched on.
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3111 • Rev. 1.6 13
FAN3111 — Single 1A High-Speed, Low-Side Gate Driver
The output-pin slew rate is determined by VDD voltage
and the load on the output. It is not user adjustable, but
if a slower rise or fall time at the MOSFET gate is
needed, a series resistor can be added.
Input
stage
VDD
VOUT
Figure 38. MillerDrive™ Output Architecture
VDD Bypass Capacitor Guidelines
To enable this IC to turn a power device on quickly, a
local, high-frequency, bypass capacitor CBYP with low
ESR and ESL should be connected between the VDD
and GND pins with minimal trace length. This capacitor
is in addition to bulk electrolytic capacitance of 10 µF to
47 µF often found on driver and controller bias circuits.
A typical criterion for choosing the value of CBYP is to
keep the ripple voltage on the VDD supply ≤5%. Often
this is achieved with a value ≥ 20 times the equivalent
load capacitance CEQV, defined here as Qgate/VDD.
Ceramic capacitors of 0.1 µF to 1 µF or larger are
common choices, as are dielectrics, such as X5R and
X7R, which have good temperature characteristics and
high pulse current capability.
If circuit noise affects normal operation, the value of
CBYP may be increased to 50-100 times the CEQV or
CBYP may be split into two capacitors. One should be a
larger value, based on equivalent load capacitance, and
the other a smaller value, such as 1-10 nF, mounted
closest to the VDD and GND pins to carry the higher-
frequency components of the current pulses.
Layout and Connection Guidelines
The FAN3111 incorporates fast reacting input circuits,
short propagation delays, and output stages capable of
delivering current peaks over 1 A to facilitate voltage
transition times from under 10 ns to over 100 ns. The
following layout and connection guidelines are strongly
recommended:
Keep high-current output and power ground paths
separate from logic input signals and signal ground
paths. This is especially critical when dealing with
TTL-level logic thresholds.
Keep the driver as close to the load as possible to
minimize the length of high-current traces. This
reduces the series inductance to improve high-
speed switching, while reducing the loop area that
can radiate EMI to the driver inputs and other
surrounding circuitry.
Many high-speed power circuits can be susceptible
to noise injected from their own output or other
external sources, possibly causing output re-
triggering. These effects can be especially obvious
if the circuit is tested in breadboard or non-optimal
circuit layouts with long input, enable, or output
leads. For best results, make connections to all
pins as short and direct as possible.
The turn-on and turn-off current paths should be
minimized as discussed in the following sections.
Figure 39 shows the pulsed gate-drive current path
when the gate driver is supplying gate charge to turn
the MOSFET on. The current is supplied from the local
bypass capacitor, CBYP, and flows through the driver to
the MOSFET gate and to ground. To reach the high
peak currents possible, the resistance and inductance
in the path should be minimized. The localized CBYP
acts to contain the high peak-current pulses within this
driver-MOSFET circuit, preventing them from disturbing
the sensitive analog circuitry in the PWM controller.
PWM
VDS
VDD
CBYP
FAN3111
Figure 39. Current Path for MOSFET Turn-On
Figure 40 shows the current path when the gate driver
turns the MOSFET off. Ideally, the driver shunts the
current directly to the source of the MOSFET in a small
circuit loop. For fast turn-off times, the resistance and
inductance in this path should be minimized.
PWM
VDS
VDD
CBYP FAN3111
Figure 40. Current Path for MOSFET Turn-Off
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3111 • Rev. 1.6 14
FAN3111 — Single 1A High-Speed, Low-Side Gate Driver
Truth Table of Logic Operation
The FAN3111 truth table indicates the operational
states using the dual-input configuration. In a non-
inverting driver configuration, the IN- pin should be a
logic low signal. If the IN- pin is connected to logic high,
a disable function is realized, and the driver output
remains low regardless of the state of the IN+ pin.
Table 1. FAN3111 Truth Table
IN+
IN-
OUT
0
0
0
0
1
0
1
0
1
1
1
0
In the non-inverting driver configuration in Figure 41,
the IN- pin is tied to ground and the input signal (PWM)
is applied to the IN+ pin. The IN- pin can be connected
to logic high to disable the driver and the output
remains low, regardless of the state of the IN+ pin.
VDD
GND
IN-
IN+ OUT
PWM FAN3111
Figure 41. Dual-Input Driver Enabled, Non-
Inverting Configuration
In the inverting driver application shown in Figure 42, the
IN+ pin is tied high. Pulling the IN+ pin to GND forces the
output low, regardless of the state of the IN- pin.
VDD
GND
IN-
IN+ OUT
PWM FAN3111
Figure 42. Dual-Input Driver Enabled, Inverting
Configuration
Thermal Guidelines
Gate drivers used to switch MOSFETs and IGBTs at
high frequencies can dissipate significant amounts of
power. It is important to determine the driver power
dissipation and the resulting junction temperature in the
application to ensure that the part is operating within
acceptable temperature limits.
The total power dissipation in a gate driver is the sum of
three components; PGATE, PQUIESCENT, and PDYNAMIC:
Dynamicgatetotal P P P
(1)
Gate Driving Loss: The most significant power loss
results from supplying gate current (charge per unit
time) to switch the load MOSFET on and off at the
switching frequency. The power dissipation that results
from driving a MOSFET at a specified gate-source
voltage, VGS, with gate charge, QG, at switching
frequency, fSW, is determined by:
swGSGGATE f V Q P
(2)
Dynamic Pre-drive / Shoot-through Current: A power loss
resulting from internal current consumption under
dynamic operating conditions, including pin pull-up /
pull-down resistors, can be obtained using the graphs in
Figure 11 and Figure 12 in Typical Performance
Characteristics to determine the current IDYNAMIC drawn
from VDD under actual operating conditions:
DDDYNAMICDYNAMIC V I P
(3)
Once the power dissipated in the driver is determined,
the driver junction temperature rise with respect to the
device lead can be evaluated using thermal equation:
CJLTOTALJ T P T
(4)
where:
TJ = driver junction temperature;
θJL = thermal resistance from junction to lead; and
TL = lead temperature of device in application.
The power dissipated in a gate-drive circuit is
independent of the drive-circuit resistance and is split
proportionately among the resistances present in the
driver, any discrete series resistor present, and the gate
resistance internal to the power switching MOSFET.
Power dissipated in the driver may be estimated using
the following equation:
FETGATE,EXTDRIVEROUT,
DriverOUT,
TOTALPKG RRR R
PP
(5)
where:
PPKG = power dissipated in the driver package;
ROUT,DRIVER = estimated driver impedance derived from
IOUT vs. VOUT waveforms;
REXT = external series resistance connected between
the driver output and the gate of the MOSFET; and
RGATE,FET = resistance internal to the load MOSFET gate
and source connections.
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3111 • Rev. 1.6 15
FAN3111 — Single 1A High-Speed, Low-Side Gate Driver
Typical Application Diagrams
Logic
PWM
33W
33W
Downstream
Converters
Rectified
AC Input
FAN3111
FAN3111
VDD
VDD
Q1B
Q1A
Figure 43. PFC Boost Circuit Utilizing Distributed Drivers for Parallel Power Switches Q1A and Q1B
VIN
PWM
VDD
FAN3111
Figure 44. Driver for Forward Converter Low-Side Switch
VIN
Q2
VSEC
D1
D2
Q1
T1
VDD
CC
PWM 0.1µF
T2
FAN3111
Figure 45. Driver for Two-Transistor, Forward-Converter Gate Transformer
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3111 • Rev. 1.6 16
FAN3111 — Single 1A High-Speed, Low-Side Gate Driver
Table 2. Related Products
Part
Number
Type
Gate
Drive(10)
(Sink/Src)
Input
Threshold
Logic
Package
FAN3111C
Single 1A
+1.1 A /-0.9 A
CMOS
Single Channel of Dual-Input/Single-Output
SOT23-5
FAN3111E
Single 1A
+1.1 A /-0.9 A
External(11)
Single Non-Inverting Channel with External
Reference
SOT23-5
FAN3100C
Single 2A
+2.5A / -1.8A
CMOS
Single Channel of Two-Input/One-Output
SOT23-5, MLP6
FAN3100T
Single 2A
+2.5A / -1.8A
TTL
Single Channel of Two-Input/One-Output
SOT23-5, MLP6
FAN3226C
Dual 2A
+2.4A / -1.6A
CMOS
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3226T
Dual 2A
+2.4A / -1.6A
TTL
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3227C
Dual 2A
+2.4A / -1.6A
CMOS
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3227T
Dual 2A
+2.4A / -1.6A
TTL
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3228C
Dual 2A
+2.4A / -1.6A
CMOS
Dual Channels of Two-Input/One-Output, Pin Config.1
SOIC8, MLP8
FAN3228T
Dual 2A
+2.4A / -1.6A
TTL
Dual Channels of Two-Input/One-Output, Pin Config.1
SOIC8, MLP8
FAN3229C
Dual 2A
+2.4A / -1.6A
CMOS
Dual Channels of Two-Input/One-Output, Pin Config.2
SOIC8, MLP8
FAN3229T
Dual 2A
+2.4A / -1.6A
TTL
Dual Channels of Two-Input/One-Output, Pin Config.2
SOIC8, MLP8
FAN3268T
Dual 2A
+2.4A / -1.6A
TTL
18V Half-Bridge Driver: Non-Inverting Channel (NMOS)
and Inverting Channel (PMOS) + Dual Enables
SOIC8
FAN3223C
Dual 4A
+4.3A / -2.8A
CMOS
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3223T
Dual 4A
+4.3A / -2.8A
TTL
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3224C
Dual 4A
+4.3A / -2.8A
CMOS
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3224T
Dual 4A
+4.3A / -2.8A
TTL
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3225C
Dual 4A
+4.3A / -2.8A
CMOS
Dual Channels of Two-Input/One-Output
SOIC8, MLP8
FAN3225T
Dual 4A
+4.3A / -2.8A
TTL
Dual Channels of Two-Input/One-Output
SOIC8, MLP8
FAN3121C
Single 9A
+9.7A / -7.1A
CMOS
Single Inverting Channel + Enable
SOIC8, MLP8
FAN3121T
Single 9A
+9.7A / -7.1A
TTL
Single Inverting Channel + Enable
SOIC8, MLP8
FAN3122T
Single 9A
+9.7A / -7.1A
CMOS
Single Non-Inverting Channel + Enable
SOIC8, MLP8
FAN3122C
Single 9A
+9.7A / -7.1A
TTL
Single Non-Inverting Channel + Enable
SOIC8, MLP8
Notes:
10. Typical currents with OUT at 6V and VDD = 12V.
11. Thresholds proportional to an externally supplied reference voltage.
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