Control IC for Switched-Mode Power Supplies using MOS-Transistors TDA 4605 Bipolar IC Features Fold-back characteristic provides overload protection for external components Burst operation under short-circuit conditions Loop error protection Switch-off if line voltage is too low (undervoltage switch-off) Line voltage compensation of overload point Soft-start for quiet start-up Chip-over temperature protection (thermal shutdown) On-chip parasitic transformer oscillation suppression circuitry P-DIP-8-1 Type Ordering Code Package TDA 4605 Q67000-A8078 P-DIP-8-1 The IC TDA 4605-1 controls the MOS-power transistor and performs all necessary regulation and monitoring functions in free running flyback converters. Since good load regulation over a wide load range is attained, this IC is applicable tor consumer and industrial power supplies. The serial circuit of power transistor and primary winding of the flyback transformer is connected to the input voltage. During the switch - on period of the transistor, energy is stored in the transformer and during the switch - off period it is fed to the load via the secondary winding. By varying switchon time of the power transistor, the IC controls each portion of energy transferred to the secondary side such that the output voltage remains nearly independent ot load variations. The required control information is taken from the input voltage during the switch-on period and from a regulation winding during the switch-off period. Semiconductor Group 33 06.94 TDA 4605 In the different load ranges the switched-mode power supply (SMPS) behaves as follow: No load operation: The power supply unit oscillates at its resonant frequency typ. 100 kHz to 200 kHz. Depending upon the transformator windings the output voltage can be slightly above nominal value. Nominal operation: The switching frequency declines with increasing load and decreasing AC-voltage. The duty factor primarly depends on the AC-voltage. The output voltage is load-dependent only. Overload point: Maximal output power is available at this point ot the output characteristic. Overload: The energy transferred per operation cycle is limited at the top. Therefore the output voltage declines by secondary overloading. Semiconductor Group 34 TDA 4605 Pin Definitions and Functions Pin No. Function 1 Regulating Voltage: Information input concerning secondary voltage. By comparing the regulating voltage - obtained from the regulating winding ot the transformer - with the internal reference voltage, the output impulse width on pin 5 is adapted to the load ot the secondary side (normal, overload, short-circuit, no load). 2 Primary Current Simulation: Information input regarding the primary current. The primary current rise in the primary winding is simulated at pin 2 as a voltage rise by means ot external RC-element. When a value is reached that is derived from the regulating voltage at pin 1, the output impulse at pin 5 is terminated. The RC-element serves to set the maximum power at the overload point set. 3 Input for Primary Voltage Monitoring: In the normal operation V3 is moving between the thresholds V3H and V3L (V3H > V3 > V3L). V3 < V3L: SMPS is switched OFF (line voltage too low). V3 > V3H : Compensation of the overload point regulation (controlled by pin 2) starts at V3H : V3L = 1.7. 4 Ground 5 Output: Push-pull-output provides 1 A for rapid charge and discharge of the gate capacitance ot the power MOS-transistor. 6 Supply Voltage Input: A stable internal reference voltage VREF is derived from the supply voltage also the switching thresholds V6A , V6E , V6 max and V6 min for the supply voltage detector. If V6 > V6E then VREF is switched on and swiched off when V6 < V6A . In addition the logic is only enable for V6 min < V6 < V6 max. 7 Soft-Start: Input for soft-start. Start-up will begin with short pulses by connecting a capacitor from pin 7 to ground. 8 Zero Detector: Input tor the oscillation feedback. After starting oscillation, every zero transit of the feedback voltage (falling edge) triggers an output impulse at pin 5. The trigger threshold is at + 50 mV typical. Semiconductor Group 35 TDA 4605 Block Diagram Semiconductor Group 36 TDA 4605 Circuit Description Application Circuit Application circuit shows a flyback converter for video recorders with a power rating of 50 W. The circuit is designed as a wide-range power supply tor AC-line voltages ot 90 to 270 V. The AC-input voltage is rectified by bridge rectifier GR1 and smoothed by C1 . The NTC limits the rush in current. In the period before the switch-on threshold is reached the IC is supplied via resistor R 1 ; during the start-up phase it uses the energy stored in C2 , under steady-state conditions the IC receives its supply voltage from transformer winding n1 via diode D1. The switching transistor T1 is a BUZ 90. The parallel-connected capacitor C3 and the inductance ot primary winding 112 determine the system resonance frequency. The R 2 - C4 - D2 circuitry limits overshoot peaks, and R 3 protects the gate of T1 against static charges. While T1 conducts, the current rise in the primary winding depends on the winding's inductance and the VC1 voltage. A voltage reproduction ot the current rise is tabbed using the R4 - C5 network and forwarded into pin 2 ot the IC. The RC-time constant ot R 4 , R 5 must be dimensioned correctly in order to prevent driving the transformer core into saturation. The R 10/R 11 divider ratio provides the line voltage threshold controlling the undervoltage control circuit in the IC. The voltage present at pin 3 also determines the overload. Detection of overload together with the current characteristic at pin 2 controls the on period ot T1. This keeps the cut-off point stable even with higher AC-line voltages. Regulation of the switched-mode power supply is via pin 1. The control voltage of winding n1 during the off-period of T1 is rectified by D3, smoothed by C6 and stepped down at an adjustable ratio by R 5 , R 6 and R 7 . The R 6 - C7 network suppresses parasitic overshoots (transformer oscillation). The peak voltage at pin 2, and thus the primary peak current, is adjusted by the IC so that the voltage applied across the control winding, and hence the output voltages, are at the desired level. When the transformer has supplied its energy to the load, the control voltage passes through zero. The IC detects the zero crossing via series resistors R 9 connected to pin 8. But zero crossings are also produced by transformer oscillation after T1 has turned off if output is short-circuited. Therefore the IC ignores zero crossings occurring within a specitied period of time after T1 turn-off. The capacitor C8 connected to pin 7 causes the power supply to be started with shorter pulses to keep the operating ftrequency outside the audible range during start-up. On the secondary side, tive output voltages are produced across winding n3 to n7 rectified by D4 to D8 and smoothed by C9 to C13 . Resistors R 12 , R 14 and R 19 to R 21 are used as bleeder resistors. Fusable resistors R 15 to R 18 protect the rectifiers against short circuits in the output circuits, which are designed to supply only small loads. Semiconductor Group 37 TDA 4605 Block Diagram Pin 1 The regulating voltage forwarded to this pin is compared with a stable internal reference voltage VR in the regulating and overload amplifier. The output of this stage is ted to the stop comparator. Pin 2 A voltage proportional to the drain current ot the switching transistor is generated there by the external RC-combination in conjunction with the primary current transducer. The output of this transducer is controlled by the logic and referenced to the internal stable voltage V2B . If the voltage V2 exceeds the output voltage of the regulating amplifier, the logic is reset by the stop comparator and consequently the output ot pin 5 is switched to low potential. Further inputs tor the logic stage are the output for the start impulse generator with the stable reference potential VST and the supply voltage monitor. Pin 3 The down-divide primary voltage applied there stabilizes the overload point. In addition the logic is disabled in the event of low voltage by comparison with the internal stable voltage VV in the primary voltage monitor block. Pin 4 Ground Pin 5 In the output stage the output signals produced by the logic are shifted to a leved suitable for MOSpower transistors. Pin 6 From the supply voltage V6 are derived a stable internal reference VREF and the switching threshold V6A , V6E , V6 max and V6 min for the supply voltage monitor. All reference values (VR , V2B , VST) are derived from VREF . If V6 > VVE the VREF is switched on and switched off when V6 < V6A . In addition, the logic is released only for V6 min < V6 < V6 max . Pin 7 The output of the overload amplifier is connected to pin 7. A load on this output causes a reduction in maximal impulse duration. This function can be used to implement a soft start, when pin 7 is connected to ground by a capacitor. Semiconductor Group 38 TDA 4605 Pin 8 The zero detector controlling the logic block recognizes the transformer being discharged by positive to negative zero crossing of pin 8 voltage and enables the logic for a new pulse. Parasitic oscillations occurring at the end of a pulse cannot lead to a new pulse (double-pulsing), because an internal circuit inhibits the zero detector for a finite time tUL after the end of each pulse. Start-Up Behaviour The start-up behaviour of the application circuit per sheet 48 is represented on sheet 50 for a line voltage barely above the lower acceptable limit voltage value (without soft-start). After applying the line voltage at the time t0 to the tollowing voltages built up: - V6 corresponding to the half-wave charge current over R 1 - V2 to V2 max (typically 6.6 V) - V3 to the value determined by the divider R 10/R 11 . The current drawn by the IC in this case is less than 1.6 mA. If V6 reaches the threshold V6E (time point t1), the IC switches on the internal reference voltage. The currentdraw max. rises to 12 mA. The primary current- voltage reproducer regulates V2 down to V2E and the starting impulse generator generates the starting impulses from time point t5 to t6 . The feedback to pin 8 starts the next impulse and so on. All impulses including the starting impulse are controlled in width by regulating voltage of pin 1. When switching on this corresponds to a short-circuit event, i.e. V1 = 0. Hence the IC starts up with "short-circuit impulses" to assume a width depending on the regulating voltage feedback (the IC operates in the overload range). The maximum pulse width is reached at time point t2 (V2 = V2 max). The IC operates at the overload point. Thereafter the peak values ot V2 decrease rapidly, as the IC is operating within the regulation range. The regulating loop has built up. If voltage V6 falls below the switch-off threshold V6 min before the reversal point is reached, the starting attempt is aborted (pin 5 is switched to low). As the IC remains switched on, V6 further decreases to V6 . The IC switches off; V6 can rise again (time point 14) and a new start-up attempt begins at time point t1 . If the rectified alternating line voltage (primary voltage) collapses during load, V3 can fall below V3A , as is happening at time point t3 (switch-on attempt when voltage is too low). The primary voltage monitor then clamps V3 to V3S until the IC switches off (V6 < V6A). Then a new start-up attempt begins at time point t1 . Semiconductor Group 39 TDA 4605 Regulation, Overload and No-Load Behaviour When the IC has started up, it is operating in the regulation range. The potential at pin 1 typically is 400 mV. If the output is loaded, the regulation amplifier allows broader impulses (V5 = H). The peak voltage value at pin 2 increases up to V2S max . If the secondary load is further increased, the overload amplifier begins to regulate the pulse width downward. This point is referred to as the overload point of the power supply. As the IC supply voltage V6 is directly proportional to the secondary voltage, it goes down in accordance with the overload regulation behaviour. If V6 falls below the value V6 min , the IC goes into burst operation. As the time constant of the half-wave charge-up is relatively large, the short-circuit power remains small. The overload amplifier cuts back to the pulse width tpk . This pulse width must remain possible, in order to permit the IC to start-up without problems from the virtual short circuit, which every switching on with V1 = 0 represents. If the secondary side is unloaded, the loading impulses (V5 = H) become shorter. The frequency increases up to the resonance frequency of the system. If the load is further reduced, the secondary voltages and V6 increase. When V6 = V6 max , the logic is blocked. The IC converts to burst operation. This renders the circuit absolutely safe under no-load conditions. Behaviour when Temperature Exceeds Limit An integrated temperature protection disables the logic when the chip temperature becomes too high. The IC automatically interrogates the temperature and starts as soon as the temperature decreases to permissible values. Semiconductor Group 40 TDA 4605 Absolute Maximum Ratings TA = 25 C Parameter Voltages Currents Symbol pin 1 pin 2 pin 3 pin 5 pin 6 pin 7 V1 V2 V3 V5 V6 V7 pin 1 pin 2 pin 3 pin 4 pin 5 pin 6 pin 7 pin 8 V1 V2 V3 V4 V5 V6 V7 V8 Limit Values min. max. - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 3 V6 20 6 3 3 3 - 1.5 - 1.5 -3 Unit V V V V V V 1.5 1.5 3 3 mA mA mA A A A mA mA 125 C Junction temperature Tj Storage temperature Tstg - 40 125 C Supply voltage V6 8 14 V Ambient temperature TA - 20 85 C Heat resistance Junction environment Junction case R th JE R th JC 100 70 K/W K/W Remarks Supply voltage t p 50 s; v 0.1*) t p 50 s; v 0.1 t p 50 s; v 0.1 Operating Range *) t p= pulse width v= duty circle Semiconductor Group 41 IC "on" measured at pin 4 TDA 4605 Characteristics TA = 25 C Parameter Symbol Limit Values min. typ. max. Unit Test Condition Test Circuit V6 = V6E 1 Start-Up Hysteresis Start-up current I 6E0 0.5 1.1 1.6 mA Switch-on voltage V6E 11 12 13 V 1 Switch-off voltage V6A 6.4 6.9 7.4 V 1 Switch-on current I 6E1 7 9 12 mA V6 = V6E 1 Switch-off current I 6A1 6.5 8 10 mA V6 = V6A 1 I 2 = 1 mA I 3 = 1 mA 1 1 Voltage Clamp (V6 = 10 V, IC switched off) At pin 2 (V6 V6E) At pin 3 (V6 V6E) V2 max V3 max 5.6 5.6 6.6 6.6 7.6 7.6 V V V1R 370 400 430 mV - VR 47 50 53 dB Regulation Range Regulation input voltage Voltage gain regulation range Regulation transmittance RR 20 k 2 VR = d (V2S - V2B)/- dV1 2 RR = d (V2S - V2B)/- dI1 2 Primary Current Reproducer Basic value V2B Input resistance R2B = V2B/I2B Slew rate falling edge Semiconductor Group 0.90 1.00 1.15 V 2 R 2B 25 40 2 V3 = 1.5 V; 1.2 V < V2 < 3 V 0.1 mA < I 2B < 3 mA dV2/dt -1 V 2 42 TDA 4605 Characteristics (cont'd) TA = 25 C Parameter Symbol Limit Values min. typ. Unit Test Condition max. Test Circuit Overload Range and Short-Circuit Operation Overload range lower V1U limit 60 230 290 Voltage gain in overload range VU 1 2 3 Input current in short circuit operation - I1 90 120 180 Peak value in overload range V2U Peak value in short circuit operation V2K 3.0 mV 2 VU = d (V2S - V2B)/dV1 2 A V1 = 0 V 2 V V1 = V1R - 10 mV 2 2.2 2.6 3.0 V V1 = 0 V 2 400 660 850 A V3'= 4 V; V2'= 0 V 1 0.75 0.80 V I8 = 1 mA 2 I8 = - 1 mA 2 Generally Valid Data (V6 = 10 V) Overload Point Correction Overload point correction current - I2 Zero Transition Detector Voltage Positive clamp V8P 0.70 Negative clamp V8N - 0.15 - 0.22 - 0.25 V Threshold value V8S 40 Input current - I8 Delay time between V8 and V5 td2 Zero detector disable time tUL Semiconductor Group 50 mV 2 4 A 0.2 0.4 0.7 s 2 2 6 s 43 2 V8 = 0 2 2 TDA 4605 Characteristics (cont'd) TA = 25 C Parameter Symbol Limit Values min. Unit Test Condition Test Circuit V V V V I 5 = - 0.1 A I5=-1A I 5 = 0.1 A I 5 = 0.5 A 1 1 1 1 typ. max. VSat0 VSat0 VSatV VSatV 1.5 2.5 1.0 1.4 2.0 3.0 1.2 1.8 Rising slope + dV5/dt 50 V/s 2 Falling slope + dV5/dt 80 V/s 2 Output Stage Saturation voltages S in position 1 Output sourcing Output sourcing Output sinking Output sinking Output slew rate Soft-Start Open-circuit V7 2.2 2.6 2.9 V V1 = 0 2 Input resistance R 7L 4 6 9 k 0.5 V V7 3 V 2 Peak voltage V2S 1.0 1.2 1.4 V V7 = 0 2 Protection Circuit Undervoltage protection for V6 at pin 5 = V5 min if V6 < V6 min (definition: V6 min = V6A + V6) V6 Overvoltage protection for V6 voltage at pin 5 = V5 min if V6 > V6 max V6 max 14 15 V3A 925 1000 Undervoltage protection for VAC voltage at pin 5 = V5 min if V3 < V3A 100 mV 2 16 V 2 1075 mV V2' = 0 V 1 C - 2 Over temperature chip temperature for V5 min Semiconductor Group Tj 125 44 TDA 4605 Characteristics (cont'd) TA = 25 C Parameter Symbol Limit Values min. typ. max. Voltage at pin 3 when protection function occurred; (V3 will be clamped until V6 < V6A) V3S 0.4 0.8 Burst operation quiescient current 8 Semiconductor Group I6 45 Unit Test Condition Test Circuit V I 3 = 1 mA 1 mA V3 = V2 = 0 V 1 TDA 4605 TDA 4605 Test Circuit 1 TDA 4605 Test Circuit 2 Semiconductor Group 46 TDA 4605 Application Circuit Semiconductor Group 47 TDA 4605 Diagrams Semiconductor Group 48 TDA 4605 Semiconductor Group 49 TDA 4605 Start-Up Hysteresis Semiconductor Group 50 TDA 4605 Operation in Test Circuit 2 Semiconductor Group 51 TDA 4605 Start-Up Current as a Function of the Ambient Temperature Overload Point Correction as a Function of the Voltage at Pin 3 Peak Value of the Primary Current Reproduction Voltage as a Function of the Regulating Voltage Peak Value of the Primary Current Reproduction Voltage by Loading Pin 7 Semiconductor Group 52 TDA 4605 Recommended Heat Sink by 60 C Ambient Temperature Narrow Range 180 V ... 270 V ~ Narrow Range 180 V ... 270 V ~ Semiconductor Group 53 Control IC for Switched-Mode Power Supplies using MOS-Transistors TDA 4605-2 Bipolar IC Features Fold-back characteristics provides overload protection for external components Burst operation under secondary short-circuit condition implemented Protection against open or a short of the control loop Switch-off if line voltage is too low (undervoltage switch-off) Line voltage depending compensation of fold-back point Soft-start for quiet start-up without noise generated by the transformer Chip-over temperature protection implemented (thermal shutdown) On-chip ringing suppression circuit against parasitic oscillations of the transformer P-DIP-8-1 Type Ordering Code Package TDA 4605-2 Q67000-A5020 P-DIP-8-1 The IC TDA 4605-2 controls the MOS-power transistor and performs all necessary regulation and monitoring functions in free running flyback converters. Because of the fact that a wide load range is achieved, this IC is applicable for consumer as well as industrial power supplies. The serial circuit and primary winding of the flyback transformer are connected in series to the input voltage. During the switch-on period of the transistor, energy is stored in the transformer. During the switch-off period the energy is fed to the load via the secondary winding. By varying switch-on time of the power transistor, the IC controls each portion of energy transferred to the secondary side such that the output voltage remains nearly independent of load variations. The required control information is taken from the input voltage during the switch-on period and from a regulation winding during the switch-off period. A new cycle will start if the transformer has transferred the stored energy completely into the load. Semiconductor Group 54 06.94 TDA 4605-2 In the different load ranges the switched-mode power supply (SMPS) behaves as follow: No load operation The power supply is operating in the burst mode at typical 20 to 40 kHz. The output voltage can be a little bit higher or lower than the nominal value depending of the design of the transformer and the resistors of the control voltage divider. Nominal operation The switching frequency is reduced with increasing load and decreasing AC-voltage. The duty factor primarily depends on the AC-voltage. The output voltage is only dependent on the load. Overload point Maximal output power is available at this point of the output characteristic. Overload The energy transferred per operation cycle is limited at the top. Therefore the output voltages declines by secondary overloading. Semiconductor Group 55 TDA 4605-2 Pin Definitions and Functions Pin No. Function 1 Information Input Concerning Secondary Voltage. By comparing the regulating voltage - obtained from the regulating winding of the transformer - with the internal reference voltage, the output impulse width on pin 5 is adjusted to the load of the secondary side (normal load, overload, short-circuit, no load). 2 Information Input Regarding the Primary Current. The primary current rise in the primary winding is simulated at pin 2 as a voltage rise by means of external RC-circuit. If a voltage level is reached which is derived from the control voltage at pin 1, the output impulse at pin 5 is terminated. The RC-circuit is used to set the maximum power of the foldback point. 3 Input for Primary Voltage Monitoring: In the normal operation V3 is moving between the thresholds V3H and V3L (V3H > V3 > V3L). V3 < V3L: SMPS is switched OFF (line voltage too low). V3 > V3H : Compensation of the overload point regulation (controlled by pin 2) starts at V3H : V3L = 1.7. 4 Ground 5 Output: Push-pull output for charging or discharging the gate capacity of the power MOSFET-transistor. 6 Supply Voltage Input. From the voltage at pin 6 a stable internal reference voltage VREF and the switching thresholds V6A , V6E , V6 max and V6 min for the supply voltage detector are derived. If V6 > V6E then VREF is switched on. The reference voltage will be switched off if V6 < V6A . In addition the logic is only enable, for V6 min < V6 < V6 max . 7 Input for Soft-Start and Integrator Circuit. The capacitor connected to ground causes a slow increase of the duration of the output pulse during start-up and an integrating response of the control amplifier. 8 Input for the Feedback of the Oscillator. After the oscillations of the SMPS started, every transition of the feedback voltage through zero (falling edge) triggers an output pulse at pin 5. The trigger threshold is at + 50 mV typical. Semiconductor Group 56 TDA 4605-2 Block Diagram Semiconductor Group 57 TDA 4605-2 Circuit Description Application Circuit The application circuit shows a flyback converter for video recorders with an output power rating of 70 W. The circuit is designed as a wide-range power supply for AC-line voltages of 180 to 264 V. The AC-input voltage is rectified by the bridge rectifier GR1 and smoothed by C1 . The NTC limits the rush-in current. The IC includes an internal circuit to avoid the turn-on of the power transistor T1 because of static charges applied to the transistors gate, during the turn-off state of the IC. The resistor R 13 helps to limit the spectrum of the radiated noise. During the conductive phase of the power transistor T1 the current rise in the primary winding depends on the winding inductance and the mains voltage. The network consisting of R 4-C5 is used to create a model of the sawtooth shaped rise of the collector current. The resulting control voltage is fed into pin 2 of the IC. The RC-time constant given by R 4-C5 must be designed that way that driving the transistor core into saturation is avoided. The ratio of the voltage divider R 10/R 11 is fixing a voltage level threshold. Below this threshold the switching power supply shall stop operation because of the low mains voltage. The control voltage present at pin 3 also determines the correction current for the foldback point. This current added to the current flowing through R 4 and represents an additional charge to C5 in order to reduce the turn-on phase of T1. This is done to stabilize the fold-back point even under higher mains voltages. The control of the switched-mode power supply is done by means of a control voltage applied to pin 1. The control voltage of winding n1 during the off-period of T1 is rectified by D3 smoothed by C6 and stepped down at an adjustable ratio by R 5 , R 6 and R 7 . The primary peak current, is adjusted by the IC so that the voltage applied across the control winding, and hence the output voltages, are at the desired level. When the energy stored in the transformer is transferred into the load the control voltage passes through zero. The IC detects the zero crossing via the series R 9 connected to pin 8. But zero crossings of the control voltage can also be produced by ringing of the transformer after the turn-off of the power transistor for T1 or when a short-circuit is applied to the output of the SMPS. The capacitor C8 is connected to pin 7. During the start-up phase this capacitor assures pulses with a shorter duty cycle in order to keep the operating frequency outside the audible frequency range. On the secondary side of the transformer 3 output voltages are produced using the windings n 2 to n5 , rectified by D4 to D6 and smoothed by C9 to C11 . The resistor R 12 is used as a bleeder resistor, the resistors with implemented fuse R 15 and R 16 protect the rectifies against short circuits in the output circuits, which are designed to supply only small loads. Semiconductor Group 58 TDA 4605-2 Block Diagram Pin 1 In the control and overload amplifier the control voltage applied to this pin is compared with a stable internal reference voltage V. The output signal of this stage is fed to the "stop" comparator. If the control voltage is rather small at pin 1 an additional current is added by means of current source which is controlled according the level at pin 7. This additional current is virtually reducing the control voltage present at pin 1. Pin 2 A voltage proportional to the drain current of the switching transistor is generated by means of an external RC-combination in conjunction with the internal functional block primary current / voltage converter. The output of this converter is controlled by the internal functional block "logic" and is also connected to the internal reference voltage V2B . If the voltage V2 exceeds the output voltage of the "control and overload amplifier" the stop comparator will reset the control logic. Consequently the output of pin 5 is switched to low potential. Further inputs for the logic stage are the outputs of the start impulse generator with the stable reference potential VST , the supply voltage monitoring circuit as well as the primary voltage supervision circuit. Pin 3 The primary voltage applied here via a voltage divider is used to stabilize the fold-back point. In addition the logic is disable if - in comparison with the internal reference voltage VV - a mains undervoltage condition is detected. Pin 4 Ground Pin 5 In the output stage the output signals from the "logic" block are converted into driving signals suitable for power MOS-transistors. Pin 6 From the supply voltage V6 applied to this pin internally a stable reference voltage VREF as well as the switching threshold V6A , V6E , V6 max and V6 min , for the supply voltage monitor section of the IC. All other inter reference value (VR , V2B , VST and Vv) are derived for VREF . If V6 > V6E the VREF voltage source is switched on and the source is switched off if V6 < V6A . In addition the logic is enable only if V6 min < V6 < V6 max . Semiconductor Group 59 TDA 4605-2 Pin 7 By means of a resistor pin 7 is connected with the output of the control amplifier. If V1 is approx. equal to the control voltage VR the control amplifier has a proportional integrating control characteristics. The response of the control loop is derived from the capacitor connected to pin 7. If V1 is equal to 0 V the control and overload amplifier is generating a ramp-up function using the capacitor connected to pin 7. Pin 8 The zero crossing detector controlling the logic block recognizes the complete discharge of the energy stored in the transformator core by detecting the zero crossing the positive to negative voltage transition of the voltage at pin 8. This enables the logic for a new pulse. Parasitic oscillations occurring at the end of a pulse cannot lead to a new pulse because of an internal circuit which inhibits the zero detector for a certain dead time tUL after the end of each pulse. Start-Up Behaviour The start-up behaviour of the application circuit (which is given on page 68) is explained in the diagrams on page 70 for a line voltage barely above the lower acceptable lower limit of the mains voltage. After applying the mains voltage at the time t0 the following built up of different voltages can be seen: - V6 corresponding to the half-wave charge current over R1 - V2 to V2 max (typically 6.6 V) - V3 to the value determined by the divider R10/R11 The current drawn by the IC in this case is less than 0.8 mA. If V6 reaches the threshold (at the time t1 in the diagram), the IC internal reference voltage is switched on. The supply current drawn by the IC rises to 12 mA max.. The primary current/voltage converter reduces V2 down to V2B and the start pulse generator generates the start pulses from time point t5 to t6 in the diagram. The feedback to pin 8 starts the next pulse and so on. The width of all pulses including the start pulse are controlled by means of the control and overload amplifier. After turn on the IC is generating a signal at pin 7 which slowly ramping up. This signal is used to increase the duration of the output pulses slowly (soft-start function). The max. output pulse width is limited by means of the overload amplifier. If the feedback control voltage V1 is increasing, the overload amplifier allows the generation of output pulses with a wider pulse width. The max. pulse width is reached at time t2 in the diagram (V2 = V2S max). The IC is then operating at the fold-back point. Thereafter the peak values of V2 decrease rapidly, because of the IC control range. The control loop is in a steady, operational state. If the voltage V6 falls below the switch-off threshold V6 min before the foldback point is reached, the attempt to start the SMPS is aborted (pin 5 is switched to low). As the internal circuits of the IC remain switched on, V6 further decreases to V6A . The IC switches off; V6 can rise again (time t4 in the diagram) and new start-up attempt begins at time t1 . Semiconductor Group 60 TDA 4605-2 If the voltage level of the rectified mains voltage is reduced strongly under the influence of the applied load it can happen that V3 is below the voltage level V3A - please refer to the time t3 in the diagram. This is because if an attempt is made to start the SMPS with a too low mains voltage. The internal primary voltage monitor circuit then clamps the voltage V3 to the voltage level V3S until the IC switches off (V6 < V6A). After this a new attempt to start the SMPS will begin at the time t1 in the diagram. Control Range, Overload and No-Load Behaviour After the IC has started, it is operating in the control range. The voltage level at pin 1 is typically 400 mV. The gain of the control circuit consist of two parts: at first a fixed proportional part which is internally fixed and an integrating part which can be set by means of the external capacitor at pin 7. If the load is applied to the output of the SMPS, the control and overload amplifier allows wider pulses (V5 = "H") .The peak voltage value at pin 2 increases up to V2S max . If the secondary load is increased further the overload amplifier begins to reduce the pulse width of the output pulse. This point is referred to as the fold-back point of the power supply. Because of the fact that the IC supply voltage is directly proportional to the secondary voltage, the supply voltage V6 will be reduced according to the behaviour of the control circuit under the overload condition. If V6 falls below the value V6 min , the IC will operate in the burst mode. Because of the large time constant of the startup circuit which is operating with half-wave rectification, only a small output power is transferred into the load during the secondary short-circuit of the SMPS. The overload amplifier reduces the output pulse width down to the pulse width tpk . This pulse width must remain possible in order to permit the IC to start up without problems from the virtual short-circuit, which every switching on with V1 = 0 is representing. If no load is applied to the secondary side, the output pulses (V5 = H) become shorter. If the pulse width is reduced be low a certain internal limit the IC will suppress some of the output pulses. If the load is reduced further because of the decreasing duty cycle the measurement error of the rectifier network (R8 , D3, C6 of the application circuit) is increasing and therefore the secondary output voltage will increase, too. If the IC is operating with small pulse width of the output pulse the control amplifier applies an additional current to the control amplifier in order to reduce the output voltage. The value of the additional current depends on the size of the resistors R 5 , R 8 , R 7 . This can be used to compensate the increase of the secondary voltages. Behaviour if the Chip Temperature Exceeds Predefined Limits An integrated protection circuit against over temperature disables the internal logic if the chip temperature is too high. The internal logic automatically checks the chip temperature and restart the SMPS as soon as the temperature decreases to a permissible level. Semiconductor Group 61 TDA 4605-2 Absolute Maximum Ratings TA = - 20 to 85 C; all voltages relatives to Vpp Parameter Voltages Currents Symbol pin 1 pin 2 pin 3 pin 5 pin 6 pin 7 V1 V2 V3 V5 V6 V7 pin 1 pin 2 pin 3 pin 4 pin 5 pin 6 pin 7 pin 8 I1 I2 I3 I4 I5 I6 I7 I8 Limit Values min. max. - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 3 V6 20 3 3 3 - 1.5 - 0.5 -5 Unit V V V V V V 1.5 0.5 3 3 mA mA mA A A A mA mA 125 C Junction temperature Tj Storage temperature Tstg - 40 125 C Supply voltage V6 7.5 15.5 V Ambient temperature TA - 20 85 C Heat resistance Junction environment Junction package Rth JE Rth JG 100 70 K/W K/W Remarks Supply voltage tp 50 s; v 0.1*) tp 50 s; v 0.1 tp 50 s; v 0.1 Operating Range *) t p= pulse width v= duty circle Semiconductor Group 62 IC "on" measured at pin 4 TDA 4605-2 Characteristics TA = 25 C; VS = 10 V Parameter Symbol Limit Values min. Unit Test Condition Test Circuit V6 = V6E 1 typ. max. 0.6 0.8 mA Start-Up Hysteresis Start-up current drain I6E0 Switch-on voltage V6E 11 12 13 V 1 Switch-off voltage V6A 4.5 5 5.5 V 1 Switch-on current I6E1 11 mA V6 = V6E 1 Switch-off current I6A1 10 mA V6 = V6A 1 I2 = 1 mA I3 = 1 mA 1 1 Voltage Clamp (V6 = 10 V, IC switched off) At pin 2 (V6 V6E) At pin 3 (V6 V6E) V2 max V3 max 5.6 5.6 6.6 6.6 8 8 V V Control input voltage V1R 390 400 410 mV Voltage gain of the control circuit in the control range - VR Control Range 43 dB 2 VR = d (V2S - V2B)/- dV1 f = 1 kHz 2 Primary Current Simulation Voltage Basic value V2B 0.97 1.00 1.03 V 2 Overload Range and Short-Circuit Operation V2O 2.9 3.0 3.1 V V1 = V1R - 10 mV 2 Peak value in the V2S range of secondary short-circuit operation 2.2 2.4 2.6 V V1 = 0 V 2 300 500 650 A V3 = 3.7 V 1 Peak value in the range of secondary overload Fold-Back Point Correction Fold-back point correction current Semiconductor Group - I2 63 TDA 4605-2 Characteristics (cont'd) TA = 25 C; VS = 10 V Parameter Symbol Limit Values min. typ. Unit Test Condition Test Circuit max. Generally Valid Data (V6 = 10 V) Voltage of the Zero Transition Detector Positive clamping voltage V8P 0.75 V I8 = 1 mA 2 Negative clamping voltage V8N - 0.2 V I8 = - 1 mA 2 Threshold value V8S 40 50 mV 2 Suppression of transformer ringing tUL 4 4.5 5.5 s 2 Input current - I8 0 4 A V8 = 0 2.0 1.2 1.8 V V V I5 = - 0.1 A I5 = + 0.1 A I5 = + 0.5 A Push-Pull Output Stage Saturation voltages Pin 5 sourcing Pin 5 sinking Pin 5 sinking VSat0 VSatV VSatV 1.5 1.0 1.4 Rising edge + dV5/dt 20 V/s 2 Falling edge + dV5/dt 50 V/s 2 50 A 1 1 1 Output Slew Rate Reduction of Control Voltage Current to reduce the - I1 control voltage Semiconductor Group 64 V7 = 1.1 V TDA 4605-2 Characteristics (cont'd) TA = 25 C; VS = 10 V Parameter Symbol Limit Values min. typ. max. Unit Test Condition Test Circuit Protection Circuit Undervoltage protection for V6 : voltage at pin 5 = V5 min if V6 < V6 min V6 min 7.0 7.25 7.5 V 2 Undervoltage protection for V6 : voltage at pin 5 = V5 min if V6 > V6 max V6 max 15.5 16 16.5 V 2 Undervoltage protection for VAC : voltage at pin 5 = V5 min if V3 < V3A V3A 985 1000 1015 mV Over temperature at the given chip the temperature IC will switch V5 to V5 min Tj 150 Voltage at pin 3 if one of the protection functions was triggered; (V3 will be clamped until V6 < V6A) V3Sat 0.4 Current drain during burst operation 8 Semiconductor Group I6 V2 = 0 V C 0.8 65 1 2 V I3 = 750 A 1 mA V3 = V2 = 0 V 1 TDA 4605-2 Test Circuit 1 Test Circuit 2 Semiconductor Group 66 TDA 4605-2 Application Circuit Semiconductor Group 67 TDA 4605-2 Diagrams Semiconductor Group 68 TDA 4605-2 Semiconductor Group 69 TDA 4605-2 Start-Up Hysteresis Semiconductor Group 70 TDA 4605-2 Operation in Test Circuit 2 Semiconductor Group 71 TDA 4605-2 Start-Up Current as a Function of the Ambient Temperature Semiconductor Group Overload Point Correction as a Function of the Voltage at Pin 3 72 TDA 4605-2 Recommended Heat Sink by 60 C Ambient Temperature Narrow Range 180 V ... 120 V ~ Narrow Range 90 V ... 270 V ~ Semiconductor Group 73 Control IC for Switched-Mode Power Supplies using MOS-Transistor TDA 4605-3 Bipolar IC Features Fold-back characteristics provides overload protection for external components Burst operation under secondary short-circuit condition implemented Protection against open or a short of the control loop Switch-off if line voltage is too low (undervoltage switch-off) Line voltage depending compensation of fold-back point Soft-start for quiet start-up without noise generated by the transformer Chip-over temperature protection implemented (thermal shutdown) On-chip ringing suppression circuit against parasitic oscillations of the transformer AGC-voltage reduction at low load P-DIP-8-1 Type Ordering Code Package TDA 4605-3 Q67000-A5066 P-DIP-8-1 The IC TDA 4605-3 controls the MOS-power transistor and performs all necessary control and protection functions in free running flyback converters. Because of the fact that a wide load range is achieved, this IC is applicable for consumer as well as industrial power supplies. The serial circuit and primary winding of the flyback transformer are connected in series to the input voltage. During the switch-on period of the transistor, energy is stored in the transformer. During the switch-off period the energy is fed to the load via the secondary winding. By varying switch-on time of the power transistor, the IC controls each portion of energy transferred to the secondary side such that the output voltage remains nearly independent of load variations. The required control information is taken from the input voltage during the switch-on period and from a regulation winding during the switch-off period. A new cycle will start if the transformer has transferred the stored energy completely into the load. Semiconductor Group 74 06.94 TDA 4605-3 In the different load ranges the switched-mode power supply (SMPS) behaves as follows: No load operation The power supply is operating in the burst mode at typical 20 to 40 kHz. The output voltage can be a little bit higher or lower than the nominal value depending of the design of the transformer and the resistors of the control voltage divider. Nominal operation The switching frequency is reduced with increasing load and decreasing AC-voltage. The output voltage is only dependent on the load. Overload point Maximal output power is available at this point of the output characteristic. Overload The energy transferred per operation cycle is limited at the top. Therefore the output voltages declines by secondary overloading. Semiconductor Group 75 TDA 4605-3 Pin Definitions and Functions Pin No. Function 1 Information Input Concerning Secondary Voltage. By comparing the regulating voltage - obtained trom the regulating winding of the transformer - with the internal reference voltage, the output impulse width on pin 5 is adjusted to the load of the secondary side (normal, overload, short-circuit, no load). 2 Information Input Regarding the Primary Current. The primary current rise in the primary winding is simulated at pin 2 as a voltage rise by means of external RC-element. When a voltage level is reached thats derived from the regulating voltage at pin 1, the output impulse at pin 5 is terminated. The RC-element serves to set the maximum power at the overload point set. 3 Input for Primary Voltage Monitoring: In the normal operation V3 is moving between the thresholds V3H and V3L (V3H > V3 > V3L). V3 < V3L: SMPS is switched OFF (line voltage too low). V3 > V3H : Compensation of the overload point regulation (controlled by pin 2) starts at V3H : V3L = 1.7. 4 Ground 5 Output: Push-pull output provides 1 A for rapid charge and discharge of the gate capacitance of the power MOS-transistor. 6 Supply Voltage Input: A stable internal reference voltage VREF is derived from the supply voltage also the switching thresholds V6A , V6E , V6 max and V6 min for the supply voltage detector. If V6 > V6E then VREF is switched on and swiched off when V6 < V6A . In addition the logic is only enable for V6 min < V6 < V6 max. 7 Input for Soft-Start. Start-up will begin with short pulses by connecting a capacitor from pin 7 to ground. 8 Input for the Oscillation Feedback. After starting oscillation, every zero transition of the feedback voltage (falling edge) through zero (falling edge) triggers an output pulse at pin 5. The trigger threshold is at + 50 mV typical. Semiconductor Group 76 TDA 4605-3 Block Diagram Semiconductor Group 77 TDA 4605-3 Circuit Description Application Circuit The application circuit shows a flyback converter for video recorders with an output power rating of 70 W. The circuit is designed as a wide-range power supply for AC-line voltages of 180 to 264 V. The AC-input voltage is rectified by the bridge rectifier GR1 and smoothed by C1 . The NTC limits the rush-in current. In the period before the switch-on threshold is reached the IC is suppled via resistor R 1 ; during the start-up phase it uses the energy stored in C2 , under steady state conditions the IC receives its supply voltage from transformer winding n1 via diode D1. The switching transistor T1 is a BUZ 90. The parallel connected capacitor C3 and the inductance of primary winding n 2 determine the system resonance frequency. The R 2-C4-D2 circuitry limits overshoot peaks, and R 3 protects the gate of T1 against static charges. During the conductive phase of the power transistor T1 the current rise in the primary winding depends on the winding inductance and the mains voltage. The network consisting of R 4-C5 is used to create a model of the sawtooth shaped rise of the collector current. The resulting control voltage is fed into pin 2 of the IC. The RC-time constant given by R 4-C5 must be designed that way that driving the transistor core into saturation is avoided. The ratio of the voltage divider R 10/R 11 is fixing a voltage level threshold. Below this threshold the switching power supply shall stop operation because of the low mains voltage. The control voltage present at pin 3 also determines the correction current for the fold-back point. This current added to the current flowing through R 4 and represents an additional charge to C5 in order to reduce the turnon phase of T1. This is done to stabilize the fold-back point even under higher mains voltages. Regulation of the switched-mode power supplies via pin 1. The control voltage of winding n1 during the off period of T1 is rectified by D3, smoothed by C6 and stepped down at an adjustable ratio by R 5 , R 6 and R 7 . The R 8-C7 network suppresses parasitic overshoots (transformer oscillation). The peak voltage at pin 2, and thus the primary peak current, is adjusted by the IC so that the voltage applied across the control winding, and hence the output voltages, are at the desired level. When the transformer has supplied its energy to the load, the control voltage passes through zero. The IC detects the zero crossing via series resistors R 9 connected to pin 8. But zero crossings are also produced by transformer oscillation after T1 has turned off if output is short-circuited. Therefore the IC ignores zero crossings occurring within a specified period of time after T1 turn-off. The capacitor C8 connected to pin 7 causes the power supply to be started with shorter pulses to keep the operating frequency outside the audible range during start-up. On the secondary side, five output voltages are produced across winding n3 to n7 rectified by D4 to D8 and smoothed by C9 to C13 . Resistors R 12 , R 14 and R 19 to R 21 are used as bleeder resistors. Fusable resistors R 15 to R 18 protect the rectifiers against short circuits in the output circuits, which are designed to supply only small loads. Semiconductor Group 78 TDA 4605-3 Block Diagram Pin 1 The regulating voltage forwarded to this pin is compared with a stable internal reference voltage VR in the regulating and overload amplifier. The output of this stage is fed to the stop comparator. If the control voltage is rather small at pin 1 an additional current is added by means of current source which is controlled according the level at pin 7. This additional current is virtually reducing the control voltage present at pin 1. Pin 2 A voltage proportional to the drain current of the switching transistor is generated there by the external RC-combination in conjunction with the primary current transducer. The output of this transducer is controlled by the logic and referenced to the internal stable voltage V2B . If the voltage V2 exceeds the output voltage of the regulations amplifier, the logic is reset by the stop comparator and consequently the output of pin 5 is switched to low potential. Further inputs for the logic stage are the output for the start impulse generator with the stable reference potential VST and the supply voltage motor. Pin 3 The down divided primary voltage applied there stabilizes the overload point. In addition the logic is disabled in the event of low voltage by comparison with the internal stable voltage VV in the primary voltage monitor block. Pin 4 Ground Pin 5 In the output stage the output signals produced by the logic are shifted to a level suitable for MOSpower transistors. Pin 6 From the supply voltage V6 are derived a stable internal references VREF and the switching threshold V6A , V6E , V6 max and V6 min for the supply voltage monitor. All references values (VR , V2B , VST) are derived from VREF . If V6 > VVE , the VREF is switched on and switched off when V6 < V 6A . In addition, the logic is released only for V6 min < V6 < V6 max . Pin 7 The output of the overload amplifier is connected to pin 7. A load on this output causes a reduction in maximal impulse duration. This function can be used to implement a soft start, when pin 7 is connected to ground by a capacitor. Semiconductor Group 79 TDA 4605-3 Pin 8 The zero detector controlling the logic block recognizes the transformer being discharged by positive to negative zero crossing of pin 8 voltage and enables the logic for a new pulse. Parasitic oscillations occurring at the end of a pulse cannot lead to a new pulse (double pulsing), because an internal circuit inhibits the zero detector for a finite time tUL after the end of each pulse. Start-Up Behaviour The start-up behaviour of the application circuit per sheet 88 is represented an sheet 90 for a line voltage barely above the lower acceptable limit time t0 the following voltages built up: - V6 corresponding to the half-wave charge current over R1 - V2 to V2 max (typically 6.6 V) - V3 to the value determined by the divider R 10/R 11 . The current drawn by the IC in this case is less than 1.6 mA. If V6 reaches the threshold V6E (time point t1), the IC switches on the internal reference voltage. The current draw max. rises to 12 mA. The primary current- voltage reproducer regulates V2 down to V2B and the starting impulse generator generates the starting impulses from time point t5 to t6 . The feedback to pin 8 starts the next impulse and so on. All impulses including the starting impulse are controlled in width by regulating voltage of pin 1. When switching on this corresponds to a shortcircuit event, i.e. V1 = 0. Hence the IC starts up with "short-circuit impulses" to assume a width depending on the regulating voltage feedback (the IC operates in the overload range). The IC operates at the overload point. Thereafter the peak values of V2 decrease rapidly, as the starting attempt is aborted (pin 5 is switched to low). As the IC remains switched on, V6 further decreases to V6 . The IC switches off; V6 can rise again (time point t4) and a new start-up attempt begins at time point t1 . If the rectified alternating Iine voltage (primary voltage) collapses during load, V3 can fall below V3A , as is happening at time point t3 (switch-on attempt when voltage is too low). The primary voltage monitor then clamps V3 to V3S until the IC switches off (V6 < V6A). Then a new startup attempt begins at time point t1 . Semiconductor Group 80 TDA 4605-3 Regulation, Overload and No-Load Behaviour When the IC has started up, it is operating in the regulation range. The potential at pin 1 typically is 400 mV. If the output is loaded, the regulation amplifier allows broader impulses (V5 = H). The peak voltage value at pin 2 increases up to V2S max . If the secondary load is further increased, the overload amplifier begins to regulate the pulse width downward. This point is referred to as the overload point of the power supply. As the IC-supply voltage V6 is directly proportional to the secondary voltage, it goes down in accordance with the overload regulation behaviour. If V6 falls below the value V6 min , the IC goes into burst operation. As the time constant of the half-wave charge-up is relatively large, the short-circuit power remains small. The overload amplifier cuts back to the pulse width tpk . This pulse width must remain possible, in order to permit the IC to start-up without problems from the virtual short-circuit, which every switching on with V1 = 0 represents. If the secondary side is unloaded, the loading impulses (V5 = H) become shorter. The frequency increases up to the resonance frequency of the system. If the load is further reduced, the secondary voltages and V6 increase. When V6 = V6 max the logic is blocked. The IC converts to burst operation.This renders the circuit absolutely safe under no-load conditions. Behaviour when Temperature Exceeds Limit An integrated temperature protection disables the logic when the chip temperature becomes too high. The IC automatically interrogates the temperature and starts as soon as the temperature decreases to permissible values. Semiconductor Group 81 TDA 4605-3 Absolute Maximum Ratings TA = - 20 to 85 C Parameter Voltages Currents Symbol pin 1 pin 2 pin 3 pin 5 pin 6 pin 7 V1 V2 V3 V5 V6 V7 pin 1 pin 2 pin 3 pin 4 pin 5 pin 6 pin 7 pin 8 I1 I2 I3 I4 I5 I6 I7 I8 Limit Values min. max. - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 3 V6 20 3 3 3 - 1.5 - 0.5 -5 Unit V V V V V V 1.5 0.5 3 3 mA mA mA A A A mA mA 125 C Junction temperature Tj Storage temperature Tstg - 40 125 C Supply voltage V6 7.5 15.5 V Ambient temperature TA - 20 85 C Remarks Supply voltage tp 50 s; v 0.1*) tp 50 s; v 0.1 tp 50 s; v 0.1 Operating Range IC "on" Heat resistance Junction to environment Rth JE 100 K/W Junction case Rth JC 70 K/W *) t p= pulse width v= duty circle Semiconductor Group 82 measured at pin 4 TDA 4605-3 Characteristics TA = 25 C; VS = 10 V Parameter Symbol Limit Values min. Unit Test Condition Test Circuit V6 = V6E 1 typ. max. 0.6 0.8 mA Start-Up Hysteresis Start-up current drain I6E0 Switch-on voltage V6E 11 12 13 V 1 Switch-off voltage V6A 4.5 5 5.5 V 1 Switch-on current I6E1 7 11 14 mA V6 = V6E 1 Switch-off current I6A1 5 10 13 mA V6 = V6A 1 I2 = 1 mA I3 = 1 mA 1 1 Voltage Clamp (V6 = 10 V, IC switched off) At pin 2 (V6 V6E) At pin 3 (V6 V6E) V2 max V3 max 5.6 5.6 6.6 6.6 8 8 V V Control input voltage V1R 390 400 410 mV Voltage gain of the control circuit in the control range - VR 30 43 60 dB 1.00 1.03 V Control Range 2 VR = d (V2S - V2B) / - dV1 f = 1 kHz 2 Primary Current Simulation Voltage Basic value V2B 0.97 2 Overload Range and Short-Circuit Operation V2B 2.9 3.0 3.1 V V1 = V1R - 10 mV 2 Peak value in the V2K range of secondary short-circuit operation 2.2 2.4 2.6 V V1 = 0 V 2 300 500 650 A V3 = 3.7 V 1 Peak value in the range of secondary overload Fold-Back Point Correction Fold-back point correction current Semiconductor Group - I2 83 TDA 4605-3 Characteristics (cont'd) TA = 25 C; VS = 10 V Parameter Symbol Limit Values min. typ. max. 0.75 0.82 Unit Test Condition Test Circuit V I8 = 1 mA 2 I8 = - 1 mA 2 Generally Valid Data (V6 = 10 V) Voltage of the Zero Transition Detector Positive clamping voltage V8P 0.7 Negative clamping voltage V8N - 0.25 - 0.2 - 0.15 V Threshold value V8S 40 50 76 mV 2 Suppression of transformer ringing tUL 3.0 3.5 3.8 s 2 Input current - I8 0 4 A V8 = 0 2 Push-Pull Output Stage Saturation voltages Pin 5 sourcing VSat0 1.5 2.0 V I5 = - 0.1 A 1 Pin 5 sinking VSatV 1.0 1.2 V I5 = + 0.1 A 1 Pin 5 sinking VSatV 1.4 1.8 V I5 = + 0.5 A 1 Rising edge + dV5/dt 70 V/s 2 Falling edge + dV5/dt 100 V/s 2 Output Slew Rate Reduction of Control Voltage Current to reduce the - I1 control voltage Semiconductor Group 50 130 84 A V7 = 1.1 V, V1 = 0.4 V TDA 4605-3 Characteristics (cont'd) TA = 25 C; VS = 10 V Parameter Symbol Limit Values min. typ. max. Unit Test Condition Test Circuit Protection Circuit Undervoltage protection for V6 : voltage at pin 5 = V5 min if V6 < V5 min V6 min 7.0 7.25 7.5 V 2 Undervoltage protection for V6 : voltage at pin 5 = V5 min if V6 > V6 max V6 max 15.5 16 16.5 V 2 Undervoltage protection for VAC : voltage at pin 4 = V5 min if V3 < V3A V3A 985 1000 1015 mV Over temperature at the given chip temperature the IC will switch V5 toV5 min Tj 150 Voltage at pin 3 if one of the protection function was triggered; (V3 will be clamped until V6 < V6A) V3Sat 0.4 Current drain during burst operation 8 Semiconductor Group I6 V2 = 0 V C 0.8 85 1 2 V I3 = 750 A 1 mA V3 = V2 = 0 V 1 TDA 4605-3 Test Circuit 1 Test Circuit 2 Semiconductor Group 86 TDA 4605-3 Application Circuit Semiconductor Group 87 TDA 4605-3 Diagrams Semiconductor Group 88 TDA 4605-3 Semiconductor Group 89 TDA 4605-3 Start-Up Hysteresis Semiconductor Group 90 TDA 4605-3 Operation in Test Circuit 2 Semiconductor Group 91 TDA 4605-3 Start-Up Current as a Function of the Ambient Temperature Semiconductor Group Overload Point Correction as a Function of the Voltage at Pin 3 92 TDA 4605-3 Recommended Heat Sink by 60 C Ambient Temperature Narrow Range 180 V ... 120 V ~ Narrow Range 90 V ... 270 V ~ Semiconductor Group 93 TDA 4700 TDA 4718 Control IC for Single-Ended and Push-Pull Switched-Mode Power Supplies (SMPS) Features Feed-forward control (line hum suppression) Symmetry inputs for push-pull converter (TDA 4700) Push-pull outputs Dynamic output current limitation Overvoltage protection Undervoltage protection Soft start Double pulse suppression Type Ordering Code Package Temp.-Range TDA 4700 A Q67000-Y594 P-DIP-24-1 - 0 to 70 C TDA 4718 A Q67000-Y639 P-DIP-18-1 - 0 to 70 C Not for new design P-DIP-24-1 P-DIP-18-1 These versatile SMPS control ICs comprise digital and analog functions which are required to design highquality flyback, single-ended and push-pull converters in normal, half-bridge and full-bridge configurations. The component can also be used in single-ended voltage multipliers and speed-controlled motors. Malfunctions in electrical operation are recognized by the integrated operational amplifiers, which activate protective functions. 1) Is now available for temperature range - 25 to 85 C. Semiconductor Group 1 05.95 Pin Configuration (TDA 4700) (top view) TDA 4700 TDA 4718 Pin Definitions and Functions (TDA 4700) Pin Symbol Function 1 GND Ground 0 V 2 3 + VREF + VS Reference voltage Supply voltage 4 5 Q2 Q1 Output Q2 Output Q1 6 7 8 I SYM Q2 Q SYNC Csoft start Symmetry Q2 Sync. output Soft start 9 10 11 RT Cfilter CT VCO RT Capacitance VCO CT 12 13 RR CR Ramp generator RR Ramp generator CR 14 15 I COMP Q Op Amp Comparator input Operational amplifier output 16 - I Op Amp Operational amplifier input (-) 17 + I Op Amp Operational amplifier input (+) 18 I SYNC Sync. input 19 ON/OFF/IUV ON/OFF, undervoltage 20 21 QOV IOV Overvoltage output Overvoltage input 22 - IDYN Dynamic current limitation (-) 23 + IDYN Dynamic current limitation (+) 24 I SYM Q1 Symmetry Semiconductor Group 3 TDA 4700 TDA 4718 Pin Configuration (TDA 4718) (top view) Semiconductor Group 4 TDA 4700 TDA 4718 Pin Definitions and Functions (TDA 4718) Pin Symbol Function 1 GND Ground 0 V 2 3 RR CR Ramp generator RR Ramp generator CR 4 5 I COMP I SYNC + Input comparator K2 Sync. input 6 7 IUV IOV Input undervoltage, ON/OFF Input overvoltage 8 9 - IDYN + IDYN Input dynamic current limitation (-) Input dynamic current limitation (+) 10 11 + VREF + VS Reference voltage Supply voltage 12 13 Q2 Q1 Output Q2 Output Q1 14 15 Q SYNC Csoft start Sync. output Soft start 16 17 18 RT Cfilter CT VCO RT Capacitance VCO CT Circuit Description Voltage Controlled Oscillator (VCO) The VCO generates a sawtooth voltage. The duration of the falling edge is determined by the value of CT. The duration of the rising edge of the waveform and, therefore, approximately the frequency, is determined by the value of RT. By varying the voltage at Cfilter, the oscillator frequency can be changed by its rated value. During the fall time, the VCO provides a trigger signal for the ramp generator, as well as an L signal for a number of IC parts to be controlled. Semiconductor Group 5 TDA 4700 TDA 4718 Ramp Generator The ramp generator is triggered by the VCO and oscillates at the same frequency. The duration of the falling edge of the ramp generator waveform is to be shorter than the fall time of the VCO. To control the pulse width at the output, the voltage of the rising edge of the ramp generator signal is compared with a DC voltage at comparator K2. The slope of the rising edge of the ramp generator signal is controlled by the current through RR. This offers the possibility of an additional, superimposed control of the output duty cycle. This additional control capability, called "feed-forward control", is utilized to compensate for known interference such as ripple on the input voltage. Phase Comparator If the component is operated without external synchronization, the sync input must be connected to the sync output for the phase comparator to set the rated voltage at Cfilter. The VCO then oscillates with rated frequency. In the case of external synchronization, other components can be synchronized with the sync output. The component can be frequency-synchronized, but not phase-synchronized, with the sync input. The duty cycle of the squarewave voltage at the sync input is arbitrary. The best stability as to small phase and frequency interference deviation is achieved with a duty cycle as offered by the sync output. Push-Pull Flipflop The push-pull flipflop is switched by the falling edge of the VCO. This ensures that only one output of the two push-pull outputs is enabled at a time. Comparator K2 The two plus inputs of the comparator are switched such that the lower plus level is always compared with the level of the minus input. As soon as the voltage of the rising sawtooth edge exceeds the lower of the two plus levels, both outputs are disabled via the pulse turn-off flipflop. The period during which the respective, active outputs is low can be infinitely varied. As the frequency remains constant, this process corresponds to a change in duty cycle. Operational Amplifier K1 (TDA 4700; A) The K1 op amp is a high-quality amplifier. Fluctuations in the output voltage of the power supply are amplified by K1 and applied to the free + input of comparator K2. Variations in output voltage are, in this way, converted to a corresponding change in output duty cycle. K1 has a common-mode input voltage range between 0 V and + 5 V. Semiconductor Group 6 TDA 4700 TDA 4718 Pulse-Turn-OFF Flipflop The pulse turn-OFF flipflop enables the outputs at the start of each half cycle. If an error signal from comparator K7 or a turn-off signal from K2 is present, the outputs will immediately be switched off. Comparator K3 Comparator K3 limits the voltage at capacitance Csoft start (and also at K2) to a maximum of + 5 V. The voltage at the ramp generator output may, however rise to 5.5 V. With a corresponding slope of the rising ramp generator edge, the duty cycle can be limited to a desired maximum value. Comparator K4 The comparator has its switching threshold at 1.5 V and sets the error flipflop with its output if the voltage at capacitance Csoft start is below 1.5 V. However, the error flipflop accepts the set signal only if no reset pulse (error) is applied. In this way the outputs cannot be turned on again as long as an error signal is present. Soft Start The lower one of the two voltages at the plus inputs of K2 is a measure for the duty cycle at the output. At the instant of turning on the component, the voltage at capacitor Csoft start equals 0 V. As long as no error is present, this capacitor is charged with a current of 6 A to the maximum value of 5 V. In case of an error, Csoft start is discharged with a current of 2 A. A set signal is pending at the error flipflop below a charge of 1.5 V and the outputs are enabled if no reset signal is pending simultaneously. As the minimum ramp generator voltage, however, is 1.8 V, the duty cycle at the outputs is actually increased slowly and continuously not before the voltage at Csoft start exceeds 1.8 V. Error Flipflop Error signals, which are led to input R of the error flipflop cause an immediate disabling of the outputs, and after the error has been eliminated, cause the component to switch on again by the soft start. Comparator K5, K6, K8, VREF Overcurrent Load These are error detectors which cause immediate disabling of the outputs via the error flipflop when an error occurs. After elimination of the error, the component switches on again using the soft start. The output of K5 can be fed back to the input. This causes the IC output stage to remain disabled even after elimination of the overvoltage. However, it requires high-ohmic overvoltage coupling. Semiconductor Group 7 TDA 4700 TDA 4718 Comparator K7 K7 serves to recognize overcurrents. This is the reason why both inputs of the op amp have been brought out. Turning on is resumed after error recovery at the beginning of the next half period but without using the soft start. K7 has a common-mode range covers 0 V and + 4 V. The delay time between occurrence of an error and disabling of the outputs is only 250 ns. Symmetry (TDA 4700; A) In push-pull converters, a saturation of the transformer core must be prevented. The degree of saturation of the transformer can be determined with an external circuit, thus the active periods of the outputs can be decreased unsymmetrically at the symmetry inputs. Outputs Both outputs are transistors with open collectors and operate in a push-pull arrangement. They are active low. The time in which only one of the two outputs is conductive can be varied infinitely. The length of the falling edge at VCO is equal to the minimum time during which both outputs are disabled simultaneously. The minimum L voltage is 0.7 V. Reference Voltage The reference voltage source is a highly constant source with regard to its temperature behavior. It can be utilized in the external wiring of the op amp, the error comparators, the ramp generator, or other external components. Semiconductor Group 8 Block Diagram (TDA 4700) TDA 4700 TDA 4718 Block Diagram (TDA 4718) Semiconductor Group 10 TDA 4700 TDA 4718 Absolute Maximum Ratings Parameter Symbol Limit Values Unit min. max. - 0.3 - 0.3 33 33 V V Q1, Q2 high 70 mA Q1, Q2 low Supply voltage Voltage at Q1, Q2 VS VQ Current at Q1, Q2 IQ Symmetry 1, 2 TDA 4700; A VSYM - 0.3 33 V Sync output VSYNC Q ISYNC Q - 0.3 0 7 10 V mA Sync input Input Cfilter Input RT Input CT Input RR Input CR Input comparator K2, K5, K6, K7 VSYNC I VI Cf VI RT VI CT VI RR II CR - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 10 33 7 7 7 7 10 V V V V V mA VI K - 0.3 33 V Output K5 VQ K5 - 0.3 33 V VI Op Amp - 0.3 33 V VQ Op Amp - 0.3 VS - 1 max. 7 V V Input op amp TDA 4700; A Output op amp TDA 4700; A Reference voltage VREF - 0.3 VREF V Input Csoft start VI soft start - 0.3 7 V Junction temperature Storage temperature Tj Tstg - 55 150 125 C C Thermal resistance system - air TDA 4700; A TDA 4718 TDA 4718 A Rth SA Rth SA Rth SA 65 70 60 K/W K/W K/W Semiconductor Group Test Condition 11 SYNC Q high SYNC Q low TDA 4700 TDA 4718 Operating Range Parameter Symbol Limit Values min. max. Unit Supply voltage VS 10.5 30 V Ambient temperature TDA 4700 TDA 4718 TDA 4700 A TDA 4718 A TA - 25 85 C TA 0 70 C VCO frequency Ramp generator frequency f fRG 40 40 250 000 250 000 Hz Hz Test Condition Characteristics VS = 11 to 30 V; TA = - 25 to 85 C Parameter Symbol Limit Values min. Supply current IS 8 VREF 2.35 typ. Unit Test Condition 20 mA CT = 1 nF fVCO = 100 kHz 2.65 V 0 mA < IREF < 5 mA max. Reference Reference voltage Reference voltage change Reference voltage change Reference voltage change Temperature coefficient Response threshold of IREF overcurrent 1) 2.5 VREF 8 mV 14 V 20 % VREF 15 mV 25 V 20 % mV 0 mA < IREF < 5 mA VREF 151) TC 0.25 0.4 mV/K IREF 10 mA At TA = 0 to 70 C, this value falls to max. 5 mV Semiconductor Group 12 TDA 4700 TDA 4718 Characteristics (cont'd) VS = 11 to 30 V; TA = - 25 to 85 C Parameter Symbol Limit Values min. typ. Unit max. Test Condition Oscillator (VCO) Frequency range Frequency change Frequency change Tolerance Fall time sawtooth RC combination VCO fVCO f/fVCO f/fVCO f/fVCO t t CT RT 40 0.82 5 47 700 Hz % % % s s nF k f 40 100 000 Hz 100 000 0.5 -1 -7 1 7 1 10 14 V 20 % 25 V 20 % RT = 0; CT = 0 CT = 1 nF CT = 10 nF Ramp Generator Frequency range Maximum voltage at CR Minimum voltage at CR Input current through RR Current transformation ratio VH 5.5 V VL 1.8 V IRR 400 0 IRR/ICR A 1/4 Synchronization Sync output Sync input Input current Semiconductor Group VQ H VQ L VI H VI L - II 4 0.4 2 0.8 5 13 V V V V A IQ H = - 200 A IQ L = 1.6 mA TDA 4700 TDA 4718 Characteristics (cont'd) VS = 11 to 30 V; TA = - 25 to 85 C Parameter Symbol Limit Values min. typ. Unit max. Test Condition Comparator K2 Input current Turn-OFF delay1) Input voltage - II K2 2 500 tD OFF VI K2 V V 1.8 5 Common-mode input voltage range VI C 5.5 0 A ns for duty cycle D=0 D = max. V Soft Start K3, K4 Charge current for Csoft start Ich 6 A Idch Vlim VK4 2 5 1.5 A V V Discharge current for Csoft start Upper limiting voltage Switching voltage K4 Operational Amplifier K1 (TDA 4700; TDA 4700 A) Open-loop voltage gain Input offset voltage Temperature coefficient of VIO Input current Common-mode input voltage range Output current Rise time of output voltage Transition frequency Phase at fT Output voltage 1) GV0 VIO 60 - 10 TC - II VIC IQ 10 dB mV - 30 30 2 V/K A 0 -3 5 1.5 V mA 5.5 V/s MHz deg. V V/t 1 3 120 fT T VQ H/L 1.5 At the input: step function V = - 100 mV Semiconductor Group 80 V = + 100 mV 14 - 3 mA < I < 1.5 mA TDA 4700 TDA 4718 Characteristics (cont'd) VS = 11 to 30 V; TA = - 25 to 85 C Parameter Symbol Limit Values min. typ. Unit max. Test Condition Symmetry (TDA 4700; TDA 4700 A) Input voltage Input current VI H VI L - II 2.0 0.8 2 V V A VQ H VQ L 30 1.1 V V IQ = 20 mA IQ 2 A VQ H = 30 V Output Stages Q1, Q2 Output voltage Output leakage current ON, OFF, Undervoltage K6 Switching voltage Input current Turn-OFF delay time1) Error detection time1) V - II VREF - 0.03 tD OFF t VREF + 0.03 V 2 A ns ns 4 10 2 V mV A ns ns 250 50 Dynamic Current Limitation K7 Common-mode input voltage range Input offset voltage Input current Turn-OFF delay time2) Error detection time2) VIC VIO - II tD OFF t 0 - 10 250 50 Overvoltage K5 Switching voltage Input current Output current Turn-OFF delay time1) Error detection time1) 1) 2) V - II - IQ VREF - 0.03 VREF + 0.03 V 0 2 200 tD OFF t 250 50 At the input: step function V = VREF - 100 mV VREF + 100 mV At the input: step function V = - 100 mV V = + 100 mV Semiconductor Group 15 A A ns ns VQH min = 5 V TDA 4700 TDA 4718 Characteristics (cont'd) VS = 11 to 30 V; TA = - 25 to 85 C Parameter Symbol Limit Values min. typ. Unit max. Test Condition Supply Undervoltage Turn-ON threshold for VS rising Turn-OFF threshold for VS falling VS 8.8 VS 8.5 11 10.5 10.5 10 V V V V Input Cfilter Rated voltage for rated frequency VR Frequency approx. proportional to voltage within the range VR Voltage at open sync input VC filter Semiconductor Group 4 3 V 5 1.6 16 V V 0 C < TA < 70 C 0 C < TA < 70 C Dimensioning Notes for RC Network 1. Determination of the minimum time during which both outputs must be disabled selection of CT; selection of CR CT. 2. Determination of the VCO frequency = 2 x output frequency selection of RT. 3. Determination of the rated slope of the rising ramp generator voltage, which the maximum possible turn-on period per half wave depends on selection of RR. 4. Duration of the soft start process selection of Csoft start. 5. In the case of a free-running VCO: connect sync output with sync input. 6. Wiring of the op amp according to the dynamic requirements and connection of its output with the free input of K2. (TDA 4700; TDA 4700 A) 7. Capacitance Cfilter is not required in the free-running operation (sync input connected with sync output). In the case of external synchronization, that value depends on the selected operating frequency and the required maximum phase interference deviation. Rated VCO frequency: Cfilter favourable: 100 kHz 10 nF 50 Hz 1F Pulse Diagram VCO Frequency versus RT and CT TDA 4700 TDA 4718 VCO Temperature Response VS = 12 V; D = max. f VCO ----------------- [ 1 K ] with CT as parameter fK x K Semiconductor Group 20 TDA 4700 TDA 4718 Current Consumption versus Temperature Semiconductor Group Output Current versus Output Voltage 21 TDA 4718 A Control IC for Single-Ended and Push-Pull Switched-Mode Power Supplies (SMPS) Features Feed-forward control (line hum suppression) Push-pull outputs Dynamic output current limitation Overvoltage protection Undervoltage protection Soft start Double pulse suppression P-DIP-18-1 Type Ordering Code Package Temp.-Range TDA 4718 A Q67000-Y639 P-DIP-18-1 - 25 to 85 C These versatile SMPS control ICs comprise digital and analog functions which are required to design high-quality flyback, single-ended and push-pull converters in normal, half-bridge and full-bridge configurations. The component can also be used in singleended voltage multipliers and speed-controlled motors. Malfunctions in electrical operation are recognized by the integrated operational amplifiers, which activate protective functions. Semiconductor Group 1 05.95 TDA 4718 A Pin Configuration (top view) Semiconductor Group 2 TDA 4718 A Pin Definitions and Functions Pin Symbol Function 1 GND Ground 0 V 2 3 RR CR Ramp generator RR Ramp generator CR 4 5 I COMP I SYNC + Input comparator K2 Sync. input 6 7 IUV IOV Input undervoltage, ON/OFF Input overvoltage 8 9 - IDYN + IDYN Input dynamic current limitation (-) Input dynamic current limitation (+) 10 11 + VREF + VS Reference voltage Supply voltage 12 13 Q2 Q1 Output Q2 Output Q1 14 15 Q SYNC Csoft start Sync. output Soft start 16 17 18 RT Cfilter CT VCO RT Capacitance VCO CT Circuit Description Voltage Controlled Oscillator (VCO) The VCO generates a sawtooth voltage. The duration of the falling edge is determined by the value of CT. The duration of the rising edge of the waveform and, therefore, approximately the frequency, is determined by the value of RT. By varying the voltage at Cfilter, the oscillator frequency can be changed by its rated value. During the fall time, the VCO provides a trigger signal for the ramp generator, as well as an L signal for a number of IC parts to be controlled. Semiconductor Group 3 TDA 4718 A Ramp Generator The ramp generator is triggered by the VCO and oscillates at the same frequency. The duration of the falling edge of the ramp generator waveform is to be shorter than the fall time of the VCO. To control the pulse width at the output, the voltage of the rising edge of the ramp generator signal is compared with a DC voltage at comparator K2. The slope of the rising edge of the ramp generator signal is controlled by the current through RR. This offers the possibility of an additional, superimposed control of the output duty cycle. This additional control capability, called "feed-forward control", is utilized to compensate for known interference such as ripple on the input voltage. Phase Comparator If the component is operated without external synchronization, the sync input must be connected to the sync output for the phase comparator to set the rated voltage at Cfilter. The VCO then oscillates with rated frequency. In the case of external synchronization, other components can be synchronized with the sync output. The component can be frequency-synchronized, but not phase-synchronized, with the sync input. The duty cycle of the squarewave voltage at the sync input is arbitrary. The best stability as to small phase and frequency interference deviation is achieved with a duty cycle as offered by the sync output. Push-Pull Flipflop The push-pull flipflop is switched by the falling edge of the VCO. This ensures that only one output of the two push-pull outputs is enabled at a time. Comparator K2 The two plus inputs of the comparator are switched such that the lower plus level is always compared with the level of the minus input. As soon as the voltage of the rising sawtooth edge exceeds the lower of the two plus levels, both outputs are disabled via the pulse turn-off flipflop. The period during which the respective, active outputs is low can be infinitely varied. As the frequency remains constant, this process corresponds to a change in duty cycle. Pulse-Turn-OFF Flipflop The pulse turn-OFF flipflop enables the outputs at the start of each half cycle. If an error signal from comparator K7 or a turn-off signal from K2 is present, the outputs will immediately be switched off. Semiconductor Group 4 TDA 4718 A Comparator K3 Comparator K3 limits the voltage at capacitance Csoft start (and also at K2) to a maximum of + 5 V. The voltage at the ramp generator output may, however rise to 5.5 V. With a corresponding slope of the rising ramp generator edge, the duty cycle can be limited to a desired maximum value. Comparator K4 The comparator has its switching threshold at 1.5 V and sets the error flipflop with its output if the voltage at capacitance Csoft start is below 1.5 V. However, the error flipflop accepts the set signal only if no reset pulse (error) is applied. In this way the outputs cannot be turned on again as long as an error signal is present. Soft Start The lower one of the two voltages at the plus inputs of K2 is a measure for the duty cycle at the output. At the instant of turning on the component, the voltage at capacitor Csoft start equals 0 V. As long as no error is present, this capacitor is charged with a current of 6 A to the maximum value of 5 V. In case of an error, Csoft start is discharged with a current of 2 A. A set signal is pending at the error flipflop below a charge of 1.5 V and the outputs are enabled if no reset signal is pending simultaneously. As the minimum ramp generator voltage, however, is 1.8 V, the duty cycle at the outputs is actually increased slowly and continuously not before the voltage at Csoft start exceeds 1.8 V. Error Flipflop Error signals, which are led to input R of the error flipflop cause an immediate disabling of the outputs, and after the error has been eliminated, cause the component to switch on again by the soft start. Comparator K5, K6, K8, VREF Overcurrent Load These are error detectors which cause immediate disabling of the outputs via the error flipflop when an error occurs. After elimination of the error, the component switches on again using the soft start. The output of K5 can be fed back to the input. This causes the IC output stage to remain disabled even after elimination of the overvoltage. However, it requires high-ohmic overvoltage coupling. Comparator K7 K7 serves to recognize overcurrents. This is the reason why both inputs of the op amp have been brought out. Turning on is resumed after error recovery at the beginning of the next half period but without using the soft start. K7 has a common-mode range covers 0 V and + 4 V. The delay time between occurrence of an error and disabling of the outputs is only 250 ns. Semiconductor Group 5 TDA 4718 A Outputs Both outputs are transistors with open collectors and operate in a push-pull arrangement. They are active low. The time in which only one of the two outputs is conductive can be varied infinitely. The length of the falling edge at VCO is equal to the minimum time during which both outputs are disabled simultaneously. The minimum L voltage is 0.7 V. Reference Voltage The reference voltage source is a highly constant source with regard to its temperature behavior. It can be utilized in the external wiring of the op amp, the error comparators, the ramp generator, or other external components. Semiconductor Group 6 TDA 4718 A Block Diagram Semiconductor Group 7 TDA 4718 A Absolute Maximum Ratings Parameter Symbol Limit Values Unit min. max. - 0.3 - 0.3 33 33 V V Q1, Q2 high 70 mA Q1, Q2 low SYNC Q high SYNC Q low Supply voltage Voltage at Q1, Q2 VS VQ Current at Q1, Q2 IQ Sync output VSYNC Q ISYNC Q - 0.3 0 7 10 V mA Sync input Input Cfilter Input RT Input CT Input RR Input CR Input comparator K2, K5, K6, K7 VSYNC I VI Cf VI RT VI CT VI RR II CR - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 10 33 7 7 7 7 10 V V V V V mA VI K - 0.3 33 V Output K5 VQ K5 - 0.3 33 V Reference voltage VREF - 0.3 VREF V Input Csoft start VI soft start - 0.3 7 V Junction temperature Storage temperature Tj Tstg - 55 150 125 C C 60 K/W Thermal resistance system-air Rth SA Semiconductor Group Test Condition 8 TDA 4718 A Operating Range Parameter Symbol Limit Values min. max. Unit Supply voltage VS 10.5 30 V Ambient temperature TA - 25 85 C VCO frequency Ramp generator frequency f fRG 40 40 250 000 250 000 Hz Hz Test Condition Characteristics VS = 11 to 30 V; TA = - 25 to 85 C Parameter Symbol Limit Values min. Supply current IS 8 VREF 2.35 typ. Unit Test Condition 20 mA CT = 1 nF fVCO = 100 kHz 2.65 V 0 mA < IREF < 5 mA max. Reference Reference voltage Reference voltage change Reference voltage change Reference voltage change Temperature coefficient Response threshold of IREF overcurrent Semiconductor Group 2.5 VREF 8 mV 14 V 20 % VREF 15 mV 25 V 20 % mV 0 mA < IREF < 5 mA VREF 15 TC 0.25 0.4 mV/K IREF 10 mA 9 TDA 4718 A Characteristics (cont'd) VS = 11 to 30 V; TA = - 25 to 85 C Parameter Symbol Limit Values min. typ. Unit max. Test Condition Oscillator (VCO) Frequency range Frequency change Frequency change Tolerance Fall time sawtooth RC combination VCO fVCO f/fVCO f/fVCO f/fVCO t t CT RT 40 0.82 5 47 700 Hz % % % s s nF k f 40 100 000 Hz 100 000 0.5 -1 -7 1 7 1 10 14 V 20 % 25 V 20 % RT = 0; CT = 0 CT = 1 nF CT = 10 nF Ramp Generator Frequency range Maximum voltage at CR Minimum voltage at CR Input current through RR Current transformation ratio VH 5.5 V VL 1.8 V IRR 400 0 IRR/ICR A 1/4 Synchronization Sync output Sync input Input current Semiconductor Group VQ H VQ L VI H VI L - II 4 0.4 2 0.8 5 10 V V V V A IQ H = - 200 A IQ L = 1.6 mA TDA 4718 A Characteristics (cont'd) VS = 11 to 30 V; TA = - 25 to 85 C Parameter Symbol Limit Values min. typ. Unit max. Test Condition Comparator K2 Input current Turn-OFF delay 1) Input voltage - II K2 2 500 tD OFF VI K2 V V 1.8 5 Common-mode input voltage range VI C 5.5 0 A ns for duty cycle D=0 D = max. V Soft Start K3, K4 Charge current for Csoft start Ich 6 A Idch Vlim VK4 2 5 1.5 A V V Discharge current for Csoft start Upper limiting voltage Switching voltage K4 Output Stages Q1, Q2 Output voltage Output leakage current VQ H VQ L 30 1.1 V V IQ = 20 mA IQ 2 A VQ H = 30 V ON, OFF, Undervoltage K6 Switching voltage Input current Turn-OFF delay time 2) Error detection time 2) 1) 2) V - II VREF - 0.03 VREF + 0.03 V 2 tD OFF t 250 50 At the input: step function V = - 100 mV V = + 100 mV At the input: step function V = VREF - 100 mV VREF + 100 mV Semiconductor Group 11 A ns ns TDA 4718 A Characteristics (cont'd) VS = 11 to 30 V; TA = - 25 to 85 C Parameter Symbol Limit Values min. typ. Unit max. Test Condition Dynamic Current Limitation K7 Common-mode input voltage range Input offset voltage Input current Turn-OFF delay time 1) Error detection time 1) VIC VIO - II tD OFF t 4 10 2 0 - 10 250 50 V mV A ns ns Overvoltage K5 Switching voltage Input current Output current Turn-OFF delay time 2) Error detection time 2) V - II - IQ VREF - 0.03 VREF + 0.03 V 0 2 200 A A ns ns tD OFF t 250 50 Supply Undervoltage Turn-ON threshold for VS rising Turn-OFF threshold for VS falling VS 8.8 11 V VS 8.5 10.5 V Input Cfilter Rated voltage for rated frequency VR Frequency approx. proportional to voltage within the range VR Voltage at open sync input VC filter 1) 2) 4 3 V 5 1.6 At the input: step function V = - 100 mV V = + 100 mV At the input: step function V = VREF - 100 mV VREF + 100 mV Semiconductor Group 12 V V VQH min = 5 V TDA 4718 A Dimensioning Notes for RC Network 1. Determination of the minimum time during which both outputs must be disabled selection of CT; selection of CR CT. 2. Determination of the VCO frequency = 2 x output frequency selection of RT. 3. Determination of the rated slope of the rising ramp generator voltage, which the maximum possible turn-on period per half wave depends on selection of RR. 4. Duration of the soft start process selection of Csoft start. 5. In the case of a free-running VCO: connect sync output with sync input. 6. Capacitance Cfilter is not required in the free-running operation (sync input connected with sync output). In the case of external synchronization, that value depends on the selected operating frequency and the required maximum phase interference deviation. Rated VCO frequency: Cfilter favourable: Semiconductor Group 100 kHz 10 nF 50 Hz 1F 13 TDA 4718 A Pulse Diagram Semiconductor Group 14 TDA 4718 A VCO Frequency versus RT and CT Semiconductor Group 15 TDA 4718 A VCO Temperature Response VS = 12 V; D = max. f VCO ----------------- [ 1 K ] with CT as parameter fK x K Semiconductor Group 16 TDA 4718 A Current Consumption versus Temperature Semiconductor Group Output Current versus Output Voltage 17