National Semiconductor GAL22V 10, -15, -20, -25, -30 Generic Array Logic General Description The NSC E2CMOS GAL devices combine a high per- formance CMOS process with electrically erasable floating gate technology. This programmable memory technology applied to array logic provides designers with reconfigurable logic and bipolar performance at significantiy reduced pow- er levels. The 24-pin GAL22V10 features 22 inputs, and 10 program- mable Output Logic Macro Cells (OLMCs) allowing each TRI-STATE output to be configured by the user. The archi- tecture of each output is user-programmabie for registered or combinatorial operation, active high or low polarity, and as an input, output or bidirectional I/O. This architecture teatures variable product term distribution, from & to 16 logi- cal product terms to each output, as shown in the logic dia- gram. CMOS circuitry allows the GAL22V 10 to consume just 90 mA typical Icc which represents a 50% saving in power when compared to its bipolar counterparts. Synchronous preset and asynchronous reset product terms have been added which are common to all output registers to enhance system operation. The GAL22V10 is directly compatible with the bipolar PAL22V10 in terms of functionality, fuse map, pinout, and electrical characteristics. Programming is accomplished using industry standard avail- able hardware and software tools. NSC guarantees a mini- mum 100 srase/write cycles. Unique test circuitry and reprogrammable calls allow com- plete AC, DC, cell and functionality testing during manufac- ture. Therefore, NSC guarantees 100% field programmiabili- ty of all GAL devices. In addition, electronic signature is available to provide positive device ID. A security circuit is built-in, providing proprietary designs with copy protection. PRELIMINARY Features @ High performance E2CMOS technology 15 ns maximum propagation delay fmax = 50 MHz with feedback 8 ns maximum from clock input to data output TTL compatible 16 mA outputs UltraMOS Ili advanced CMOS technology Interna! pull-up resistor on all pins m Electrically erasable cell technology Reconfigurable logic Reprogrammable cells 100% tested/guaranteed 100% yields High speed electrical erasure (<50 ms) 20 year data retention @ Ten output logic macrocelis Maximum Fiexibility Programmable output polarity Maximum flexibility for complex logic designs Full function/fuse map/parametric compatibility with PAL22V10 devices @ Variable product term distribution From 8 to 16 product terms per output data function gw Synchronous preset and asynchronous reset to all registers Preload and power-up reset of all registers 100% functional testability @ Fully supported by National PLANT and other industry standard development software @ Security celi prevents copying logic Ordering Information Generic Array Logic Family Number of Array tnputs Output Type: V = Variable Architecture Number of Outputs Speed: 18: tpp = 15ns 20: tpp = 20ns 25: tpp = 25ns 30: tpp = 30ns L = Low Power Package Type: N = 24-Pin Plastic DIP J = 24-Pin Caramic DIP V = 28-Leaad Plastic Chip Carrier Temperature Range: | C = Commercial (0C to + 75C) {Comm} (ind/Mil) (Comm) (Ind/Mi) | = Industrial { 40C to + 85C) M = Military ( 55C to + 125C) | + Qo > TT nL net <t =| O-15LNC Block DiagramGAL22V10 1 a 23. 2 TL/L/10406-2 2-193 OLAZCTYDGAL22V10 Absolute Maximum Ratings (note 1) if Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Ambient Temperatura with Power Applied 65C to + 125C Junction Temperature 65C to + 150C Supply Voltage (Vcc) (Note 2) 0.5V ta +7.0V Lead Temperature Input Voltage (Note 2) 2.5V to Vee + 1.0V (Soldering, 10 seconds) 260C Off-State Output Voltage (Note 2) 2,5V to Vocg + 1.0V ESD Tolerance TaD Output Current +100 mA PZAP = oot = 0 e Tam _ + 9. ZAP Storage Temperature 65C to + 150C Test Method: Human Body Model Test Specification: NSC SOP-5-028 Recommended Operating Conditions SUPPLY VOLTAGE AND TEMPERATURE Symbol Parameter Commerciai Industrial Military Units Min Typ Max Min Typ Max Min Typ Max Veco Supply Voitage 4.75 5 .25 4.6 5 5.5 45 5 .5 Vv Ta Operating Free-Air Temperature 0 25 75 40 25 85 55 25 C Te Operating Case Temperature 125 C AC TIMING REQUIREMENTS GAL22V10-15L GAL22V10-20L GAL22V10-25L GAL22V 10-30L Symbol Parameter COM IND/MIL COM IND/MIL Units Min Max Min Max Min Max Min Max tsu Set-Up Time (Input or Feedback before Clock) 12 1s 20 2s ns tH Hold Time (Input after Clock) 0 0 0 0 ns tw Clock Pulse Width (High/Low) 10 12 15 20 ns taw Asynchronous Reset Input Pulse Width 15 20 25 30 ns taR Asynchronous Reset Recovery Time 15 20 25 30 ns teycLe | Clock Cycle Period (with Feedback) 29 30 45 45 ns (Note 3} foik Clock Frequency | With Feedback 45.4 33.3 28.5 22.2 (Note 4) Without Feedback 50.0 416 33.3 33.3. | MHz f Input Frequency (Note 5) 66.6 60.0 40.0 33.3 tpr Clock Valid after Power-Up 100 100 100 100 ns Note 1: Absolute maximum ratings are thoss values beyond which the device may be permanently damaged. Proper operation is not guaranteed outside the specitiad recommended operating conditions. Note 2: Some device pins may be raised above these limits during programming and preload operations according to the applicable specification. Note 3: toycLe = tsu + toik Note 4: fcoLk (with feedback) = (tcycLe)~ 1 ici (without feedback) = (2 ty) 1 Note 5: f, = (tpp) 1 2-194. as > Electrical Characteristics over Recommended Operating Conditions m NR T t Symbol Parameter Conditions emperature Min Typ Max Units < Range Oo Vie High Level Input Voltage 2.0 Voo+1 v Vit Low Level Input Voltage Vg50.5 0.8 v Vou High Level Output Voltage Voc = Min lon = ~3.2mA CGM/IND 2.4 Vv lou = 2.0mA MIL 2.4 Vv VoL Low Level Output Voltage Voc = Min lo. = 16 mA COM/IND 0.5 v lo = 12 mA MIL 0.5 v 1OZH High Level Off State Veo = Max, Vo = Voc (Max) 10 A Output Current u loz Low Level Off State Voc = Max, Vo = GND 160 A Output Current a I Maximum Input Current Voc = Max, Vi = Voc (Max) 150 10 pA lin High Level Input Current Voc = Max, Vi = Voc (Max) 10 pA lit Low Level Input Current Voc = Max Vv, = GND ~ 160 pa los* Output Short Circuit Current Voc = 5.0V, Vo = GND 50 135 mA lec Supply Current f = 15 MHz, Veco = Max COM 90 130 mA MIL/IND 150 mA C, Input Capacitance Voc = 5.0V, Vy = 2.0V 8 pF Cio I/O Capacitance Voc = .0V, Vizo = 2.0V 10 pF *One output at a time for a maximum duration of one second. Switching Characteristics over Recommended Operating Conditions GAL22V10-15L | GAL22V10-20L | GAL22V10-25L | GAL22V10-30L Symbol Parameter Conditions COM IND/MIL COM IND/MIL Units Min Max Min Max Min Max Min Max Input or F t $1 Cl , Cy = 80 pF tpp Inpu or sedback lO jased, CL p 15 20 25 30 ns Combinatorial Output tol Clock to Registered Output [Si Closed, C_ = 50 pF a 10 45 20 ns or Feedback tpzxt Input to Combinatorial Output Active High; S1 Open, CG, = 50 pF 45 20 25 25 ns Enabled via Product Term Active Low; 51 Closed, CL = 50 pF Combinatorial Output| Fi Vou: : = F tpxzi Input to om inatoriat Output! From Voy; $1 Open, GC, = 5p 45 20 25 25 ns Disabled via Product Term =| From Vo,; S1 Closed, CL = 5 pF tar Asynchronous Reset Input to Register 20 25 25 30 ns Output P -Up to Regist , CL. = 50 pF treset |Power- p o Registered $1 Closed, C pl 45 45 45 45 us Output High 2-195GAL22V10 AC Test Load Sv << a OUTPUT T" a2 Test Waveforms Setup and Hold TIMING i WwW INPUT, A" ov set-up tHoLo DATA YY w INPUT rt ov TL/L/10406-4 Propagation Delay _____________3y INPUT er ee aa IN=PHASE You OUTPUT a OUT OF PHASE OUTPUT f oH (S1 CLOSED) evennerenc Vey TL/L/ 10406-6 Notes: , includes probe and jig capacitance, Vy = 15V. Test inputs have rise and fall times of 5 ns between 0.3V and 2.7V. In the examples above, the phase redationships between inputs and outputs have been chosen arbitrarily. MIL Ri = 300 R2 = 750 COML/IND Ri = 300 R2 = 390 TL/L/10406-3 HIGH=LEVEL PULSE INPUT LOW-LEVEL PULSE INPUT ENABLE INPUT NORMALLY HIGH OUTPUT _(S1 OPEN) NORMALLY LOW OUTPUT (St CLOSED) wv ov You Pulse Width Vr Vy Vr Vy TL/L/10406-5 Enable and Disabie XV, ENABLED V7 2K DISABLED ~| -e'P7H tpyz pate + y 0.5 Vy KE --| pete. te] +V, K*r yt oy t TL/L/10406-7 2-196Switching Waveforms INPUT a VALID INPUT XY ree WwW | CLOCK / \ / force | ho be OLAec TVD INPUT USED FOR ASYNCHRONOUS /RESET acre XX _ACTIVE tw -| INPUT USED FOR TRISTATE CONTROL x VALID DISABLE xX VALID ENABLE t t tpp | pxzi| - PIX | COMBINATORIAL Ve TOK 5 f_ b tour J tap | | REGISTERED YX XY \ feo OUTPUT / \ TLIL/10406~8 Power-Up Reset Waveforms 90% v ___/ oC oy }+ ter aLock . HOU POO GOK coe Bau, tRESET ee a WW INTERNAL REGSTERS CC FEED KKK RRMA KK RR RRA R REMARK LY NERA ROSTERS TL/L/10406-9 Input/Output Schematics Phased Output Turn-On Circuit TRI=STATE TL/L/10406-14 2-197GAL22V10 Functional Description The GAL22V10 logic array consists of a programmable AND array with fixed OR-gate connections, similar to the traditional bipolar PAL architecture. The logic array is orga- nized as 22 complementary input lines crossing 132 prod- uct term lines with a programmable E2PROM cell at each intersection (5808 cells). Each programmable cell may es- tablish a connection between an input line (true or comple- ment phase of an array input signal) and a product term. A product term is satisfied (logically true) while all of the input lines connected to it are in the high logic state. Of the 132 product terms, 130 are distributed amang ten output logic macrocelis (OLMCs) with a varying number of terms allocated to each OLMC (as shown in Figure 7). The ten OLMCs control the flow of input and output signals be- tween the logic array and the devices I/O pins. For a given OLMC, B, 10, 12, 14 or 16 product terms feed into an OR- gate to produce each output value. This varied distribution of product terms among outputs allows more optimum use of device resources. One additional product term in each of the ten GLMCs is used to control the associated TRI- STATE device output. One giobal product term is used to control an asynchronous preset, and another global product term is used for a synchronous reset, and both are connect- ed to all ten of the output registers. The fundamental transfer function of each GAL22V10 out- put is the familiar Boolean sum-of-products. Design devel- opment software is available which accepts Boolean equa- tions and converts them automatically into GAL22V10 pro- gramming patterns. Under control of an OLMC, each output may be designated either registered or combinatorial (non-registered). In the registered output configuration, the logic function output passes through a D-type flip-flop triggered by the rising edge of the clock input. Additionally, the logic function's out- put polarity may be designated active-low or active-high (ad- justed after the register, if present). OLMC options such as these ara selected using a set of programmable architec- ture control cells. These architecture cells are normally con- figured automatically by the development software or pro- gramming hardware. The four possible I/O configurations of each GAL22V10 OLMC are: registered-active low, registered-active high, combinatorial-active low, and combinatorial-active high. These combinations are shown in Figure 3. The feedback paths are redirected with the register selection. The regis- tered configurations include an internal feedback path taken directly from the register output. The combinatorial configu- rations include feedback from the I/O pin, thus allowing for bidirectional I/O or additional input channets. Ail registers ina GAL22V10 device are reset to the low state upon power-up. Outputs, in turn, assume either low or high logic levels (if enabied} depending on the selected output polarity. Power-up reset may simplify sequential circuit de- sign and test. To ensure successful power-up reset, Voc must rise monotonically until the specified operating voltage is attained. During power-up, the clock input should assume a valid, stable logic state as early as possible (within the specified time, tpp) to avoid interfering with the reset opera- tion. The clock input should also remain stable until after the power-up reset operation is completed to allow the registers to capture the proper next state on the first high-going clock transition. It should be noted that the switching of any input not logical- ly connected to a product term or jogic function has no ef- fect on the associated output logic state. To minimize power consumption, however, unused inputs should be connected to a stable logic level such as ground or Voc (CMOS GAL inputs may be tied directly to the supply voltage without causing excessive loading conditions). Programmable Preset and Reset The ten macrocell flip-flops share common programmable preset and reset control for easy system initialization. The outputs of the register will go to the logic high state follow- ing a low-to-high transition of the clock input when the syn- chronous preset (SP) product term is asserted. The register will be forced to the logic low state independent of the clock when the asynchronous reset (AR) product term is asserted. Product term controf allows preset and reset te be functions of any combination of device inputs and output feedback. The outputs will be high or low depending upon the polarity option chosen. Note that preset and reset control the flip-flop, not the out- put. Thus, if active low polarity is selected, a synchronous preset would produce low-level outputs, and an asynchro- nous reset would produce high-level outputs (if enabled). 2-198GAL22V10 Biock Diagram-DIP Connections | {9] | 10) 1 [114] GND [14] 12 13 [28} [27] [26] [21] [20] [16] PLCC PIN NUMBERS | PCC Pin Numbers FIGURE 1 \/0 /0 /0 1/0 1/0 fo \(/0 \(/O \/0 1/0 TL/L/10406-12 2-199 OLACZ1V5GAL22V10 28-Lead PLCC Connection Diagram 1 Cl Ver W/O 1/0 I conet, EG GI El Bs ILS 2h | 26] i [4] [21] 1/o | 5] i/o | i/o Ne * Gas Ne ' fo i (fo | [3] i/o [4] G2) we [3] 4) G5] I | GND 1 io io TL/L/10406-13 FIGURE 2 file can be down-loaded into industry standard programming Clock/Input Frequency equipment. Many software packages and programming Specifications units support a multitude of programmable logic products as The clock frequency (fco_K) parameter listed in the Recom- well. The PLAN software package from National Semicon- mended Operating Conditions table specifies the maximum ductor supports all programmable logic products availabie speed at which the GAL22V10 registers are quaranteed to from National and is fully JEDEC-compatible. PLAN soft- operate. Clock frequency is defined differently for the two ware also provides automatic device selection based on the cases in which register feedback is used versus when it is designer's Boolean logic equations. not. In a data-path type application, when the logic functions Nationa! strongly recommends using only approved pro- fed into the registers are not dependent on register feed- gramming hardware and software for developing GAL de- back from the previous cycle {i.e. based only on external signs. Programming using unapproved equipment generally inputs), the minimum required cycle period (foLK~ 1 without voids all guarantees. Approved programmers incorporate feedback) is defined as the greater of the minimum clock specialized programming algorithms that program the array period (ty high + ty low) and the minimum data window and automatically configure the architecture cells. To en- period (tgy + ty). This assumes optimal alignment between sure data retention and reliability, the programming algo- data inputs and the clock input. in sequential logic applica- rithm also tracks the number of programming cycles to tions such as state machines, the minimum required cycle which each GAL device has been subjected since shipment, period (teycLte = fcik 71 with feedback) is defined as tok and stores this information automatically in the device. + tgp. This provides sufficient time for outputs from the The GAL22V10 can accept fuse-maps prepared for other ragisters to feed back through the logic array and set up on PAL22V10 devices. PAL22V10 fuse-maps can be created the inputs to the registers before the end of each cycle. by any JEDEC-compatible PAL development software or by The input frequency (f) parameter specifies the maximum loading the fuse pattem from an existing programmed rate at which each GAL22V10 input can be toggled and still PAL22V10 device into the programming unit (provided the produce valid logic transitions on each combinatorial output. PAL device has not been secured). The f specification is derived as the inverse of the combina- Detailed logic diagrams showing all JEDEC cell-map ad- torial propagation delay (tpp). dresses in the GAL22V 10 logic array and OLMC are provid- . ed for direct map editing and diagnostic purposes. Figure 6 Design Development Support and Tabie II show details of the OLMC and the programma- A variety of software tools and programming equipment are ble architecture cell combinations. Figure 7 shows the available to support the development of designs using JEDEC logic diagram and details of all programmable cell GAL22V10 products. Typical software packages, including locations. For a list of current software and programming Nationals PLAN software, accept Boolean logic equations support tools available far these devices, please contact to define desired functions. Most are available to run on your local National sales representative or distributor. If de- personal computers and generate a JEDEC-compatible tailed specifications of the GAL22V10 programming alge- cell-map (analogous to a PAL fuse-map}. The industry- rithm are needed, please contact the National Semiconduc- standard JEDEC format ensures that the resulting cell-map tor Programmable Device Support department. 2-200OLMC Selection Table Y U) v o | v oI FIGURE 3-1. Registered/Active Low [} 3 =1 = D> | ar : D+ ~ Doe. C omy > 6 | SP FIGURE 3-2. Registered/Active High Sy = 0 S,=1 _ a e FIGURE 3-3. Combinatorial/Active Low FIGURE 3-4. Combinatorial/Active High TL/L/10406~14 TL/L/10406-15 TL/L/10406-16 TL/L/10406- 17 2-201 OLAZZ1V9DGAL22V10 Security Cell A security cell is provided on all GAL22V10 devices as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, the circuitry enabling array ac- cess is disabled, preventing further programming or verifica- tion of the array. The security cell can be erased only in conjunction with the array during a bulk erase cycle, so the original configuration can never be examined once this cell is programmed. Electronic Signature Each GAL device contains an electronic signature word consisting of 64 bits of reprogrammable memory. The elec- tronic signature word can be programmed to contain any identification information desired by the user. Some uses include pattern identification labels, revision numbers, dates, inventory control information, etc. The data stored in the electronic signature word has no effect on the function- ality of the device. The information is read out of the device using the normal program verification procedure provided by the programming equipment. The information may be ac- cessed at any time independent of the state of the security cell. Nationals PLAN development software allows elec- tronic signature data to be entered by the user and down- loaded to the programming equipment. Bulk Erase The programming equipment automatically performs a bulk erase operation prior to each programming operation. No special erase operation need be performed by the user. Bulk erase clears the logic array, architecture cells, security ceil, and electronic signature information. The GAL device is thereby reverted back to its virgin state. Latch-Up Protection GAL devices are designed with an on-chip charge pump to negatively bias the substrate. The negative bias is of suffi- cient magnitude to prevent input undershoots from causing the circuitry to latch. Additionally, outputs are designed with n-channel pullups instead of the traditional p-channel pull- ups to eliminate any possibility of SCA induced latching. Manufacturer Testing Because of E2CMOS technology, GAL devices can be re- programmed in milliseconds. This allows each device to be completely tested by the manufacturer using numerous log- i array and architecture patterns prior to shipping. Every programmable ceil and every logic path through every de- vice is fully tested for programmability, functionality and per- formance to all AC and DC parameters, The customer can therefore expect 100% programming and functional yield and 100% compliance of all GAL products to datasheet specifications. The testing procedure performed on all GAL devices by the manufacturer tests all aspects of device operation. Exten- sive testing of all programmable cells in the device include margin testing, internal verify, and program retention during high-temperature bake. All DC and AC parameters are tast- ed at hot and cold temperatures using a variety of worst- case logic and signal patterns. Functional tests include re- programming each OLMC to all valid architectural configura- tions. Register Preload The register preload feature allows OLMC registers to be directly loaded with any desired data pattern. It also allows the present state of OLMC registers to be examined regard- less of TRI-STATE control conditions. This simplifies testing of devices after programming. A device may be put into any desired register state at any point during the functional test sequence. The test sequence may then be resumed to veri- fy proper next-state transitions. This allows complete verifi- cation of sequential logic circuits, including states that are normally impossible or difficult to reach. It may also shorten the overall test time significantly. A typical functional test sequence would be to verify all pos- sible state transitions for the device being tested. To verify these transitions requires the ability to set the state registers into an arbitrary present state value, and to set the device inputs to any arbitrary present input value. Once this is done, the state machine is then clocked into a new state, or next state. The next state is then checked to validate the transition from the present state. In this way any state tran- sition can be checked. Register preload is not an operational mode and is not in- tended for board-level testing because elevated voltage lev- els must be applied to the device. The programming equip- ment normally provides the register preload capability as part of its functional test facility. Note that the testing of GAL devices after programming by the user may be considered unnecessary because all E27CMOS GAL products are com- pletely tested by the manufacturer, guaranteeing 100% post-programming functional yield. The register preload algorithm is described for those users who wish to test programmed GAL devices using test equip- ment other than approved GAL programming equipment. As shown in the register preload waveform in Figure 5, the pre- load sequence must not begin until the normal power-up reset operation has completed {after time taeseT). The de- vice is placed into preload mode by raising the PRLD in- put (pin 13*) to voltage Vjes, as specified in the register preload specifications (Table |). To preload the OLMC registers, a series of data bits are shifted into the device on the Spin input (pin 11*), one bit for each OLMC in which registered output has been select- ed. (Non-registered OLMCs are bypassed.) The shift se- quence is clocked by the rising edge of the Dc _, input (pin 1*). The data stream is shifted in through the registered OLMC with the lowest corresponding pin number, and then upward through all remaining registered OLMCs in pin- number ascending order. Therefore, the first data bit in the series is ultimately loaded into the registered OLMC with the highest corresponding pin number, as shown in Figure 4. *Applies to 24-pin DIP packages for GAL22V10; refer to the 2B-lead PCC. Connection Diagram for conversion. 2-202Register Preload (Continued) OLAZz v5 As the data series is shifted into the Spjy input, the contents Voc of all ragistars (in registered OLMCs) are shifted upward 7 and out onto the Spour output (pin 15*). Compiete pres- Dok~T! 24 ant-state information can be examined in this manner. Test - fixtures can be devised to test several GAL devices in which = the Spout pin of each chip is connected to the Spiny pin of = = the next, and ail preload and present-state data can be = shifted around a single serial loop. ] a Note that when shifting register data into Spi or out of ~ = Spout: Vir/Vor = register reset (0), and Viq/VoH = regis- = = ter set (1). These 0 and 1 register states are always inverted (active-low) on the normal output pins regardless of the se- 7 15 T lected output polarity (polarity affects logic function values 7h Spout** before register inputs). Son Applies to 24-pin DIP packages for GAL22V10; refer to the 28-lead PCC a" 12 13 PRLD Connection Diagram for conversion. = TL/L/10406-18 **The Spout output buffer is an open drain output during preload. This pin should be terminated to Voc with a 10 k0 rasistar. FIGURE 4. Output Register Preload Pinout Register Preload Specifications TABLE J Symbo! Parameter Conditions Min Typ Max Units Vin Input Voltage (High) 2.40 Voc V Vi Input Voltage (Low) 0.00 0.50 Vv Vies Register Preload Input Voltage 14.5 16 15.5 Vv VoH Output Voltage (High) (Note 1} Voc Vv VoL Output Voltage (Low) (Note 1) lo. = 12mA 0.00 0.50 Vv lis Ie Input Current (Programming) +1 10 pA lou High Level Output Current (Note 1) Vou = Voc 10 pA tewy Verify Pulse Width 1 5 10 pS to Pulse Sequence Delay 1 6 10 ps tReseT Register Reset Time from Valid Voc 45 ps Note 1: The Spout output buffer is an open drain output. This pin should be terminated to Vcc with a 10k resistor. Register Preload Waveforms Vv, --2--- KO Cs Yoo 90% ied ov t RESET Ves-------- bb aS BIT 1 xX (BTN AX gg NN p You 55 Spout VALID DATA VALID DATA TL/L/10406-19 FIGURE 5 **The Spout output butfer is an open drain output during preload. This pin should be terminated to Voc with a 10 kfi resistor. 2-203GAL22V10 OLMC Logic Diagram AND PI FIGURE 6 TABLE Il bowen gererrrrre Output Configuration = OC -~ O+-+ Registered/ Active Low Registered/ Active High Combinatorial/Active Low Combinatorial/Active High FL/L/10406-20- 2-204GAL22V 10 Logic Diagram OP PM NUMBERS tuNE OP PIM NUMBERS | PRODUCT UNE FIRST CELL HUMBERS O27 46 810 1214 618 2022 2628 HID ELSE SEB ae ! t 24 23 Sassi 22 2 SOmsat2 S1a5aiy 2 3 So sSatd 1 =sBi 20 4 oun 50-586 St = 5817 19 5 s0= 5818 $1=5819 18 6 7 7 16 8 ts 9 S412 5500 3568 14 5678 10 5764 "1 13 2_ = 13 37 Or 1315 We 223 ag m3 3535 a7 38 aes USER ELECTRONIC SIGHATURE WORD: 3828 5891 L i. JEDEC Logic Array Cell Numbers = Product Line First Cell Number + input Line Numbers FIGURE 7 TL/L/10406-21 2-205 OLACZ IVD